Semiconductor memory structure and preparation method thereof
By using metal filler layers and dielectric layer structures in semiconductor memories, the problem of poor trench filling was solved, improving memory yield and film alignment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2022-04-21
- Publication Date
- 2026-05-12
AI Technical Summary
During the semiconductor memory manufacturing process, unwanted grooves can easily appear when filling the trench with material layers, leading to a decrease in flatness and affecting yield.
A metal filler layer is used to fill the groove, and combined with a dielectric layer structure, a load stack and a gate stack structure are formed to ensure the groove filling effect and electrical insulation.
It effectively eliminates trench collapse, improves the yield of semiconductor memory, and achieves film alignment by positioning the trench boundary through the metal filling layer.
Smart Images
Figure CN122028720A_ABST
Abstract
Description
[0001] This application is a divisional application. The original application has the application number 202210427201.4 and the original application date is April 21, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor memory structures, specifically to semiconductor memory structures and fabrication methods. Background Technology
[0003] In the manufacturing process of semiconductor memories, it is usually necessary to form trenches on the substrate surface and fill the trenches with other material layers. During the filling of these material layers, it is possible for issues such as… Figure 1 As shown, unwanted grooves appear on the substrate surface. Please refer to [link / reference]. Figure 1 The trench containing the shallow trench isolation structure is sequentially filled with a first material layer 103, a second material layer 104, and a third material layer 105. The top height of the first material layer 103 is lower than the surface height of the substrate 101 and the top height of the second material layer 104, resulting in a groove 102 between the second material layer 104 and the substrate 101. These grooves 102 are difficult to fill and level in the subsequent semiconductor memory manufacturing process, and may collapse as the material layers accumulate during the subsequent semiconductor memory manufacturing process, affecting the flatness of the semiconductor memory and thus affecting the yield of the semiconductor memory. Summary of the Invention
[0004] In view of this, this application provides a semiconductor memory structure and fabrication method that can eliminate the grooves that occur during the process of filling multiple material layers in the trench, thereby improving the yield of the semiconductor memory.
[0005] This application provides a semiconductor memory structure, comprising: a substrate; at least one first trench located on the upper surface of the substrate; a first dielectric layer distributed along the inner wall of the first trench; a second dielectric layer located on the surface of the first dielectric layer and filling the first trench; the top of the first dielectric layer being lower than the top of the second dielectric layer and the upper surface of the substrate, thereby forming a first groove between the second dielectric layer and the substrate; a fourth dielectric layer covering the inner wall of the first groove and filling a portion of the space in the first groove, the fourth dielectric layer also covering the second dielectric layer; and a load stack structure located on the fourth dielectric layer and above the top of the second dielectric layer.
[0006] Optionally, it further includes: a metal filler layer located within the first groove, filling a portion of the space within the first groove, and the fourth dielectric layer located between the metal filler layer and the substrate, for isolating the electrical connection between the metal filler layer and the substrate.
[0007] Optionally, it may also include: a third dielectric layer located above the metal filler layer and within the first groove, filling the first groove.
[0008] Optionally, the second dielectric layer includes a first sublayer and a second sublayer, wherein the first sublayer is formed on the surface of the first dielectric layer, the second sublayer is formed on the surface of the first sublayer, and fills the first trench.
[0009] Optionally, the first dielectric layer comprises an oxide dielectric layer; and / or, the second dielectric layer comprises a nitride dielectric layer.
[0010] Optionally, the first sublayer includes a nitride dielectric layer, and the second sublayer includes an oxide dielectric layer.
[0011] Optionally, it also includes a gate stack structure formed on top of the substrate.
[0012] Optionally, the gate stack structure includes at least a first polysilicon layer, a first conductive layer, and a first mask layer sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate; and / or, the load stack structure includes a second polysilicon layer, a second conductive layer, and a second mask layer sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate.
[0013] Optionally, the material used to prepare the metal filling layer is the same as the material used to prepare the first conductive layer and the second conductive layer.
[0014] Optionally, the top edge corner of the first trench is arc-shaped.
[0015] This application provides a method for fabricating a semiconductor memory structure, comprising the following steps: providing a substrate, wherein a first trench is formed on the upper surface of the substrate; sequentially forming a first dielectric material layer and a second dielectric material layer along the inner wall of the first trench; partially removing the first dielectric material layer and the second dielectric material layer, and respectively forming a first dielectric layer and a second dielectric layer, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, thereby forming a first groove between the second dielectric layer and the substrate; forming a fourth dielectric layer on the inner wall of the first groove, wherein the fourth dielectric layer covers the inner wall of the first groove and fills part of the space of the first groove, and the fourth dielectric layer also covers the second dielectric layer; and forming a load stack structure on the fourth dielectric layer and located above the top of the second dielectric layer.
[0016] Optionally, after forming the fourth dielectric layer on the inner wall of the first groove, the method further includes the following step: forming a metal filling layer in the first groove to partially fill the first groove, and the fourth dielectric layer is partially located between the metal filling layer and the substrate. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 The semiconductor memory structure described in the prior art;
[0019] Figure 2 This is a schematic flowchart of the steps involved in fabricating the semiconductor memory structure described in one embodiment of this application;
[0020] Figure 3 This is a schematic diagram of the structure after the first trench is formed in an embodiment of this application;
[0021] Figure 4 This is a schematic diagram of the structure after the first dielectric material layer is formed in an embodiment of this application;
[0022] Figure 5 This is a schematic diagram of the structure after the formation of the first sub-material layer and the second sub-material layer in the embodiments of this application;
[0023] Figure 6 This is a schematic diagram of the structure after the third mask layer is formed in an embodiment of this application;
[0024] Figure 7 This is a schematic diagram of the structure after the first groove is formed in an embodiment of this application;
[0025] Figure 8 This is a schematic diagram of the structure after the fourth dielectric layer is formed in an embodiment of this application;
[0026] Figure 9 This is a schematic diagram of the structure after the metal layer is formed in an embodiment of this application;
[0027] Figure 10 This is a schematic diagram of the structure after the metal layer is etched back in an embodiment of this application;
[0028] Figure 11 This is a schematic diagram of the structure after the dielectric material layer is formed in the embodiments of this application;
[0029] Figure 12This is a schematic diagram of the structure after the third dielectric layer is formed in an embodiment of this application;
[0030] Figure 13 This is a schematic diagram of the structure after the gate stack structure is formed in the embodiments of this application;
[0031] Figure 14 This is a schematic diagram of the structure after the fourth mask layer is formed in an embodiment of this application;
[0032] Figure 15 This is a schematic diagram of the structure after etching the first mask layer, the first conductive layer, and the first polysilicon layer in an embodiment of this application;
[0033] Figure 16 This is a schematic diagram of the structure after the insulating layer is formed in an embodiment of this application;
[0034] Figure 17 This is a schematic diagram of a semiconductor memory structure described in one embodiment of this application;
[0035] Figure 18 This is a schematic diagram of a semiconductor memory structure according to an embodiment of this application. Detailed Implementation
[0036] The semiconductor memory structure and its fabrication method will be further described below with reference to the accompanying drawings and embodiments.
[0037] This application provides a method for fabricating a semiconductor memory structure in its first aspect.
[0038] Please see Figures 2 to 16 ,in Figure 2 This is a schematic flowchart of the steps involved in fabricating the semiconductor memory structure described in one embodiment. Figures 3 to 16 This is a schematic diagram of the structure corresponding to each step of the method for fabricating the semiconductor memory structure described in the embodiments of this application.
[0039] In this embodiment, the method for fabricating the semiconductor memory structure includes the following steps: Step S101: Providing a substrate 201, wherein a first trench 200 is formed on the upper surface of the substrate 201 (see [link to documentation]). Figure 3 Step S102: A first dielectric material layer 2031 is sequentially formed along the inner wall of the first trench 200 (see [link]). Figure 4Step S103: Partially remove the first dielectric material layer 2031 and the second dielectric material layer to make the top edge corner of the first trench 200 arc-shaped, and respectively form the first dielectric layer 203 and the second dielectric layer 204, and the top of the first dielectric layer 203 is lower than the top of the second dielectric layer 204 and the upper surface of the substrate 201, thereby forming a first groove 202 between the second dielectric layer 204 and the substrate 201 (see [link]). Figure 7 Step S104: A metal filling layer 207 is formed in the first groove 202 to partially fill the first groove 202 (see [link]). Figure 10 ).
[0040] In this embodiment, the semiconductor memory structure fabrication method uses a metal filling layer 207 to fill part of the space in the first groove 202. Since the metal filling layer 207 has high strength and a certain degree of ductility, after filling the first groove 202 with the metal filling layer 207, the probability of the first groove 202 collapsing in the subsequent semiconductor memory structure fabrication process is significantly reduced. This can effectively eliminate the unwanted grooves on the upper surface of the substrate 201 and reduce the possibility of the first groove 202 collapsing after filling, thereby achieving a better groove filling effect and effectively improving the yield of the semiconductor memory structure.
[0041] Furthermore, since the first groove 202 is filled with metal, the opacity and good light reflection properties of the metal filling layer can be used to locate the boundary of the first trench 200 during the subsequent fabrication of the semiconductor memory structure, thereby determining the center position of the first trench 200 and achieving a better film alignment effect.
[0042] In some embodiments, after forming a metal filling layer 207 within the first groove 202, the method further includes the following step: forming a third dielectric layer 208 above the top of the metal filling layer 207, wherein the third dielectric layer 208 fills the first groove 202 (see [link to documentation]). Figure 12 ).
[0043] In these embodiments, a third dielectric layer 208 is also used to fill the remaining portion of the first groove 202, which can effectively isolate the electrical connection between the metal filling layer 207 and other conductive structures, thereby achieving a certain insulation effect and preventing the metal filling layer 207 from short-circuiting with other conductive structures, which would lead to damage to the semiconductor memory structure.
[0044] In some embodiments, the partial removal of the first dielectric material layer 2031 and the second dielectric material layer includes the following steps: using at least one of dry etching or wet etching to partially remove the first dielectric material layer 2031 and the second dielectric material layer, wherein the etching rate of the selected etching gas or etching liquid on the first dielectric material layer 2031 is greater than the etching rate on the second dielectric material layer, thereby making the top height of the first dielectric layer 203 formed after etching lower than the top height of the second dielectric layer 204.
[0045] In some embodiments, the partial removal of the first dielectric material layer 2031 and the second dielectric material layer further includes the following steps: forming a third mask layer 2080 on the upper surface of the first dielectric layer 203, wherein the patterned third mask layer 2080 exposes the first dielectric material layer 2031 and the second dielectric layer filling the first trench 200, as well as a portion of the first dielectric material layer 2031 at the edge of the first trench 200, so that the etching gas or etching liquid can be etched only within the first trench 200 and at the edge of the first trench 200 to obtain the desired shape. (See also...) Figure 6 .
[0046] In some further embodiments, the etching rate of the etching gas or etching liquid on the first dielectric material layer 2031 is greater than the etching rate on the substrate 201. Therefore, after etching, the top height of the formed first dielectric layer 203 is still lower than the height of the upper surface of the substrate 201. (See reference here.) Figure 7 As shown.
[0047] In some embodiments, the second dielectric layer 204 includes a first sub-layer 205 and a second sub-layer 206. Forming the second dielectric layer 204 includes the following steps: forming a first sub-material layer 2051 on the surface of the first dielectric layer 203; forming a second sub-material layer 2061 on the surface of the first sub-material layer 2051, wherein the second sub-material layer 2061 fills the first trench 200. (See attached document for more details.) Figure 5 .
[0048] exist Figure 7 In the illustrated embodiment, the first dielectric layer 203 comprises an oxide dielectric layer, the first sublayer 205 comprises a nitride dielectric layer, and the second sublayer 206 comprises an oxide dielectric layer. After etching, the top of the first sublayer 205 is higher than the top of the first dielectric layer 203 and also higher than the top of the second sublayer 206. The central region of the filler in the first trench 200 is recessed.
[0049] exist Figure 18In the illustrated embodiment, the second dielectric layer 204 comprises only a single dielectric layer and does not include multiple separate sublayers. In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer, and the second dielectric layer 204 comprises a nitride dielectric layer.
[0050] Before forming the metal filling layer 207 in the first groove 202, the method further includes the following step: forming a fourth dielectric layer 209 on the inner wall surface of the first groove 202. (See attached image for details.) Figure 8 .
[0051] The fourth dielectric layer 209 is located between the metal filler layer 207 and the substrate 201, and can be used to isolate the electrical connection between the metal filler layer 207 and the substrate 201, prevent short circuit between the metal filler layer 207 and the substrate 201, thereby preventing the semiconductor memory structure from being electrically damaged due to the metal filler layer 207.
[0052] The formation of a metal filling layer 207 within the first groove 202 includes: forming a metal layer 2071 within the first groove 202, above the top of the second dielectric layer 204, and on the upper surface of the substrate 201, wherein the metal layer 2071 at least completely fills the first groove 202. (See reference [link to relevant documentation]). Figure 9 The metal layer 2071 is etched back, and the metal layer 2071 in the first groove 202 is retained as the metal filling layer 207. (See reference [link to relevant documentation]). Figure 10 .
[0053] In some embodiments, at least one of physical vapor deposition, chemical vapor deposition, etc., is used to form a metal layer 2071 in the first groove 202. The metal layer 2071 can be etched back using at least one of dry etching or wet etching. Furthermore, the etch-back method used has a high etching selectivity for both the fourth dielectric layer 209 and the metal layer 2071.
[0054] The formation of the third dielectric layer 208 on the upper surface of the metal filler layer 207 includes: forming a dielectric material layer 2081 above the top of the metal filler layer 207, above the top of the second dielectric layer 204, and on the upper surface of the substrate 201. The dielectric material layer 2081 at least fills the first groove 202. (See reference here.) Figure 11 The dielectric material layer 2081 is etched back, and the dielectric material layer 2081 in the first groove 202 is retained as the third dielectric layer 208. (See reference [link to relevant documentation]). Figure 12 .
[0055] In some embodiments, the dielectric material layer 2081 is prepared using at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The dielectric material layer 2081 includes a silicon nitride layer, etc. The third dielectric layer 208 here can be used to isolate the metal filling layer 207 from electrical connections with other conductive structures, thereby providing a certain insulating effect and preventing short circuits between the metal filling layer 207 and other conductive structures, which could lead to damage to the semiconductor memory structure.
[0056] In some embodiments, the fabrication method further includes fabricating a gate stack structure 300 on the upper surface of the substrate 201. See also... Figure 13 On the surface of the fourth dielectric layer 209 and the surface of the third dielectric layer 208 on the substrate 201, a first polysilicon layer 210, a first conductive layer 211, and a first mask layer 212 in the gate stack structure 300 are sequentially formed. See also... Figure 14 A fourth mask layer 213 is formed on the upper surface of the first mask layer 212, and the patterned fourth mask layer 213 exposes the first mask layer 212 above the first trench 200.
[0057] Afterwards, please refer to Figure 15 The first mask layer 212, the first conductive layer 211, and the first polysilicon layer 210 are etched in a direction perpendicular to and downward from the first mask layer 212 to expose the fourth dielectric layer 209. (See also...) Figure 16 Then, an insulating layer 214 is formed on the upper surface of the exposed fourth dielectric layer 209, thereby completing the fabrication of the gate stack structure 300. The insulating layer 214 includes a silicon oxide layer.
[0058] In some embodiments, the fabrication method further includes fabricating a load stack structure 301 above the top of the second dielectric layer to allow the gate stack structure 300 to have a better etching loading effect. When fabricating the load stack structure 301, a metal filler layer filling the first groove 202 is also used for positioning.
[0059] Specifically, the first mask layer 212 and the second mask layer 2121 are formed by partially removing the same mask material layer, the first conductive layer 211 and the second conductive layer 2111 are formed by partially removing the same conductive material layer, and the first polysilicon layer 210 and the second polysilicon layer 2101 are formed by partially removing the same polysilicon material layer. Therefore, by forming a patterned mask layer on the uppermost mask material layer and exposing the area corresponding to the position of the metal filling layer mark, the load stack structure 301 and the gate stack structure 300 can be formed.
[0060] The first patterned photomask needs to expose the area corresponding to the metal filling layer.
[0061] In some embodiments, the load stack structure 301 includes a second polysilicon layer, a second conductive layer, and a second mask layer sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate. (See here for more details.) Figure 17 .
[0062] In a second aspect, this application provides a semiconductor memory structure.
[0063] Please see Figure 12 This is a schematic diagram of the semiconductor memory structure described in one embodiment of this application.
[0064] In this embodiment, the semiconductor memory structure includes: a substrate 201; at least one first trench 200 located on the upper surface of the substrate 201, wherein the top edge corner of the first trench 200 is arc-shaped; a first dielectric layer 203 distributed along the inner wall of the first trench 200; a second dielectric layer 204 formed on the surface of the first dielectric layer 203 and filling the first trench 200; the top of the first dielectric layer 203 is lower than the top of the second dielectric layer 204 and the upper surface of the substrate 201, thereby forming a first groove 202 between the second dielectric layer 204 and the substrate 201; and a metal filling layer 207 located within the first groove 202, filling a portion of the space within the first groove 202.
[0065] The semiconductor memory structure of this application uses a metal filling layer 207 to fill part of the space of the first groove 202. Since the metal filling layer 207 has high strength and a certain degree of ductility, after filling the first groove 202 with the metal filling layer 207, the probability of the first groove 202 collapsing in the subsequent semiconductor memory structure fabrication process is significantly reduced. This can effectively eliminate the unwanted grooves on the upper surface of the substrate 201 and reduce the possibility of the first groove 202 collapsing after filling, thereby achieving a better groove filling effect and effectively improving the yield of the semiconductor memory structure.
[0066] Furthermore, since the first groove 202 is filled with metal, the opacity and good light reflection properties of the metal filling layer can be used to locate the boundary of the first trench 200 during the subsequent fabrication of the semiconductor memory structure, thereby determining the center position of the first trench 200 and achieving a better film alignment effect.
[0067] In some other embodiments, the semiconductor memory structure further includes a third dielectric layer 208 located above the metal filling layer 207 and within the first groove 202, filling the first groove 202.
[0068] By filling the remaining portion of the first groove 202 with a third dielectric layer 208, the electrical connection between the metal filling layer 207 and other conductive structures can be effectively isolated, thereby achieving a certain insulation effect and preventing the metal filling layer 207 from short-circuiting with other conductive structures, which could lead to damage to the semiconductor memory structure.
[0069] In this embodiment, the reason for forming the first groove 202 is that the top edge corner of the first groove 200 needs to be arc-shaped, without steep sharp corners and more rounded, so as to reduce the probability of discharge at the edge corner tip of the first groove 200.
[0070] In some embodiments, a method for making the top edge corner of the first trench 200 arc-shaped includes: first forming the first trench 200, and sequentially forming a first dielectric layer 203 and a second dielectric layer 204 along the inner wall of the first trench 200, wherein the first dielectric layer 203 is also deposited on the upper surface of the substrate 201. Next, a photomask is formed on the upper surface of the first dielectric layer 203, and the photomask is patterned to expose the filler of the first trench 200 and a first portion of the first dielectric layer 203 disposed on the upper surface of the substrate 201, the first portion being distributed along the edge corner of the first trench 200. Then, along the area exposed by the patterned photomask, the filler of the first trench 200 and the first portion of the first dielectric layer 203 disposed on the upper surface of the substrate 201 are partially removed, thereby achieving the arc-shaped treatment of the edge corner of the first trench 200.
[0071] In this embodiment, the first dielectric layer 203 and the second dielectric layer 204 are made of different materials.
[0072] exist Figure 18 In the illustrated embodiment, the second dielectric layer 204 comprises only a single dielectric layer and does not comprise multiple separate sublayers. In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer, and the second dielectric layer 204 comprises a nitride dielectric layer.
[0073] During the arc-shaped processing, because the materials of the first dielectric layer 203 and the second dielectric layer 204 are different, the etching rate ratio of the etching gas or etching liquid on the first dielectric layer 203 and the second dielectric layer 204 also differs. Figure 3In the described embodiment, the etching rate of the selected etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate on the second dielectric layer 204, and the etching rate of the etching gas or etching liquid on the first dielectric layer 203 is greater than the etching rate on the substrate 201. After etching, the top height of the first dielectric layer 203 is lower than the top height of the second dielectric layer 204 and lower than the height of the upper surface of the substrate 201.
[0074] like Figure 12 As shown, the second dielectric layer 204 includes a first sublayer 205 and a second sublayer 206. The first sublayer 205 is formed on the surface of the first dielectric layer 203, and the second sublayer 206 is formed on the surface of the first sublayer 205 and fills the first trench 200.
[0075] In some embodiments, the first dielectric layer 203 comprises an oxide dielectric layer, the first sublayer 205 comprises a nitride dielectric layer, and the second sublayer 206 comprises an oxide dielectric layer. After etching, the top of the first sublayer 205 is higher than the top of the first dielectric layer 203 and also higher than the top of the second sublayer 206, thus the central region of the filler in the first trench 200 is recessed.
[0076] In some other embodiments, the specific material of the second dielectric layer 204 may also be set as needed.
[0077] The semiconductor memory structure further includes a fourth dielectric layer 209, which covers the inner wall of the first groove 202 and the upper surface of the substrate 201, and fills a portion of the space in the first groove 202. The fourth dielectric layer 209 is partially located between the metal filler layer 207 and the substrate 201, and can be used to isolate the electrical connection between the metal filler layer 207 and the substrate 201, preventing short circuits between them, thereby preventing electrical damage to the semiconductor memory structure due to the metal filler layer 207.
[0078] In some other embodiments, the semiconductor memory structure further includes an insulating layer 214 formed over the second dielectric layer 204, over the metal filling layer 207, and on the upper surface of the substrate 201. Specifically, it is distributed in a portion of the upper surface of the substrate 201 and is located near the first trench 200.
[0079] In some other embodiments, a third dielectric layer 208 is also formed above the metal filler layer 207, and the insulating layer 214 is also located on top of the third dielectric layer 208.
[0080] In some embodiments, the semiconductor memory structure further includes: a gate stack structure 300 formed on top of the substrate, and / or: a load stack structure 301 formed on top of the second dielectric layer.
[0081] In some embodiments, the gate stack structure 300 includes at least a first polysilicon layer 210, a first conductive layer 211, and a first mask layer 212 that are sequentially distributed upward along a direction perpendicular to the upper surface of the substrate 201, for forming connection lines.
[0082] In some other embodiments, the load stack structure 301 includes a second polysilicon layer 2101, a second conductive layer 2111, and a second mask layer 2121 sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate, as shown here. Figure 17 As shown.
[0083] In some embodiments, the first conductive layer 211 and the second conductive layer 2111 comprise at least one conductive material layer selected from copper, tungsten, titanium nitride, etc. Figure 12 In the illustrated embodiment, the first conductive layer 211 and / or the second conductive layer 2111 comprises only one conductive material, which may be a tungsten metal layer, a titanium nitride layer, or a copper layer. In some other embodiments, the first conductive layer 211 and / or the second conductive layer 2111 may also comprise two adjacent conductive material layers. In some embodiments, the conductive material layer closer to the substrate is a tungsten metal layer or a titanium nitride layer, and the conductive material layer farther from the substrate is a titanium nitride layer or a tungsten metal layer.
[0084] In some embodiments, the top of the first polysilicon layer 210 is flush with the top of the second polysilicon layer 2101, the top of the first conductive layer 211 is flush with the top of the second conductive layer 2111, and the tops of the first mask layer 212 and the second mask layer 2121 are flush.
[0085] In some embodiments, the material used to prepare the metal filling layer 207 is the same as the material used to prepare the first conductive layer 211. Therefore, the same set of metal deposition equipment and metal target can be used to prepare the metal filling layer 207 and the first conductive layer 211, reducing the difficulty of preparation.
[0086] In some embodiments, the metal filler layer 207 is formed using conductive materials such as titanium, tungsten, or titanium nitride. In practice, the specific materials used to prepare the first conductive layer 211 and the metal filler layer 207 can also be selected as needed.
[0087] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A semiconductor memory structure, characterized in that, include: Substrate; At least one first trench located on the upper surface of the substrate; A first dielectric layer is distributed along the inner wall of the first trench; The second dielectric layer is located on the surface of the first dielectric layer and fills the first trench; The top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate; A fourth dielectric layer covers the inner wall of the first groove and fills part of the space of the first groove. The fourth dielectric layer also covers the second dielectric layer. A load stack structure is located on the fourth dielectric layer and above the top of the second dielectric layer.
2. The semiconductor memory structure according to claim 1, characterized in that, Also includes: A metal filler layer is located within the first groove, filling a portion of the space within the first groove. The fourth dielectric layer is located between the metal filler layer and the substrate, serving to disconnect the electrical connection between the metal filler layer and the substrate.
3. The semiconductor memory structure according to claim 2, characterized in that, The third dielectric layer is located above the metal filler layer and within the first groove, filling the first groove.
4. The semiconductor memory structure according to claim 1, characterized in that, The second dielectric layer includes a first sublayer and a second sublayer, wherein the first sublayer is formed on the surface of the first dielectric layer, the second sublayer is formed on the surface of the first sublayer, and fills the first trench.
5. The semiconductor memory structure according to claim 1, characterized in that, The first dielectric layer includes an oxide dielectric layer; and / or, The second dielectric layer includes a nitride dielectric layer.
6. The semiconductor memory structure according to claim 4, characterized in that, The first sublayer includes a nitride dielectric layer, and the second sublayer includes an oxide dielectric layer.
7. The semiconductor memory structure according to claim 2, characterized in that, Also includes: A gate stack structure is formed on top of the substrate.
8. The semiconductor memory structure according to claim 7, characterized in that, The gate stack structure includes at least a first polysilicon layer, a first conductive layer, and a first mask layer sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate; and / or, The load stack structure includes a second polysilicon layer, a second conductive layer, and a second mask layer that are sequentially distributed upwards along a direction perpendicular to the upper surface of the substrate.
9. The semiconductor memory structure according to claim 8, characterized in that, The metal filler layer is made of the same material as the first conductive layer and the second conductive layer.
10. The semiconductor memory structure according to claim 1, characterized in that, The top edge corner of the first trench is arc-shaped.
11. A method for fabricating a semiconductor memory structure, characterized in that, Includes the following steps: A substrate is provided, wherein a first trench is formed on the upper surface of the substrate; A first dielectric material layer and a second dielectric material layer are sequentially formed along the inner wall of the first trench; The first dielectric material layer and the second dielectric material layer are partially removed, and a first dielectric layer and a second dielectric layer are formed accordingly, with the top of the first dielectric layer being lower than the top of the second dielectric layer and the upper surface of the substrate, thereby forming a first groove between the second dielectric layer and the substrate; A fourth dielectric layer is formed on the inner wall of the first groove, the fourth dielectric layer covers the inner wall of the first groove and fills part of the space of the first groove, and the fourth dielectric layer also covers the second dielectric layer; A load stack structure is formed on the fourth dielectric layer and above the second dielectric layer.
12. The preparation method according to claim 11, characterized in that, After the fourth dielectric layer is formed on the inner wall of the first groove, the following steps are also included: A metal filler layer is formed in the first groove to partially fill the first groove, and the fourth dielectric layer is located between the metal filler layer and the substrate.