A method for manufacturing a high-reliability silicon capacitor

Abstract

The application provides a high-reliability silicon capacitor manufacturing method, comprising the following steps: deep groove etching of a silicon substrate; depositing a dielectric layer on the surface of the deep groove and the surface of the silicon substrate outside the deep groove; filling polycrystalline silicon in the deep groove and on the surface of the silicon substrate outside the deep groove; removing the dielectric layer and the polycrystalline silicon on the surface by using a CMP process; depositing a layer of silicon oxide with a thickness not less than 0.5 microns on the surface; etching a through hole; depositing a layer of metal as an upper electrode on the surface; and depositing a layer of metal as a lower electrode on the bottom of the silicon substrate. The application grinds all the dielectric and poly layers on the plane by using the CMP process, and then deposits a layer of thick silicon oxide, which can significantly improve the service life of the silicon capacitor, significantly improve the working voltage under the same working condition, enhance the reliability, reduce the poly etching step, save the mask plate, reduce the photoetching, and save the cost.

Description

Technical Field

[0001] This invention relates to the field of silicon capacitor manufacturing technology, and in particular to a method for manufacturing a high-reliability silicon capacitor. Background Technology

[0002] Silicon capacitors typically feature deep trench structures to increase the relative area and thus improve capacitance. After deep trench etching, a dielectric layer is deposited on the inner wall of the trench and the surface of the silicon substrate as the capacitor's insulating layer. The uniformity and thickness of the dielectric layer directly affect the capacitor's withstand voltage and reliability. After dielectric layer deposition, a polysilicon conductive layer (poly fill) is filled into the deep trench, and then excess material is removed through a poly etching step to optimize the capacitor's electric field distribution and subsequent metal electrode contact. Traditional polysilicon etching uses wet etching, which mainly utilizes the reaction between the etching solution and the material to be etched to generate soluble or volatile products. Currently, the mainstream method is dry etching, which mainly achieves removal through the synergistic effect of gas reacting with polysilicon to generate volatile products and ion bombardment forming physical sputtering. However, both wet and dry etching inevitably over-etch into the dielectric layer, causing damage and significantly affecting reliability.

[0003] To address these issues, the etching process is typically optimized. This includes adjusting the gas formulation, using highly selective gases in conjunction with protective gases. Specifically, chlorine can be used to increase the etching rate, inert gases to enhance physical sputtering, and gases such as hydrogen bromide, perfluorocyclobutane, and trifluoromethane can be used to form a protective film on the dielectric layer surface, preventing further corrosion of the dielectric layer by the etching gases. This process can usually increase the polysilicon-to-silicon oxide selectivity ratio from the conventional 10-20:1 to over 50:1. However, the use of multiple gas combinations in this process leads to complex process parameter control, significantly increased raw material and equipment maintenance costs, and the protective film inevitably reduces the etching rate while protecting the dielectric layer. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a high-reliability silicon capacitor, so as to overcome the above-mentioned defects in the prior art.

[0005] This invention is achieved using the following technical solution: A method for manufacturing a high-reliability silicon capacitor includes the following steps: S1. Deep trench etching is performed on the silicon substrate; S2. Deposit the dielectric layer on the surface of the deep trench and on the surface of the silicon substrate outside the deep trench; S3. Fill the polycrystalline silicon inside the deep trench and on the surface of the silicon substrate outside the deep trench; S4. Use CMP process to remove the dielectric layer and polysilicon on the surface; S5. Deposit a layer of silicon oxide with a thickness of not less than 0.5 μm on the surface; S6. Perform through-hole etching; S7. Deposit a metal layer on the surface as the upper electrode; S8. A metal layer is deposited at the bottom of the silicon substrate as the lower electrode.

[0006] In this invention, there is no particular limitation on the specific process of deep trench etching. Various etching processes commonly used in the field can be adopted, such as, but not limited to, DRIE (Deep Reactive Ion Etching), ICPE (Inductively Coupled Plasma Etching), ECRE (Electron Cyclotron Resonance Etching), and CCPE (Capacitively Coupled Plasma Etching).

[0007] Furthermore, the silicon substrate mentioned in step S1 is a low-resistivity silicon wafer with a resistivity of 0.001~0.004 Ω·cm.

[0008] Furthermore, step S2 involves depositing a dielectric layer using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or thermal oxidation. The material of the dielectric layer is selected from at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide, preferably silicon oxide or silicon nitride. The thickness of the dielectric layer is preferably 0.5~1 μm.

[0009] Furthermore, step S3 involves filling the polycrystalline silicon using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or thermal oxidation. Preferably, the resistivity of the polycrystalline silicon is ≤0.003 Ω·cm.

[0010] Furthermore, the CMP mentioned in step S4, namely Chemical Mechanical Polishing, removes excess material such as polysilicon, silicon oxide, and silicon nitride from the wafer surface through the synergistic effect of chemical etching and mechanical abrasion, providing an ideal flat substrate for subsequent etching, deposition, and other processes. In this invention, conventional CMP processes in the art can be used to remove the dielectric layer and polysilicon on the surface.

[0011] Furthermore, in step S5, a silicon oxide layer is deposited using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or thermal oxidation, with a thickness preferably of 0.5-2 μm, more preferably 1-2 μm.

[0012] Furthermore, step S6 employs the ICPE method for through-hole etching.

[0013] Furthermore, in step S7, the upper electrode metal is selected from one or both of aluminum or gold, and the thickness of the upper electrode metal layer is 0.5-10 μm.

[0014] Furthermore, the lower electrode metal in step S8 is selected from at least one of titanium, nickel, gold, and silver, and the thickness of the lower electrode metal layer is 0.5-2 μm.

[0015] The inventors discovered that after poly filling, removing the dielectric layer and poly layer on the upper plane of the deep trench using CMP (Chemical Metallurgy) followed by the deposition of a thick silicon oxide layer can significantly improve the lifespan of silicon capacitors. Under the same operating conditions, it can also significantly increase the operating voltage and enhance reliability. The specific reason is speculated to be that CMP avoids damage to the underlying dielectric layer caused by poly edge etching. Furthermore, the effective cleaning after CMP yields an extremely clean surface, reducing random defects such as pinholes in the dielectric layer and electrode short circuits caused by particles, thus improving reliability. The inventors completed this invention based on the above findings.

[0016] This invention is applicable to double-layer poly silicon capacitors, and the method for manufacturing the high-reliability silicon capacitor includes the following steps: S1. Deep trench etching is performed on the silicon substrate; S2a. A first dielectric layer is formed by depositing a dielectric layer on the surface of the deep trench and on the surface of the silicon substrate outside the deep trench. S3a. Deposit polysilicon on the surface of the first dielectric layer to form a first polysilicon layer; S2b, Deposit a dielectric layer on the surface of the first polysilicon layer to form a second dielectric layer; S3b: Fill polysilicon into the deep trench and the surface of the second dielectric layer outside the deep trench; S4. Use CMP process to remove the dielectric layer and polysilicon on the surface; S5. Deposit a layer of silicon oxide with a thickness of not less than 0.5 μm on the surface; S6. Perform through-hole etching; S7. Deposit a metal layer on the surface as the upper electrode; S8. A metal layer is deposited at the bottom of the silicon substrate as the lower electrode.

[0017] The deposition methods in steps S2a and S2b are the same as those in step S2, and the deposition / filling methods in steps S3a and S3b are the same as those in step S3.

[0018] Preferably, the thickness of the first dielectric layer is 0.05-0.5 μm, the thickness of the first polycrystalline silicon layer is 0.2-1 μm, and the thickness of the second dielectric layer is 0.05-0.5 μm.

[0019] This invention is also applicable to three-layer poly silicon capacitors, and the method for manufacturing the high-reliability silicon capacitor includes the following steps: S1. Deep trench etching is performed on the silicon substrate; S2a. A first dielectric layer is formed by depositing a dielectric layer on the surface of the deep trench and on the surface of the silicon substrate outside the deep trench. S3a. Deposit polysilicon on the surface of the first dielectric layer to form a first polysilicon layer; S2b, Deposit a dielectric layer on the surface of the first polysilicon layer to form a second dielectric layer; S3b: Deposit polysilicon onto the surface of the second dielectric layer to form a second polysilicon layer; S2c, Deposit a dielectric layer on the surface of the second polysilicon layer to form a third dielectric layer; S3c, fill polysilicon into the deep trench and the surface of the third dielectric layer outside the deep trench; S4. Use CMP process to remove the dielectric layer and polysilicon on the surface; S5. Deposit a layer of silicon oxide with a thickness of not less than 0.5 μm on the surface; S6. Perform through-hole etching; S7. Deposit a metal layer on the surface as the upper electrode; S8. A metal layer is deposited at the bottom of the silicon substrate as the lower electrode.

[0020] The deposition methods in steps S2a, S2b, and S2c are the same as those in step S2, and the deposition / filling methods in steps S3a, S3b, and S3c are the same as those in step S3.

[0021] Preferably, the thickness of the first dielectric layer is 0.05-0.5 μm, the thickness of the first polysilicon layer is 0.2-1 μm, the thickness of the second dielectric layer is 0.05-0.5 μm, the thickness of the second polysilicon layer is 0.2-1 μm, and the thickness of the third dielectric layer is 0.05-0.5 μm.

[0022] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention uses CMP process to grind all planar dielectric and poly layers flat, which can reduce poly etching steps, save on photomasks, reduce photolithography, and save costs.

[0023] 2. In this invention, after CMP grinding of the surface, the breakdown voltage is determined by the dielectric thickness of the deep trench sidewall. Because the dielectric thickness of the deep trench sidewall is uniform, the withstand voltage is stable, and the increased thick silicon oxide significantly improves reliability. While the planar thick silicon oxide will reduce the capacitance slightly, the planar area is negligible compared to the area inside the deep trench. The improved silicon capacitor has a significantly longer lifespan. Attached Figure Description

[0024] Figure 1 This is a schematic diagram illustrating the fabrication steps of the single-layer poly silicon capacitor of the present invention, wherein... Figure 1 'a' represents etching a deep trench on a silicon substrate. Figure 1 b represents the deposition medium layer. Figure 1 c represents filled polycrystalline silicon. Figure 1 d represents CMP removal of the surface dielectric layer and polysilicon. Figure 1 e represents a thick layer of deposited silicon oxide. Figure 1 f represents the etched through-hole. Figure 1 g represents the deposition of a metal layer to form the upper electrode. Figure 1 h represents the deposition of a metal layer to form the lower electrode.

[0025] Figure 2 This is a schematic diagram illustrating the fabrication steps of the double-layer poly silicon capacitor of the present invention, wherein... Figure 2 'a' represents etching a deep trench on a silicon substrate. Figure 2 b represents the first deposition medium layer. Figure 2 c represents the deposition of the first polycrystalline silicon layer. Figure 2 d represents the deposition of the second medium layer. Figure 2 e represents filled polycrystalline silicon. Figure 2 f represents CMP removal of the surface dielectric layer and polysilicon. Figure 2 g represents a thick deposit of silicon oxide. Figure 2 h represents an etched through-hole. Figure 2 i represents the deposition of a metal layer to form the upper electrode. Figure 2 j represents the deposition of a metal layer to form the lower electrode.

[0026] Figure 3 This is a schematic diagram illustrating the fabrication steps of the three-layer poly silicon capacitor of the present invention, wherein... Figure 3 'a' represents etching a deep trench on a silicon substrate. Figure 3 b represents the first deposition medium layer. Figure 3 c represents the deposition of the first polycrystalline silicon layer. Figure 3 d represents the deposition of the second medium layer. Figure 3 e represents the deposition of a second polycrystalline silicon layer. Figure 3 f represents the deposition of the third medium layer. Figure 3 g represents filled polycrystalline silicon. Figure 3 h represents CMP removal of the surface dielectric layer and polysilicon. Figure 3 i represents the deposition of thick silicon oxide. Figure 3 j represents an etched through-hole. Figure 3 k deposited metal layer forms the upper electrode Figure 3 A metal layer is deposited to form the lower electrode.

[0027] Figure 4 This is a lifespan curve of the silicon capacitor manufactured in Embodiment 1 of the present invention under different temperatures and pressures.

[0028] Figure 5 This is a graph showing the lifespan of a silicon capacitor fabricated on a scale under different temperatures and pressures.

[0029] In the figure, 1-silicon substrate, 2-dielectric layer, 21-first dielectric layer, 22-second dielectric layer, 23-third dielectric layer, 3-polycrystalline silicon, 31-first polycrystalline silicon layer, 32-second polycrystalline silicon layer, 4-thick silicon oxide, 5-upper electrode, 6-lower electrode. Detailed Implementation

[0030] The following description is provided to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples and are not intended to limit the scope of the invention; other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0031] Unless otherwise specified, all instruments and materials used in this invention are conventional commercial instruments or materials. The silicon substrate used is a low-resistivity silicon wafer with a resistivity of 0.002 Ω·cm.

[0032] Unless otherwise mentioned, all detection indicators involved in this invention are tested using conventional detection methods in the art. The lifespan of the silicon capacitors was determined using a TDDB lifespan experiment, with the lifespan curve obtained through fitting. Specific experimental conditions were as follows: voltage: 105V, 110V, 115V; temperature: 140℃, 145℃, 150℃. Nine groups of samples were tested under each voltage and temperature condition.

[0033] Example 1 like Figure 1 As shown, the method for fabricating the single-layer poly silicon capacitor of the present invention is as follows: (1) A low-resistivity silicon wafer is used as one electrode of the capacitor, and a deep trench is etched on the silicon substrate using DRIE. (2) A silicon oxide dielectric layer with a thickness of 0.1 μm is deposited on the surface of the deep trench and the surface of the silicon substrate outside the deep trench using a low-pressure chemical vapor deposition method. (3) Polycrystalline silicon is filled in the deep trench and on the surface of the dielectric layer outside the deep trench using low-pressure chemical vapor deposition. (4) The planar dielectric layer and polysilicon are removed using CMP process; (5) Deposit a 1µm layer of silicon oxide on the surface; (6) Etching through holes; (7) A metal layer is deposited on the surface as the upper electrode. The upper electrode metal is aluminum and the electrode thickness is 3 μm.

[0034] (8) A metal layer is deposited at the bottom of the silicon substrate as the lower electrode. The lower electrode metal is Ti / Ni / Ag=1:3:7 (thickness ratio) and the thickness of the lower electrode metal is 0.5um.

[0035] The lifespan of the fabricated silicon capacitors was tested under different voltage and temperature conditions. See the detailed results below. Figure 4 See Table 1.

[0036] Table 1. Lifespan of silicon capacitors in Example 1 under different temperature and voltage conditions. Example 2 like Figure 2 As shown, the fabrication method of the double-layer poly silicon capacitor of the present invention is as follows: (1) A low-resistivity silicon wafer is used as one electrode of the capacitor, and a deep trench is etched on the silicon substrate using DRIE. (2) A first dielectric layer with a thickness of 0.1 μm is formed by depositing a silicon oxide dielectric layer on the surface of the deep trench and the surface of the silicon substrate outside the deep trench using a low-pressure chemical vapor deposition method; (3) Polycrystalline silicon is deposited on the surface of the first dielectric layer using low-pressure chemical vapor deposition to form a first polycrystalline silicon layer with a thickness of 0.5 μm; (4) A second dielectric layer with a thickness of 0.1 μm is formed by depositing a silicon oxide dielectric layer on the surface of the first polysilicon layer using a low-pressure chemical vapor deposition method; (5) Polycrystalline silicon is filled in the deep trench and on the surface of the second dielectric layer outside the deep trench using low-pressure chemical vapor deposition. (6) All dielectric layers and polysilicon in the plane are removed using CMP process; (7) A 1.5 μm layer of silicon oxide is deposited on the surface; (8) Etching through holes; (9) A metal layer is deposited on the surface as the top electrode. The metal of the top electrode is gold, and the electrode thickness is 5 μm. (10) A metal layer is deposited at the bottom of the silicon substrate as the lower electrode. The lower electrode metal is Ti / Ni / Au=1:3:1 (thickness ratio) and the thickness of the lower electrode metal is 1um.

[0037] Example 3 like Figure 3 As shown, the fabrication method of the three-layer poly silicon capacitor of the present invention is as follows: (1) A low-resistivity silicon wafer is used as one electrode of the capacitor, and a deep trench is etched on the silicon substrate using DRIE. (2) A first dielectric layer with a thickness of 0.1 μm is formed by depositing a silicon oxide dielectric layer on the surface of the deep trench and the surface of the silicon substrate outside the deep trench using a low-pressure chemical vapor deposition method; (3) Polycrystalline silicon is deposited on the surface of the first dielectric layer using low-pressure chemical vapor deposition to form a first polycrystalline silicon layer with a thickness of 0.5 μm; (4) A second dielectric layer with a thickness of 0.1 μm is formed by depositing a silicon oxide dielectric layer on the surface of the first polysilicon layer using a low-pressure chemical vapor deposition method; (5) Polycrystalline silicon is deposited on the surface of the second dielectric layer using low-pressure chemical vapor deposition to form a second polycrystalline silicon layer with a thickness of 0.5 μm; (6) A silicon oxide dielectric layer is deposited on the surface of the second polysilicon layer using low-pressure chemical vapor deposition to form a third dielectric layer with a thickness of 0.1 μm; (7) Polycrystalline silicon is filled in the deep trench and on the surface of the third dielectric layer outside the deep trench using low-pressure chemical vapor deposition. (8) Remove all dielectric layers and polysilicon from the plane using CMP process; (9) Deposit a 2µm layer of silicon oxide on the surface; (10) Etching through holes; (11) A metal layer is deposited on the surface as the top electrode. The metal of the top electrode is gold, and the electrode thickness is 8 μm.

[0038] (12) A metal layer is deposited at the bottom of the silicon substrate as the lower electrode. The lower electrode metal is Ti / Ni / Au=1:3:1 (thickness ratio) and the thickness of the lower electrode metal is 0.5um.

[0039] Comparative Example Compared to Example 1, steps 4 and 5 are omitted, i.e., CMP is not used to remove the planar dielectric layer and polysilicon, nor is the subsequent thick oxide deposition performed. Otherwise, the process is the same as in Example 1. The specific fabrication method is as follows: (1) A low-resistivity silicon wafer is used as one electrode of the capacitor, and a deep trench is etched on the silicon substrate using DRIE. (2) A silicon oxide dielectric layer with a thickness of 0.1 μm is deposited on the surface of the deep trench and the surface of the silicon substrate outside the deep trench using a low-pressure chemical vapor deposition method. (3) Polycrystalline silicon is filled in the deep trench and on the surface of the dielectric layer outside the deep trench using chemical vapor deposition. (4) Etching through holes; (5) A metal layer is deposited on the surface as the upper electrode. The upper electrode metal is aluminum and the electrode thickness is 3 μm.

[0040] (6) A metal layer is deposited at the bottom of the silicon substrate as the lower electrode. The lower electrode metal is Ti / Ni / Ag=1:3:7 (thickness ratio) and the thickness of the lower electrode metal is 0.5um.

[0041] The lifespan of the fabricated silicon capacitors was tested under different voltage and temperature conditions. See the detailed results below. Figure 5And Table 2.

[0042] Table 2. Lifespan of comparative silicon capacitors under different temperature and voltage conditions from Figure 4 , Figure 5 A comparison of the data in Tables 1 and 2 shows that the present invention can greatly improve the lifespan of the chip. For example, under the original process, the chip can only work for 10 years at a working voltage of 33.9V at 100℃. However, under the same 100℃ environment, the chip of the present invention can work at a working voltage of 56.2V for ten years, which is a significant improvement in the operating voltage and a great improvement in the lifespan under the same working voltage.

[0043] Those skilled in the art should understand that the above embodiments are merely examples and do not limit the invention. The objectives of the invention have been fully and effectively achieved. The functions and structural principles of the invention have been shown and explained in the embodiments, and any variations or modifications can be made to the implementation of the invention without departing from the stated principles.

Claims

1. A method for manufacturing a high-reliability silicon capacitor, characterized in that, Includes the following steps: S1. Deep trench etching is performed on the silicon substrate; S2. Deposit the dielectric layer on the surface of the deep trench and on the surface of the silicon substrate outside the deep trench; S3. Fill the deep trench and the surface of the dielectric layer outside the deep trench with polysilicon; S4. Use CMP process to remove the dielectric layer and polysilicon on the surface; S5. Deposit a layer of silicon oxide with a thickness of not less than 0.5 μm on the surface; S6. Perform through-hole etching; S7. Deposit a metal layer on the surface as the upper electrode; S8. A metal layer is deposited at the bottom of the silicon substrate as the lower electrode.

2. The method as described in claim 1, characterized in that, The silicon substrate mentioned in step S1 is a low-resistivity silicon wafer with a resistivity of 0.001~0.004 Ω·cm.

3. The method as described in claim 1, characterized in that, Step S2 involves depositing a dielectric layer using low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or thermal oxidation.

4. The method as described in claim 1, characterized in that, The material of the dielectric layer is selected from at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide, and the thickness of the dielectric layer is 0.5~1μm.

5. The method as described in claim 1, characterized in that, Step S3 involves filling polycrystalline silicon using chemical vapor deposition, physical vapor deposition, or thermal oxidation filling methods, wherein the resistivity of the polycrystalline silicon is ≤0.003Ω·cm.

6. The method as described in claim 1, characterized in that, Step S5 involves depositing a silicon oxide layer with a thickness of 1-2 μm using low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or thermal oxidation.

7. The method as described in claim 1, characterized in that, The upper electrode metal in step S7 is selected from one or both of aluminum or gold, and the thickness of the upper electrode metal layer is 0.5-10 μm.

8. The method as described in claim 1, characterized in that, The lower electrode metal in step S8 is selected from at least one of titanium, nickel, gold, and silver, and the thickness of the lower electrode metal layer is 0.5-2 μm.

9. The method according to any one of claims 1-8, characterized in that, Includes the following steps: S1. Deep trench etching is performed on the silicon substrate; S2a. A first dielectric layer is formed by depositing a dielectric layer on the surface of the deep trench and on the surface of the silicon substrate outside the deep trench. S3a. Deposit polysilicon on the surface of the first dielectric layer to form a first polysilicon layer; S2b, Deposit a dielectric layer on the surface of the first polysilicon layer to form a second dielectric layer; S3b: Fill polysilicon into the deep trench and the surface of the second dielectric layer outside the deep trench; S4. Use CMP process to remove the dielectric layer and polysilicon on the surface; S5. Deposit a layer of silicon oxide with a thickness of not less than 0.5 μm on the surface; S6. Perform through-hole etching; S7. Deposit a metal layer on the surface as the upper electrode; S8. A metal layer is deposited at the bottom of the silicon substrate as the lower electrode.

10. The method according to any one of claims 1-8, characterized in that, Includes the following steps: S1. Deep trench etching is performed on the silicon substrate; S2a. A first dielectric layer is formed by depositing a dielectric layer on the surface of the deep trench and on the surface of the silicon substrate outside the deep trench. S3a. Deposit polysilicon on the surface of the first dielectric layer to form a first polysilicon layer; S2b, Deposit a dielectric layer on the surface of the first polysilicon layer to form a second dielectric layer; S3b: Deposit polysilicon onto the surface of the second dielectric layer to form a second polysilicon layer; S2c, Deposit a dielectric layer on the surface of the second polysilicon layer to form a third dielectric layer; S3c, fill polysilicon into the deep trench and the surface of the third dielectric layer outside the deep trench; S4. Use CMP process to remove the dielectric layer and polysilicon on the surface; S5. Deposit a layer of silicon oxide with a thickness of not less than 0.5 μm on the surface; S6. Perform through-hole etching; S7. Deposit a metal layer on the surface as the upper electrode; S8. A metal layer is deposited at the bottom of the silicon substrate as the lower electrode.

Images