Metal substrate power device package

Abstract

A metal substrate power device package comprises a power transistor wafer, a drain electrode bonding pad is arranged on the bottom surface of the power transistor wafer, and a source electrode bonding pad and a switch control electrode bonding pad are arranged on the top surface of the power transistor wafer; the power transistor further comprises an L-shaped metal substrate, the thickness of one side of the L-shaped metal substrate is small, and the power transistor wafer is welded to the top face of the side, with the small thickness, of the L-shaped metal substrate through a drain electrode bonding pad. The insulating rubber material is filled around the power transistor wafer horizontally. The L-shaped metal substrate is simultaneously used as a drain electrode conductive pole piece of the power transistor wafer, a packaged drain electrode bonding pad, a packaged cooling fin and a packaged substrate; and high-power transistor packaging with high cost performance is realized.

Description

Technical Field

[0001] This invention relates to the optimization of packaging processes and chip heat dissipation processes and architecture design for power devices, and to packaging technologies for silicon-based transistors, third-generation and fourth-generation semiconductor transistors. Background Technology

[0002] Power transistors (such as MOSFETs, high electron mobility transistors (HEMTs), and IGBTs) are widely used in high-power electronic devices, such as power management modules, electric vehicle drive systems, and industrial motor control.

[0003] Third-generation semiconductor materials GaN (gallium nitride) and SiC (silicon carbide) are representative of wide-bandgap semiconductors. Power devices made of gallium nitride have significant advantages such as fast switching speed, low on-resistance, and small chip area, and are widely used in power adapters, industrial power supplies, and automotive electronics.

[0004] Fourth-generation semiconductor materials, mainly represented by diamond and gallium oxide, have begun to be used in ultra-wide bandgap power devices; power devices made from them can also operate at higher temperatures.

[0005] Traditional power transistor packages typically employ complex lead frames and metal clip structures to achieve electrical connections between the source, gate, and drain. However, this packaging method suffers from the following problems: Complex manufacturing process, requiring additional metal clips and soldering steps, increasing manufacturing costs and time; Large size, with traditional packaging structures occupying a significant amount of space, making it difficult to meet the miniaturization requirements of modern electronic devices; Limited heat dissipation performance, with long heat dissipation paths in traditional packages resulting in high thermal resistance, affecting device performance. Summary of the Invention

[0006] To address the aforementioned issues, this invention proposes a power transistor packaging structure based on an L-shaped metal substrate, which simplifies the packaging process, improves heat dissipation performance, and reduces manufacturing costs.

[0007] To achieve this technical objective, the present invention provides a metal substrate power device package, including a power transistor wafer. The power transistors include MOSFETs, high electron mobility transistors (HEMTs), and IGBTs. The bottom surface of the power transistor wafer has drain pads, and the top surface has source pads and switch control pads. The pads on the wafer are made of solderable materials used in surface mount technology (SMT) manufacturing of electronic products and can be achieved using chemical plating or copper bumping processes. In existing wafer mass production processes, these wafer pad processing techniques belong to wafer-level chip packaging (WLCSP) processes. The package also includes an L-shaped metal substrate, which can be fabricated using CNC machining or etching processes. One side of the L-shaped metal substrate is thinner. The power transistor wafer is soldered to the top surface of the thinner side of the L-shaped metal substrate via drain pads. The top surface of the power transistor wafer is connected to the L-shaped substrate... The top surface of the thicker side of the L-shaped metal substrate is flush with the top surface of the L-shaped metal substrate, which is connected to the drain signal of the power transistor wafer and serves as the drain pad for the finished package. The source pads and switch control pads on the top surface of the power transistor wafer serve as the source pads and switch control pads for the finished package. The package also includes an insulating filler, which is applied to the top surface of the thinner side of the L-shaped metal substrate and around the horizontal perimeter of the power transistor wafer to protect it. The insulating filler can be epoxy resin or PI engineering plastic (polyimide). To achieve mass production, the L-shaped metal substrate needs to be fabricated into a connecting plate consisting of multiple L-shaped metal substrates. After the insulating filler is applied, the connecting plate is cut into individual small packages.

[0008] Preferably, the power transistor wafer is a group of two or more transistor wafers, which are respectively soldered to the top surface of the thinner side of the L-shaped metal substrate via drain pads. The group of transistor wafers are packaged in the same package, and their drains are electrically connected; the finished transistor package can be used as a transistor to expand current carrying capacity, or as a high-side circuit in a bridge circuit.

[0009] The beneficial effects of this technical solution are: It simplifies the packaging process by directly connecting the drain pad via an L-shaped metal substrate, eliminating the need for metal clips and complex soldering steps in traditional packaging, thus reducing manufacturing costs. It improves heat dissipation performance, as the L-shaped metal substrate can directly contact an external heat sink, shortening the heat dissipation path, reducing thermal resistance, and improving the device's thermal management capabilities. Its miniaturized design and compact packaging structure make it suitable for high-density electronic devices. It is compatible with wafer-level packaging technology, facilitating large-scale production. Attached Figure Description

[0010] Figure 1This is a cross-sectional schematic diagram of a specific embodiment of the present invention.

[0011] Figure 2 This is a top view of a power transistor wafer according to a specific embodiment of the present invention.

[0012] Figure 3 This is a bottom view of a power transistor wafer according to a specific embodiment of the present invention.

[0013] Figure 4 This is a top view of the packaged structure according to a specific embodiment of the present invention.

[0014] Figure 5 This is a bottom view of the packaged structure according to a specific embodiment of the present invention.

[0015] Figure 6 This is a top view of a mass production connecting plate according to a specific embodiment two of the present invention.

[0016] Figure 7 This is a cross-sectional schematic diagram of the mass production connecting plate according to a specific embodiment two of the present invention.

[0017] Figure 8 This is a top view of a group of power transistor wafers within the same package, according to a specific embodiment three of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0019] like Figure 1 The diagram shown is a cross-sectional view of a specific embodiment of the present invention. A metal substrate power device package includes a power transistor wafer 1. The bottom surface of the power transistor wafer 1 has a drain pad 11, and the top surface of the power transistor wafer 1 has a source pad 12 and a switching control pad 13. The thickness of the power transistor wafer 1 is 0.3 mm. It also includes an L-shaped metal substrate 2. The L-shaped metal substrate 2 is a copper substrate. The thickness of the thicker side 21 of the L-shaped metal substrate 2 is 1 mm, and the thickness of the thinner side 22 is 0.7 mm. The power transistor wafer 1 is soldered to the top surface of the thinner side 22 of the L-shaped metal substrate 2 through the drain pad 11. The top surface of the power transistor wafer 1 is flush with the top surface of the thicker side 21 of the L-shaped metal substrate 2. The source pad 12 and the switch control electrode pad 13 arranged on the top surface of the thicker side 21 of the L-shaped metal substrate 2 and the top surface of the power transistor wafer 1 serve as the drain pad, source pad, and switch control electrode pad for packaging. It also includes an insulating filler 3, which is made of PI engineering plastic. The insulating filler 3 is filled on the top surface of the thinner side 22 of the L-shaped metal substrate 2 and coated on the horizontal periphery of the power transistor wafer 1.

[0020] like Figure 2The image shown is a top view of a power transistor wafer according to a specific embodiment of the present invention. The top surface of the power transistor wafer 1 is provided with source pads 12 and switch control pads 13.

[0021] like Figure 3 The image shown is a bottom view of a power transistor wafer according to a specific embodiment of the present invention. Drain pads 11 are arranged on the bottom surface of the power transistor wafer 1.

[0022] The source and drain pads of a vertical power transistor wafer are located on the top and bottom sides of the wafer, respectively.

[0023] like Figure 4 The image shown is a top view of the packaged structure according to a specific embodiment of the present invention.

[0024] The source pad 12 and the switch control electrode pad 13 arranged on the top surface 211 of the thicker side of the L-shaped metal substrate 2 and the top surface of the power transistor wafer 1 serve as the drain pad, source pad, and switch control electrode pad for packaging. Insulating filler 3 is filled on the top surface of the thinner side 22 of the L-shaped metal substrate 2 and coated on the horizontal periphery of the power transistor wafer 1.

[0025] like Figure 5 The image shown is a bottom view of a specific embodiment of the package of the present invention. The bottom surface of the package is the bottom surface 232 of the L-shaped metal substrate 2. After the power transistor of this package is soldered onto the circuit board, the bottom surface 232 can directly contact the external heat sink, shortening the heat dissipation path and reducing thermal resistance.

[0026] like Figure 6 The image shown is a top view of a mass-produced interconnect board according to a specific embodiment two of the present invention. The interconnect board consists of two rows and three columns of individual unit packages. A group of six power transistor wafers (1-1 to 1-6) are soldered to the metal substrate interconnect board, which includes six L-shaped metal substrate units, via wafer drain pads. After insulating filler is applied to the horizontal perimeter of the group of six power transistor wafers (1-1 to 1-6), transverse cuts are made along line X-1 and longitudinal cuts are made along lines Y-1 and Y-2 to cut the interconnect board into individual packages, enabling mass production. During production, process edges need to be added to the metal substrate interconnect board according to equipment and production line parameters to facilitate production.

[0027] like Figure 7The diagram shown is a cross-sectional schematic of a mass production interconnect board according to a specific embodiment of the present invention. It is a cross-sectional view of the first row of individual packages on the interconnect board; it includes three power transistor wafers 1-1, 1-2, and 1-3; and three L-shaped metal substrates 2-1, 2-2, and 2-3 connected together. The power transistor wafers 1-1, 1-2, and 1-3 are respectively soldered to the top surface of the thinner side of the L-shaped metal substrates 2-1, 2-2, and 2-3 via drain pads. Insulating filler materials 3-1, 3-2, and 3-3 are filled around the horizontal perimeter of the power transistor wafers 1-1, 1-2, and 1-3. After filling, the wafers are longitudinally cut along lines Y-1 and Y-2 to obtain batches of individual packages.

[0028] like Figure 8 The image shows a top view of a group of power transistor wafers within the same package according to a specific embodiment three of the present invention. A single package includes three power transistor wafers 1-1, 1-2, and 1-3; it includes an L-shaped metal substrate 2. Power transistor wafers 1-1, 1-2, and 1-3 are respectively soldered to the top surface of the side with the smaller thickness of the L-shaped metal substrate 2 via drain pads. Insulating filler is filled around the horizontal perimeter of power transistor wafers 1-1, 1-2, and 1-3. The top surface 211 of the side with the larger thickness of the L-shaped metal substrate 2 serves as the drain pad for the package, which is the parallel drain pad for power transistor wafers 1-1, 1-2, and 1-3. The power transistors in this package can be used as parallel transistors or as the high-side circuit of a bridge circuit.

[0029] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any minor modifications, equivalent substitutions, and improvements made to the above embodiments based on the technical essence of the present invention should be included within the protection scope of the present invention.

Claims

1. A metal substrate power device package, characterized in that: The device includes a power transistor wafer, with a drain pad on the bottom surface and a source pad and a switch control pad on the top surface; it also includes an L-shaped metal substrate, one side of which is thinner, and the power transistor wafer is soldered to the top surface of the thinner side of the L-shaped metal substrate via the drain pad, with the top surface of the power transistor wafer flush with the top surface of the thicker side of the L-shaped metal substrate; and it also includes an insulating filler, which fills the top surface of the thinner side of the L-shaped metal substrate and the horizontal perimeter of the power transistor wafer.

2. The metal substrate power device package according to claim 1, characterized in that: The power transistor wafer is a group of two or more transistor wafers, which are respectively soldered to the top surface of the thinner side of the L-shaped metal substrate through drain pads.

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