Semiconductor package and semiconductor package assembly with edge side

Abstract

The invention discloses a semiconductor package with edge-side interconnects and a semiconductor package assembly and a method of forming the same. An integrated circuit (IC) stack includes: a plurality of integrated circuit (IC) structures horizontally separated from each other, where each IC structure includes a top surface, a bottom surface opposite the top surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any side wall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upwardly extending thermally conductive layer between two adjacent IC structures.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device having side-edge interconnects and a method of forming the same. Background Technology

[0002] Thanks to significant advancements in engineering and materials science, the scaling of conventional transistors in two-dimensional (2D) geometry has made tremendous progress, involving extremely complex multi-step lithography patterning, novel strain-enhancing materials, and metal-oxide gates. However, as these technologies approach their practical limits, 2D device scaling is losing momentum. Three-dimensional integrated circuit (3D IC) integration, representing a radical departure from traditional 2D IC integration, is widely recognized as the next-generation semiconductor technology that simultaneously achieves high performance, low power consumption, small physical size, and high integration density. 3D ICs offer a pathway to continuously meet the performance and cost requirements of next-generation devices, while still allowing for more flexible gate lengths and lower process complexity for advanced applications such as high-performance computing (HPC), data centers, and artificial intelligence (AI).

[0003] 3D IC integration can be achieved through the following methods:

[0004] - Monolithic integration, and / or

[0005] - Vertical integration of completely different chips.

[0006] 3D monolithic integration typically involves the vertical integration of multiple active silicon layers and vertical interconnects between them. Recently, a 3D IC structure featuring a "CPU-on-high-speed cache memory" has been demonstrated and commercialized using copper hybrid bonding technology. Currently, high-bandwidth memory (HBM) dynamic random-access memory (DRAM) stacks (each created by vertically integrating several DRAM chips onto a control IC) represent the highest capacity commercially available 3D ICs. These HBM DRAM stacks are typically mounted side-by-side with the processor IC in a 2.5D IC package. Figure 1A2.5D ICs are used for high-end applications such as HPC, data centers, and AI on silicon interposers. 2.5D ICs typically contain through-silicon vias (TSVs) in active wafers, such as DRAM and control ICs, and in silicon interposers that can be passive or active. 2.5D ICs may also contain redistribution layers (RDLs) in the interposers and active wafers. For example, ChatGPT is driven by an NVIDIA H100 GPU in a 2.5D IC configuration. Looking ahead, 3D ICs can utilize interconnect technologies to implement memory-on-memory, logic-on-memory, and logic-on-logic structures. Interconnect technologies include TSVs, RDLs with interconnect wiring and microvias, flip-chip bonding based on copper pillar microbumps or solder bumps, and emerging copper hybrid bonding technologies. 3D ICs resulting from monolithic integration and / or heterogeneous integration allow for the vertical stacking of heterogeneous wafers and / or active silicon layers from different processes and nodes, wafer / wafer reuse, and wafers in SiP (System-in-Package). Finally, 3D IC integration will enable HBM DRAM stacking on top of the processor, significantly reducing data transfer time between DRAM chips and the processor and greatly reducing peak computing memory bandwidth gaps. 3D ICs are well-suited for applications requiring more transistors to be integrated within a given coverage area (e.g., mobile system-on-a-chip, SoC) or applications that have already pushed the limits of single-chip capacity at state-of-the-art nodes, such as HPC, data centers, AI / machine learning, 5G / 6G networks, graphics, smartphones / wearables, automotive, and other applications requiring ultra-high performance and energy efficiency. These devices include CPUs, GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), TPUs (Tensor Processing Units), integrated photonics, APs (Application Processors), packet buffer / router devices, and the like.

[0007] To accelerate adoption, 3D IC systems must be designed holistically through IC packaging system co-design, involving silicon IP, IC / diegetic chips, and IC packaging, while addressing the associated power and thermal challenges. Compared to PPAC (performance, power, area, and cost) optimization per square centimeter used in 2D packaging, 3D IC IC packaging system co-design aims for "PPAC optimization per cubic millimeter," where all trade-off decisions must comprehensively consider the vertical dimensions covering the IC, interposers, IC packaging substrate, IC package, and system printed circuit board (PCB).

[0008] Currently, all 3D ICs employ packaging topologies with single-sided electrical interconnects, such as from the bottom side of the control IC (connected to the interposer) in an HBM DRAM stack to the DRAM chip on top of the control IC, or from the laminate to the bottom side of the CPU in the high-speed cache on the CPU. When powering a 3D IC that relies on single-sided interconnects, designers must consider all stacked layers when designing the power delivery network. The topmost chip receives power from the chip below it, the chip below that receives power from the chip immediately below it, and so on. The bottom chip and processor chip receive power from the 2.5D interposer, which in turn receives power from the laminate, which in turn receives power from the PCB. Single-sided interconnects are not scalable because the 3D IC coverage area does not change with the number of chips vertically implemented. For example, in an HBM DRAM stack, the number of chips in the stack increases from 5 in HBM1 to 13 in HBM3. Single-sided electrical interconnects impose severe limitations on PPAC optimization for 3D ICs. Summary of the Invention

[0009] One embodiment of this disclosure provides an IC stack comprising: a plurality of horizontally separated integrated circuit (IC) structures, wherein each IC structure includes a top surface, a bottom surface opposite to the top surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of ​​the bottom surface or the top surface is greater than the area of ​​any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upwardly extending thermally conductive layer between two adjacent IC structures.

[0010] Other embodiments of this disclosure provide an IC stack comprising: a plurality of horizontally separated integrated circuit (IC) structures, wherein each IC structure includes a top surface, a bottom surface opposite the top surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of ​​the bottom surface or the top surface is greater than the area of ​​any of the four sidewalls; a set of upwardly extending thermal conductive layers, wherein corresponding upwardly extending thermal conductive layers are disposed between any two adjacent IC structures of the plurality of IC structures; and a first laterally extending thermal conductive layer covering each second sidewall of the plurality of IC structures and thermally coupled to the set of upwardly extending thermal conductive layers.

[0011] Another embodiment of this disclosure provides an IC stack comprising: a plurality of horizontally separated semiconductor structures, each semiconductor structure having a top surface, a bottom surface opposite the top surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of ​​the bottom surface or the top surface is larger than the area of ​​any sidewall; and a laterally extending RDL structure covering the first sidewall of each semiconductor structure. The first semiconductor structure of the plurality of semiconductor structures includes a first integrated circuit (IC) structure and a first adjacent structure physically separated from the first IC structure, wherein the first IC structure and the first adjacent structure are arranged along the first sidewall of the first semiconductor structure. The laterally extending RDL structure includes a first plurality of bonding pads arranged along the first sidewall of the first semiconductor structure, wherein the first plurality of bonding pads are located above the edge of the first integrated circuit (IC) structure and above the edge of the first adjacent structure.

[0012] In this disclosure, four unused sidewalls of the 3DIC stack are used for interconnection with the chips in the 3DIC stack to allow signal and power distribution and heat dissipation across the chips and multiple sides. Therefore, power and signal routing and heat dissipation paths are supplied from the front of the bottom chip (or from the interposer supporting the bottom chip) not only to the adjacent chip above but also to all other chips in the chip stack. Thus, routing area, thermal performance, and design flexibility can be increased or enhanced with substantially no increase in the 3D IC's coverage area, and performance can be improved due to a more efficient interconnect strategy. Attached Figure Description

[0013] The aspects of this disclosure are best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily increased or decreased.

[0014] Figures 1A to 1F Various system-in-packages (SIPs) according to comparative embodiments of this disclosure are shown.

[0015] Figures 2A to 2C Cross-sectional views of structures at different stages of a method for manufacturing an integrated circuit (IC) structure according to some embodiments of the present disclosure are shown.

[0016] Figure 2D A perspective view showing the redistribution layers according to various embodiments of the present disclosure.

[0017] Figure 2E and 2F Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0018] Figure 2G Various embodiments according to this disclosure are shown. Figure 2B , 2C Cross-sectional views of the redistribution layers of the IC structure shown in Figures 2E and 2F.

[0019] Figures 3A to 3D Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown.

[0020] Figure 3E and 3F Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0021] Figure 4A to 4G Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown.

[0022] Figure 4H to 4N Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0023] Figure 5A and 5B Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0024] Figure 5C Various embodiments according to this disclosure are shown. Figure 5A and 5B The diagram shows a cross-sectional view of the interconnect structure of the IC structure.

[0025] Figures 6A to 6E Cross-sectional views illustrating the structure of different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure.

[0026] Figures 7A to 7H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0027] Figure 7I and 7J Cross-sectional views of semiconductor packages according to various embodiments of the present disclosure are shown.

[0028] Figures 8A to 8E Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0029] Figure 9A and 9B Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0030] Figures 10A to 10H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0031] Figure 11A and 11B Cross-sectional views of semiconductor packages according to various embodiments of the present disclosure are shown.

[0032] Figures 12A to 12C Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0033] Figures 13A to 13C Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0034] Figure 13D Various embodiments according to this disclosure are shown. Figure 13C The image shows a 3D view of a semiconductor package.

[0035] Figure 14A and 14B A cross-sectional view of a semiconductor package assembly according to various embodiments of the present disclosure is shown.

[0036] Figure 15A A cross-sectional view of a semiconductor packaging assembly according to a comparative example of the present disclosure is shown.

[0037] Figure 15B A cross-sectional view of a semiconductor package assembly according to various embodiments of the present disclosure is shown.

[0038] Figures 16A to 16E Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0039] Figure 17 A cross-sectional view of a semiconductor package assembly according to various embodiments of the present disclosure is shown.

[0040] Figures 18A to 18H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0041] Figure 19A and 19B A cross-sectional view of a semiconductor package assembly according to various embodiments of the present disclosure is shown.

[0042] Figure 20A and 20B Block diagrams illustrating circuits of semiconductor package assemblies according to various embodiments of the present disclosure.

[0043] In the following detailed description, numerous specific details are set forth for the purpose of explanation to provide a thorough understanding of the disclosed embodiments. However, it should be understood that one or more embodiments may be practiced without these specific details. In other examples, well-known structures and apparatuses are illustrated schematically to simplify the drawings. Furthermore, the same component symbols in different figures indicate similar features, and thus a detailed explanation of such features is provided when they are first introduced in this disclosure and need not be repeated thereafter. Detailed Implementation

[0044] This application is a partial continuation of U.S. Non-Provisional Application No. 18 / 471,670, filed September 1, 2023, which claims rights to U.S. Provisional Application No. 63 / 409,852, filed September 26, 2022. This application also claims rights to U.S. Provisional Application No. 63 / 716,506, filed November 5, 2024, U.S. Non-Provisional Patent Application No. 19 / 059,275, filed February 21, 2025, and U.S. Non-Provisional Patent Application No. 19 / 059,297, filed February 21, 2025. The disclosures of all of the above U.S. applications are incorporated herein by reference in their entirety.

[0045] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, an embodiment in which a first member is formed above or on a second member may include instances in which the first and second members form direct contact, and may also include instances in which additional members may be formed between the first and second members such that the first and second members do not form direct contact. Additionally, component symbols and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0046] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “on,” “on top,” and similar terms may be used herein to describe the relationship of one component or member to another component(s), as illustrated in the figures. Spatial relative terms are intended to cover not only the orientation depicted in the figures but also different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and thus the spatial relative descriptive terms used herein may also be interpreted.

[0047] As used herein, although terms such as “first,” “second,” and “third” describe various components, parts, regions, layers, and / or sections, these components, parts, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish components, parts, regions, layers, or sections from one another. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and “third” as used herein do not imply a sequence or order.

[0048] Embodiments of the present invention disclose methods, processes, and structures for forming redistribution layers (RDLs) and interconnects (e.g., through-silicon vias, through-hole vias, metal vias, metal pads for copper hybrid bonding technology, and microbumps or solder bumps for flip-chip assembly) on the four side surfaces of a 3D IC and a low-profile 3D IC stack (detailed description provided below), wherein each stack layer consists of one or more ICs in the xy direction (in-plane direction) and the z direction (out-plane direction or IC thickness direction).

[0049] Embodiments of the packaging structure proposed in this disclosure allow for at least the following features: (a) five-sided power and signal distribution (through one front and four sides of the 3D IC package); (b) interconnection across the die and multiple sides using a combination of RDLs, TSVs, and through-hole vias (TMVs) through the four sides and / or internal interconnects (e.g., directly from the bottom die or substrate such as an interposer to the top die and other ICs in the stack); (c) RDLs on the side surfaces interconnected in three dimensions using flexible printed circuits (flexible circuits); and (d) the ability to use a variety of interconnect technologies, covering RDLs, TSVs, microbumps, solder bumps, copper hybrid bonding technology, and fine-pitch flexible interconnects (Flex). Therefore, the proposed packaging structure effectively reduces the length of global and IC package interconnect wiring and increases the number of transistors accessed in one clock cycle.

[0050] Figures 1A to 1F Various system-in-packages (SIPs) according to comparative embodiments of this disclosure are shown.

[0051] For high-end applications such as HPC, data centers, AI, and smart handheld devices, the cost of miniaturizing ICs (integrated circuits) in System-on-Chip (SoC) designs increases exponentially. The industry is increasingly reliant on complex, advanced SiPs (System-in-Packages) to package advanced ICs, which increases complexity and cost. The advanced SiPs described in this article include... Figure 1A The 2.5D IC shown in the article Figure 1B The fan-out SiP shown in the article Figure 1C The embedded SiP shown in the article Figure 1D The silicon photonics shown in the article Figure 1EThe 3D ICs assembled using chip-to-wafer (C2W) bonding, as shown in the image, Figure 1F The 3D IC shown is assembled using wafer-to-wafer (W2W) bonding. Advanced SiP can also include SiP wafers to utilize one or more of the wafer and advanced SiP technologies. Figures 1A to 1F The technology showcased enables advanced SoC partitioning to improve yield, cost, time-to-market, and performance. All advanced SiPs involve the integration of multiple wafers, and some SiPs (e.g., 2.5D and 3D ICs) may contain wafer-level components with tiny through-silicon vias (TSVs) with diameters as small as approximately 5 μm (and depths of approximately 30 μm, equal to the thickness of a typical silicon substrate) within thin active ICs (e.g., HBM DRAM wafers), as well as fine L (linewidth) / S (line pitch) redistribution layers (RDLs) with L / S ratios of 2 μm / 2 μm and below. All commercially available advanced SiPs are packaged with single-sided power supply and signal transmission.

[0052] refer to Figure 1A The 2.5D IC structure 90 includes a laminated substrate 901 supporting a silicon interposer 902 via multiple solder connections 903. The silicon interposer 902, commonly used in 2.5D IC packaging, contains through-silicon vias (TSVs) 904 and serves as a platform bridging the laminated substrate 901 with fine-line / space / pitch capabilities between the IC module encompassing 3D ICs (e.g., HBM DRAM stacks, i.e., memory structures 905 and processor ICs 907). Various electronic components manufactured using wafer-level processes can be mounted on the silicon interposer 902 and can include memory devices (e.g., 905), logic ICs (e.g., 907), MEMS (microelectromechanical systems) devices, and passive devices mounted on the top side (i.e., wafer side) of the silicon interposer 902, while the electronic components can be arranged in 2D IC, 2.5D IC, or 3D IC package configurations. For example, memory structure 905 can be an HBM DRAM stack comprising multiple DRAM chips 905a vertically stacked above a substrate chip (typically a control chip) 905b via copper pillar microbumps. If desired, the combination of interposer 902 and laminate 901 can be replaced with a laminate containing a silicon interconnect substrate embedded in the substrate. Figure 1C (or mounted on a substrate.) For example... Figure 1A As shown, the laminate 901 on which the silicon interposer 902 is bonded using microbumps or solder bumps can be bonded to a printed circuit board (PCB, not shown) via a plurality of ball grid array (BGA) solder balls 906 beneath the laminate 901.

[0053] refer to Figure 1BThe fan-out package structure 91 can be used in conjunction with electrical connections on wafers 913a and 913b, wherein the electrical connections fan out from the active surfaces of wafers 913a and 913b to allow solder bumps 903a to be placed beyond the boundaries of the wafers, serving as external I / O at the distal ends of wafers 913a and 913b. The fan-out package structure 91, which may include one or more semiconductor wafers (e.g., wafers 913a and 913b), allows individual wafers to be connected to the fan-out wiring layer 911 and solder bumps 903a, or alternatively, microbumps, depending on the application. Figure 1B As depicted, a fan-out package structure 91, produced by a wafer-level fan-out process, is bonded to a substrate 901, wherein the substrate 901 may be a laminate, an interlayer, or another fan-out package structure and is bonded to a next-level substrate using solder bumps or solder balls 906.

[0054] exist Figure 1C In this embodiment, the embedded SiP 92 includes one or more devices 923 embedded in a laminate 901. The one or more devices 923 may be embedded silicon interconnects (which may be passive or active devices), active devices (e.g., power ICs), or embedded passive devices (e.g., capacitors or inductors). Furthermore, depending on the application, the laminate 901 having the embedded devices 923 can be bonded to another laminate or PCB 908 via solder balls 906 or microbumps.

[0055] refer to Figure 1D The silicon photonic structure 93 includes a CMOS wafer 916, a waveguide RDL structure 918, a modulator 919 embedded in the waveguide RDL structure 918, a photodetector 920, and an optical fiber 921 coupling optical signals in and out of the waveguide RDL structure 918. A laser diode 917, the waveguide RDL structure 918, and components coupled to the waveguide RDL structure 918 are integrated over a silicon interposer 914, with or without a TSV. The silicon interposer 914, fabricated using a wafer-level process, is configured to be mounted on a substrate via a plurality of solder bumps or microbumps 903 for external interconnection.

[0056] refer to Figure 1E The C2W structure 94 includes a first carrier 940, a first wafer 941, and a second wafer 942. The first wafer 941 and the second wafer 942 are placed on the first carrier 940 using various suitable bonding techniques including microbump-based flip-chip assembly and copper hybrid bonding technology. The first carrier 940 may be an active or passive device including an interposer layer with through-holes 943, and the first carrier 940 serves as a platform for interconnecting the first wafer 941 and the second wafer 942 with a substrate (not shown) on which the C2W structure 94 is mounted.

[0057] refer to Figure 1FThe W2W structure 95 includes a first carrier 951, a second carrier 952, and an interconnect layer 953 electrically coupling the first carrier 951 to the second carrier 952. The interconnect layer 953 includes flip-chip bonding, copper hybrid bonding technology based on polyimide (PI) to PI or oxide to oxide, or another suitable bonding structure. For example, a through-hole 954 may be formed in the first carrier 951 to establish an electrical connection between the first carrier 951, the second carrier 952, and a substrate (not shown) on which the W2W structure 95 is mounted using solder bumps, microbumps, or solder balls 955.

[0058] exist Figures 1A to 1F Currently, interconnections between components are typically achieved through flip-chip assembly based on solder bumps, microbumps, or BGA solder balls. Relatively new copper hybrid bonding technology, for high-end applications including HPC, data centers, and AI, can in principle achieve finer pitch bonding and higher density functional integration than flip-chip bonding, as required by the applications.

[0059] 3D ICs typically contain ICs and / or interconnects (e.g., interposers) with top or bottom surfaces of the same or similar size. In some embodiments of this disclosure, the semiconductor package structure interconnected via its sides can be an IC stack comprising ICs of the same or similar size, or an IC stack consisting of several package layers containing ICs of different sizes but having the same size after embedding, or an IC stack containing an IC and embedded ICs of the same size. Fan-out processes and potting materials, molding compounds, or sealing materials (which are dielectric materials) are used to achieve IC embedding to ensure that ICs of different sizes in different stack layers have the same size after embedding. Therefore, conductive edge interconnects are used to form the side interconnects of the 3D IC, such as edge contact pads or edge vias in an RDL, edge through-silicon vias, and edge through-mold vias located at the edges of the package layers. Components integrated into a 3D IC can provide different electronic functions and are preferably known good wafers or components. It can include ICs, other types of active devices (e.g., MEMS (microelectromechanical systems) devices), and passive devices. This means that virtually a vast number of component options are available for stacking and embedding.

[0060] Figures 2A to 2C Cross-sectional views of the structure at different stages of a method for manufacturing an IC structure 100A according to some embodiments of the present disclosure are shown. Figure 2CThe IC structure 100A shown is a semiconductor packaging device. The IC structure 100A can be formed from a semiconductor device 100W, which is a wafer-level device, wherein the IC structure 100A is formed by isolating the semiconductor device 100W using a monomerization or dicing process covering mechanical dicing, laser dicing, plasma etching or dicing, dry etching, wet etching (e.g., acid etching), or similar or combinations thereof.

[0061] refer to Figure 2A The system receives or provides a semiconductor device 100W. First, a substrate 102 is provided or received. According to some embodiments, the substrate 102 is formed of a semiconductor material such as bulk silicon. According to some embodiments, the substrate 102 is formed of other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In this embodiment, the substrate 102 is a P-type semiconducting substrate (acceptor type). In some other embodiments, an N-type semiconductor substrate (donor type) may be used. Alternatively, the substrate 102 includes: another elemental semiconductor, such as germanium; a compound semiconductor comprising gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or combinations thereof. In yet another embodiment, the substrate 102 includes a portion forming a semiconductor-on-insulator (SOI) substrate. In other embodiments, the substrate 102 may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer covering another type of semiconductor layer, such as a silicon-germanium layer stacked on a silicon layer.

[0062] A plurality of conductive vias 104 are formed in substrate 102. The conductive vias 104 may extend from a main surface 102P1 of substrate 102 to a thickness of substrate 102. In this disclosure, "main surface" is used to refer to the upper or bottom surface of a circuit or device that has the largest surface area among the six surfaces of the device or layer. Similarly, "sub-surface" is used to refer to the lateral side surfaces of a circuit or device (a circuit or device typically has four such side surfaces) whose surface area is smaller than that of the main surface. The conductive vias 104 may contain conductive materials such as copper, tungsten, molybdenum, cobalt, ruthenium, titanium, tantalum, aluminum, silver, gold, or other suitable materials. The conductive vias 104 may comprise a single-layer or multi-layer structure, which may include a diffusion barrier layer, a seed layer facilitating electroplating, a filler layer, a combination thereof, or the like.

[0063] In the exemplary formation process of conductive via 104, a plurality of holes (not shown) are formed on the main surface 102P1 of substrate 102. Dry etching (e.g., reactive ion etching, RIE), wet etching, combinations thereof, or the like can be used to form the holes. After the opening is completed, a deposition process such as plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit silicon dioxide to passivate the opening, and physical vapor deposition (PVD), sputtering deposition, atomic layer deposition (ALD), or other suitable deposition steps can be performed to deposit material for the conductive via 104 in the holes and over the main surface 102P1. After the hole-filling process, the conductive via 104 may be referred to herein as a through-silicon via (TSV).

[0064] According to some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP), dry etching (e.g., using RIE), polishing, wet etching, and / or other suitable etching steps) is performed to remove excess conductive material and planarize the upper surface of the conductive via 104 flush with the main surface 102P1. After planarization, a main RDL 108A with surface treatment and a pad is deposited on the main surface 102P1 for subsequent bonding as needed.

[0065] refer to Figure 2B The device provides or receives another substrate or temporary carrier 106 and bonds the semiconductor structure 100W to the temporary carrier 106. According to some embodiments, the substrate 106 is a carrier substrate or support substrate. The carrier substrate 106 may be formed of glass, silicon, ceramic, or other suitable carrier materials. A release layer 110 is formed over the carrier substrate 106. Examples of release layers include release / adhesive layers commonly used in fan-out processes. The release layer 110 is a temporary layer formed over the carrier substrate 106 and allows for easier removal of the carrier substrate 106 from the semiconductor device 100W by laser irradiation, thermomechanical release, polishing, CMP, dry or wet etching / cleaning, or combinations thereof.

[0066] In addition to being used as a release layer in fan-out processing, the release layer can also be a combination of Ti (titanium) / Au (gold) stacked on the carrier and Ti / Au stacked on the back of the IC structure. The Au here can also be Cu (copper) or solder on both surfaces. Compression or reflow bonding can be used to achieve bonding between the carrier and the IC structure. Annealing is optional and can be performed as needed. When silicon is used as the carrier, the release layer can be SiO2, Si3N4, and other materials commonly used in wafer BEOL and / or MEMS / NEMS processing. The release layer can therefore also serve as a permanent bonding layer between IC structures (e.g., Figure 7B (The bonding layer shown in the image).

[0067] The pre-bonding conditions between the carrier and the IC structure surface may involve:

[0068] - Chemical mechanical polishing (CMP) is used to achieve a preferred surface roughness (RA) of <1 nm for diamond and silicon, as required. This RA level can be achieved through a combination of CMP for silicon and SiO2 sacrificial layer deposition and CMP SiO2 planarization, and deep reactive ion etching (DRIE) for diamond.

[0069] - Wet surface pretreatment, which involves ultrasonic deionized (DI) water cleaning, H2SO4 / H2O2 treatment, NH3 / H2O2 treatment, and N2 drying.

[0070] - Plasma / Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE): O2, H2 / O2,

[0071] -Depth RIE (DRIE): O2 / CF4, and

[0072] - The bonding surface (with and / or without adhesive layer) is activated in the bonding machine by using a fast atomic beam gun (FAB) (e.g., using an argon neutral atomic beam of about 1 keV) or by using an ion gun (e.g., using argon ions of about 60 eV) to remove the oxide film in vacuum and expose dangling bonds at the bonding surface.

[0073] -(Note 1: FAB is well-suited for (sputtering) Si / Si, Si / SiO2, metals, compound semiconductors and single-crystal oxides, while ion guns are known to be suitable for SiO2 / SiO2, glass, Si3N4 (silicon nitride) / Si3N4, Si / Si, Si / SiO2, metals, compound semiconductors and single-crystal oxides.)

[0074] -(Note 2: A vacuum of 10⁻⁶ Pa is required during bonding to prevent re-adsorption onto the activated bonding surface.)

[0075] In addition to the direct bonding methods described above, ultrathin adhesive or bonding layers (e.g., CVD polysilicon (poly-Si)) can be deposited as permanent bonding layers on mating IC structures. Figure 7B Alternatively, it can be deposited as a temporary release layer on both the IC structure and the carrier to achieve higher low-temperature direct bonding yield. For thermally sensitive applications, polysilicon (whose thermal conductivity TC is more than 100 times that of SiO2) is preferred over SiO2 for producing thin bonding layers in order to minimize the impact on the thermal resistivity of the final IC or package structure. Adhesive layers are typically ultra-thin (approximately 100 nm or less) to minimize their thermal impact. When used as a permanent layer, materials with higher TC and lower thermal expansion are preferred. Adhesive layer candidate materials include the following and combinations (or alloys thereof):

[0076] - Non-metallic materials: Si (e.g., polycrystalline silicon), SiO2, Si3N4, Al2O3 (alumina), diamond, boron nitride, graphene

[0077] -Metals: Ti, W, Pt, Cr, Au, Cu, Ir, Nickel (Ni), Iron (Fe), Ag-In, Au-In, Ag, Sn, Mo

[0078] - Oxide-based metal cascades: SrTiO3 cascaded with Ir, YSZ / Si cascaded with Ir, MgO, sapphire or TaO3 cascaded with Ir

[0079] When metal adhesive layers are used to bond IC structures (e.g., see...) Figure 7B When depositing a binder layer, it is recommended to deposit a barrier layer, such as Ti, on the back side of the IC structure before depositing the binder layer to prevent metal diffusion in the silicon lattice, which can poison the device. This is especially true for ultrathin ICs. During diamond CVD, growing diamond on a silicon seed crystal is a common practice. Silicon nitride (Si3N4) is commonly used in wafer BEOL processing. Alumina can be deposited via atomic layer deposition. When it comes to extreme thermal conductivity, graphene is another material worth considering besides diamond. In a monolayer, graphene can have a thermal conductivity of 30 to 50 W / cm·K. It can be considered as a binder or bonding layer to present a suitable 3D molecular structure. Graphene can be grown on silicon (100) surfaces using direct cobalt-assisted two-step ion beam synthesis. It can also be grown on silicon using a simple transfer-free synthesis method. Epitaxial graphene can be grown on crystalline and semi-insulating surfaces (such as SiC and silicon), and graphene nanostructures with excellent properties have been achieved through selective growth processes on SiC surfaces. Besides diamond and graphene, boron nitride is also of interest, especially cubic boron nitride, as it is known to have a similar crystal structure to diamond and a high in-plane TC (approximately 16 W / cm·K). Furthermore, the adhesive layer can be a combination of Ti / Au on one IC structure and Ti / Au on the back of another IC structure for bonding. Thin metal platings based on Ti, W, or Cr can also be deposited prior to Au deposition, if desired. Thin layers of transient liquid bonding materials, such as silver-indium (Ag-In) and Au-In, sintered Ag, In, Au, or Cu, can also be applied together with matching metal platings (e.g., Au, Ag, or Cu). The adhesive layer can be deposited by CVD, atomic layer deposition (ALD), physical vapor deposition, thermal oxidation (in the case of silicon), or other methods. After deposition, the adhesive layer can be modulated in the bonding station by a combination of the aforementioned pre-bonded surface pretreatment, DRIE (e.g., using a mixture of SF6 and O2), plasma / ICP-RIE (using O2, Ar, N2, Ar / O2) and FAB (using (e.g.) neutral Ar atoms) or ion gun (using (e.g.) Ar ions).

[0080] After generating the main RDL 108A, the planarized structure having the main RDL 108A is bonded to the substrate 106 using a release layer, and the blocky portion of the substrate 102 below the conductive via 104 is removed to expose the bottom surface of the conductive via 104 (see...). Figure 2B Then you can... Figure 2B Another RDL 108B is deposited on the exposed conductive via 104, which, when completed, may have a surface finish and solder bumps or microbumps as required. After forming RDL 108B, mounting the resulting structure with RDLs 108A and 108B on carrier 106 onto a wafer bonding tape frame, releasing carrier 106, and individualizing the packages, a complete package is formed. Figure 2C The semiconductor structure in it is 100A.

[0081] based on Figures 2A to 2C The process shown can form various layers and structures to produce exposed edge pads, edge vias, and edge TSVs (which can penetrate the thickness of silicon or potting material, or a subset thereof, either completely or partially, such as a structure containing only RDL108A with edge pad / via interconnects in the RDL). Figure 2E ), or a structure containing both RDL 108A with edge interconnects and edge TSVs (see Figure 2F )) Semiconductor structure 100A.

[0082] According to some embodiments, release layer 110 comprises a polymer-based material. According to some embodiments, release layer 110 is a heat-release material based on epoxy resin, such as a photothermal conversion (LTHC) release coating, which loses its adhesiveness upon heating or exposure to laser. According to other embodiments, release layer 110 is an ultraviolet (UV) adhesive, which loses its adhesiveness upon exposure to UV light. Release layer 110 may be a thermoplastic or thermosetting material. According to some embodiments, release layer 110 comprises a polyimide or silicone-based material. According to some other embodiments, release layer 110 is a mixture of metallic and non-metallic materials. Metallic candidates for the release layer may include nickel, chromium, titanium, gold, copper, manganese, iron, cobalt, tungsten, molybdenum, ruthenium, and tantalum, while non-metallic candidates may include metal oxides, nitrides, phosphates, and chromates. Release layer 110 can be disposed and cured by liquid spin coating. In other embodiments, release layer 110 may be a laminated film laminated onto carrier substrate 106. In some other embodiments, the bonding between the substrate 102 and the temporary carrier 106 can be achieved by direct bonding based on, for example, oxide-to-oxide or polyimide-to-polyimide, without the need for release layer 110.

[0083] RDL 108A is part of the interconnect structure 101 of IC structure 100A. RDL 108A includes one or more interconnect conductive paths formed through one or more conductive lines in a conductive line layer and one or more conductive vias (not shown separately) in a conductive via layer to route power and signals of a first circuit from one side of RDL 108A to a second circuit on the same or opposite side of RDL 108A. RDL 108A may include a sealing material (or, for example, a sealant for polyimide or oxide layers that facilitates direct or copper-mixed bonding) sealing the conductive line layer and conductive via layer. According to some embodiments, the sealing material comprises one or more dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, combinations thereof, or the like. Due to the use of RDL 108A in interconnect structure 101, the signal and power distribution of devices or circuits in IC structure 100A can meet design requirements. In this disclosure, an RDL (e.g., RDL 108A) formed on the main surface (e.g., main surface 102P1) of a circuit or device is referred to as main RDL 108A. Further structural details of main RDL 108A are discussed below.

[0084] According to some embodiments, substrate 102 is disposed above and bonded to main RDL 108A. Bonding of substrate 102 to main RDL 108A can be performed using thermal bonding, thermoforming bonding, flip-chip bonding, hybrid bonding, or the like. Although not explicitly stated, conductive vias 104 of substrate 102 are electrically coupled to one of the conductive lines or vias of main RDL 108A to extend the signal transmission network or power transmission network of RDL 108A. Furthermore, the upper portion of substrate 102 is removed or thinned from the top of substrate 102, thus exposing the bottom surface of conductive vias 104. The removal or thinning of the upper portion of substrate 102 can be performed using CMP, polishing, dry etching (e.g., RIE), wet etching, or the like. Subsequently, conductive via 104 becomes TSV 104.

[0085] refer to Figure 2C The semiconductor device 100W is isolated into individual IC structures 100A after the structures having RDL 108A and RDL 108B are mounted on a wafer mounting frame and the carrier 106 is released. The monomerization or dicing process can be performed using diamond blades, lasers, plasma with a masking layer deposited on (e.g.) RDL 108A, wet etching, or a combination thereof to monomerize the semiconductor device 100W along dicing paths to form individual IC structures 100A. The interconnect structures 101 in the IC structure 100A include TSV wafer 122A, internal interconnect structures 108X such as internal pads and vias in RDL 108A and 108B, and edge interconnect structures 118X such as edge pads and vias in the RDL.

[0086] During monomerization or dicing, the area removed is called a dicing, sawing, or wafer track, and it is typically between 50 μm and 100 μm wide. The dicing saw can use a diamond blade rotating at 30,000 revolutions per minute and is cooled with deionized water. To expose edge pads or vias, preferably, the size of the edge pads or vias is comparable to the dicing track width, and the cut is made immediately adjacent to the edge pads or vias (but not directly through them), followed by a light wet etching of the silicon as needed and permitted. To minimize underside chipping during mechanical blade dicing, it is advantageous to first dice the wafer placed on a carrier support and then release the carrier. Laser ablation dicing, which can achieve dicing track widths of 10 μm, can also be used to first remove the fine-line layer on the dicing track surface using a non-contact laser (and expose the adjacent edge pads), followed by laser scribing and / or blade dicing to cut the remaining substrate. This process reduces problems such as debris, wafer breakage, and layer delamination. In laser ablation dicing, a laser heats the material to a temperature that causes the area under the laser beam to be ablated or simply evaporated. Alternatively, dicing can be performed using dry, liquid-free stealth dicing. Stealth dicing is a two-stage process where a laser beam (e.g., a pulsed Nd:YAG laser with a wavelength of 1064 nm for silicon) is first guided to scan along the desired dicing path to create defect areas, followed by expansion of the underlying thin film (attached to the wafer, then released from the wafer carrier) to induce cracking. Stealth laser dicing has the potential to replace blade dicing as the next-generation ultra-thin wafer monolithization technology supporting 3DIC packaging because it allows for faster cutting, higher accuracy, less damage, and smaller dicing widths. Compared to mechanical and laser dicing, plasma dicing (also known as deep reactive ion etching) is a relatively new method using Bosch's dry etching process, which can achieve particle-free and contamination-free wafer cutting with high precision. This method requires a custom photomask design for effective plasma dicing. Plasma dicing uses plasma gases, such as sulfur hexafluoride, to simultaneously etch all narrow kerfs into the wafer, resulting in high precision, high throughput, and high quality. Plasma dicing produces non-rectangular kerfs, which is impossible with blade dicing. It causes minimal damage to the wafer surface or trench sidewalls, leading to better wafer strength, improved device reliability, and longer device life. Plasma dicing has rapidly gained popularity in the semiconductor industry as a preferred solution, especially as wafers become smaller, thinner, and more complex.

[0087] Due to the monomerization or dicing process, the IC structure 100A contains four sub-planes or side planes 100AS, but Figure 2DOnly two sub-planes 100AS are described. The TSV wafer 122A includes side surfaces 108S on its four sides, while the main RDLs 108A and 108B also include side surfaces 108S on their four sides. The side surfaces 102S of the TSV wafer 122A and the side surfaces 108S of the two main RDLs 108A and 108B together constitute or coincide with the sub-planes 100AS of the IC structure 100A. Through proper arrangement, a TSV 104 is formed in the TSV wafer 122A and, after monomerization or dicing, includes two TSV types: an internal TSV 104A and an edge TSV 104B. The internal TSV 104A is completely surrounded by the substrate 102 and the main RDLs 108A and 108B, while the edge TSV 104B has at least one side surface exposed through the side surfaces 102S of the substrate 102.

[0088] Similarly, main RDL 108A or 108B includes conductive pads 212 and conductive vias 214 formed by conductive components 202 (e.g., conductive lines and conductive vias), respectively. The conductive components 202 comprise two parts: an internal conductive component 202 and an edge conductive component 202. With appropriate arrangement, the conductive pads 212 and conductive vias 214 are formed in the IC structure 100A and, after monomerization or dicing processes, comprise two parts: internal conductive pads / vias 212 and 214 and edge conductive pads / vias 212 and 214. The internal conductive pads / vias 212 and 214 are completely surrounded by the substrate material and sealing material of the two main RDLs 108A and 108B, while the edge conductive pads / vias 212 and 214 have at least one side surface exposed through the side surface 108S of the main RDL 108A or 108B.

[0089] According to some embodiments, the edge conductive pad 212 has at least one upper surface exposed through the main surface 108P of the main RDL 108A or 108B. The inner or edge conductive pad 212 may be disposed on the uppermost conductive layer of the corresponding main RDL 108A or 108B, the uppermost conductive layer being furthest from the TSV wafer 122A. According to some embodiments, the conductive pad 212 is disposed parallel to the main surface 108P of the main RDL 108A or 108B. The conductive pad 212 may not reach the TSV wafer 122A. Furthermore, the edge conductive pad 212 has at least one side surface exposed through the sub-plane 100AS of the IC structure 100A or the sub-surface 108S of the main RDL 108A or 108B.

[0090] Similarly, according to some embodiments, the edge conductive via 214 has at least one upper surface exposed through the main surface 108P of the main RDL 108A or 108B. The edge conductive via 214 may be arranged to extend through the thickness (in the z-direction) of the respective main RDL 108A or 108B. According to some embodiments, the edge conductive via 214 is referred to herein as a TSV of the main RDL 108A or 108B. Furthermore, the edge conductive via 214 has at least one side surface exposed through the sub-plane 100AS of the IC structure 100A or the sub-surface 108S of the main RDL 108A or 108B.

[0091] Figure 2D A perspective view of a main RDL 108A or 108B according to various embodiments of the present disclosure is shown. The main RDL 108A or 108B includes a main surface 108P (e.g., an upper main surface 108P1 and a lower main surface 108P2) and four secondary (side) surfaces 108S (e.g., a front secondary surface 108S1, a rear secondary surface 108S2, a right secondary surface 108S3, and a left secondary surface 108S4). A plurality of conductive components 202 (e.g., conductive pads / vias 212) are formed on the main RDL 108A or 108B and exposed through the four secondary surfaces 108S. (Shown for illustration) Figure 2D Arrangement of conductive pads 212 of the main RDL 108A or 108B. Conductive pads 212 or other conductive components may be formed or exposed through one or more of the four secondary surfaces 108S.

[0092] As discussed above, in this disclosure, Figure 2C TSV 104 of the interconnect structure 101 (see Figure 2C 104A and 104B), conductive pad 212, conductive via 214, and all other conductive components are part of the interconnect structure 101 of IC structure 100A, collectively referred to as conductive assembly 202. TSV 104, conductive pad 212, and conductive via 214 are configured to form at least a portion of the interconnect structure 101 of IC structure 100A for communication with the interconnect structure 100A via the IC structure 100A. Figure 2C The two principal surfaces 108P (i.e., upper principal surface 108P1 and lower principal surface 108P2; see Figure 2D ) and through the four sub-surfaces 108S1 to 108S4 of the IC structure 100A (see Figure 2D Devices electrically coupled to the IC structure 100A or its package layer are fan-in or fan-out interconnected. According to some embodiments, the conductive vias 214 of TSV 104 and main RDLs 108A and 108B can be coupled to form a common TSV for the IC structure 100A. For example, the conductive via 214 on the right edge of the main RDL 108A (… Figure 2CThe right edge TSV 104 and the right edge conductive via 214 of the main RDL 108B constitute the stacked edge TSV of the IC structure 100A to extend through the substrate thickness of the IC structure 100A.

[0093] Figure 2E A cross-sectional view of an IC structure 100B according to various embodiments of the present disclosure is shown. The IC structure 100B is similar to the IC structure 100A in many respects (e.g., main RDL 108A, conductive pad 212, and conductive via 214), therefore, for the sake of brevity, details of such similar aspects are not repeated. The main difference between the IC structure 100A and the IC structure 100B is that the TSV chip 122A of the IC structure 100A is replaced by a semiconductor chip 122B in the IC structure 100B, and the main RDL 108B in the IC structure 100A is not present in the IC structure 100B. According to some embodiments, the semiconductor chip 122B may be at least one of a CPU chip, GPU chip, TPU chip, MEMS chip, AP chip, FPGA chip, ASIC chip, memory chip, transceiver chip, network interface chip, integrated photonics chip, packet buffer / router chip, or another suitable chip. The semiconductor chip 122B may include a substrate 102 comprising materials similar to... Figure 2D The material of the substrate 102 of the IC structure 100A shown is illustrated. Therefore, the semiconductor wafer 122B constitutes the substrate or body of the IC structure 100B. According to some embodiments, the semiconductor wafer 122B does not contain any edge interconnect structures 118X exposed through the side surface 102S of the semiconductor wafer 122B.

[0094] Figure 2F A cross-sectional view of an IC structure 100C according to various embodiments of the present disclosure is shown. The IC structure 100C is similar to the IC structure 100B in many respects (e.g., main RDL 108A, conductive pad 212, and conductive via 214), therefore, for the sake of brevity, details of such similar aspects are not repeated. Furthermore, the IC structure 100C includes a semiconductor wafer 122C, which may be at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer. The semiconductor wafer 122C may contain components similar to... Figure 2DThe substrate 102 of the IC structure 100A shown herein is a substrate 102. The main difference between semiconductor wafer 122C and semiconductor wafer 122B is that semiconductor wafer 122C further includes edge interconnect structures 118X, such as edge conductive pads 222, exposed through the sub-plane or side surface 102S of semiconductor wafer 122C. According to some embodiments, the edge conductive pads 222 are electrically connected to conductive vias 214 of the main RDL 108A to establish stacked conductive vias for semiconductor wafer 122C. Therefore, semiconductor wafer 122C constitutes the body of IC structure 100C.

[0095] Figure 2G Various embodiments according to this disclosure are shown. Figures 2B to 2F The diagram shows a cross-sectional view of the main RDL 108A or 108B of the IC structure 100A, 100B, or 100C. Figure 2G As described, the main RDL 108A or 108B is formed by a first main wire / via layer 240 and a second main wire / via layer 250 below the first main wire / via layer 240. Each of the first main wire / via layer 240 and the second main wire / via layer 250 includes one or more conductive wires and conductive vias extending in a horizontal or vertical direction (all of which are part of the common conductive component 202 of the interconnection structure 101 in the main RDL 108A or 108B). The conductive wires or vias are electrically insulated by a dielectric layer called an intermetallic dielectric (IMD) layer. The IMD layer may contain one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, or other suitable dielectric materials. Some conductive vias in the first primary wire / via layer 240 extend halfway in the vertical direction, while some conductive vias in the first primary wire / via layer 240 (e.g., conductive via 214-1) extend through the entire thickness of the first primary wire / via layer 240. Similarly, some conductive vias in the second primary wire / via layer 250 extend halfway in the vertical direction, while some conductive vias in the second primary wire / via layer 250 (e.g., conductive via 214-2) extend through the thickness of the second primary wire / via layer 250. Conductive vias 214-1 and 214-2 are electrically connected to form a stacked conductive via 214 through the primary RDL 108A or 108B. According to some embodiments, the first primary wire / via layer 240 includes two conductive wire layers and a conductive via layer between the two conductive wire layers, wherein conductive vias 216 are arranged in the conductive via layer to electrically connect two conductive wires in adjacent conductive wire layers. refer to Figure 2F and Figure 2G , Figure 2FThe conductive via 214 of the IC structure 100C shown is considered to be a conductive via connecting adjacent first and second main wire / via layers 240 and 250. According to some embodiments, the stacked conductive via 214 is part of the edge interconnect structure 118X and is exposed through the sub-surface 108S of the main RDL 108A or 108B. Although Figure 2G Only two main wire / via layers 240 and 250 are described, but this disclosure is not limited thereto. Other numbers of main wire / via layers and the configuration of conductive wires or conductive vias in each main wire / via layer are also within the scope of this disclosure.

[0096] Figures 3A to 3D Cross-sectional views of the structure at different stages of a method for manufacturing an IC structure 300A according to some embodiments of the present disclosure are shown. Figure 3D The IC structure 300A shown is a semiconductor packaging device. The IC structure 300A can be formed from a semiconductor device 300W, which is a wafer-level device, wherein the IC structure 300A is formed by separating the semiconductor device 300W through a monomerization or dicing process.

[0097] refer to Figure 3A It receives or provides the carrier substrate 106. Furthermore, a release layer 110 is formed above the carrier substrate 106, as... Figures 2A to 2C In this configuration, multiple semiconductor wafers 122D are arranged above the release layer 110. The semiconductor wafers 122D may include at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or other suitable wafer. Furthermore, multiple conductive pillars or vias 232 are formed at suitable spacing above the release layer 110 between adjacent semiconductor wafers 122D and sealed by a molding compound or suitable potting material (e.g., epoxy resin, such as Epotek 377). Figure 3B As shown in the diagram. Conductive vias 232 may be alternately formed in the semiconductor wafer 122D. Multiple semiconductor wafers 122D and conductive vias (pillars) 232, referred to herein as a reconfigured structure, are arranged on the carrier surface 110S or carrier substrate 106 of the release layer 110. The conductive vias 232 may contain conductive materials, such as tungsten, copper, titanium, tantalum, molybdenum, ruthenium, cobalt, aluminum, silver, gold, or another suitable material. The multiple semiconductor wafers 122D and conductive vias 232 may have substantially equal heights. According to some embodiments, the semiconductor wafers 122D and conductive vias 232 are arranged above the release layer 110 via a pick-and-place bonding process.

[0098] refer to Figure 3BThe reconstructed structure of the semiconductor device 300W is molded or sealed using a potting material (e.g., sealing material, molding material, or insulating component) 242. The potting material 242 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, epoxy-based molding material, polymeric material, or the like. A molding or deposition process is performed to deposit the potting material 242 between the semiconductor wafer 122D and a conductive via 232, which may be created prior to bonding the semiconductor wafer 122D and depositing the potting material. According to some embodiments, a planarization process (e.g., CMP, polishing, wet etching, dry etching (e.g., RIE), and / or another suitable etching step) is performed to remove excess potting material 242 and planarize the upper surface of the potting material 242 to expose the conductive via 232 from the upper surface of the semiconductor wafer 122D. According to some embodiments, since the conductive via 232 is within and laterally surrounded by the potting material 242, the conductive via 232 is also referred to herein as a through-hole (TMV) 232.

[0099] refer to Figure 3C The main RDL 108A is formed above the upper surface of the potting material 242, the semiconductor wafer 122D, and the TMV 232. The materials, configuration, and method for forming the main RDL 108A are similar to those in the reference. Figures 2B to 2G The materials, configurations, and methods described are omitted for brevity, avoiding repetitive descriptions of the main RDL 108A.

[0100] refer to Figure 3D The semiconductor device 300W is isolated into individual IC structures 300A by performing a monomerization or dicing process. Furthermore, the carrier substrate 106 is removed or detached from the semiconductor device 300W by releasing the release layer 110. Conductive pads / vias 212 / 214 are formed in the IC structure 300A through appropriate arrangement and include two types of pads / vias after the monomerization or dicing process: internal conductive pads / vias (not shown separately) 212 and edge conductive pads / vias 214. The properties of the conductive pads / vias 212 and 214 are similar to... Figure 2F The properties of IC structure 100C shown are presented herein, and for the sake of brevity, repeated descriptions are omitted. The main difference between IC structure 300A and IC structure 100C is that in IC structure 300A, the semiconductor wafer 122D is laterally surrounded or sealed by potting material 242, while in the case of 100C, only the edges of the wafer and RDL are exposed. The semiconductor wafer 122D and the potting material 242 constitute the main body of IC structure 300A.

[0101] Figure 3EA cross-sectional view of an IC structure 300B according to various embodiments of the present disclosure is shown. The IC structure 300B is similar to the IC structure 300A in many respects (e.g., main RDL 108A, conductive pad 212, and conductive via 214), therefore, for the sake of brevity, details of such similar aspects are not repeated. The main difference between the IC structure 300A and the IC structure 300B is that, in addition to the semiconductor wafer 122D and the potting material 242, the body of the IC structure 300B further includes an edge TMV 232 that extends through or partially through the thickness of the semiconductor wafer 122D. The edge TMV 232 is part of the edge interconnect structure 118X.

[0102] Figure 3F A cross-sectional view of an IC structure 300C according to various embodiments of the present disclosure is shown. The IC structure 300C is similar to the IC structure 300B in many respects (e.g., main RDL 108A, conductive pad 212, conductive via 214, and TMV 232), therefore, for the sake of brevity, details of such similar aspects are not repeated. Furthermore, the IC structure 300C includes a semiconductor wafer 122D1, which replaces semiconductor wafer 122D and may be at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer. The main difference between semiconductor wafer 122D and semiconductor wafer 122D1 is that semiconductor wafer 122D1 further includes portions of an edge interconnect structure 118X, such as edge conductive pads 222 exposed through the sub-plane or side surface 102S of semiconductor wafer 122D1. The materials, configuration, and methods for forming the edge conductive pads 222 of the IC structure 300C are similar to those in the reference. Figure 2F The materials, configuration, and methods for the conductive via 222 are described. Therefore, the body of the IC structure 300C includes a semiconductor wafer 122D1, a potting material 242, the conductive via 222, and a TMV 232. According to some embodiments, the main RDL 108A of the IC structure 300C includes a conductive via 214 electrically connected to the TMV 232 in the body of the IC structure 300C for creating stacked conductive vias for the IC structure 300C.

[0103] Figure 4A to 4G Cross-sectional views of the structure at different stages of a method for manufacturing an IC structure 400A according to some embodiments of the present disclosure are shown. Figure 4G The IC structure 400A shown is a semiconductor package device. The IC structure 400A can be comprised of a semiconductor device 100W (see...). Figure 4AThe semiconductor device 100W is a wafer-level device, wherein the IC structure 400A is formed by separating the semiconductor device 400W through a monomerization or dicing process.

[0104] refer to Figure 4A The substrate 102 is used to receive or supply semiconductor device 100W. Furthermore, conductive vias 104 are formed in the substrate 102. (See reference) Figure 4B For example, the bulk portion of the substrate 102 beneath the conductive via 104 is removed via CMP, grinding, or etching steps, transforming the conductive via 104 into a TSV 104. A monomerization or dicing process is then performed to separate the semiconductor device 100W into multiple TSV wafers 122E, similar to the reference process. Figure 2C The TSV chip 122A is described.

[0105] refer to Figure 4C A carrier substrate 106 is received or provided in a semiconductor device 400W. Furthermore, a release layer 110 is formed above the carrier substrate 106. A plurality of TSV wafers 122E and a plurality of TMVs 232 are arranged above the release layer 110 to form a reconstructed structure on the carrier surface 110S of the release layer 110 or on the carrier substrate 106. The TMVs 232 may be arranged alternately with the TSV wafers 122E. The TMVs 232 may contain conductive materials, such as tungsten, copper, titanium, tantalum, molybdenum, cobalt, ruthenium, aluminum, silver, gold, or another suitable material. The plurality of TSV wafers 122E and the plurality of TMVs 232 may have substantially equal heights. According to some embodiments, the TSV wafers 122E and TMVs 232 are arranged above the release layer 110 via a pick-and-place bonding process.

[0106] refer to Figure 4D A potting material (e.g., sealing material or molding material) 242 is used to mold or seal the semiconductor device 400W. A deposition process or molding process is performed to deposit the potting material 242 between the TSV wafer 122E and the TMV 232. According to some embodiments, a planarization process (e.g., CMP, polishing, wet etching, or another suitable etching step) is performed to remove excess potting material 242 and planarize the upper surface of the potting material 242, the upper surface of the TSV wafer 122E, and the upper surface of the TMV 232 to expose the TSV and TMV.

[0107] refer to Figure 4E The main RDL 108A is formed above the upper surfaces of the potting material 242, the TSV wafer 122E, and the TMV 232. The materials, configuration, and method for forming the main RDL 108A are similar to those in the reference. Figures 2B to 2G The materials, configurations, and methods described are omitted for brevity, avoiding repetitive descriptions of the main RDL 108A.

[0108] According to some embodiments, modifications may be made. Figure 4C and 4D The sequence of processing steps is shown in the diagram. For example, firstly, multiple TSV wafers 122E are arranged above release layer 110, without TMV 232. Subsequently, potting material 242 is deposited to fill the gaps between the TSV wafers 122E and the potting material 242 is planarized. An opening step is performed by, for example, laser to form vias between the TSV wafers 122E, which are then filled with conductive material to form TMV 232. The vias may be laterally surrounded by potting material 242.

[0109] refer to Figure 4F Another carrier substrate 116 is provided or received in another semiconductor device 401W. Another release layer 120 is formed over the carrier substrate 116. Furthermore, Figure 4E The structure is flipped so that its RDL 108A side is bonded to the second carrier substrate 116 and the carrier 106 is released by using the release layer 120. Subsequently, another main RDL 108B with surface treatment and bonding pads is formed on the other side of the TSV wafer 122E, encapsulation material 242 and TMV 232 supported by the second carrier 116. The materials, configuration and method of forming the carrier substrate 116, the release layer 120 and the main RDL 108B are similar to those in the reference. Figure 2C The materials, configuration, and methods for the carrier substrate 106, release layer 110, and main RDL 108A described herein will not be repeated in detail for the sake of brevity. Furthermore, the carrier substrate 116 is removed from the semiconductor device 401W by releasing the release layer 120 after wafer mounting.

[0110] refer to Figure 4G The monomerization or dicing process is performed to separate the reconstructed structure of the semiconductor device 401W into individual IC structures 400A. Through appropriate arrangement, the TMV 232 and the edge TSV 104B are formed within the IC structure 400A and include...

[0111] - Two types of TMV after monomerization or dicing processes: internal TMV (not shown) and edge TMV 232, and

[0112] - Two types of TSVs after monomerization or cutting process: internal TSV and edge TSV 104B.

[0113] The properties of the conductive pad 212 and conductive via 214 of the main RDL 108A or 108B are similar to those of the conductive pad 212 and conductive via 214. Figure 2CThe properties of IC structure 100A shown are presented herein, and for the sake of brevity, repeated descriptions are omitted. The main difference between IC structure 400A and IC structure 100A is that IC structure 400A further includes potting material 242 filling the space between semiconductor wafer 122D and TMV 232. Semiconductor wafer 122D, TMV 232, and potting material 242 constitute the main body of IC structure 400A.

[0114] Figure 4H to 4N Cross-sectional views of IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H according to various embodiments of the present disclosure are shown respectively. Since IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H are considered variations of the base IC structure 400A in many respects, the following description will focus only on the differences between IC structure 400A and the other IC structures 400B to 400H.

[0115] refer to Figure 4H The main difference between IC structure 400B and IC structure 400A is that in IC structure 400B, the TSV wafer 122E containing the internal TSV is laterally surrounded or sealed by the potting material 242, and there is no edge TSV in IC structure 400B.

[0116] refer to Figure 4I The main difference between IC structure 400C and IC structure 400A is that IC structure 400C does not contain TMV 232. (Reference) Figure 4J IC structure 400D has neither edge TSV nor edge TMV, while both TSV and TMV exist in IC structure 400A.

[0117] Figure 4K to 4N The IC structures 400E, 400F, 400G, and 400H shown can be considered as multi-chip versions of the corresponding single-chip IC structures 400A, 400B, 400C, and 400D, with multiple chips arranged in the same package layer of IC structures 400E to 400H. (Reference) Figure 4KThe main difference between IC structure 400E and IC structure 400A is that, in addition to the first semiconductor wafer (i.e., TSV wafer 122E), IC structure 400E further includes a second semiconductor wafer 122D, which may have the same or different sizes. Therefore, the main body of IC structure 400E includes semiconductor wafer 122D, TSV wafer 122E, TMV 232, potting material 242, and RDLs 108A and 108B. Semiconductor wafer 122D and TSV wafer 122E are arranged in the same packaging layer. Semiconductor wafer 122D (which may also contain internal or edge TSVs) is laterally surrounded or encapsulated by potting material 242. Furthermore, in IC structure 400E, TMV 232 serves as an edge TMV, which can be electrically connected to the edge conductive vias 214 of the main RDL 108A and the edge conductive vias 214 of the main RDL 108B to form a stacked TSV extending through the entire thickness of IC structure 400E.

[0118] refer to Figure 4L The main difference between IC structure 400F and IC structure 400E is that in IC structure 400F, the TSV wafer 122E is further laterally surrounded or sealed by potting material 242 and IC structure 400F does not contain edge TSV.

[0119] refer to Figure 4M The main difference between IC structure 400G and IC structure 400E is that IC structure 400G, which contains edge TSV 104B, does not have edge TMV 232.

[0120] refer to Figure 4N The IC structure 400H can be considered as a combination of features of IC structures 400F and 400G, wherein the main body of the IC structure 400H only includes a semiconductor wafer 122D, a TSV wafer 122E, a potting material 242, and RDLs 108A and 108B, without edge TSVs and edge TMVs. According to some embodiments, the potting material 242 laterally surrounds and seals the semiconductor wafers 122D and 122E. The potting material 242 is exposed through two sub-planes 102S of the main body of the IC structure 400H.

[0121] Figure 5A A cross-sectional view of an IC structure 500A according to various embodiments of the present disclosure is shown. The main body of the IC structure 500A includes a semiconductor wafer 122F, a TMV 232, and a potting material 242. The semiconductor wafer 122F may include at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer. The semiconductor wafer 122F is similar to... Figure 3F The semiconductor wafer 122D1 shown is an example in which the edge conductive pads 222 are replaced by multiple TSVs 104 (including internal TSVs 104A and edge TSVs 104B), one of which is exposed through the sub-plane 500AS of the IC structure 500A. Furthermore, compared to the aforementioned IC structure, the IC structure 500A further includes a sub-RDL 118A disposed on the sub-plane 500AS and electrically connected to the main RDL 108A.

[0122] Figure 5C More detailed description of various embodiments according to this disclosure Figure 5A The diagram shows a cross-sectional view of the sub-RDL118A of the IC structure 500A. Sub-RDL118A is similar to the reference design. Figure 2G The described main RDL 108, such as main RDL 108A or 108B. Figure 5C The sub-RDL 118A shown in the image contains similar features. Figure 2G The first and second main wire / via layers 240 and 250 of the main RDL 108A or 108B, and the two main wire / via layers 340 and 350. (Reference) Figure 5C The secondary RDL 118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite to the front interconnect surface 118F. The secondary RDL 118A is electrically connected to the edge interconnect structure 118X of the IC structure 500A, such as the edge TSV 104B of the semiconductor wafer 122F or the edge conductive pad 212 of the main RDL 108A. According to some embodiments, the secondary RDL 118A is considered part of the edge interconnect structure 118X of the IC structure 500A. Using this configuration, the main RDL 108A can be electrically connected to the semiconductor wafer 122F via the main surface 102P of the substrate 102 of the IC structure 500A and the main surface 108P of the main RDL 108A facing the substrate 102 through the internal interconnect structure 108X. Furthermore, it can be electrically connected to the semiconductor wafer 122F via the side surface (sub-plane) 102S of the main body of the IC structure 500A and the front interconnect surface 118F of the sub-RDL 118A through the edge interconnect structure 118X including the edge TSV 104B and the sub-RDL 118A. Therefore, compared to an IC structure without the sub-RDL 118A and other edge interconnects, the IC structure 500A provides enhanced wiring capabilities and design flexibility for the semiconductor wafer 122F.

[0123] Figure 5BA cross-sectional view of an IC structure 500B according to various embodiments of the present disclosure is shown. The IC structure 500B is substantially similar to the IC structure 500A in many respects; therefore, for the sake of brevity, descriptions of similar features are not repeated. The main difference between the IC structure 500B and the IC structure 500A is that, in addition to the sub-RDL 118A disposed on the left sub-plane 500BS1 of the IC structure 500B, the IC structure 500B further includes a sub-RDL 118B disposed on the right sub-plane 500BS2 of the IC structure 500B opposite to the sub-RDL 118A. The material and configuration of the sub-RDL 118B may be similar to those of the sub-RDL 118A, such as... Figure 5C As described herein. However, the other configurations and numbers of the main wire / via layers of sub-RDLs 118A and 118B are also within the scope of this disclosure. Therefore, sub-RDL 118B is also considered to be part of the edge interconnect structure 118X of IC structure 500B and is electrically connected to main RDL 108A.

[0124] Figures 6A to 6E Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 600A according to various embodiments of the present disclosure are shown. According to some embodiments, Figure 6E The IC structure 600A shown is a semiconductor packaging device. The IC structure 600A can be formed from a semiconductor device 600W, which is a wafer-level device. Figure 6E The IC structure 600A is formed by separating the semiconductor device 600W through a monomerization or dicing process.

[0125] refer to Figure 6A A carrier substrate 106 is provided or received. A release layer 110 is formed above the upper surface of the carrier substrate 106. A plurality of semiconductor wafers, such as semiconductor wafers 122E, 122G, and 122H, are fabricated. The TSV wafer 122E can be replaced by the aforementioned semiconductor wafers, such as semiconductor wafers 100A, 100B, 100C, 300A, 300B, 300C, and 400A to 400H. The TSV wafer 122E includes a plurality of TSVs 104 and a main RDL 108A on the upper surface of the TSVs 104. According to some embodiments, the semiconductor wafers 122G or 122H may be a CPU wafer, a GPU wafer, a TPU wafer, a MEMS wafer, an AP wafer, an FPGA wafer, an ASIC wafer, a memory wafer, a transceiver wafer, a network interface wafer, an integrated photonics wafer, a packet buffer / router wafer, another suitable wafer, or at least one of the aforementioned semiconductor wafers.

[0126] The semiconductor wafers 122E, 122G, and 122H may be similar or different in size or dimensions. For example, semiconductor wafers 122E, 122G, and 122H may have substantially the same or different height, length, or width.

[0127] A pick-and-place process is performed to pick up a known good wafer (KGD) from semiconductor wafers 122E, 122G, and 122H and bond the KGD over release layer 110. After semiconductor wafer 122H is placed over release layer 110, a bonding layer or wafer attachment layer 160 is formed on semiconductor wafer 122H. Bonding layer 160 may facilitate attachment of semiconductor wafer 122G to semiconductor wafer 122H. According to some embodiments, bonding layer 160 is a wafer attachment film, an array of microbumps configured to perform flip-chip bonding, a direct bonding layer configured to produce a bonding, or a hybrid bonding layer. According to some embodiments, semiconductor wafers 122G and 122H are vertically stacked. Semiconductor wafer 122E may be arranged side-by-side adjacent to stacked semiconductor wafers 122G and 122H in the same package layer. Semiconductor wafers 122E, 122G, and 122H may have substantially the same or different sizes.

[0128] refer to Figure 6B A 600W semiconductor device is molded or sealed using a potting material or suitable material 252. The material and configuration of the potting material 252 are similar to those of the potting material 242 and may include a molding compound and a thick-film photoresist. A molding or deposition process is performed to deposit the potting material 252 between and embed it into semiconductor wafers 122E, 122G, and 122H. The potting material 252 may have a height greater than the height of semiconductor wafers 122E, 122G, and 122H. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry and / or wet), or another suitable etching step) is performed to remove excess potting material 252 and produce a uniform upper surface of the potting material 252 (see [link to documentation]). Figure 6B ).

[0129] Figure 6C This describes the formation of multiple vias 252R within the potting material 252. The vias can be created by laser ablation. Alternatively, if a thick-film photoresist is used as the sealing material, it can be laminated, patterned, and developed to create vias extending from the upper surface of the potting material 252 to the bonding pads, and to give the semiconductor wafers 122E, 122G, and 122H appropriate surface treatments, wherein the pads are exposed beneath the vias 252R.

[0130] refer to Figure 6DFor example, a suitably passivated conductive material is deposited in the via 252R by PVD, CVD, ALD, electroplating, or the like. The conductive material may include at least one of tungsten, copper, titanium, molybdenum, cobalt, ruthenium, tantalum, aluminum, silver, gold, and other suitable materials. Therefore, one or more conductive pillars 224 are formed above and electrically connected to the semiconductor wafer 122G. At least one conductive pillar 224 formed on the sub-plane 600AS2 of the semiconductor device 600W (currently, this sub-plane 600AS2 is still an imaginary plane before the dicing process) is configured as an edge conductive pillar 224. Furthermore, one or more conductive plugs 234 are formed above and electrically connected to the TSV wafer 122E and / or the semiconductor wafer 122H. Therefore, the main body of IC structure 600A includes semiconductor wafers 122E, 122H, and 122G, main RDL 108A, bonding layer 160, potting material 252, conductive vias 104, internal conductive pillars 224, conductive plugs 234, and edge conductive pillars 224. According to some embodiments, TSV 104, conductive pillars 224, and conductive plugs 334 have substantially the same or different lengths.

[0131] Another main RDL 108C is formed above the upper surface of the potting material 252 and is electrically connected to the semiconductor wafers 122E, 122G, and 122H. According to some embodiments, the main RDL 108C includes at least an edge conductive pad 212 on the sub-plane 600AS1 or 600AS2 of the semiconductor wafer 600W (currently, the sub-planes 600AS1 and 600AS2 are still imaginary planes before the dicing process).

[0132] Subsequently, after the wafer is mounted, the carrier substrate 106 is removed or detached from the semiconductor device 600W by removing or releasing the release layer 110 from the semiconductor device 600W. Figure 6E This demonstrates the individual IC structures 600A formed by isolating a semiconductor device 600W into individual IC structures 600A using a monomerization or dicing process. With appropriate arrangement, edge conductive pads 212, edge TSVs 104B, and edge conductive pillars 224 can be formed and exposed through at least one of the sub-planes 600AS1 and 600AS2 of the IC structure 600A. A main RDL 108C is configured to be electrically connected to semiconductor wafers 122E, 122G, and 122H via internal interconnect structures 108X (e.g., conductive plugs 234 and internal conductive copper pillars 224). Furthermore, the main RDL 108C is configured to be electrically connected to semiconductor wafers 122E, 122G, and 122H via edge interconnect structures 118X (e.g., edge TSVs 104 and edge conductive pillars 224). Therefore, wiring distances can be reduced by means of the edge interconnect structure 118X.

[0133] refer to Figure 6E and Figure 5A and 5B According to some embodiments, the secondary RDLs 118A and 118B of IC structures 500A and 500B are adapted to IC structure 600A. In other words, although not shown separately, secondary RDLs 118A or 118B can be arranged on secondary surfaces 600AS1 and 600AS2 respectively to be electrically connected to the main RDL 108C and the edge TSV 104 (in Figure 6E Use 104 instead of 104B to match Figure 6D (Consistent) and / or conductive components 202 of edge conductive posts 224. According to some embodiments, when the IC structure 600A includes edge conductive plug 234, sub-RDL 118A or 118B may be electrically connected to this edge conductive plug 234.

[0134] The embodiments of this disclosure discussed above offer advantages. The common edge conductive component 202 may appear in the form of an edge conductive pad 212, an edge conductive via 214, an edge TSV 104, or an edge TMV 224, as... Figure 6E As shown in the diagram. Additionally, the main RDL 108A and 108C or the secondary RDL 118A and 118B (see...) Figure 5B It can form conductive pads 212 with or without edges, conductive vias 214 with or without edges, conductive TSVs 104 with or without edges, and conductive vias 222 with or without edges (see...). Figure 2F and 3F ), with or without edge TMV 232 ( Figure 5B The edge conductive assembly 202 may or may not have edge conductive pillars 224 and edge conductive plugs 234. The edge conductive assembly 202 may be disposed around the periphery of the IC structure or the periphery of the RDL. Furthermore, the edge conductive via 222 may cover all or part of the thickness of the corresponding IC structure body. Additionally, edge TSV 104, edge TMV 232, edge conductive pillars 224, and edge conductive plugs 234 may appear inside the IC structure to facilitate internal interconnections of IC structures in different stacked layers and edge interconnections arranged on the sides.

[0135] Conductive pillar 224, conductive plug 234 and TMV 232 ( Figure 5BThe via is formed based on the opening and filling process steps, and can be generated by various methods, including bonding vertical conductors (e.g., Cu coated with palladium (Pd)), laser vias, and through-film photosensitive thick film (TPTF) methods. The bonding vertical conductor method follows the high-copper pillar process steps, replacing the high-copper pillar formation steps with conductor bonding. When using Pd-coated Cu, thin gold (Au) can be used as a bonding pad. In the laser via method, the IC is first bonded to the carrier substrate 106, followed by, for example, overmolding, planarization, laser via opening, Cu plating on the via sidewalls, via electroplating or filling with photosensitive polymer or solder, planarization, RDL generation, carrier release, and cutting. The TPTF process flow consists of the following sequential steps: laminating a thick photosensitive film onto the bonding IC, multiple or single exposures and development to create TMV vias (i.e., through-holes penetrating the photosensitive thick film), barrier / seed layer deposition, Cu plating, via filling as needed, backside grinding / planarization, RDL generation, carrier release, and dicing. The IC here can have both RDL and TSV. Multiple exposures provide process freedom for forming vias of different sizes and depths. TMV-related processes can accommodate multiple ICs in the xy plane and vertical z-axis, such as... Figure 6E As explained in the text. Furthermore... Figure 6E The semiconductor wafers 122E, 122H and / or 122G in the semiconductor wafers can be bonded to Figure 6A Solder bumps or copper pillar microbumps are pre-fabricated on the carrier substrate 106. After wafer bonding, overmolding can occur, followed by planarization and RDL generation.

[0136] Figures 7A to 7H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 700A according to various embodiments of the present disclosure are shown. According to some embodiments, Figure 7H The semiconductor package 700A shown is a semiconductor packaging device. The semiconductor package 700A can be formed from semiconductor devices 700W and 701W, which are wafer-level devices. The semiconductor package 700A is formed by separating the semiconductor device 701W through a monomerization or dicing process.

[0137] Figures 7A to 7C This illustrates that multiple IC structures 142 form a multi-high IC stack 322. (Reference) Figure 7A The carrier substrate or support substrate 106 is provided or received. A release layer 110 is formed above the upper surface of the carrier substrate 106. A pick-and-place process is performed to pick up multiple known good IC structures 142 (e.g., IC structure 142A) and to bond the IC structures by means of a bonding layer to form a first layer (e.g., a low-profile IC stack 312) at a suitable spacing above the release layer 110. Figure 7A(As shown in the figure) to improve yield. According to some embodiments, IC structure 142 may be composed of IC structures 400A, 400B, 400C, 400D, 400E, 400F, 400G, 400H, 500A, 500B and / or 600A; however, other types of IC structures (e.g. IC structures 100A, 100B, 100C, 300A, 300B, 300C and / or similar) are also possible. Figure 7B The IC structure 142, which is illustrated for demonstration purposes and includes 142A, 142B, 142C, and 142D, may contain memory and / or processor analog chips. The IC structure 142 may also include MEMS devices, passive devices, and analog, mixed-signal, and digital signal processing ICs.

[0138] refer to Figure 7B Multiple IC structures 142 (e.g., IC structure 142B) are bonded to corresponding IC structures 142A to form a second layer of a low-profile IC stack 312. Bonding IC structures 142B to IC structures 142A can be achieved using thermocompression bonding (TCB), flip-chip bonding, hybrid bonding, direct bonding, bonding via an adhesive layer (e.g., Ti / Au), wafer attachment film or paste, or other suitable bonding processes. The process of forming the low-profile IC stack 312 can continue until a predetermined number of layers (total number of layers) K is reached, where the number of layers K is a natural number. Figure 7B In the example depicted, the number of levels K is 4, meaning that each dwarf IC stack 312 consists of four stacked IC structures 142A, 142B, 142C, and 142D. This process produces a known good dwarf IC stack. Alternatively, a dwarf IC stack 312 can be formed by joining multiple 142Ds to multiple 142Cs, wherein the resulting structures are further processed as needed and then released, a known good structure is picked up, a known good structure is joined to multiple known good 142Bs, and so on, and the process is repeated until... Figure 7B A short IC stack 312 is formed in the middle.

[0139] After the first low-profile IC stack 312 is completed, a release (or bonding) layer 140 of suitable thickness is formed over each low-profile IC stack 312. The material of the release layer 140 may differ from the material of the release layer 110 to avoid interference between them during the respective release process. Subsequently, another set of known good low-profile IC stacks 312 is formed over the release layer 140 of the first known good low-profile IC stack 312. Figure 7B As shown, the formation of the low-profile IC stack 312 and the formation of the release layer 140 are performed alternately until a predetermined L low-profile IC stacks are reached to form Figure 7CThe high IC stack 322 is formed by stacking the low IC stacks 312, where the number of low IC stacks L (i.e., the total number of low IC stacks) is a natural number. In the depicted example, the number of low IC stacks L is 4. Therefore, the low IC stacks 312 are stacked to form the high IC stack 322 through the release layer 140.

[0140] refer to Figure 7C Each high IC stack 322 is released from the carrier substrate 106 by releasing the release layer 110. Therefore, four low IC stacks 312 and three release layers 140 are arranged alternately to form a row of high IC stacks 322. In the depicted example, there are three rows of high IC stacks 322 in the semiconductor device 700W. The numbers K, L, and row number introduced above are for illustrative purposes. Other numbers are also within the scope of this disclosure.

[0141] Figures 7D to 7H This describes a semiconductor package 700A formed by stacking multiple high-performance ICs (322). (Reference) Figure 7D The carrier substrate 116 is provided or received. A release layer 120 is formed above the upper surface of the carrier substrate 116. A pick-and-place process is performed to pick up and join multiple known good high-quality IC stacks 322 and arrange them at appropriate spacing above the release layer 120 to improve yield. The high-quality IC stacks 322 are reconstructed on the carrier substrate 116 and bonded to the release layer 120 through their side surfaces. In other words, the high-quality IC stacks 322 are laid down such that the vertically stacked IC structures 142 in the high-quality IC stacks 322 are positioned upright in the xy plane or in the IC length and width directions, with one of their four side surfaces bonded to the release layer 120.

[0142] refer to Figure 7E The reconstructed high IC stack 322 of the semiconductor device 701W is molded or sealed using potting material 262. The material and configuration of potting material 262 are similar to those of potting materials 242 or 252. A molding or deposition process is performed to deposit potting material 262 between the laid-down high IC stack 322. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry and / or wet) or another suitable etching step) is performed to remove excess potting material 262 and planarize the upper surface of potting material 262 so that it is flush with the side surface of the high IC stack 322. Subsequently, an edge interconnect structure RDL 118A is formed over or bonded to at least the edge interconnects on the side surface (sub-plane) of the high IC stack 322.

[0143] Figure 7FThe diagram illustrates the formation of another edge interconnect structure RDL 118B on the opposite surface of the high IC stack 322, opposite to sub-RDL 118A. Another carrier substrate 126 is provided or received in another semiconductor device 702W. Another release layer 130 is formed over the carrier substrate 126 to facilitate the formation of sub-RDL 118B. The materials, configuration, and methods for forming the carrier substrate 126 and sub-RDLs 118A and 118B are similar to those described above. Figure 5B The sub-RDL 108A and 108B described in the document Figure 2C The main RDLs 108A and 108B are used in this context, so for the sake of brevity, details of such similar features will not be repeated. The material of release layer 130 may differ from that of release layer 120 to avoid interference between them during the respective release processes. Subsequently, in Figure 7E After the semiconductor structure 701W is bonded to the second carrier 126 on the side of RDL 118A, the carrier substrate 116 is removed from the semiconductor device 701W by removing the release layer 120. The edge interconnect RDL structure 118B is formed or bonded to the lower sub-surface of the high IC stack 322, which is opposite to the upper sub-surface of the high IC stack 322.

[0144] refer to Figure 7G A monomerization or dicing process is performed to isolate the semiconductor device 701W into a high-IC stack structure 700L. The monomerization or dicing process may be performed to cut through the semiconductor device 701W at the location of the potting material 262, wherein the potting material 262 is cleaned by, for example, dry and / or wet etching, while taking care to keep each high-IC stack 322 intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove residual potting material 262 remaining on the high-IC stack structure 700L.

[0145] Figure 7H This describes the formation of individual semiconductor packages 700A (i.e., low-profile IC stacked structures) from corresponding IC structures (i.e., high IC stacked structures 700L). Release processes, monomerization processes, and / or dicing processes are performed to separate release layers 140 from each of the high IC stacked structures 700L. Figure 7B This allows the different semiconductor packages 700A (i.e., the respective low-profile IC stacks 312 containing edge interconnect RDL structures 118A and 118B) to be separated from each other. According to some embodiments, etching or dicing processes are performed to facilitate the release process, such as by dicing, continuous-wave laser beam, dry etching (e.g., by plasma), and / or wet etching to cut through the sub-RDLs 118A and 118B at the location of the release layer 140. Figure 7HAs described, the semiconductor package 700A includes a stack of low-profile IC stack 142 and two sub-RDLs 118A and 118B disposed on two side surfaces of the low-profile IC stack 142. Sub-RDLs 118A and 118B can help increase the wiring area of ​​IC structure 142, reduce wiring distance, and improve the wiring capability and design flexibility of semiconductor package 700A.

[0146] Figure 7I and 7J Cross-sectional views of semiconductor packages 700B and 700C according to various embodiments of the present disclosure are shown. Semiconductor packages 700B and 700C can be considered as detailed versions of semiconductor package 700A, with some minor variations. For example, refer to... Figure 7I The semiconductor package 700B includes three IC structures 142A, 142B, and 142C stacked vertically. Each IC structure 142A, 142B, or 142C includes a corresponding body and a corresponding main RDL 108A, 108B, or 108C disposed on a corresponding upper main surface 142AP, 142BP, or 142CP on its top side. The body of IC structure 142A includes a semiconductor wafer 143A, an edge TMV 232, an edge TSV 104, and a potting material 242, wherein the semiconductor wafer 143A includes a plurality of TSVs 104 and a plurality of TMVs 232. Similarly, the body of IC structure 142B includes a semiconductor wafer 143B, an edge TMV 232, and a potting material 242, wherein the semiconductor wafer 143B includes a plurality of TSVs 104 and a plurality of TMVs 232. Similarly, the main body of IC structure 142C includes a semiconductor wafer 143C, edge TMV 232, and encapsulation material 242, wherein the semiconductor wafer 143C includes multiple TSVs 104 and multiple TMVs 232. IC structures 142A, 142B, and 142C may be of different sizes and may contain various combinations of internal and edge interconnects covering the TSVs and TMVs. According to some embodiments, semiconductor wafers 143A, 143B, or 143C may be at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer (e.g., an interconnect wafer, such as an interposer). According to some embodiments, semiconductor package 700B includes only a single sub-RDL 118A disposed on the left sub-plane 700BS of semiconductor package 700B.

[0147] According to some embodiments, IC structures 142A, 142B, and 142C are characterized by substantially equal or unequal thicknesses T1, T2, and T3, respectively. Each IC structure 142A, 142B, or 142C may contain a thickness ranging from about 30 μm to about 775 μm.

[0148] Sub-RDL 118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite to the front interconnect surface 118F. Sub-RDL 118A is electrically connected to the sub-plane 700BS via the front interconnect surface 118F to facilitate wiring efficiency and flexibility. For example, sub-RDL 118A includes conductive traces or wires 172 that extend along the longitudinal axis of sub-RDL 118A and electrically connect the edge conductive pads 212 of the main RDL 108C and the edge TSV 104B of semiconductor wafers 143C and 143A, while bypassing the bodies of IC structures 142A, 142B, and 142C. Furthermore, sub-RDL 118A can be used to connect other circuitry via the rear interconnect surface 118R. For example, sub-RDL 118A includes one or more conductive bumps, microbumps, or bump pad arrays 244 (all of which are external connections referred to as sub-RDL 118A) on the back interconnect surface 118R, wherein the conductive bumps 244 are configured to electrically connect sub-RDL 118A to circuitry or layers adjacent to sub-RDL 118A.

[0149] refer to Figure 7J Semiconductor package 700C is similar to semiconductor package 700B in many respects, and for the sake of brevity, descriptions of such similar features will not be repeated. According to some embodiments, semiconductor package 700C includes three IC structures 142D, 142E, and 142F stacked together, wherein each IC structure 142D, 142E, or 142F includes a respective body and two respective main RDLs 108A / 108D, 108B / 108E, and 108C / 108F disposed on respective upper and lower main surfaces 142AP, 142BP, and 142CP.

[0150] The difference between semiconductor package 700C and semiconductor package 700B is further that, in the case of 700C, the sub-RDL 118A disposed on the sub-plane 700CS1 of semiconductor package 700C includes an array of conductive pads 254 on the rear interconnect surface 118R of sub-RDL 118A. According to some embodiments, the conductive pads 254 have an upper surface coplanar with the rear interconnect surface 118R of sub-RDL 118A. This coplanar arrangement of sub-RDL 118A facilitates hybrid bonding with other circuits or layers. Additionally, compared to semiconductor package 700B, semiconductor package 700C further includes another sub-RDL 118B disposed on the sub-plane 700CS2. The interconnect configuration in sub-RDL 118B may be similar to or different from the interconnect configuration in sub-RDL 118A. Sub-RDL 118B may include external connections, such as microbumps, hybrid bonding layers, direct bonding layers, flexible circuit connections (details of which are referenced below). Figure 9A Provided), combinations thereof, or similar. Furthermore, the secondary RDL 118A (or 118B) includes conductive traces or wires 172 extending along the longitudinal axis of the secondary RDL 118A and electrically connecting the edge conductive pads 212 of the main RDLs 108C and 108B and the edge conductive vias 214 of the main RDL 108D, while bypassing the bodies of the IC structures 142D, 142E, and 142F to achieve power supply and signal transmission across the chip and multiple surfaces.

[0151] According to some embodiments, IC structures 142D, 142E, and 142F have substantially equal or unequal thicknesses T4, T5, and T6, respectively. Each IC structure 142D, 142E, or 142F may contain a thickness ranging from about 30 μm to about 775 μm.

[0152] Semiconductor packages 700A, 700B, and 700C allow for power supply and signal transmission across the die and multiple sides via an internal interconnect structure 108X covering the TMV, main RDL 108, and TSV; an edge interconnect structure 118X covering the secondary RDL 118 and edge interconnects; and both the internal interconnect structure 108X and the edge interconnect structure 118X. These semiconductor packages with multi-sided power supply and signal transmission enable “PPAC optimization per cubic millimeter” for 3D ICs (using low-profile IC stacks as an example in this paper), where the vertical dimension of the 3DIC can be extended to cover the IC, interposer, IC packaging substrate, IC package, and system PCB (e.g., see...). Figure 7I , 7J 12C, 13C, 14A and 14B).

[0153] Figures 8A to 8ECross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 800A according to various embodiments of the present disclosure are shown. Figures 8A to 8E The steps shown in the document are similar in many ways to Figures 7D to 7H The steps shown in the document will be repeated for the sake of brevity. Figures 8A to 8E The steps shown in the document are Figures 7D to 7H The main difference between the steps shown in the document is: Figures 7D to 7H The edge interconnect RDL structures 118A and 118B in the original are replaced by edge interconnect RDL structures 138A and 138B, which are formed by bonding flexible printed circuits (flexible circuits) to the side surfaces of low-profile and high-profile IC stacks. The flexible circuits may be formed from multiple conductive line layers (not shown separately), each containing conductive lines of an IMD layer and materials (e.g., polyimide or benzocyclobutene (BCB)) for electrically insulating the conductive lines. The flexible circuits may further include bonding pads (not shown separately) formed of gold, solder, or other suitable bonding materials. The flexible circuits offer the advantages of bendability and high-density, fine-pitch bonding pads (pitch as low as approximately 10 μm), and are therefore suitable for the sub-RDLs 138A and 138B of the edge interconnect structure 118X.

[0154] Figure 9A Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 900A according to various embodiments of the present disclosure are shown. A cross-sectional view of a semiconductor device 900W is also shown. Figure 8C A detailed representation of the semiconductor device 802W shown in the image. Figure 9A As can be seen, the semiconductor device 900W includes two interconnect layers 150, such as a first interconnect layer 150A disposed between the molded high IC stack 322 and the edge interconnect structure 118A, and a second interconnect layer 150B disposed between the molded high IC stack 322 and the edge interconnect structure 118B. According to some embodiments, interconnect layers 150A or 150B may include an array of flexible circuit connectors 154 and a non-conductive filler 152 sealing the flexible circuit connectors 154. The flexible circuit connectors 154 are bonded to the subplane 900AS of the low IC stack 312. Figure 9B Flexible circuit connector 154 may contain a conductive material, such as copper, tin, gold, or other conductive materials suitable for bonding. Non-conductive filler 152 may be a sealant, such as a non-conductive adhesive (NCA), a non-conductive film, a non-conductive paste (NCP), or a sealant in a wafer-on-film (CoF) package for a driver IC in a display application. The sealant or non-conductive filler 152 may fill the spaces between flexible circuit connectors 154 and between the sub-plane 900AS and the corresponding connection layers 150A and 150B. Reference Figure 9BAfter the monomerization or dicing process, individual low-profile IC stacked structures 900A are formed by semiconductor device 900W.

[0155] Flexible circuits with multiple (e.g., two) metal (copper, Cu) layers based on polyimide dielectrics offer excellent interconnect solutions for high-speed applications. Because flexible circuits can be mechanically shaped and bent, they can also be used to interconnect metal pads not only on one side but also on multiple sides. Flexible circuits provide high-density interconnects (pitch as low as 20 μm and even as low as 10 μm), DC power distribution, integrated I / O (inputs and outputs), power delivery, decoupling, and electromagnetic compatibility. All of the aforementioned desirable properties associated with flexible circuits can be tested prior to bonding to ensure they are known to be good enough to make flexible circuits (especially adhesive-free flexible circuits) ideal candidates for 3D IC edge interconnects covering one or more sides. For example, in COF bonding for liquid crystal display applications, adhesive-free flexible circuits with Cu leads (which may be pre-plated with tin, Sn) are bonded using thermocompression bonding (TCB) to, for example, gold bumps, Sn bumps, or tin / copper (Sn / Cu) bumps on glass for applications such as mobile phones. Solvent-free epoxy-based underfill can be applied after bonding to avoid bubbles, which can be associated with improperly baked solvent-based underfill. Alternatively, in a manner similar to fine-pitch flip-chip microbump assemblies, non-conductive adhesive (NCA) or non-conductive paste (NCP) can be applied before bonding to the glass, followed by TCB. For edge interconnects of low-profile 3DIC stacks using flexible circuitry, bumps can be first created on edge pads, edge vias, edge TSVs, and / or edge TMVs, and then the flexible circuitry can be bonded to the bumps on one or more sides using thermoforming and NCA. Pre-baking of the circuitry system can be performed before flexible bonding to ensure no delamination occurs. Flexible circuitry can also be used to interconnect metal pads and RDLs on different sides of low-profile 3DIC stacks. Metal pads on bonding flexible circuitry on different sides can be interconnected using, for example, flexible circuitry with leads / pads containing palladium (Pd) passivation for flexible-to-flexible bonding at low temperatures, such as 140°C.

[0156] Figures 10A to 10H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1000A according to various embodiments of the present disclosure are shown. Figures 10A to 10H The steps shown in the document are similar in many ways to Figures 7D to 7H The steps shown in the document are presented here, and for the sake of brevity, descriptions of similar features will not be repeated. (See references.) Figure 10AA semiconductor device 1001W is provided. The semiconductor device 1001W includes a carrier substrate 106 and a release layer 110 above the carrier substrate 106. Multiple high-performance IC stacks 422 are fabricated and arranged on the release layer 110. Each high-performance IC stack 422 is arranged in a manner similar to a reference... Figures 7A to 7C The steps described are formed in a manner that allows for their arrangement. In other words, each high-IC stack 422 contains multiple release layers 140 (see...). Figure 10G Multiple low-profile ICs stacked alternately for 1000A (see...) Figure 10H In addition, each low-profile IC stack 1000A contains multiple IC structures 162 (e.g., Figure 10H The IC structures shown are 162A, 162B, 162C, and 162D. Figures 7D to 7H The main difference between IC structure 162 and IC structure 142 is that IC structure 162 includes edge conductive pads 282 disposed on two side surfaces of the corresponding IC structure 162, such as edge conductive pads 282A and 282B. Figure 10B The edge conductive pads 282A and 282B can be similar to the IC structure 100A. Figure 2D The edge TSV104B, edge conductive via 214 or edge conductive pad 212, IC structure 300C in the ) Figure 3F The edge TMV 232 or similar in the IC structure 162 is arranged in a manner similar to that of the edge TMV 232 or similar in the IC structure 162.

[0157] refer to Figure 10B The semiconductor device 1001W (i.e., high IC stack 422) is similar to Figure 7E The method shown uses potting material 262 for molding or encapsulation and is planarized. (Reference) Figure 10C In semiconductor device 1002W, another carrier substrate 126 is provided, and another release layer or sacrificial layer 120 is formed over the carrier substrate 126. A sub-RDL 148A is formed over the release layer or sacrificial layer 120, wherein the sub-RDL 148A includes an array of conductive pads 264 on the upper surface of the sub-RDL 148A. According to some embodiments, semiconductor device 1001W is bonded to the RDL 148A supported by the carrier substrate 126 to form semiconductor device 1002W by a hybrid or flip-chip bonding process. Semiconductor device 1001W may include a bonding surface formed by a metal surface of conductive pad 282A and a dielectric surface that is substantially similar to or different from the dielectric surface of the sub-RDL 148A. Similarly, the sub-RDL 148A includes a bonding surface formed by a metal surface of matching conductive pad 264 and a dielectric surface of the IMD layer of the sub-RDL 148A. Perform hybrid bonding to form metal-to-metal bonding and dielectric-to-dielectric bonding at the interface of the bonding surfaces of semiconductor device 1001W and sub-RDL 148A.

[0158] refer to Figure 10D The carrier substrate 126 is removed or detached from the semiconductor device 1002W by releasing the release layer 120. According to some embodiments, see reference... Figure 10C The carrier substrate 126 includes a plurality of holes 124 extending through the thickness of the carrier substrate 126. The holes 124 facilitate the release of the carrier substrate 126 from the semiconductor device 1002W by wet chemical processing.

[0159] Figure 10C The release or sacrificial layer 120 can be made of a mixture of metals and non-metals. Metal candidates may include nickel (Ni), chromium (Cr), titanium (Ti), copper (Cu), manganese (Mn), iron (Fe), cobalt (Co), tungsten (W), molybdenum (Mo), and tantalum (Ta), while non-metal candidates may include metal oxides, phosphates, and chromates. Preferred mixtures include chromium and chromium oxide, and nickel and nickel oxide. Deposition methods include vapor deposition, sputtering, electroplating, and dip plating. Many types of sacrificial layers for MEMS processing are also considered: metallic materials such as Cu, Al (aluminum), Ti, and Cr; and non-metallic materials such as silica, polycrystalline silicon, and polymers such as poly(methyl methacrylate), polyimide, and photoresists (including photosensitive polyimide). The release layer can be very thin, for example, less than 0.3 μm thick. Chromium oxide (Cr₂O₃) offers several desirable properties as a sacrificial layer: it can be sputtered to form stress-controlled films hundreds of nanometers thick; it adheres well to both dielectric and metal surfaces; it is resistant to most acids and alkalis; it etchs rapidly in standard chromium etchants; and it reacts little with other commonly used materials, even at high temperatures. To facilitate subsequent removal by etching, vias can be created in the substrate to expose the release layer and accelerate wet chemical removal.

[0160] Figure 10EThe formation of the secondary RDL 148B is explained. In semiconductor device 1003W, another carrier substrate 136 with vias 134 is provided, and another release or sacrificial layer 130 is formed over the carrier substrate 136. The secondary RDL 148B is formed over the release layer 130, wherein the secondary RDL 148B includes an array of conductive pads 274 on its upper surface. Semiconductor device 1002W is bonded to carrier substrate 136 via the release layer 130, as in 1001W, and after releasing carrier substrate 106, is bonded to semiconductor device 1003W, while being supported by carrier substrate 136 for wafer-level bonding through a hybrid bonding process. Semiconductor device 1003W includes a bonding surface formed by the metal surface of conductive pads 282B and a dielectric surface substantially similar to or different from that of the secondary RDL 148B. Similarly, the secondary RDL 148B includes a bonding surface formed by the metal surface of the conductive pad 274 and the matching dielectric surface of the IMD layer of the secondary RDL 148B. A hybrid bonding process is performed to form a metal-to-metal bond and a dielectric-to-dielectric bond at the interface between the bonding surfaces of the semiconductor device 1003W and the secondary RDL 148B. After bonding, the carrier substrate 136 is released from the semiconductor structure 1003W (see...). Figure 10F Furthermore, the semiconductor structure 1003W is mounted on a wafer, and the carrier substrate 136 is removed to leave... Figure 10F The semiconductor structure 1003W shown is mounted on a wafer mounting frame and is ready to be monomerized or cut from the semiconductor device 1003W.

[0161] refer to Figure 10G Next, a monomerization or dicing process is performed to isolate the semiconductor device 1003W into individual IC structures 1000L, i.e., high IC stacks. Monomerization or dicing processes involving dicing, laser ablation, plasma etching, dry etching, wet etching (e.g., acid etching), wet cleaning, or combinations thereof can be performed to cut through the semiconductor device 1003W at the location of the potting material 262 to separate the semiconductor structure 1003W ( Figure 10F Release high IC stack 422 ( Figure 10G Sub-RDLs 148A and 148B can be facilitated by forming a release layer 140 at a cut or monomerization channel between adjacent low IC stacks.

[0162] Figure 10HThe diagram illustrates the formation of individual semiconductor packages 1000A, i.e., low-profile IC stacks, from corresponding IC structures 1000L. A release process is performed to remove release layers 140 from each of the IC structures 1000L, thereby separating the semiconductor packages 1000A (i.e., the low-profile IC stack 332 containing sub-RDLs 148A and 148B) from each other. According to some embodiments, a monomerization or dicing process involving laser irradiation, thermomechanical shearing, dicing, laser ablation, plasma etching, dry etching, wet etching (e.g., acid etching), wet cleaning, or combinations thereof is performed to facilitate the release process by cutting through the sub-RDLs 148A and 148B at the location of the release layers 140. The sub-RDLs may be formed such that they are not present at the release layers 140 in the dicing paths between adjacent low-profile IC stacks to facilitate monomerization. Figure 10H As described, the semiconductor package 1000A includes a stack of IC structures 162 and two sub-RDLs 148A and 148B disposed on two side surfaces of the stack of IC structures 162. Sub-RDLs 148A and 148B help increase the wiring area of ​​IC structures 162, reduce wiring distance, and improve the wiring capability and flexibility of the semiconductor package 1000A.

[0163] Figure 11A A cross-sectional view of a semiconductor package 1100A according to various embodiments of the present disclosure is shown. The semiconductor package 1100A is similar to the semiconductor package 1000A in many respects, and such similar features are not repeated for the sake of simplicity. The semiconductor package 1100A includes IC structures 162A, 162B, 162C, and 162D, and sub-RDLs 148A and 148B. The semiconductor package 1100A further includes a first bonding layer 322L1 and a second bonding layer 322L2 disposed on two opposing sub-planes 1100AS1 and 1100AS2, respectively, for performing edge interconnects. The first bonding layer 322L1 includes a first bonding surface on the sub-plane 1100AS1. The second bonding layer 322L2 includes a second bonding surface on the sub-plane 1100AS2. The sub-RDL 148A faces the sub-plane 1100AS1, wherein the sub-RDL 148A includes a first bonding layer 148L1 configured to bond to the first bonding layer 322L1. Similarly, sub-RDL 148B faces sub-plane 1100AS2, wherein sub-RDL 148B includes a second bonding layer 148L2 configured to bond to the second bonding layer 322L2.

[0164] According to some embodiments, the first bonding layer 322L1 is bonded to the first bonding layer 148L1 via a hybrid bonding process. The first bonding layer 322L1 includes a bonding surface formed by the metal surface of the conductive pad 282A and the dielectric surface of the dielectric material of the first bonding layer 322L1 (e.g., the IMD layer of the first bonding layer 322L1). Similarly, the sub-RDL 148A includes a first bonding surface formed by the metal surface of the conductive pad 264 and the dielectric surface of the IMD layer of the sub-RDL 148A. Hybrid bonding is performed to form a metal-to-metal bond and a dielectric-to-dielectric (e.g., oxide-to-oxide or polyimide-to-polyimide) bond at the interface of the first bonding surfaces of the first bonding layers 322L1 and 148L1. In cases where hybrid bonding is employed, the first bonding layers 322L1 and 148L1 are referred to herein as hybrid bonding layers.

[0165] Similarly, according to some embodiments, the second bonding layer 322L2 is bonded to the second bonding layer 148L2 via a hybrid bonding process. The second bonding layer 322L2 includes a second bonding surface formed by the metal surface of the conductive pad 282B and the dielectric surface of the dielectric material of the second bonding layer 322L2 (e.g., the IMD layer in the second bonding layer 322L2). Similarly, the sub-RDL 148B includes a second bonding surface formed by the metal surface of the conductive pad 274 and the dielectric surface of the IMD layer of the sub-RDL 148B. Hybrid bonding is performed to form metal-to-metal and dielectric-to-dielectric (e.g., oxide-to-oxide or polyimide-to-polyimide) bonds at the interface of the second bonding surfaces of the second bonding layers 322L2 and 148L2. In cases where hybrid bonding is employed, the second bonding layers 322L2 and 148L2 are referred to herein as hybrid bonding layers.

[0166] According to some embodiments, a first bonding layer 322L1 includes an array of microbumps 282A protruding from a bonding surface of the first bonding layer 322L1, and a first bonding layer 148L1 includes an array of bonding pads (or microbumps) 264 or bonding pads protruding from a first bonding surface of the first bonding layer 148L1, wherein the bonding pads match the bonding pads of the microbumps 282A. The first bonding layer 322L1 is bonded to the first bonding layer 148L1 via flip-chip bonding. An underlayer filler (e.g., an epoxy-based material, a non-conductive paste, or a non-conductive film) may be distributed between the first bonding layers 322L1 and 148L1 to fill the space between the microbumps 282A and the bonding pads 264. Similarly, according to some embodiments, a second bonding layer 322L2 includes an array of microbumps 282B protruding from a second bonding surface of the second bonding layer 322L2, and a second bonding layer 148L2 includes an array of bonding pads (or microbumps) 274 corresponding to the microbumps 282B. The second bonding layer 322L2 is bonded to the second bonding layer 148L2 via flip-chip bonding. An underlayer filler (e.g., an epoxy-based material, a non-conductive paste, or a non-conductive film) may be distributed between the second bonding layers 322L2 and 148L2 to fill the space between the microbumps 282B and the bonding pads 274. In the case where flip-chip bonding is employed, the first bonding layers 322L1, 148L1 and the second bonding layers 322L2, 148L2 are referred to herein as flip-chip bonding layers.

[0167] According to some embodiments, at least one of the sub-RDLs 148A and 148B includes a third bonding layer 148L3 on a third bonding surface 148S1 opposite to the sub-planes 1100AS1 and 1100AS2 or the aforementioned first / second bonding surfaces. Figure 11A Only a third bonding layer 148L3 in sub-RDL 148B is described. The third bonding layer 148L3 may include conductive pads 284 or microbumps 284 on the third bonding surface 148S1, the configuration of which is similar to the configuration of the first bonding layer 148L1 or the second bonding layer 148L2 depending on the application, and the third bonding layer 148L3 is configured to be suitably used for hybrid bonding, flip-chip bonding or flexible bonding to another circuit or device.

[0168] Figure 11BA cross-sectional view of a semiconductor package 1100B according to various embodiments of the present disclosure is shown. Semiconductor package 1100B is similar to semiconductor package 1100A in many respects, and such similar features are not repeated for the sake of simplicity. The main difference between semiconductor package 1100B and semiconductor package 1100A is that semiconductor package 1100B includes a fourth bonding layer 148L4 instead of the third bonding layer 148L3 of semiconductor package 1100A. The fourth bonding layer 148L4 may be disposed in a sub-RDL 148A or 148B on a bonding surface 148S1, wherein bonding pads protrude from surface 148S1 opposite to sub-planes 1100BS1 or 1100BS2. Furthermore, the fourth bonding layer 148L4 includes an array of bonding pads 286 disposed on the bonding surface 148S1 of the sub-RDL 148B. The array of bonding pads of the fourth bonding layer 148L4 can be used to perform flip-chip bonding or other suitable bonding processes with adjacent circuitry or devices. Depending on the bonding configuration, the third bonding layer 148L3 or the fourth bonding layer 148L4 is referred to as a hybrid bonding layer or a flip-chip bonding layer.

[0169] Figures 12A to 12C Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1200A according to various embodiments of the present disclosure are shown. Reference Figure 12A A carrier substrate 106 is provided or received in a semiconductor device 1200W. A release layer 110 is formed above the upper surface of the carrier substrate 106. A pick-and-place process is performed to pick up and bond a plurality of known good IC structures 142 (e.g., IC structure 142A) and arrange them at appropriate spacing in a first layer of a corresponding low-profile IC stack 312 above the release layer 110. According to some embodiments, the IC structure 142 may be IC structure 500A, 500B, or 600A; however, other types of IC structures (e.g., IC structures 100A, 100B, 100C, 300A, 300B, 300C, or the like) are also possible. Another plurality of IC structures 142 (e.g., IC structure 142B) are bonded to a corresponding IC structure 142A to form IC structures 142 in a second layer of the corresponding low-profile IC stack 312. The bonding between IC structures 142A and 142B can be performed using flip-chip bonding, hybrid bonding, wafer attachment, or another suitable bonding process. The process of forming the dwarf IC stack 312 can continue until a predetermined number of levels K is reached, where K is a natural number. In the depicted instance, the number of levels K is 4. This means that each dwarf IC stack 312 includes four stacked IC structures 142A, 142B, 142C, and 142D.

[0170] refer to Figure 12BThe semiconductor device 1200W is molded or sealed using potting material 242. A molding or deposition process is performed to deposit the potting material 242 between the low-profile IC stacks 312. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry (e.g., by RIE) and / or wet) and / or another suitable etching step) is performed to remove excess potting material 242 and planarize the upper surface of the potting material 242 to be flush with the main surface of the low-profile IC stack 312. Subsequently, an array of microbumps 302 is formed above the main surface of the low-profile IC stack 312 or the top wafer (e.g., IC structure 142D) to serve as part of the internal interconnect structure 108X of the low-profile IC stack 312.

[0171] refer to Figure 12C A monomerization or dicing process is performed to isolate the semiconductor device 1200W into individual semiconductor packages 1200A. The monomerization or dicing process can be performed to cut through the semiconductor device 1200W at the location of the potting material 242, while keeping each low-profile IC stack 312 intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove residual potting material 242 remaining on the semiconductor package 1200A.

[0172] Figures 13A to 13C Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1300A according to various embodiments of the present disclosure are shown. Reference Figure 13A A carrier substrate 106 is provided or received in the semiconductor device 1300W. A release layer 110 is formed above the upper surface of the carrier substrate 106. A plurality of low-profile IC stacks 312 are fabricated in a separate process, each of the low-profile IC stacks 312 including, for example, four stacked IC structures 142A, 142B, 142C, and 142D, and the low-profile IC stacks 312 are formed by the aforementioned process. The low-profile IC stacks 312 are arranged on the release layer 110 at a suitable spacing. The main difference between the steps for manufacturing semiconductor package 1300A and the steps for manufacturing semiconductor package 1200A is: Figure 13A The low-profile IC stack 312 shown is arranged in a vertical orientation and in Figure 13A and 13B One side surface is exposed upwards. In other words, the main surfaces of the ICs in the low IC stack 312 face each other in the horizontal direction.

[0173] refer to Figure 13B , in a similar reference Figure 12B The described method uses potting material 242 to mold or seal the semiconductor device 1300W. Subsequently, an array of microbumps 302 is formed above the side surface of the low-profile IC stack 312 as part of the edge interconnect structure 118X of the low-profile IC stack 312.

[0174] refer to Figure 13C A monomerization or dicing process is performed to isolate the semiconductor device 1300W into individual semiconductor packages 1300A. A monomerization or dicing process may be performed to cut through the semiconductor device 1300W at the location of the potting material 242 to release the low-profile IC stack 312 from the potting material 242. According to some embodiments, a wet etching or cleaning process is performed to remove residual potting material 242 remaining on the semiconductor package 1300A.

[0175] Figure 13D Various embodiments according to this disclosure are shown. Figure 13C The image shows a perspective view of semiconductor package 1300A. Semiconductor package 1300A is an exemplary low-profile IC stack structure with six side surfaces, including an upper main surface 312P1, a lower main surface 312P2, and four lateral side surfaces 312S1, 312S2, 312S3, and 312S4 between the two main surfaces 312P1 and 312P2. Semiconductor package 1300A further includes edge conductive components 302, such as edge conductive pads, edge conductive vias, edge conductive bumps, microbumps, and / or hybrid bonding pads, distributed on the side surfaces of four IC structures 142A, 142B, 142C, and 142D. Semiconductor package 1300A also includes edge conductive traces or wires 304 and 306. Conductive traces 304 can be configured as adjacent die interconnects and for interconnecting the edge conductive components of adjacent IC structures 142 (e.g., IC structures 142B and 142C). Furthermore, the conductive trace 306 can be configured to span the die interconnect and interconnect edge conductive components of non-adjacent IC structures 142 (e.g., IC structures 142A and 142C), while bypassing the body of IC structure 142B. With this configuration, the semiconductor package 1300A offers shorter wiring distances, higher wiring efficiency, and greater flexibility compared to existing semiconductor packages lacking the edge interconnect structure 118X.

[0176] Figure 14A A cross-sectional view of a semiconductor package assembly 1400A according to various embodiments of the present disclosure is shown. The semiconductor package assembly 1400A includes a substrate 1410, a carrier 1420, a first semiconductor package 1430, and a second semiconductor package 1440, all of which are bonded to each other.

[0177] According to some embodiments, the carrier 1420 may be a silicon interposer or a laminated substrate, and the substrate 1410 may be a laminated substrate or a printed circuit board (PCB). The substrate 1410 may be formed of a first addendum layer 1412, a second addendum layer 1414, and a core layer 1416 sandwiched between the first addendum layer 1412 and the second addendum layer 1414. Each of the first addendum layer 1412 and the second addendum layer 1414 is formed of one or more conductive / dielectric layers containing copper or other suitable conductive materials. The conductive materials are insulated from each other by insulating materials (e.g., BT, ABF, polyimide, FR-4, or the like). The core layer 1416 may be formed of one or more dielectric materials (e.g., glass, resin, or the like). The core layer 1416 may include plated vias 1418 formed of a conductive material such as copper and configured to be electrically connected to the first addendum layer 1412 and the second addendum layer 1414. The semiconductor package assembly 1400A further includes an external electrical connection 1413 for connection to a next-stage substrate (not shown). The external connection 1413 may be a microbump, solder bump, ball grid array ball, substrate grid array pad, or other suitable interconnect.

[0178] According to some embodiments, the carrier 1420 is the aforementioned IC structure, interposer, or the like. The carrier 1420 may be configured to support a first semiconductor package 1430 and a second semiconductor package 1440 and electrically connect the first semiconductor package 1430 to the second semiconductor package 1440, or electrically connect the first semiconductor package 1430 and the second semiconductor package 1440 to a substrate 1410. According to some embodiments, the carrier 1420 includes a substrate 102 and a plurality of TSVs 104 within the substrate 102. The materials, configuration, and methods for forming the substrate 102 and the TSVs 104 are similar to those described in the references. Figure 2D The materials, configurations, and methods described in the IC structure 100A or other suitable IC structures shown above are applicable. The carrier 1420 further includes a first main RDL 108A disposed on the upper side of the substrate 102 and a second main RDL 108B disposed on the lower side of the substrate 102. The first main RDL 108A is electrically connected to the secondary RDL 108B via a TSV 104. The first main RDL 108A includes interconnect surfaces 1420S1 electrically bonded to the first semiconductor package 1430 and the second semiconductor package 1440. Similarly, the second main RDL 108B includes interconnect surfaces 1420S2 electrically bonded to the substrate 1410. The semiconductor package assembly 1400A may include external connections 1423 electrically connecting the substrate 1410 to the carrier 1420 via a flip-chip bonding process. The external connections 1423 may include microbumps, solder bumps, ball grid array balls, or other suitable connectors.

[0179] According to some embodiments, the structural configuration of the first semiconductor package 1430 is similar to that of [the packages described in the original text]. Figure 13C , 7I The structural configurations of semiconductor packages 1300A, 700B, 700C, and 1100A are shown in Figures 7J and 11A. Therefore, details of the first semiconductor package 1430 can be found by referring to the descriptions of these semiconductor packages. (Reference) Figure 11A and Figure 14A The first semiconductor package 1430 includes a sub-RDL 118B formed on the lower sub-plane 1430S of the first semiconductor package 1430. Furthermore, as... Figure 14A As shown, sub-RDL 118B includes a front interconnect surface 118F facing IC structures 143A, 143B, and 143C, and a rear interconnect surface 118R opposite to the front interconnect surface 118F. The rear interconnect surface 118R is electrically bonded to the interconnect surface 1420S1 of the carrier 1420. Therefore, the first semiconductor package 1430 is bonded to the carrier 1420 via the edge interconnect structure 118X of the first semiconductor package 1430. According to some embodiments, the rear interconnect surface 118R includes a first bonding pad array, and the interconnect surface 1420S1 includes a second bonding pad array corresponding to the first bonding pad array. The first bonding pad array and the second bonding pad array are joined via flip-chip bonding and together form a flip-chip assembly by performing flip-chip bonding.

[0180] According to some embodiments, the structural configuration of the second semiconductor package 1440 is similar to... Figure 12C and 7J The structural configurations of semiconductor packages 1200A and 700C are shown in the diagram. Therefore, details of the second semiconductor package 1440 can be found by referring to semiconductor package 700C. Figure 7I and Figure 14AThe second semiconductor package 1440 includes three bodies comprising IC structures 144A, 144B, and 144C. The body of IC structure 144A includes an upper main surface 144AP1 and a lower main surface 144AP2 that overlaps with the lower main surface 1440P of the second semiconductor package 1440, and thus the lower main surface 1440P serves as the interconnect surface of the second semiconductor package 1440. A semiconductor package assembly 1400A is further included between the second semiconductor package 1440 and the carrier 1420, and electrically connects the second semiconductor package 1440 and the carrier 1420 via an external connection 1443. According to some embodiments, the external connection 1443 includes microbumps, solder bumps, or other suitable connectors. The carrier 1420 is bonded to the second semiconductor package 1440 via a flip-chip bonding process through the first interconnect surface 1420S1 of the carrier 1420 and the interconnect surface of the lower main surface 1440P of the second semiconductor package 1440. According to some embodiments, the interconnect surface of the lower main surface 1440P includes a third bonding pad array, and the interconnect surface 1420S1 includes a second bonding pad array corresponding to the third bonding pad array. The second bonding pad array and the third bonding pad array together form a flip-chip assembly by performing flip-chip bonding.

[0181] Figure 14B A cross-sectional view of a semiconductor package assembly 1400B according to various embodiments of the present disclosure is shown. The semiconductor package assembly 1400B is similar to the semiconductor package assembly 1400A in many respects, and such similar aspects are not repeated for the sake of simplicity. References Figure 7J and Figure 14B The first semiconductor package 1430 includes a sub-RDL 118A bonded to a lower sub-plane 1430S of the first semiconductor package 1430. Furthermore, the sub-RDL 118A includes a front interconnect surface 118F facing IC structures 143A, 143B, and 143C, and a rear interconnect surface 118R opposite to the front interconnect surface 118F. The rear interconnect surface 118R is electrically bonded to an interconnect surface 1420S1 of the carrier 1420. Therefore, the first semiconductor package 1430 is bonded to the carrier 1420 via an edge interconnect structure 118X of the first semiconductor package 1430. According to some embodiments, the sub-RDL 118A includes a first bonding layer 118L1 bonded to a first bonding layer of the first main RDL 108A via a hybrid bonding process. According to some embodiments, the rear interconnect surface 118R includes a first hybrid bonding layer, and the interconnect surface 1420S1 includes a second hybrid bonding layer corresponding to the first hybrid bonding layer for performing hybrid bonding.

[0182] According to some embodiments, Figure 14B The structural configuration of the second semiconductor package 1440 shown is similar to Figure 7I The structural configuration of the 700B semiconductor package is shown in the image. (Reference) Figure 7I and Figure 14A The second semiconductor package 1440 includes three bodies, comprising IC structures 144A, 144B, and 144C. The body of IC structure 144A includes an upper main surface 144AP1 and a lower main surface 144AP2 that overlaps with the lower main surface 1440P of the second semiconductor package 1440, and therefore the lower main surface 1440P is the interconnect surface of the second semiconductor package 1440. IC structure 144A further includes a bonding layer facing a carrier 1420, and the first main RDL 108A further includes a bonding layer facing the second semiconductor package 1440. The carrier 1420 is bonded to the second semiconductor package 1440 via a hybrid bonding process through a first interconnect surface 1420S1 and the interconnect surface 1440P of the semiconductor package 1440. According to some embodiments, the interconnect surface of the lower main surface 1440P includes a third hybrid bonding layer, and the interconnect surface 1420S1 includes a second hybrid bonding layer corresponding to the third hybrid bonding layer for performing hybrid bonding.

[0183] The embodiments discussed above are described using 3DIC as an example. However, this disclosure is not limited thereto. The methods, processes, and structures discussed in this disclosure can also be applied to other advanced system-in-package (SiP) architectures, including fan-out, embedded SiP, silicon photonics, and combinations thereof, for example... Figure 1A , 1B The embodiments shown in 1C, 1D, 1E and 1F employ SiP involving wafer stacking in the thickness direction.

[0184] According to some embodiments, IC structures 100A, 300A to 300C and 400A to 400H may be based on silicon substrate 102 or other types of substrate 102, such as SiC.

[0185] refer to Figure 7A and 7B According to some embodiments, the carrier substrate 106 can be a 12-inch wafer carrier or a larger panel carrier to improve carrier utilization. (Reference) Figure 7B The release layer 140 may also be a permanent bonding layer, such as a die attach film (DAF) for stacked wafer packaging, similar to the film used to bond wafers (IC structures, 142A to 142D) to jointly form a low-profile 3D IC stack 312, wherein the film is pre-placed on the back side of the wafers 142A to 142B while still in wafer form, and the wafer / film combination is picked up for wafer bonding of the wafer tape after wafer dicing.

[0186] refer to Figure 7EAs previously described, a reconstructed high IC stack 322 of the semiconductor device 701W is molded or sealed using potting material 262. The material and configuration of potting material 262 are similar to those of potting materials 242 or 252. A molding or deposition process is performed to deposit potting material 262 between the laid-down high IC stack 322. According to some embodiments, an overmolding operation is performed to deposit potting material 262. According to some embodiments, potting material 262 may also be a permanent bonding layer, such as a molding compound or encapsulation material. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry and / or wet) or other suitable etching operation) is performed to remove excess potting material 262 and planarize the upper surface of potting material 262, making it flush with the side surfaces of the high IC stack 322, which are also planarized simultaneously with the potting material 262. Subsequently, an edge interconnect structure RDL 118A is formed or bonded to at least one edge interconnect on the side surface (sub-plane) of the high IC stack 322. According to some embodiments, a bumping process is performed for the wafer edge interconnect, wherein a plurality of bonding pads are formed on one side of the high IC stack 322 or RDL 118A to electrically connect the high IC stack 322 to the RDL 118A.

[0187] refer to Figure 7F Other carrier substrates 126 are provided or received in other semiconductor devices 702W. Other release layers 130 are formed over the carrier substrate 126 to facilitate the formation of RDL 118B. Figure 7E The semiconductor device 701W is bonded to a second carrier 126 on the side of RDL 118A. Subsequently, the carrier substrate 116 is released from the semiconductor device 701W by releasing the release layer 120. According to some embodiments, after removing the carrier substrate 116 and before forming RDL 118B, a planarization operation is performed on the exposed sub-surfaces of the high IC stack 322 and the potting material 262. The edge interconnect RDL structure 118B is formed or bonded to the lower sub-surface of the high IC stack 322 opposite to the upper sub-surface of the high IC stack 322.

[0188] refer to Figure 7GThe carrier substrate 126 is removed or detached from the semiconductor device 702W by releasing the release layer 130. A monomerization or dicing process is performed to separate the semiconductor device 702W into high-IC stack structures 700L. The monomerization or dicing process may be performed to cut through the semiconductor device 702W at the location of the potting material 262, which may bypass metal lines or even dielectric passivation layers, to facilitate clean monomerization of the etching or dicing operation, wherein the potting material 262 is cleaned by, for example, dry and / or wet etching, while taking care to keep each high-IC stack structure 700L intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove residual potting material 262 remaining on the high-IC stack structure 700L. According to some embodiments, a planarization operation is performed on the exposed main surface of the high-IC stack structure 700L to remove residual potting material 262.

[0189] refer to Figure 7H Individual semiconductor packages 700A (i.e., low-profile IC stack 312) are formed from corresponding IC structures (i.e., high IC stack structure 700L). Release processes, monomerization processes, and / or dicing processes are performed to remove the release layer 140 from each of the high IC stack structures 700L. Figure 7B This allows the different semiconductor packages 700A (i.e., the respective low-profile IC stacks 312 containing edge interconnect RDL structures 118A and 118B) to be separated from each other. According to some embodiments, etching or dicing processes are performed to facilitate the release process, such as by dicing, continuous-wave laser beam, dry etching (e.g., by plasma), and / or wet etching to cut through the sub-RDLs 118A and 118B at the location of the release layer 140, which may bypass metal lines or even dielectric passivation layers, to promote clean monolithization of the etching or dicing operation. According to some embodiments, a combination of wet etching, dicing, and planarization operations is performed.

[0190] Figures 8A to 8E Structural cross-sectional views are shown at different stages of a method for manufacturing a semiconductor package 800A according to various embodiments of the present disclosure. Figures 8A to 8E The steps shown are similar in many ways to those described in the paragraphs above. Figures 7D to 7H The steps shown in the document will be repeated for the sake of brevity. Figures 8A to 8E The steps shown in the document are Figures 7D to 7H The main difference between the steps shown in the document is: Figures 7D to 7H The edge interconnect RDL structures 118A and 118B in the middle are replaced by edge interconnect RDL structures 138A and 138B, which are formed by bonding flexible printed circuits (flexible circuits) to the side surfaces of the low and high IC stacks.

[0191] refer to Figure 10B Using potting material 262 in a manner similar to Figure 7E The method shown in the figure is to mold, encapsulate, or seal the semiconductor device 1001W (i.e., high IC stack 422) and planarize it.

[0192] Figure 10E The formation of sub-RDL 148B is described. An additional support substrate 136 with vias 134 is provided in semiconductor device 1003W, and an additional release or sacrificial layer 130 is formed over the support substrate 136. Sub-RDL 148B is formed over the release layer 130, wherein sub-RDL 148B includes an array of conductive pads 274 on its upper surface. The carrier substrate 106 is released from semiconductor device 1002W via the release layer 110, followed by planarization operations such as CMP, polishing, etching (dry and / or wet) or other suitable etching operations. Semiconductor device 1002W is then bonded to the support substrate 136 to form semiconductor device 1003W with a wafer-level bonding process (e.g., a hybrid bonding process).

[0193] refer to Figure 10G Subsequently, a monomerization or dicing process is performed to isolate the semiconductor device 1003W into individual IC structures 1000L, i.e., high IC stacks. Monomerization or dicing processes involving dicing, laser ablation, plasma etching, dry etching, wet etching (e.g., acid etching), wet cleaning, or combinations thereof can be performed to cut through the semiconductor device 1003W at the location of the potting material 262, without passing through metal lines or even dielectric passivation layers, to facilitate clean monomerization of the semiconductor device 1003W from the semiconductor structure 1003W. Figure 10F Release high IC stack 422 ( Figure 10G Sub-RDLs 148A and 148B may be formed at release layers 140 such that they are not present in scribe lines or on monomerization between adjacent low-profile IC stacks to facilitate monomerization. According to some embodiments, planarization processes (e.g., CMP, polishing, etching (dry and / or wet) or other suitable etching operations) are performed to remove potting material 262 (see [link to documentation]). Figure 10G ) or release layer 140 (see Figure 10H Planarize the upper surfaces of sub-RDLs 148A and 148B and stack them with the high-performance IC 422 (see [link]). Figure 10G ) or high IC stack 322 (see Figure 10H The side surfaces are flush with each other.

[0194] The following section focuses on additional process options / improvements and IC options beyond those mentioned above. Figure 2C , 3DThe building module structures shown in 3E, 3F, 4G, 4H, 4I, 4J, 4K, 4L, 4M and 4N are 100A, 300A to 300C and 400A to 400H:

[0195] (a) Active ICs (e.g., IC structures 100A, 300A to 300C and 400A to 400H) may be based on silicon substrates or high thermal conductivity (HTC) and low coefficient of thermal expansion (HTCC) substrates, such as diamond, aluminum nitride, boron nitride and silicon carbide.

[0196] (b) ICs (e.g., IC structures 100A, 300A to 300C, and 400A to 400H) may also be interconnect spacers (e.g., passive or active silicon interposers) with HTC RDLs on both sides or with an RDL on one side and with or without through-holes, to assist in conducting heat away from adjacent wafers and routing more I / O to the side surface of the 3D IC (using the additional side surface area provided by the spacers), wherein the substrate material of the interconnect spacers may be an HTC material (e.g., diamond, aluminum nitride, boron nitride, silicon carbide) or a metal material (e.g., Cu, which is appropriately isolated as needed) or an HTCC material (e.g., diamond, aluminum nitride, boron nitride, silicon carbide) or a composite metal (e.g., Cu / Invar / Cu or Cu / Mo / Cu);

[0197] (c) ICs (e.g., IC structures 100A, 300A to 300C, and 400A to 400H) may also be HTCCs or HTC spacers with only HTC RDLs and no through-holes, as directly described above, to assist in heat conduction from adjacent chips and route more I / O to the IC side surface; and

[0198] (d) RDL (Re-laid Layer) structures 108A, 108B, 108C, 108D, 108E, 108F, 118A, 118B, 138A, 138B, 148A, 148B or similar may be based on HTCC or HTC dielectrics with metal wires, such as Cu or suitable metals (e.g., tungsten (W)).

[0199] Figure 15AA cross-sectional view of a conventional semiconductor package assembly 96 is shown. The semiconductor package assembly 96 includes a laminated substrate 1502, an interposer 1504, a first semiconductor HBM stack 1542, a second semiconductor logic chip 1508, and a logic memory controller chip 1510 (also referred to as a controller or controller chip). The first semiconductor HBM stack 1542 is a memory chip stack 1543 stacked on its main surface. The second logic semiconductor chip 1508 is one of a CPU chip, GPU chip, TPU chip, MEMS chip, AP chip, FPGA chip, ASIC chip, transceiver chip, network interface chip, integrated photonics chip, packet buffer / router chip, or other suitable chip. However, the next generation of HBMs (i.e., HBM4) faces challenges including:

[0200] (a) High cost due to a lack of known good wafers, low production volume and large TSVs;

[0201] (b) HBM is mainly monopolized by three giants: SK Hynix, Samsung and Micron.

[0202] (c) The three major manufacturers do not support customization or memory optimization;

[0203] (d) Advanced packaging may move from flip-chip based on copper pillar microbumps to very expensive copper hybrid bonding, which is still in its early stages and could significantly increase costs.

[0204] (e) Advanced packaging capabilities and production capacity are often bottlenecks, coupled with low yield rates, affecting the stability of HBM supply; and

[0205] (f) Regarding the overheating issues of the middle and bottom memory layers in the HBM stack (because cooling is performed from the back of the top DRAM), especially when the number of DRAMs increases from 12 in HBM3 to 16 in HBM4.

[0206] As HBM surpasses HBM4, involving more than 16 DRAM chips, the aforementioned problems will be exacerbated. Even though copper hybrid bonding was not implemented in HBM4, it is believed that it will be implemented in HBM5, which has more DRAM layers.

[0207] One or more of the above four chip side (CSS) interconnects (see Figure 13D This technology can be used to address the challenges of scaling HBM from HBM3 (12+1 wafers) to HBM4 (16+1 wafers) and beyond, and could potentially revolutionize the HBM field. For example, a 2.5D IC with side-surface bonded memory stacks (although only interconnects on one side surface are shown, these interconnects can connect to chip-side surface interconnects on other chip side surfaces to support high I / O counts) is used. Figure 15B As shown in the document, almost all of the above problems can be solved (or alleviated), as described below:

[0208] (a) Each memory chip can be a known good chip before assembly, and requires only a smaller number of TSVs and / or edge vias compared to HBM stacking, thus significantly reducing costs;

[0209] (b) Smaller memory manufacturers (DRAM, SRAM, etc.) can leverage the RDL and flip-chip technology, which are more readily available from OSATS, to compete with the Big Three.

[0210] (c) There is an opportunity to collaborate with more manufacturers beyond the three giants on customization or memory optimization;

[0211] (d) No need to use expensive copper hybrid bonding;

[0212] (e) It prevents overheating of the middle and bottom memory layers in an HBM stack (because cooling occurs on the back of the top DRAM layer) because heat is conducted through silicon, which has a thermal conductivity 100 times greater than silicon dioxide (unlike the combination of silicon and poorly heat-dissipating silicon dioxide in a conventional HBM stack). It also allows the use of HTCC substrates / interposers and / or HTC spacers as needed, enabling the number of DRAM or suitable memory devices to increase from 12 in HBM3 to 16 in HBM4, and potentially more than 16 in the future, without concern about overheating effects; and

[0213] (f) Most importantly, it can be easily scaled to more memory chips compared to conventional HBM technology, whose total height is set at approximately the height of a GPU (see [link to relevant documentation]). Figure 15B The thickness is approximately 750μm. As the number of DRAM chips increases from 12 to 16 or even more, the need for thinner DRAM chips and their interconnects further exacerbates the aforementioned technological, manufacturing, cost, and supply chain challenges.

[0214] In one embodiment of the invention, an HBM2E DRAM (10.5mm long x 9.5mm wide) is used as a control, while assuming a length of 5.25mm (half the length of HBM2E), a width of 9.5mm, and a thickness of 500 micrometers, comprising a total of 16 semiconductor structures 1522 (a combination of 16 DDR wafers and / or spacers / interconnects of the same thickness, 500μm), which, in the width direction, have one wafer side surface (see...). Figure 15BConnecting to the control chip 1510 will provide a total wafer-side surface area of ​​76 mm² (excluding the thickness of the inter-chip bonding layer). Assuming a DRAM bump pitch of 60 μm (57 μm or 29 μm in HBM2E; 60 μm is assumed here) and a DRAM bonding pad diameter of 14.6 μm (same as HBM2E), the 76 mm² surface area can support a maximum of 87,040 I / Os, far exceeding the required number. Furthermore, in addition to the bonding pads located above the edges or sidewalls of the DRAM wafer, additional bonding pads can be located above the edges or sidewalls of another integrated circuit (IC) structure, interconnect spacers, potting or molding compound layers, or high thermal conductivity layers (adjacent to the DRAM wafer, such as...). Figure 2C , 3D (As shown in 3F, 4G to 4N, and 6A to 6E). Therefore, the present invention can be... Figure 2C , 3D Adjustable or expandable bonding pads (e.g., 1200–1500 or 1500–2400, etc.) are provided above the edge or sidewall of one of the semiconductor structures to 3F, 4H to 4N and 6A to 6E, and the set of semiconductor structures may provide more than ten times the number of bonding pads (e.g., 12000–15000 or 15000–24000, etc.) on the edge or sidewall of the set of semiconductor structures.

[0215] like Figure 15B As shown, the semiconductor package assembly 1500 includes an IC stack 1501, which includes a first semiconductor stack 1506, a logic control chip 1510, a laminate substrate 1502, an interposer layer 1504, and a second semiconductor chip 1508. According to some embodiments, the first semiconductor stack 1506 is a memory stack structure, and the second semiconductor chip 1508 is one of a CPU chip, GPU chip, TPU chip, MEMS chip, AP chip, FPGA chip, ASIC chip, transceiver chip, network interface chip, integrated photonics chip, packet buffer / router chip, or another suitable chip. According to some embodiments, the first semiconductor stack 1506 includes a plurality of semiconductor structures 1522, which include a plurality of IC structures 1523 (which are low-profile IC stacks 312), a plurality of support substrates 1524, and a plurality of bonding or adhesive layers 1526 between adjacent IC structures 1523 or between one IC structure 1523 and a support substrate 1524. According to some embodiments, the adhesive layer 1526 may further include an HTC layer, wherein the thermal conductivity is higher than that of silicon or SiO2. According to some embodiments, the support substrate 1524 is an HTCC (high-temperature co-fired ceramic) interlayer, an HTCC substrate, an HTC substrate, or the like.

[0216] According to some embodiments, the support substrate 1524 is arranged as a highly thermally conductive layer adjacent to the semiconductor structure 1522, which is used to conduct a large amount of heat away from the IC structure 1523 of the semiconductor structure 1522. The semiconductor structure 1522 prevents the DRAM from overheating the environment, ensuring DRAM operation under normal conditions. The external connector 1518 is located above the edge of the IC structure 1523 and above the edge of the adjacent structure 1524.

[0217] Figures 16A to 16E Cross-sectional views are shown illustrating different stages of a method for manufacturing a semiconductor package 1600A according to various embodiments of the present disclosure. References Figure 16A The carrier substrate 106 is received or provided. A release layer 1602 is deposited on or attached to the carrier substrate 106. According to some embodiments, the release layer 1602 is a UV-release layer or a heat-release tape. A defining layer 1604 is deposited over the carrier substrate 106 and includes a plurality of recesses 1604R, wherein the recesses 1604R expose the release layer 1602.

[0218] refer to Figure 16B Multiple semiconductor wafers 1600A are fabricated or formed. Each of the semiconductor wafers 1600A may be similar to the aforementioned low-profile IC stack 312 or other IC stacks, which includes multiple IC structures 1603 disposed in the stack. According to some embodiments, the semiconductor wafer 1600A may further include external connectors 302 or bonding pads located on the side surface of the low-profile IC stack 312 on RDL 168.

[0219] refer to Figure 16C Thermal interface material (TIM) 1606 and heat sink 1608 are sequentially deposited or formed on the exposed side surface of each semiconductor wafer 1600A. According to some embodiments, the side surface of TIM 1606 or heat sink 1608 is aligned with the main surface of semiconductor wafer 1600A. According to some embodiments, TIM 1606 is pre-coated onto heat sink 1608 and deposited on the side surface of semiconductor wafer 1600A as heat sink 1608 is attached or deposited onto semiconductor wafer 1600A.

[0220] refer to Figure 16D The semiconductor wafer 1600A is removed from the carrier substrate 106 by releasing the release layer 1602. The semiconductor wafer 1600A is sequentially flipped (one surface at a time) onto two other side surfaces and two main surfaces of the low-profile IC stack, and this process is repeated. Figures 16A to 16C The process described forms all five surfaces of the low-profile IC stack beneath the TIM / heatsink assembly, except for the side surfaces used for edge interconnects.

[0221] Figure 17A cross-sectional view of a semiconductor package assembly 1700 according to various embodiments of the present disclosure is shown. The semiconductor package assembly 1700 includes a first interposer 1702, a first semiconductor structure 312A, a second semiconductor structure 312B, three bridging wafers 1704, a second interposer 1706, a third semiconductor wafer 1708, and two heat sinks 1710.

[0222] According to some embodiments, the first semiconductor structure 312A and the second semiconductor structure 312B include memory chips, and the third semiconductor chip 1708 is one of a CPU chip, a GPU chip, a TPU chip, a MEMS chip, an AP chip, an FPGA chip, an ASIC chip, a transceiver chip, a network interface chip, an integrated photonics chip, a packet buffer / router chip, or another suitable chip. According to some embodiments, each of the first semiconductor structure 312A and the second semiconductor structure 312B includes a plurality of low-profile memory IC stacks 312 (e.g., 3D IC structure stack 1901, whose references are...). Figure 19A (or as described in 19B) or other IC stacks. According to some embodiments, the first interposer 1702 or the second interposer 1706 includes a plurality of TSVs (through-silicon vias or through-holes, in the case of a substrate material other than silicon) 1722 electrically connecting the first interposer 1702 or the second interposer 1706 to adjacent circuitry. According to some embodiments, the bridging die 1704 includes a plurality of TSVs 1724 electrically connecting the first interposer 1702 to the second interposer 1706.

[0223] According to some embodiments, the first interposer 1702 is based on silicon, an HTC material, or a low thermal conductivity material (e.g., glass). The first interposer 1702 may be bonded to an IC laminate substrate or a printed circuit board. According to some embodiments, the second interposer 1706 includes an HTC substrate. According to some embodiments, the bridging chip 1704 is used to power the third semiconductor chip 1708 and provide additional signal paths for the third semiconductor chip 1708.

[0224] According to some embodiments, thermal management of the semiconductor package assembly 1700 is accomplished by direct-to-chip liquid cooling involving fluid microchannels and / or jetting on the back side of the desired third semiconductor wafer 1708, or by liquid immersion cooling involving a dielectric coolant or water, which requires the use of a conformal coating material (e.g., parylene) to protect the circuitry of the semiconductor package assembly 1700.

[0225] According to some embodiments, the semiconductor package assembly 1700 further includes a plurality of external connectors 1712 on the upper surface of the first interposer 1702, which electrically connect the first interposer 1702 to the first semiconductor wafer 312A, the second semiconductor wafer 312B, and the bridging wafer 1704. The semiconductor package assembly 1700 may further include a plurality of external connectors 1714 on the upper surface of the first semiconductor wafer 312A, the second semiconductor wafer 312B, and the bridging wafer 1704, which electrically connect the first semiconductor wafer 312A, the second semiconductor wafer 312B, and the bridging wafer 1704 to the second interposer 1706, and a plurality of external connectors 1716 on the upper surface of the second interposer 1706, which electrically connect the second interposer 1706 to the third semiconductor wafer 1708. A packaging material 242 is disposed between the plurality of external connectors 1712, 1714, and 1716. According to some embodiments, the semiconductor package assembly 1700 further includes a plurality of external connectors 1718 on the lower surface of the first interposer 1702, which electrically connect the first interposer 1702 to an external circuit.

[0226] like Figures 16A to 16E As shown, the top or back surface of the 3D memory connected to the side surface (e.g.) Figure 15B The first semiconductor chip (1506) shown can be attached to HTC materials to facilitate heat dissipation. Figure 15B and 16A A similar concept to the wafer-side surface interconnects in 16E can also be applied to Figure 17 The 3D IC in the example, wherein the low-profile 3D IC stacks 312A and 312B are memory devices connected to one or both wafer side surfaces, involves using thermal metamaterials to minimize thermal crosstalk between the GPU (e.g., the third semiconductor wafer 1708) and the HTC interposer (e.g., the second interposer 1706) and between the first interposer 1702 and the low-profile 3D IC structure (which is a novel 3D memory structure).

[0227] exist Figure 15A The conventional 2.5DIC package shown uses direct wafer liquid cooling for cooling, which involves attaching a combination of thermal interface material, heat sink, and cooling plate to the back of the top DRAM and GPU. Figure 15B The new 3D memory stacking structure shown in the diagram can also cool the GPU (e.g., the second semiconductor wafer 1508) and the 3D memory (e.g., the first semiconductor wafer 1506) through direct wafer liquid cooling or a combination of direct wafer cooling for the GPU and air cooling for the lower-power-dissipating 3D memory. Furthermore, Figure 15A and 15B The structure shown can be cooled using liquid immersion cooling.

[0228] As described in this disclosure, the side surfaces of the 3DIC stack are used to interconnect the chips in the 3DIC stack to allow for cross-chip signal and power distribution. That is, power and signals can be supplied from the front side of the bottom chip (or the interposer supporting the bottom chip) to not only the chip directly above it, but also directly to all other chips in the 3D IC stack. Furthermore, HTC material is disposed between two adjacent semiconductor chips and thermally coupled to another HTC material, which covers the other sides of the 3DIC stack.

[0229] In one embodiment, a 3DIC stack includes multiple semiconductor wafers or IC wafer structures, wherein the semiconductor wafers or IC wafer structures (e.g., wafers or wafer structures) have Figure 2D The structure 108A shown in the image has a cuboid shape and includes a top surface 108P1, a bottom surface 108P2, and four side walls 108S1, 108S2, 108S3, and 108S4. The area of ​​the top / bottom surface 108P1 / 108P2 is much larger than the area of ​​the side walls 108S1 to 108S4 (e.g., ...). Figure 2D (As shown in the image). Figure 2D The semiconductor wafer or IC wafer structure shown in the image has "edge pads / vias" in the form of peripheral pads at its periphery, side surface, or sidewalls (e.g., one or more sidewalls 108S1 to 108S4) and / or at pads / vias in the RDL structure of the semiconductor wafer. Furthermore, "edge TSVs (through-silicon vias)" in semiconductor wafers can also penetrate the entire thickness or part of the thickness of the semiconductor wafer, such as... Figure 2D As shown in the diagram. To increase the edge connection area of ​​the sidewalls or side surfaces, edge pads in the RDL structure can be connected to edge TSVs. These TSVs can penetrate part and / or all of the semiconductor wafer from the top surface 108P1.

[0230] Figures 18A to 18H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 1800A according to various embodiments of the present disclosure are shown. For forming a low-profile IC stack 1812, as... Figures 18A to 18C As shown, the IC structure 142A of the low-profile IC stack 1812 can be bonded to the carrier 106, and then:

[0231] (a) Stacking additional IC structures 142 of the same size (e.g., 142B, 142C, and 142D) on top of the bottom IC structure 142A to first form a low-profile IC stack 1812 (i.e., the final 3D IC package structure that can be interconnected on the side surfaces), wherein an HTC material (e.g., AlN / BN / W / Cu / SiC…) 1802 is inserted between two adjacent IC structures 142 (or covering all surfaces between two adjacent IC structures 142). In one embodiment, the thermal conductivity of the HTC layer 1802 is higher than that of Si or SiO2. Alternatively or additionally, for example, one low-profile IC stack 1812 can be released from the other low-profile IC stacks by heating a thermoplastic adhesive (not shown separately) to its softening temperature and applying shear force, followed by wet chemical cleaning or etching of the low-profile IC stack 1812 after release to remove the adhesive.

[0232] (b) Insert a release layer 140 on top of the low IC stack 1812, and

[0233] (c) Repeat the above process to construct a high-3D IC stack 1822 (see Figure 18B It is thick enough to allow for subsequent processing.

[0234] Processing tall 3D IC stacks 1822 on the sides is more cost-effective than processing short IC stacks 1812. Short IC stacks 1812 are typically very thin, around 100μm, while forming tall IC stacks 1822 allows for the production of edge interconnects for short IC stacks 1812 using existing commercial precision equipment with high yield. Figure 2C Taking HBM3 DRAM as an example, which uses an IC structure configuration, it can support 12 chips. The thickness of an individual DRAM IC can be approximately 30-50 μm, close to the practical limit of back-side grinding. This means that the thickness of a 3D HBM3 DRAM stack with 12 DRAM ICs and basic logic chips is approximately 500 μm (approximately 0.5 mm). Stacking 10 HBM3 chips (or based on...) Figure 2C The low IC stack 1812 with the IC structure configuration produces a total of 120 wafers (in the high IC stack 1822) with a total thickness of about 5,000 μm (i.e. 5 mm), which is easier to handle in manufacturing compared to 0.5 mm.

[0235] With the high-performance IC stack 1822, its side surfaces can then be bonded to... Figure 18D Another carrier substrate 116 is shown in the image, and it is encapsulated using polymer material 262, such as... Figure 18E As shown, for example, Epotek 377 epoxy resin, the polymer is cured in a vacuum, and then:

[0236] (a) Planarization (and light etching or grinding to ensure all edge connections are exposed);

[0237] (b) such as Figure 18E As shown, an RDL structure 118 is established on the side surface of the long IC stack 1822;

[0238] (c) such as Figure 18F As shown in the figure, it is bonded to the carrier substrate 126 and released from the carrier substrate 116;

[0239] (d) Planarize (or lightly grind) the top surface of the long IC stack 1822;

[0240] (e) such as Figure 18F As shown, a high thermal conductivity layer 1824 is constructed (or covers the sidewalls of one / two / three other high IC stacks 1822; or covers the remaining sidewalls of the high IC stack 1822 without an RDL layer structure). In one embodiment, the thermal conductivity of the high thermal conductivity layer is higher than that of Si or SiO2 (e.g., AlN / BN / W / Cu / SiC...).

[0241] (g) such as Figure 18G As shown in the figure, release carrier substrate 126;

[0242] (h) such as Figure 18F As shown, multiple high-performance IC stacks 1822 are released into individual high-performance IC stack structures 1800L; and finally...

[0243] (i) Release the high IC stack 1822 into individual low IC stacks 1812 or semiconductor packages 1800A.

[0244] The aforementioned process can also establish RDL structures on two or more sides. This can be achieved through... Figures 18E to 18H The process shown in the image is used to build the RDL structure on the other side. The high IC stack 1822 can be released by laser cutting and dicing (but great care must be taken to avoid damaging the electrical pins), and then the potting polymer 262 is removed by acid etching.

[0245] After releasing the high 3D IC structure stack 1822, the low IC stack 1812 or semiconductor package 1800A can be released through a series of steps. First, the RDL structure 118 between two low IC stacks 1812 is cut through with a laser. Then, one of the following two methods is used: (1) the release layer 140 between two adjacent low IC stacks 1812 is cut through, and wet etching, cleaning and / or light polishing are performed to remove residual material from the release layer 140; or (2) the release layer 140 is thermally softened, and the low IC stacks 1812 are mechanically separated (one at a time) using a jig, followed by wet etching, cleaning and / or light polishing to remove residual material from the release layer 140.

[0246] The low-profile IC stack 1812 or semiconductor package 1800A may contain multiple DRAM semiconductor wafers to form an HBM structure, or contain a set of DRAM semiconductor wafers and a set of FLASH or SRAM semiconductor wafers, or contain multiple logic wafers, or any other combination of DRAM / SRAM / FLASH / logic wafers.

[0247] Subsequently, the low-profile IC structure stack 1812 or semiconductor package 1800A can be bonded to another interposer or IC chip, such as Figure 19A As shown, a semiconductor package assembly 1900 is formed, comprising a 3D IC structure stack 1901, a substrate 1902, an interposer 1904, and a logic controller chip 1906. In this embodiment, the 3D IC structure stack 1901 includes a plurality of DRAM semiconductor wafers 1920 (or a plurality of DRAM wafers and a control IC) and side RDLs 118, with each DRAM semiconductor wafer 1920 horizontally separated from the others. Laterally extending RDL structures 118 on the sidewalls of the plurality of DRAM semiconductor wafers (or DRAM and control ICs) 1920 are bonded to the logic memory controller chip 1906 or the interposer 1904, and then the interposer 1904 is bonded to the substrate 1902. The RDL structures 118 can be used to handle the power / signal functions of each DRAM semiconductor wafer 1920, and the RDL structures 118 are connected to the logic memory controller chip 1906 and the interposer 1904. Unlike conventional HBM structures, in this invention, each DRAM semiconductor chip 1920 can independently transmit or receive power / signals without passing through other DRAM semiconductor chips, and each DRAM semiconductor chip can generate high-bandwidth data with low latency. Therefore, it can be appropriately named HBLM (High Bandwidth Low Latency Memory), and the combination of horizontally separated DRAM semiconductor chips 1920 can be named HBLM frame.

[0248] Furthermore, since there is an intermediate (upwardly extending) high thermal conductivity layer 1912 (e.g., AlN, BN, W, copper, SiC, etc.) and an optional HTC adhesive layer 1908 between the main surfaces of two adjacent DRAM semiconductor wafers 1920, which can be connected to a top (laterally extending) HTC layer 1914 (e.g., AlN, BN, W, copper, SiC, etc.) on other sidewalls of the low 3DIC structure stack 1901, the heat generated from these two DRAM semiconductor wafers 1920 can be transferred from the wafers through the intermediate high thermal conductivity layer 1912 to the top high thermal conductivity layer 1914 and to a heat dissipation device (e.g., a cooling plate; not shown) thermally coupled to the HTC layer 1914.

[0249] According to some embodiments, RDL 118 further includes a plurality of bonding pads 1927 on the upper surface of RDL 118, and an interposer 1904 is electrically connected to the DRAM semiconductor wafer 1920.

[0250] In cases where more signal transmission is required in multiple DRAM semiconductor wafers 1920, as described above, more upwardly extending RDL structures 1916 can be formed in, for example... Figure 19B On two or more sides shown, a bottom RDL structure 118 is formed on one side of a plurality of DRAM semiconductor wafers 1920, and another side RDL structure (or side RDL structure) may be formed on other sides of the plurality of DRAM semiconductor wafers 1920 opposite to or adjacent to the intermediate high thermal conductivity layer 1912, wherein the bottom RDL structure 118 is electrically connected to these side RDL structures 1916.

[0251] In situations where greater heat dissipation is required in multiple DRAM semiconductor wafers 1920, as described above, more intermediate HTC layers 1917, similar to the intermediate HTC 1912 or the top HTC 1914, can be formed on two or more sides and / or one or both of the main surface, such as... Figure 19B As shown, the middle HTC layer 1917 is thermally coupled to the top HTC 1914 and the middle HTC 1912. According to some embodiments, the thermal conductivity of HTC layers 1912, 1914 and 1917 is higher than that of silicon or SiO2.

[0252] Figure 20A This section describes the coupling relationship between a low-profile 3D IC stack (or HBLM frame) 2012 and a logic chip (or logic control chip or memory control IC) 2014 according to another embodiment of the present invention. The low-profile 3D IC stack 2012 includes multiple DRAM semiconductor chips MR1 ​​to MR4 (or more) to form the HBLM frame structure 2012 and a substrate chip 2022, and each DRAM semiconductor chip (or HBLM) MR1 to MR4 has multiple functions for reading / writing data therefrom. As mentioned, in this low-profile 3D IC stack 2012, each DRAM semiconductor chip MR1 to MR4 is horizontally separated from each other, rather than vertically separated. This novel HBLM frame memory architecture in the low-profile 3D IC stack 2012 further allows for ultra-fast random access times.

[0253] like Figure 20AAs shown, the logic bridge area 2024 of the logic / SOC chip (or logic control chip) 2014 includes logic I / O pads P31, P33…P3N, which are electrically coupled to I / O pads P11, P13…P1N of the substrate chip 2022, respectively, where N is a positive integer greater than 3. The I / O pads P11, P13…P1N in the substrate chip 2022 of the low-profile 3D IC stack 2012 are further coupled to external bidirectional repeaters ER1, ER2,…, ERN in the substrate chip 2022 via metal lines or the aforementioned RDL structure 118 to transmit and amplify data or signals. Furthermore, each DRAM semiconductor chip MR1, MR2, MR3, or MR4 has the same or substantially the same structure. For example, a DRAM semiconductor wafer MR1 includes multiple first memory I / O pads MIO11, bidirectional repeaters or drivers R1 corresponding to the multiple memory I / O pads MIO11, and micropads MP11, MP12. Similarly, other DRAM semiconductor wafers (e.g., MR2) include multiple second memory I / O pads MIO12, bidirectional repeaters or drivers R2 corresponding to the multiple second memory pads MIO12, and micropads MP21, MP22, etc. In another embodiment, each DRAM semiconductor wafer MR1 to MR4 has row address I / O pads (or interfaces) and column address I / O pads (or interfaces) that are physically independent of the row address I / O pads. This non-multiplexing mode using parallel access paths that simultaneously activate row and column addresses can be used in this invention.

[0254] As mentioned above, this low-profile 3D IC stack 2012 is a complete HBLM architecture, which embodies the following key design attributes: (1) access mode to simultaneously initiate row and column data selection paths without the multiplexing required by conventional packaged DRAM (in a manner similar to SRAM access mode); (2) merging the aforementioned RDL structure to make the plane smooth for simultaneously manufacturing higher I / O and higher bandwidth interconnects; (3) each DRAM semiconductor wafer MR1 to MR4 has its own complete test and probe structure to verify functionality, yield and performance based on a smaller probe pad not connected to the external environment of the wafer, thus eliminating the need for typically large probe pads. (4) Each DRAM semiconductor chip MR1 to MR4 can independently perform functions in RAM operation, such as row and column address input, READ and WRITE instruction input, pulse and control signal positions and I / O when necessary. More importantly, the signals from each DRAM chip can be directly and independently connected to the control positions on the control IC (e.g., the substrate chip 2022). The control IC is equipped with corresponding bidirectional repeaters or drivers R1, R2, ... RN, high-performance transistors and high-conductivity BEOL structures, which are common logic technologies for each DRAM chip.

[0255] In this embodiment, bidirectional repeater R1 in the DRAM semiconductor wafer MR1 is coupled to an external bidirectional repeater ER1 via the metal lines of the aforementioned RDL structure 118; bidirectional repeater R2 is coupled to bidirectional repeater R1 via other metal lines of the aforementioned RDL structure 118; bidirectional repeater R3 is coupled to bidirectional repeater R2 via other metal lines of the aforementioned RDL structure 118; and bidirectional repeater R4 is coupled to bidirectional repeater R3 via other metal lines of the aforementioned RDL structure 118. Additional selection or control signals can be applied to bidirectional repeaters ER1 and / or bidirectional repeaters R1 to R4 for data selection.

[0256] like Figure 20A The operation of the logic chip 2014 and the low-profile 3D IC stack 2012 (or HBLM frame structure) shown is described below. For example, the logic chip 2014 transmits all basic signals through its own IO pads P31 to P3N (i.e., all relevant signal pads), similar to the signal paths defined by JEDEC for HBM, except that conventional HBM requires the use of TSVs to connect all signals / IOs. The low-profile 3D IC stack or HBLM frame 2012 may not require TSVs, and the same operation can generally be achieved more easily using the aforementioned RDL structure 118 and all proven repeater / driver circuitry. Since the signal / IO paths are connected together through the aforementioned RDL structure 118, operations for receiving and transmitting are required to utilize… Figure 20A The control signals in the DRAM semiconductor wafers MR1, MR2, MR3, and MR4 are used to determine whether to load, receive, or transmit the signals. In another embodiment, the bidirectional repeaters ER1, ER2…ERN in the substrate wafer 2022 can be removed, and the substrate wafer 2022 can be... Figure 19A Or the RDL structure or bottom RDL structure 118 described in 19B.

[0257] In addition, in such Figure 20BIn another embodiment of the logic chip 2014 shown, plus the low-profile 3D IC stack 2012 (or HBLM frame structure), each of the bidirectional repeaters R1, R2, R3, and R4 is coupled to an external bidirectional repeater ER1. Specifically, bidirectional repeater R1 is coupled to the external bidirectional repeater ER1 via some metal lines of the aforementioned RDL structure 118; bidirectional repeater R2 is coupled to the external bidirectional repeater ER1 via another metal line of the aforementioned RDL structure 118; bidirectional repeater R3 is coupled to the external bidirectional repeater ER1 via other metal lines of the aforementioned RDL structure 118; and bidirectional repeater R4 is coupled to the external bidirectional repeater ER1 via another metal line of the aforementioned RDL structure 118. Selection circuitry may be coupled to bidirectional repeaters ER1 and / or bidirectional repeaters R1 to R4 to selectively pick up the desired signal.

[0258] In other embodiments of the present invention, bidirectional repeaters R1 (via MIO11), R2 (via MIO12), R3 (via MIO13), and R4 (via MIO14) can be directly coupled to I / O pad P11. That is, the external bidirectional repeaters ER1, ER2, ..., ERN shown can be ignored, and the substrate chip 2022 can be... Figure 19A Alternatively, the RDL structure or bottom RDL structure 118 described in 19B may be used. Furthermore, in another embodiment, the substrate wafer 2022 is not necessary, and all memory I / O pads MIO11 of MR1 can be directly coupled to the corresponding logic I / O pads P11, P13…P1N via the bottom RDL structure 118 instead of via MR2–MR4; all memory I / O pads MIO12 of MR2 can be directly coupled to the corresponding logic I / O pads P21, P23…P2N via the bottom RDL structure 118 instead of via MR1, MR3–MR4; all memory I / O pads MIO13 of MR3 can be directly coupled to the corresponding logic I / O pads P31, P33…P3N via the bottom RDL structure 118 instead of via MR1, MR2, and MR4; and all memory I / O pads MIO14 of MR4 can be directly coupled to the corresponding logic I / O pads P41, P43…P4N via the bottom RDL structure 118 instead of via MR1–MR3.

[0259] Furthermore, micropads MP11 and MP12 can be coupled to external probes (not shown) for testing (e.g., verifying functionality, yield, and performance). According to some embodiments, micropads MP11 and MP12 can be coupled to an environment outside the logic chip 2014 and the low-profile 3D IC stack 2012 (or HBLM frame structure). In this case, conventional electrostatic discharge (ESD) protection circuitry is required, wherein each of the micropads MP11 and MP12 is larger than the I / O pads P11, P13…P1N or other memory I / O pads MIO11, MIO12… configured to be internally coupled to the logic chip 2014.

[0260] According to some embodiments, reference Figure 19A and 19B The IC stack 1901 comprises multiple IC structures 1920 horizontally separated from each other. Each IC structure 1920 can be... Figures 2C-2F Semiconductor structures in 3D-3F, 4G-4N, and 5A-5B, having a top surface 108P1, a bottom surface 108P2 opposite to the top surface 108P1, and four sidewalls 108S, each having a first sidewall 1920S1 or 108S1, a second sidewall 1920S2 or 108S2, a third sidewall 1920S3 or 108S3 (parallel to the paper), and a fourth sidewall (shown in...). Figure 19B The sidewall opposite to the sidewall 1920S3, and parallel to Figure 2D The area of ​​the paper or sidewall 108S4). The area of ​​the bottom surface 108P2 or the top surface 108P1 is greater than Figure 2C The area of ​​any sidewall 102S (e.g., 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), or 108S4). The low-profile 3D IC stack 1901 may further include a laterally extending RDL structure 118 that covers the first sidewall 1920S1 of each of the plurality of IC structures 1920.

[0261] According to some embodiments, reference Figure 19A , 19B , Figure 4G to 4N From 5A to 5B and 6E, each semiconductor structure includes a first integrated circuit (IC) structure, for example... Figure 19A Or a 19B IC structure 1920 or Figure 4G to 4N The chip 122E, and a first adjacent structure physically separated from the first IC structure, such as Figure 19A Or the high thermal conductivity layer 1912 of 19B, or Figure 4G to 4N The molding compound layer 242 and / or wafer 122D. First IC structure and first adjacent structure: (1) arranged along a first sidewall 1912S1 extending in the Z direction, as shown in Figure 19AOr as shown in 19B, or (2) arranged along the first sidewall 1912S1 extending in the XZ plane, as Figure 19A Or as shown in 19B. In condition (2) above, refer to... Figure 4K to 4N The XZ plane of each of the IC structures 400E to 400H can face the RDL structure 118 and form an electrical connection with it. The first IC structure 122E and the first adjacent structure 122D can be arranged on the XZ plane of each of the IC structures 400E to 400H and along the X direction, such as... Figure 19A or Figure 19B As shown in the illustration. According to some embodiments, Figure 19A and 19B The laterally extended RDL structure 118 shown includes a plurality of first bonding pads 1927 arranged along the first sidewall of an individual semiconductor structure 1920, wherein the plurality of first bonding pads are above or facing the edge of the first IC structure and the edge of the first adjacent structure.

[0262] In some embodiments, the first IC structure may include more than one semiconductor wafer, for example Figure 4K to 4N or Figure 6D The wafers 122E, 122G, and / or 122H are shown in the diagram. The first adjacent structure 122D may be an active wafer or an HTC virtual interconnect spacer. The interconnect spacer may be a passive or active silicon interposer. According to some embodiments, the interconnect spacer is a semiconductor interposer having a set of through-semiconductor vias (TSVs) electrically coupled to a subset of a first plurality of bonding pads or external connectors.

[0263] According to some embodiments, the first adjacent structure includes another IC structure (e.g., Figure 4G to 4N The semiconductor wafer 122D shown in the figure), interconnect spacers (e.g.) Figure 4G to 4N The intermediate layer 122D shown in the figure), molding compound layer (e.g. Figure 4G to 4N The potting material or molding compound layer 242 shown in the figure) or the high thermal conductivity (HTC) layer (e.g.) Figure 4G to 4N The wafer 122D shown in the figure has a higher thermal conductivity than Si or SiO2 to dissipate heat from adjacent IC structures.

[0264] According to some embodiments, the number of the first plurality of bonding pads 1927 is greater than 1,300 to 1,500 per IC structure 1920.

[0265] According to some embodiments, reference Figure 4G , Figure 4I , Figure 4K , Figure 4M , Figure 5A and Figure 5BThe first IC structure 122E or another IC structure serving as the first adjacent structure includes a set of through-semiconductor vias (TSVs) 104B exposed from the sidewall 102S of the XZ plane and electrically coupled to... Figure 19A or Figure 19B The first plurality of bonding pads 1927 of the laterally extended RDL structure 118 of the 3D IC stack 1901 shown in the figure.

[0266] According to some embodiments, reference Figure 4G , Figure 4H , Figure 4K , Figure 4L , Figure 5A and Figure 5B The molding compound layer 242 includes a set of through-mold sealing vias (TMVs) 232 exposed from the molding sidewall 102S of the XZ plane, and electrically coupled to... Figure 19A Or the laterally extended RDL structure 118 of the 3D IC stack 1901 shown in 19B (e.g., see also...) Figure 5A A subset of the first plurality of mating pads 1927 shown in RDL 118A in 5B.

[0267] According to some embodiments, reference Figure 4G , Figure 4H , Figure 4K , Figure 4L , Figure 5A and Figure 5B The first adjacent structure 122D may include interconnect spacers with or without active components, having a set of through-semiconductor vias (TSVs), similar to TSV 104B in the first IC structure 122E, exposed from the sidewall 102S of the XZ plane and electrically coupled to... Figure 19A Or a subset of the first plurality of bonding pads 1927 of the laterally extended RDL structure 118 of the low 3DIC stack 1901 shown in 19B.

[0268] According to some embodiments, the IC stack 1901 further includes one of the semiconductor structures 1920, 1912 located between or adjacent to the two semiconductor structures 1920, 1912 (e.g., in a manner similar to...). Figure 19A Or, as shown in 19B, a high thermal conductivity structure with an intermediate high thermal conductivity layer 1912) (e.g. Figure 17 (The intermediate layer is 1702 or 1706). The thermal conductivity of the high thermal conductivity structure is higher than that of Si or SiO2.

[0269] According to some embodiments, each IC structure 1920 may be a DRAM semiconductor wafer, and the IC stack 1901 may be an HBM-compatible structure.

[0270] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 located below and electrically connected to the lateral extension RDL structure 118 of the IC stack 1901.

[0271] According to some embodiments, reference Figure 19A Alternatively, 19B, the IC stack 1901 further includes a laterally extending thermally conductive layer 1914 that covers each of the second sidewalls 1920S2 of the plurality of IC structures 1920, wherein the laterally extending RDL structure 118 is opposite to the laterally extending thermally conductive layer 1914, and the thermal conductivity of the laterally extending thermally conductive layer is higher than that of Si or SiO2.

[0272] According to some embodiments, reference Figure 19A and 19B The IC stack 1901 contains multiple horizontally separated IC structures 1920. (Reference) Figures 2C-2F For each IC structure (3D-3F, 4G-4N, 5A-5B, and 19A), please refer to 1920. Figures 2C to 2F IC structures from 3D to 3F, 4G to 4N, and 5A to 5B, including 100A to 100C, 300A to 300C, 400A to 400H, 500A, and 500B. For example... Figure 2D As shown, each IC structure 1920 has dimensions similar to those of the RDL structures 108A and includes a top surface 108P1, a bottom surface 108P2 opposite to the top surface 108P1, and four sidewalls having a first sidewall 1920S1 or 108S1, a second sidewall 1920S2 or 108S2, a third sidewall 1920S3 or 108S3, and a fourth sidewall 108S4. The area of ​​the bottom surface 108S2 or the top surface 108S1 is larger than the area of ​​any sidewall (e.g., 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), and 108S4). The IC stack 1901 may further include a laterally extending RDL structure 118 that covers each of the first sidewalls 1920S1 (108S1) of each of the plurality of IC structures 1920. IC stack 1901 may also include an upwardly extending thermally conductive layer 1912 between two adjacent IC structures 1920. According to some embodiments, the thermal conductivity of the upwardly extending thermally conductive layer 1912 is higher than that of Si or SiO2, for example, a SiC wafer having the same dimensions as IC structure 1920.

[0273] According to some embodiments, the IC stack 1901 further includes a laterally extending thermally conductive layer 1914 that covers each of the second sidewalls 108S2 or 1920S2 of the plurality of IC structures 1920 and is thermally coupled to each of the upwardly extending thermally conductive layers 1912, wherein the laterally extending RDL structure 118 is opposite to the laterally extending thermally conductive layer 1914, and the thermal conductivity of the laterally extending thermally conductive layer 1914 is higher than that of Si or SiO2, such as SiC wafer.

[0274] According to some embodiments, the upwardly extending thermal conductive layer 1912 or the laterally extending thermal conductive layer 1914 comprises a material of BN, AlN, W, SiC or copper.

[0275] According to some embodiments, reference Figure 19B The IC stack 1901 further includes an upwardly extending RDL structure 1916 that covers each of the third sidewalls 108S3 or 1920S3 of the plurality of IC structures 1920, wherein the upwardly extending RDL structure 1916 is electrically connected to the laterally extending RDL structure 118.

[0276] According to some embodiments, each IC structure 1920 includes a DRAM semiconductor wafer, and the IC stack 1901 is an HBM-compatible structure (i.e., the basic signals transmitted through its own IO pads P31 to P3N are compatible with the signal paths defined by JEDEC for HBM).

[0277] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 located below and electrically connected to the lateral extension RDL structure 118 of the IC stack 1901.

[0278] According to some embodiments, reference Figure 19A and Figure 20A or Figure 20B Each IC structure 1920 is a DRAM semiconductor chip MR1, MR2, MR3, or MR4, and each includes multiple memory I / O pads MIO11, MIO12, MIO13, or MIO14. According to some embodiments, Figure 19A Or the logic control chip 1906 shown in 19B could be Figure 20A Or the logic control chip 2014 shown in 20B and containing multiple logic I / O pads P31-P3N. Multiple memory I / O pads MIO11 to MIO14 of each of the DRAM semiconductor chips MR1 ​​to MR4 are connected via... Figure 19A Or the laterally extended RDL structure 118 shown in 19B is electrically coupled to multiple logic I / O pads P31 to P3N.

[0279] According to some embodiments, memory I / O pads MIO11 to MIO14 do not include electrostatic discharge (ESD) protection circuitry. Each DRAM semiconductor wafer MR1 to MR4 includes multiple row address I / O pads (not shown separately), and multiple column address I / O pads (not shown separately) are physically independent of the multiple row address I / O pads.

[0280] According to some embodiments, reference Figure 20A Each DRAM semiconductor wafer MR1 to MR4 further includes multiple external bidirectional repeaters R1, R2, R3, or R4. The bidirectional repeater R2 of the second DRAM semiconductor wafer MR2 is electrically coupled to the corresponding bidirectional repeater R1 of the first DRAM semiconductor wafer MR1 through a second metal line of the laterally extended RDL structure 118 or the upwardly extended RDL structure 1916, and the corresponding bidirectional repeater R1 of the first DRAM semiconductor wafer MR1 is electrically coupled to the corresponding logic I / O pad P31 of the logic control wafer 2014 through a first metal line of the laterally extended RDL structure 118 or the upwardly extended RDL structure 1916.

[0281] According to some embodiments, reference Figure 20B Each DRAM semiconductor wafer MR1 to MR4 further includes multiple external bidirectional repeaters R1 to R4, wherein the bidirectional repeater R1 of the first DRAM semiconductor wafer MR1 is electrically coupled to the corresponding logic I / O pad P31 of the logic control wafer 2014 through the first metal line of the laterally extended RDL structure 118 or the upwardly extended RDL structure 1916, and the bidirectional repeater R2 of the second DRAM semiconductor wafer MR2 is electrically coupled to the corresponding logic I / O pad P31 of the logic control wafer through the second metal line of the laterally extended RDL structure 118 or the upwardly extended RDL structure 1916.

[0282] According to some embodiments, reference Figure 19A , 19B and Figure 2C , 2D IC structure 1920 may include IC structures 100A to 100C, 300A to 300C, 400A to 400H, 500A, 500B, and 600A, up to 2F, 3D to 3F, 4G to 4N, 5A, 5B, and 6E. For example, refer to... Figure 5A , 5B and Figure 19AAlternatively, IC structure 1920 includes IC structure 500A, and the IC structure includes a first semiconductor body 122F and an interconnect structure 108A or 108B. The first semiconductor body (122E or 122F) has a first primary surface (102P) and a first secondary surface (102S), wherein the first primary surface is substantially perpendicular to the first secondary surface. The interconnect structure includes a primary redistribution layer (RDL) located above the first primary surface 102P. Figure 5A , 108A), which has a second sub-surface ( Figure 5A The main RDL 108A of the second sub-surface 108S is aligned with the first sub-surface 102S of the first semiconductor body 122F, wherein the first sub-surface 102S and the second sub-surface 108S together form a sub-plane. Figure 5A ,500AS), which may correspond to the first sidewall 1920S1 or the second sidewall 1920S2 of IC structure 1920, wherein the main RDL 108S further includes a first conductive element exposed through the second sub-surface 108S of the main RDL 108A ( ,500AS), Figure 5A , 212, 214).

[0283] According to some embodiments, the first conductive element may be a conductive pad 212 located on surface 108P of the main RDL structure 108A / 108B (see...). Figure 2C ), which is substantially parallel to the first main surface 102P1 and connects the adjacent layers of the main RDL 118A / 118B via conductive via 216 (see Figure 2G ), through the stacked via 214 of the main RDL 118A / 118B (see Figure 2G ), or combinations thereof.

[0284] According to some embodiments, the first semiconductor body ( Figure 4G Or 122E in 4I) further includes at least one through-silicon via 104B ( Figure 4G ), through hole 232 ( Figure 4G ) or through the first exposed insulating component 242 ( Figure 4I ).

[0285] According to some embodiments, Figure 19A The first semiconductor body of the IC structure 1920 shown in 19B can be used as... Figure 4K to 4N or Figure 6E The semiconductor wafers 400A to 400H or 600A shown in the image are mating components, and include: (1) a plurality of first wafers 122D and 122E disposed in the same packaging layer. Figure 4K to 4N (2) Multiple vertically stacked second wafers 122G, 122H Figure 6E (3) Multiple second wafers 122G, 122H placed side by side with other third wafers 122E in the same packaging layer. Figure 6E (or combinations thereof). The first, second and third wafers 122D, 122E, 122G and 122H have the same or different dimensions.

[0286] According to some embodiments, Figure 19A The first semiconductor body of the IC structure 1920 shown in 19B (see partial structure of semiconductor wafer 600A other than main RDL 108C) also includes multiple conductive vias 104B (see semiconductor wafer 122E), pillars 224 or plugs 234 of the same or different lengths, electrically connecting multiple first wafers 122E, 122G and 122H to, for example, Figure 6E The main RDL 108C shown along the Z-axis and / or electrically connected to, for example Figure 6E , 19A Or the lateral extension RDL structure 118 of the XZ plane shown in 19B.

[0287] According to some embodiments, Figure 19A Or, as shown in 19B, the laterally extended RDL structure 118 is electrically connected to the first conductive element of the main RDL. Figure 4G Or the conductive pad 212 or conductive via 214 shown in 6D. Figure 6D The column 224 or plug 234 shown in the image.

[0288] According to some embodiments, the laterally extended RDL structure 118 (corresponding to...) Figure 7I The RDL 118A shown in the image contains a hybrid bonding layer or bump pad array (244).

[0289] According to some embodiments, reference Figure 19A and 19B The IC stack 1901 contains multiple horizontally separated IC structures 1920. (Reference) Figure 2C , 2D And 19A, each IC structure 1920 can be Figure 2D The structure 108A shown includes a top surface 108P1, a bottom surface 108P2 opposite to the top surface, and four sidewalls, including a first sidewall 1920S1 or 108S1, a second sidewall 1920S2 or 108S2, a third sidewall 1920S3 or 108S3, and a fourth sidewall 108S4. The area of ​​the bottom or top surface is greater than any of the four sidewalls (e.g., 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), and 108S4). The IC stack 1901 may further include a laterally extending RDL structure 118 that covers each of the first sidewalls 1920S1 (108S1) of each of the plurality of IC structures 1920.

[0290] According to some embodiments, the IC stack 1901 further includes a set of upwardly extending thermally conductive layers 1912, wherein corresponding upwardly extending thermally conductive layers 1912 are disposed between any two adjacent IC structures 1920 of the plurality of IC structures 1920. The IC stack 1901 may also include a first laterally extending thermally conductive layer 1914, which covers each of each second sidewall 1920S2 (108S2) of each of the plurality of IC structures 1920 and is thermally coupled to the set of upwardly extending thermally conductive layers 1912. The thermal conductivity of either the upwardly extending thermally conductive layer 1912 or the first laterally extending thermally conductive layer 1914 is higher than that of Si or SiO2.

[0291] According to some embodiments, reference Figure 19B The IC stack 1901 further includes a second laterally extending thermally conductive layer 1917 that covers each of the third sidewalls 1920S3 (108S3) of the plurality of IC structures 1920. The second laterally extending thermally conductive layer 1917 is thermally coupled to the group of upwardly extending thermally conductive layers 1912.

[0292] According to some embodiments, IC stack 1901 is an HBM-compatible structure and each IC structure 1920 includes a DRAM semiconductor wafer 1920. IC stack 1901 further includes a logic control wafer 1906 located below and electrically connected to the laterally extended RDL structure 118 of IC stack 1901.

[0293] In summary, the present invention provides a 3D IC stack having multiple semiconductor wafers, with an RDL located above the sides of the 3D IC stack for interconnecting the wafers in the 3D IC stack to allow signal and power distribution across the wafers. Furthermore, a high thermal conductivity material is disposed between two adjacent semiconductor wafers and thermally coupled to other high thermal conductivity materials, covering the other sides of the 3D IC stack.

[0294] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other operations and structures to implement the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0295] Symbol Explanation

[0296] 100A: Semiconductor Packaging Device / IC Structure

[0297] 100AS: Secondary plane / Side plane

[0298] 100W: Semiconductor device

[0299] 101: Interconnection Structure

[0300] 102: Substrate

[0301] 102P, 102P1: Main surface

[0302] 102S: Side surface

[0303] 104: Conductive Through-Hole / TSV

[0304] 104A: Internal TSV

[0305] 104B: Edge TSV

[0306] 106: Temporary carrier, substrate

[0307] 108A, 108B, 108C: Main RDL

[0308] 108D, 108E, 108F: Main RDL

[0309] 108P, 108P1, 108P2: Main surface

[0310] 108S1, 108S2, 108S3, 108S4: Side surfaces

[0311] 108X: Internal interconnect structure

[0312] 110: Release Layer

[0313] 110S: Carrier surface

[0314] 116: Carrier substrate

[0315] 118A, 118B: Secondary RDL

[0316] 118F: Front interconnect surface

[0317] 118R: Post-interconnect surface

[0318] 118X: Edge interconnect structure

[0319] 120: Release Layer

[0320] 122A, 122B, 122C, 122D, 122D1: Chips

[0321] 122E, 122F, 122G, 122H: Chips

[0322] 126: Carrier substrate

[0323] 130: Release Layer

[0324] 136: Carrier substrate

[0325] 138A, 138B: Edge Interconnect RDL Structure

[0326] 140: Release Layer

[0327] 142A, 142B, 142C: IC Structure

[0328] 142AP, 142BP, 142CP: Main Surface

[0329] 142AS, 142BS, 142CS: Side surfaces

[0330] 142D, 142E, 142F: IC Structure

[0331] 143A, 143B, 143C: IC Structure

[0332] 144A, 144B, 144C: ​​IC Structure

[0333] 144AP1: Upper Main Surface

[0334] 144AP2: Lower main surface

[0335] 148A, 148B: Secondary RDL

[0336] 148L1: First bonding layer

[0337] 148L2: Second bonding layer

[0338] 148L3: Third bonding layer

[0339] 148L4: Fourth bonding layer

[0340] 148S1: Joint surface

[0341] 150A: First Connector Layer

[0342] 150B: Second Connecting Layer

[0343] 160: Bonding layer

[0344] 162A, 162B, 162C, 162D: IC Structure

[0345] 168: RDL Structure

[0346] 172: Conductive traces or wires

[0347] 202: Conductive components

[0348] 212: Conductive pad / Internal conductive pad / Edge conductive pad

[0349] 214: Conductive via / Internal via / Edge via

[0350] 214-1, 214-2: Conductive vias

[0351] 216: Conductive via

[0352] 222: Edge conductive pad

[0353] 224: Internal conductive pillar

[0354] 232: Edge TMV

[0355] 234: Conductive plug

[0356] 240: First main wire / through-hole layer

[0357] 242, 252, 262: Potting materials

[0358] 244: Conductive bump

[0359] 250: Second main wire / via layer

[0360] 252R: Through hole

[0361] 254: Conductive pad

[0362] 264, 274: Conductive pads / microbumps

[0363] 282, 282A, 282B: Edge conductive pads / microbumps

[0364] 284: Conductive pad / microbump

[0365] 286: Joint pad

[0366] 300A, 300B, 300C: IC Structure

[0367] 300W: Semiconductor device

[0368] 302: Microbumps / Edge Conductive Components

[0369] 304: Insulated conductive trace or wire / conductive trace

[0370] 306: Insulated conductive trace or wire / conductive trace

[0371] 312: Low IC stacking

[0372] 312A: First semiconductor structure

[0373] 312B: Second semiconductor structure

[0374] 312P, 312P1, 312P2: Main surface

[0375] 312S1, 312S2, 312S3, 312S4: Transverse side surfaces

[0376] 322, 422: High IC stacking

[0377] 322L1: First bonding layer

[0378] 322L2: Second bonding layer

[0379] 332: Low IC stacking

[0380] 340, 350: Main wire / through-hole layer

[0381] 400A, 400B, 400C, 400D: IC Structure

[0382] 400E, 400F, 400G, 400H: IC Structure

[0383] 400W, 401W: Semiconductor devices

[0384] 500A, 500B: IC structure

[0385] 500AS: Subplane

[0386] 500BS1, 500B2: Subplane

[0387] 600A: IC Structure

[0388] 600AS1, 600AS2: Subplane

[0389] 600W: Semiconductor wafer / semiconductor device

[0390] 700A, 700B, 700C: Semiconductor Packaging

[0391] 700BS: Subplane

[0392] 700CS1, 700CS2: Subplane

[0393] 700L: High IC stacking structure

[0394] 700W, 701W, 702W, 1001W, 1002W, 1003W: Semiconductor devices

[0395] 800A, 802W, 1000A, 1000B, 1100A, 1200A, 1300A: Semiconductor Packaging

[0396] 1000L, 1523, 1603: IC structure

[0397] 1100AS1, 1100AS2, 1100BS1, 1100BS1: Subplane

[0398] 1200W, 1300W: Semiconductor devices

[0399] 1400A, 1400B: Semiconductor package assemblies

[0400] 1410: Substrate

[0401] 1412: First Added Layer

[0402] 1413: External electrical connection

[0403] 1414: Second Added Layer

[0404] 1416: Core Layer

[0405] 1418: Plated through holes

[0406] 1420: Carrier

[0407] 1420S1, 1420S1: Interconnect surface

[0408] 1423: External Links

[0409] 1430, 1440: Semiconductor packaging

[0410] 1430S: Subplane

[0411] 1440P: Main Surface

[0412] 1443, 1512, 1514, 1516: External links

[0413] 1500: Semiconductor package assembly

[0414] 1501: IC Stacking

[0415] 1502: Laminated substrate

[0416] 1504: Intermediary Layer

[0417] 1506: First Semiconductor Stack

[0418] 1508: Second semiconductor chip, second logic semiconductor chip

[0419] 1510: Logic control chip

[0420] 1518: External connector

[0421] 1522: Semiconductor Structure

[0422] 1524: Support substrate

[0423] 1526: Adhesive layer

[0424] 1542: First Semiconductor HBM Stack

[0425] 1543: Memory chip stacking

[0426] 1600A: Semiconductor wafer

[0427] 1600W, 1800W, 1801W, 1802W: Semiconductor devices

[0428] 1602: Release layer

[0429] 1604: Definition Layer

[0430] 1606: Interface Materials (TIM)

[0431] 1608: Heatsink

[0432] 1604R: Groove

[0433] 1700: Semiconductor package assembly

[0434] 1702: First Intermediary Layer

[0435] 1704: Bridge chip

[0436] 1706: Second Intermediary Layer

[0437] 1708: Third Semiconductor Wafer

[0438] 1710: Heatsink

[0439] 1712, 1714, 1716, 1718: External connectors

[0440] 1722, 1724: TSV

[0441] 1800A: Semiconductor Packaging

[0442] 1800L: High IC stacking structure

[0443] 1802: HTC layer

[0444] 1812: Low-profile IC stacking

[0445] 1822: High IC Stacking

[0446] 1824: High thermal conductivity layer

[0447] 1900: Semiconductor package assembly

[0448] 1901: 3DIC Structure Stack

[0449] 1902: Substrate

[0450] 1904: Intermediate Layer

[0451] 1906: Logic control chip

[0452] 1908: HTC adhesive layer

[0453] 1912: High thermal conductivity layer

[0454] 1912S1: First sidewall

[0455] 1914: High thermal conductivity layer

[0456] 1916: RDL Structure

[0457] 1917: Intermediate heat-conducting layer

[0458] 1920: IC Structure

[0459] 1920S1: First sidewall

[0460] 1920S2: Second sidewall

[0461] 1920S3: Third sidewall

[0462] 1927: Joint Pad

[0463] 2000: Semiconductor Packaging Assembly

[0464] 2012: Low-profile 3D IC stacking

[0465] 2014: Logic Control Chip

[0466] 2022: Substrate Wafer

[0467] 2024: Logic Bridge Area

[0468] 90:2.5 DIC

[0469] 900A: Semiconductor Packaging / Low-Distance IC Stacking Structure

[0470] 900AS: Subplane

[0471] 900W: Semiconductor device

[0472] 901: Laminated substrate

[0473] 902: Silicon interposer

[0474] 903: Solder Support

[0475] 903: Solder bump or micro bump

[0476] 903a: Solder bump

[0477] 904: Through Silicon Via (TSV)

[0478] 905: Memory Structure

[0479] 905a: DRAM chip

[0480] 905b: Substrate wafer

[0481] 906: Welding ball

[0482] 906: Ball Grid Array (BGA) Solder Balls

[0483] 907: Processor IC

[0484] 908: Laminated substrate

[0485] 91: Fan-out SiP / Fan-out Package Structure

[0486] 911 fan-out wiring layer

[0487] 913a: Chip

[0488] 913b: Chip

[0489] 914: Silicon interposer

[0490] 916: CMOS chip

[0491] 917: Laser Diode

[0492] 918: Waveguide RDL Structure

[0493] 919: Modulator

[0494] 92: Embedded SiP

[0495] 920: Photodetector

[0496] 921: Fiber Optics

[0497] 923: Device

[0498] 93: Silicon photonic structure

[0499] 94: 3D IC

[0500] 940: The First Carrier

[0501] 941: The First Chip

[0502] 942: Second chip

[0503] 943: Through hole

[0504] 95: 3D IC

[0505] 951: The First Carrier

[0506] 952: Second Carrier

[0507] 953: Interconnect layer

[0508] 954: Through hole

[0509] 955: Solder bumps, microbumps, or solder balls

[0510] 96: Semiconductor packaging assembly

Claims

1. An IC stack comprising: Multiple horizontally separated integrated circuit (IC) structures, each IC structure including a top surface, a bottom surface opposite the top surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of ​​the bottom surface or the top surface is greater than the area of ​​any sidewall; A laterally extending RDL structure covers each of the first sidewalls of the plurality of IC structures; and An upwardly extending thermal conductive layer between two adjacent IC structures.

2. The IC stack of claim 1, further comprising a laterally extending thermally conductive layer covering each second sidewall of the plurality of IC structures and thermally coupled to the upwardly extending thermally conductive layer, wherein the laterally extending RDL structure is opposite to the laterally extending thermally conductive layer, and the thermal conductivity of the upwardly extending thermally conductive layer and / or the laterally extending thermally conductive layer is higher than that of silicon.

3. The IC stack of claim 2, wherein the upwardly extending thermal conductive layer or the laterally extending thermal conductive layer comprises BN, AlN, W, SiC or copper.

4. The IC stack of claim 1, further comprising an upwardly extending RDL structure covering each third sidewall of the plurality of IC structures, wherein the upwardly extending RDL structure is electrically connected to the laterally extending RDL structure.

5. The IC stack of claim 4, wherein each IC structure comprises a DRAM semiconductor wafer, and the IC stack is an HBM-compatible structure.

6. The IC stack of claim 4, further comprising a logic control chip located below and electrically connected to the lateral extension RDL structure of the IC stack.

7. The IC stack of claim 6, wherein each of the IC structures includes a DRAM semiconductor wafer, the DRAM semiconductor wafer includes a plurality of memory I / O pads, the logic control wafer includes a plurality of logic I / O pads, and the plurality of memory I / O pads of each DRAM semiconductor wafer are electrically coupled to the plurality of logic I / O pads through the laterally extended RDL structure.

8. The IC stack of claim 7, wherein the memory I / O pad does not include electrostatic discharge (ESD) protection circuitry, or each DRAM semiconductor wafer further includes a plurality of row address pads and a plurality of column address pads, the plurality of column address pads being physically independent of the plurality of row address pads.

9. The IC stack of claim 7, wherein each DRAM semiconductor wafer further includes a plurality of external bidirectional repeaters, wherein the bidirectional repeater of the second DRAM semiconductor wafer is electrically coupled to a corresponding bidirectional repeater of the first DRAM semiconductor wafer via a second metal line of the laterally extended RDL structure or the upwardly extended RDL structure, and the corresponding bidirectional repeater of the first DRAM semiconductor wafer is electrically coupled to a corresponding logic I / O pad of the logic control wafer via a first metal line of the laterally extended RDL structure or the upwardly extended RDL structure.

10. The IC stack of claim 7, wherein each DRAM semiconductor wafer further includes a plurality of external bidirectional repeaters, wherein the bidirectional repeater of the first DRAM semiconductor wafer is electrically coupled to a corresponding logic I / O pad of the logic control wafer via a first metal line of the laterally extended RDL structure or the upwardly extended RDL structure, and the bidirectional repeater of the second DRAM semiconductor wafer is electrically coupled to a corresponding logic I / O pad of the logic control wafer via a second metal line of the laterally extended RDL structure or the upwardly extended RDL structure.

11. The IC stack of claim 1, wherein the first IC structure of the plurality of IC structures comprises: A first semiconductor body has a first main surface and a first secondary surface, wherein the first main surface is substantially perpendicular to the first secondary surface; and An interconnect structure including a primary redistribution layer (RDL) above the first primary surface, wherein the primary RDL has a second secondary surface aligned with the first secondary surface of the first semiconductor body; The first sub-surface and the second sub-surface together form a sub-plane, and the main RDL further includes a first conductive element, which is exposed through the second sub-surface of the main RDL.

12. The IC stack of claim 11, wherein the first conductive element comprises a conductive pad on a surface of the main RDL substantially parallel to the first main surface, a conductive via connecting adjacent layers of the main RDL, a stacking via through the main RDL, or a combination thereof.

13. The IC stack of claim 12, wherein the first semiconductor body further includes at least one of a through-silicon via, a through-hole, or an insulating component exposed through the first secondary surface.

14. The IC stack of claim 11, wherein the first semiconductor body comprises a plurality of first wafers disposed in the same package layer, vertically stacked second wafers, the vertically stacked second wafers being placed side by side with other third wafers in the same package layer, or a combination thereof.

15. The IC stack of claim 14, wherein the first semiconductor body includes a plurality of conductive vias, pillars, or plugs of the same or different lengths to electrically connect the plurality of first wafers to the main RDL and / or the lateral extension RDL structure.

16. The IC stack of claim 11, wherein the laterally extended RDL structure is electrically connected to the first conductive element of the main RDL, a conductive via, a pillar or plug in the first semiconductor body, or a combination thereof; wherein the laterally extended RDL structure comprises a hybrid bonding layer or a bump pad array.

17. An IC stack comprising: Multiple horizontally separated integrated circuit (IC) structures, wherein each IC structure includes a top surface, a bottom surface opposite the top surface, and four sidewalls, having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of ​​the bottom surface or the top surface is greater than the area of ​​any of the four sidewalls; A set of upwardly extending thermal conductive layers, wherein a corresponding upwardly extending thermal conductive layer is disposed between any two adjacent IC structures of the plurality of IC structures; and A first laterally extending thermally conductive layer covers each of the second sidewalls of the plurality of IC structures and is thermally coupled to the set of upwardly extending thermally conductive layers.

18. The IC stack of claim 17, further comprising a laterally extending RDL structure that covers each of the first sidewalls of the plurality of IC structures.

19. The IC stack of claim 18, wherein each IC structure includes a DRAM semiconductor wafer, and the IC stack further includes a logic control wafer located below and electrically connected to the lateral extension RDL structure of the IC stack; wherein the IC stack is an HBM-compatible structure.

20. The IC stack of claim 17, further comprising a second laterally extending thermally conductive layer covering each third sidewall of the plurality of IC structures, wherein the second laterally extending thermally conductive layer is thermally coupled to the set of upwardly extending thermally conductive layers.

21. An IC stack comprising: Multiple horizontally separated semiconductor structures, each semiconductor structure having a top surface, a bottom surface opposite the top surface, and four sidewalls, having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of ​​the bottom surface or the top surface is greater than the area of ​​any sidewall. and A laterally extending RDL structure covers the first sidewall of each semiconductor structure; The first semiconductor structure of the plurality of semiconductor structures includes a first integrated circuit (IC) structure and a first adjacent structure physically separated from the first IC structure, wherein the first IC structure and the first adjacent structure are arranged along the first sidewall of the first semiconductor structure; The lateral extension RDL structure includes a plurality of first bonding pads arranged along a first sidewall of the first semiconductor structure, wherein the plurality of first bonding pads are located above the edge of the first integrated circuit (IC) structure and above the edge of the first adjacent structure.

22. The IC stack of claim 21, wherein the number of the first plurality of bonding pads is greater than 1300 to 1500.

23. The IC stack of claim 21, wherein the first adjacent structure includes another IC structure, interconnect spacers, molding compound layer, or a high thermal conductivity layer with a thermal conductivity higher than that of silicon.

24. The IC stack of claim 23, wherein the first IC structure or the other IC structure includes a set of through-semiconductor vias (TSVs) electrically coupled to a subset of the first plurality of bonding pads.

25. The IC stack of claim 23, wherein the molding compound layer includes a set of through-mold sealed vias (TMVs) electrically coupled to a subset of the first plurality of bonding pads.

26. The IC stack of claim 23, wherein the interconnect spacer is a semiconductor interposer having a set of through-semiconductor vias (TSVs) electrically coupled to a subset of the first plurality of bonding pads.

27. The IC stack of claim 21, further comprising a high thermal conductivity structure adjacent to the first semiconductor structure, wherein the high thermal conductivity structure has a higher thermal conductivity than silicon.

28. The IC stack of claim 21, wherein each first IC structure comprises a DRAM semiconductor wafer, and the IC stack is an HBM-compatible structure.

29. The IC stack of claim 28, further comprising a logic control chip below and an laterally extended RDL structure electrically connected to the IC stack.

30. The IC stack of claim 21, further comprising a laterally extending thermally conductive layer covering each of the second sidewalls of the plurality of semiconductor structures, wherein the laterally extending RDL structure is opposite to the laterally extending thermally conductive layer, and the thermal conductivity of the laterally extending thermally conductive layer is higher than that of silicon.

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