Plasma processing apparatus and etching method

Abstract

The plasma processing apparatus includes a chamber, a substrate support portion, a gas supply portion, a first high-frequency power source, a voltage pulse source, a second high-frequency power source, and a control portion. The substrate supporting part is arranged in the chamber and can support the substrate. The control unit is capable of performing control such that, when etching the substrate, the processing gas is supplied from the gas supply unit into the chamber, the first high-frequency electric power is supplied from the first high-frequency power source, the processing gas in the chamber is converted into plasma, and the voltage pulse is supplied from the voltage pulse source to the substrate support unit, and the first high-frequency electric power is supplied from the first high-frequency power source to the substrate support unit. Second high-frequency electric power is supplied to the substrate supporting part from a second high-frequency power supply in a manner of being superposed with the voltage pulse.

Description

Technical Field

[0001] This invention relates to plasma processing apparatus and etching method. Background Technology

[0002] Patent document 1 discloses "a plasma processing apparatus, characterized in that it comprises: a chamber; a first matching circuit coupled to the chamber; a second matching circuit coupled to the chamber; a first RF generation unit coupled to the first matching circuit, capable of generating a first RF pulse signal comprising multiple pulse cycles, each of the multiple pulse cycles comprising a first period, a second period, and a third period, the first RF pulse signal having a first power level in the first period, a second power level in the second period, and a third power level in the third period, the first period being 30 μs or less; and a second RF generation unit coupled to the second matching circuit, capable of generating a first RF pulse signal comprising the first RF pulse signal, a second RF pulse signal coupled to the second matching circuit, and ... A second RF pulse signal with multiple pulse cycles, the frequency of the second RF pulse signal being lower than the frequency of the first RF pulse signal, the second RF pulse signal having a fourth power level during the first period and a fifth power level during at least one of the second period and the third period; and a third RF generation unit coupled to the second matching circuit, capable of generating a third RF pulse signal including the multiple pulse cycles, the frequency of the third RF pulse signal being lower than the frequency of the second RF pulse signal, the third RF pulse signal having a sixth power level during the second period and a seventh power level during at least one of the first period and the third period.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-048032 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] This invention provides a technique for reducing residue.

[0008] Means for solving technical problems

[0009] A plasma processing apparatus according to one aspect of the present invention includes a chamber, a substrate support, a gas supply unit, a first high-frequency power supply, a voltage pulse source, a second high-frequency power supply, and a control unit. The substrate support is disposed within the chamber and is capable of supporting a substrate. The gas supply unit is capable of supplying processing gas into the chamber. The first high-frequency power supply is capable of supplying a first high-frequency electrical power for plasmaizing the processing gas within the chamber. The voltage pulse source is capable of supplying a voltage pulse obtained by pulsed DC voltage to the substrate support. The second high-frequency power supply is capable of supplying a second high-frequency electrical power to the substrate support. The control unit is capable of controlling the process such that, during etching of the substrate, processing gas is supplied from the gas supply unit into the chamber, and the first high-frequency electrical power is supplied from the first high-frequency power supply to plasmaize the processing gas within the chamber; a voltage pulse is supplied from the voltage pulse source to the substrate support, and a second high-frequency electrical power is supplied from the second high-frequency power supply to the substrate support in superimposed with the voltage pulse.

[0010] Invention Effects

[0011] Using this invention can reduce residue. Attached Figure Description

[0012] Figure 1 This is a diagram used to illustrate a structural example of an inductively coupled plasma processing device.

[0013] Figure 2A This is a diagram illustrating an example of etching the substrate W according to the first embodiment.

[0014] Figure 2B This is a diagram illustrating an example of etching the substrate W according to the first embodiment.

[0015] Figure 3A This is a diagram illustrating an example of etching the substrate W according to the first embodiment.

[0016] Figure 3B This is a diagram illustrating an example of etching the substrate W according to the first embodiment.

[0017] Figure 4A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the first reference example.

[0018] Figure 4B This is a diagram schematically illustrating the movement of ions and free radicals in the plasma during the etching method of the first reference example.

[0019] Figure 4C This is a diagram illustrating an example of the energy distribution of ions in the etching method of the first reference example.

[0020] Figure 5AThis is a diagram illustrating an example of the potential change of the substrate W in the etching method of the second reference example.

[0021] Figure 5B This is a diagram schematically illustrating the movement of ions and free radicals in the plasma during the etching method of the second reference example.

[0022] Figure 5C This is a diagram illustrating an example of the energy distribution of ions in the etching method of the second reference example.

[0023] Figure 6 This is a diagram showing an example of residue remaining on the substrate after etching according to the first embodiment.

[0024] Figure 7A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the first embodiment.

[0025] Figure 7B This is a diagram illustrating an example of the energy distribution of ions in the etching method of the first embodiment.

[0026] Figure 8A This diagram illustrates the processing conditions of the etching method for the first reference example during the first verification.

[0027] Figure 8B This diagram illustrates the processing conditions of the etching method of the first embodiment during the first verification.

[0028] Figure 9A This diagram illustrates the processing conditions of the etching method of the first embodiment during the second verification.

[0029] Figure 9B This diagram illustrates the processing conditions of the etching method of the first embodiment during the second verification.

[0030] Figure 10A This diagram illustrates the processing conditions of the etching method of the first embodiment during the third verification.

[0031] Figure 10B This diagram illustrates the processing conditions of the etching method of the first embodiment during the third verification.

[0032] Figure 11 This is a flowchart illustrating an example of the processing sequence of the etching process in the first embodiment.

[0033] Figure 12A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the second embodiment.

[0034] Figure 12BThis is a diagram illustrating an example of the energy distribution of ions in the etching method of the second embodiment.

[0035] Figure 13A This is a diagram illustrating the potential change of substrate W when the amplitude of the bias DC signal is changed.

[0036] Figure 13B This is a graph illustrating the change in the energy distribution of ions when the amplitude of the bias DC signal is changed.

[0037] Figure 14A This is a diagram illustrating the potential change of substrate W when the on-time of the bias DC signal is changed.

[0038] Figure 14B This is a graph illustrating the change in ion energy distribution when the on-time of the bias DC signal is altered.

[0039] Figure 15A This is a diagram illustrating the potential change of substrate W when the amplitude of the bias RF signal is changed.

[0040] Figure 15B This is a graph illustrating the change in the energy distribution of ions when the amplitude of the bias RF signal is changed.

[0041] Figure 16A This is a diagram illustrating the potential change of substrate W when the off-time of the bias DC signal is changed.

[0042] Figure 16B This is a graph illustrating the change in ion energy distribution when the off-time of the bias DC signal is altered.

[0043] Figure 17 This is a diagram illustrating the potential change of the substrate W when the superposition period of the superposition bias RF signal is changed.

[0044] Figure 18 This is a diagram illustrating the potential change of the substrate W when the superposition period of the superposition bias RF signal is changed. Detailed Implementation

[0045] Hereinafter, embodiments of the plasma processing apparatus and etching method of the present invention will be described in detail with reference to the accompanying drawings. However, the plasma processing apparatus and etching method of the present invention are not limited to these embodiments.

[0046] Plasma processing apparatuses can mount substrates on substrate supports within a cavity and generate plasma within the cavity to perform plasma processing such as etching. High vertical processing performance is required in the manufacture of semiconductor devices. Therefore, in plasma processing apparatuses, etching methods are known that apply a pulsed rectangular wave DC voltage to the substrate support to etch the substrate. By applying a rectangular wave DC voltage to the substrate support during etching, the verticality of the ions can be improved, resulting in high vertical processing performance.

[0047] However, due to the increased verticality of the ions, some residue may remain in the corners of the bottom after etching. Therefore, a technology to reduce residue is desired.

[0048] [First Implementation Method]

[0049] [Device Structure]

[0050] An example of the plasma processing apparatus of the present invention will be described. In the embodiments described below, the case of a plasma processing system in which the plasma processing apparatus of the present invention is configured is used as an example.

[0051] The following describes a structural example of a plasma processing system. Figure 1 This is a diagram used to illustrate a structural example of an inductively coupled plasma processing device.

[0052] The plasma processing system includes an inductively coupled plasma processing device 1 and a control unit 2. The inductively coupled plasma processing device 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing chamber 10 corresponds to the chamber of this invention. The plasma processing chamber 10 includes a dielectric window. Additionally, the plasma processing device 1 includes a substrate support 11, a gas inlet, and an antenna 14. The substrate support 11 is disposed within the plasma processing chamber 10. The antenna 14 is disposed on or above the plasma processing chamber 10 (i.e., on or above the dielectric window 101). The plasma processing chamber 10 has a plasma processing space 10s defined by the dielectric window 101, the sidewall 102 of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one type of processing gas to the plasma processing space 10s; and at least one gas outlet for discharging gas from the plasma processing space. The plasma processing chamber 10 is grounded.

[0053] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 when viewed from above. The substrate W is disposed on the central region 111a of the main body portion 111, and the ring assembly 112 is disposed on the annular region 111b of the main body portion 111 in such a way that it surrounds the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also referred to as a substrate support surface for supporting the substrate W, and the annular region 111b is also referred to as an annular support surface for supporting the ring assembly 112.

[0054] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive component. The conductive component of the base 1110 can function as a bias electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic component 1111a and an electrostatic electrode 1111b disposed within the ceramic component 1111a. The ceramic component 1111a has a central region 111a. In one embodiment, the ceramic component 1111a also has an annular region 111b. Alternatively, other components surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating component, may have an annular region 111b. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating component, or on both the electrostatic chuck 1111 and the annular insulating component. Additionally, at least one RF / DC electrode coupled to the RF (Radio Frequency) power supply 31 and / or DC (Direct Current) power supply 32, described later, can be disposed within the ceramic component 1111a. In this case, the at least one RF / DC electrode can function as a bias electrode. Alternatively, the conductive components of the base 1110 and the at least one RF / DC electrode can function as multiple bias electrodes. Furthermore, the electrostatic electrode 1111b can also function as a bias electrode. Therefore, the substrate support 11 includes at least one bias electrode.

[0055] The ring assembly 112 includes one or more annular components. In one embodiment, the one or more annular components include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0056] Additionally, the substrate support 11 may include a temperature control module for adjusting at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas may flow in the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are disposed within the ceramic component 1111a of the electrostatic chuck 1111. Furthermore, the substrate support 11 may include a heat transfer gas supply section capable of supplying heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0057] The gas inlet section is capable of introducing at least one type of processing gas from the gas supply section 20 into the plasma processing space 10s. In one embodiment, the gas inlet section includes a central gas injector (CGI) 13. The central gas injector 13 is disposed above the substrate support section 11 and is mounted on a central opening formed in the dielectric window 101. The central gas injector 13 has at least one gas supply port 13a, at least one gas flow path 13b, and at least one gas inlet port 13c. The processing gas supplied to the gas supply port 13a can be introduced into the plasma processing space 10s through the gas flow path 13b and the gas inlet port 13c. Alternatively, the gas inlet section may include, or replace, the central gas injector 13 by including one or more side gas injectors (SGIs) mounted on one or more openings formed on the sidewall 102.

[0058] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is capable of supplying at least one type of process gas from its respective gas source 21 to the gas inlet unit via its respective flow controller 22. Each flow controller 22 may, for example, include a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include one or more flow modulation devices for modulating or pulsedizing the flow rate of the at least one type of process gas.

[0059] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is capable of supplying at least one RF signal (RF power) to at least one bias electrode and antenna 14. This allows plasma to be formed from at least one type of processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least part of a plasma generation unit capable of generating plasma from one or more processing gases within the plasma processing chamber 10. Furthermore, by supplying a bias RF signal to at least one bias electrode, a bias potential can be generated on the substrate W, attracting ions from the formed plasma to the substrate W.

[0060] In one embodiment, the RF power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is coupled to the antenna 14 and is capable of generating a source RF signal (source RF power) for plasma generation via at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency in the range of 10MHz to 150MHz. In one embodiment, the first RF generation unit 31a may be capable of generating multiple source RF signals with different frequencies. The generated one or more source RF signals are supplied to the antenna 14. The first RF generation unit 31a corresponds to the first high-frequency power supply of the present invention. Furthermore, the source RF signal corresponds to the first high-frequency power of the present invention.

[0061] The second RF generation unit 31b is coupled to at least one bias electrode via at least one impedance matching circuit and is capable of generating a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than that of the source RF signal. In one embodiment, the bias RF signal preferably has a frequency in the range of 1MHz to 100MHz, more preferably in the range of 13MHz to 60MHz. In one embodiment, the second RF generation unit 31b may be capable of generating multiple bias RF signals with different frequencies. The generated one or more bias RF signals are supplied to at least one bias electrode. In addition, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed. The second RF generation unit 31b corresponds to the second high-frequency power supply of the present invention. Furthermore, the bias RF signal corresponds to the second high-frequency power of the present invention.

[0062] Additionally, the power supply 30 may include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a bias DC generator 32a. In one embodiment, the bias DC generator 32a is connected to at least one bias electrode and is capable of generating a bias DC signal. The generated bias DC signal is applied to at least one bias electrode.

[0063] In various implementations, the bias DC signal can be pulsed. In this case, a sequence of voltage pulses is applied to at least one bias electrode. The voltage pulses can have pulse waveforms of rectangular, trapezoidal, triangular, or combinations thereof.

[0064] The bias DC generation unit 32a can supply a bias DC signal obtained by pulsed DC voltage. For example, the bias DC generation unit 32a can supply a bias DC signal obtained by periodically switching a negative DC voltage on and off to pulse it. In one embodiment, the bias DC generation unit 32a can apply a negative DC voltage. The bias DC generation unit 32a applies a voltage pulse of a predetermined frequency as a bias DC signal to the bias electrode of the base 1110 by switching the applied DC voltage on and off at a predetermined period. The frequency of the bias DC signal is preferably in the range of 100kHz to 1200kHz, more preferably in the range of 400kHz to 800kHz. The bias DC generation unit 32a can change the duty cycle of the bias DC signal by changing the proportion of the on and off periods in one cycle. The bias DC generation unit 32a corresponds to the voltage pulse source of the present invention. Furthermore, the bias DC signal corresponds to the voltage pulse of the present invention.

[0065] Antenna 14 includes one or more coils. In one embodiment, antenna 14 may include an outer coil and an inner coil arranged coaxially. In this case, RF power supply 31 may be connected to both the outer coil and the inner coil, or it may be connected to either the outer coil or the inner coil. In the former case, the same RF generating unit may be connected to both the outer coil and the inner coil, or different RF generating units may be connected to the outer coil and the inner coil respectively.

[0066] When performing plasma processing, the plasma processing apparatus 1 can supply a source RF signal for plasma generation to the antenna 14 from the first RF generation unit 31a. Furthermore, when performing plasma processing, the plasma processing apparatus 1 can supply a pulsed bias DC signal to the lower electrode of the base 1110 from the bias DC generation unit 32a. Additionally, when performing plasma processing, the plasma processing apparatus 1 can supply a bias RF signal from the second RF generation unit 31b, superimposed on the bias DC signal.

[0067] The exhaust system 40 can be connected, for example, to a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space 10s can be regulated using the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0068] The control unit 2 is capable of processing computer-executable commands to cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 is capable of controlling the various elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, the control unit 2 may be part or entirely included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented, for example, by a computer 2a. The processing unit 2a1 is capable of reading programs from the storage unit 2a2 and performing various control actions by executing the read programs. The programs may be pre-stored in the storage unit 2a2 or retrieved via a medium when needed. The retrieved programs are stored in the storage unit 2a2 and read and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 can communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).

[0069] [Plasma processing flow]

[0070] Next, the process of performing plasma processing, such as plasma etching, on the substrate W using the plasma processing system of the embodiment will be briefly described. The substrate W is fed into the plasma processing chamber 10 by a conveying mechanism such as a conveying arm via a feed inlet / outlet (not shown), and is placed on the central region 111a of the substrate support 11. The exhaust system 40 exhausts the plasma processing chamber 10 to a predetermined vacuum level.

[0071] When etching the substrate W, the control unit 2 can control the gas supply unit 20 to supply processing gas into the plasma processing chamber 10. For example, the storage unit 2a2 stores a plasma processing recipe for the substrate. The recipe records the type and flow rate of the gas used in the etching. For example, the control unit 2 reads the recipe from the storage unit 2a2 and supplies the gas of the type registered in the recipe into the plasma processing chamber 10 from the gas supply unit 20 at the registered flow rate.

[0072] The control unit 2 can control the first RF generation unit 31a to supply a source RF signal from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10. For example, the electrical power of the active RF signal is registered in the scheme. The control unit 2 supplies the source RF signal from the first RF generation unit 31a to the antenna 14 with the electrical power registered in the scheme to generate a magnetic force in the plasma processing chamber 10, thereby plasmaizing the processing gas in the plasma processing chamber 10 and generating inductively coupled plasma.

[0073] The control unit 2 can control the bias DC generation unit 32a to supply a bias DC signal to the substrate support unit 11. The control unit 2 can also control the bias DC generation unit 32a and the duty cycle of the bias DC signal. For example, the control unit 2 preferably controls the duty cycle of the bias DC signal to 10% to 80%, and more preferably to 10% to 20%. For example, the duty cycle of the bias DC signal is registered in the scheme. The control unit 2 reads the scheme from the storage unit 2a2 and supplies a bias DC signal with the duty cycle registered in the scheme from the bias DC generation unit 32a.

[0074] The control unit 2 can control the second RF generation unit 31b to supply a bias RF signal to the substrate support unit 11, superimposed on the bias DC signal. For example, the electrical power of the bias RF signal is registered in the scheme. For example, the control unit 2 reads the scheme from the storage unit 2a2 and supplies the bias RF signal from the second RF generation unit 31b with the electrical power registered in the scheme.

[0075] Here, an example of etching the substrate W in the first embodiment will be described. Figure 2A , Figure 2B , Figure 3A and Figure 3B This is a diagram illustrating an example of etching the substrate W according to the first embodiment. Figure 2A This indicates the planar shape of the substrate W as viewed from above before etching. Figure 2B This indicates the substrate W before etching. Figure 2A The cross-sectional shape at the dashed line L1. Figure 3AThis indicates the planar shape of the etched substrate W when viewed from above. Figure 3B This indicates the etched substrate W in Figure 3A The cross-sectional shape at the dashed line L1.

[0076] A substrate layer 50 is formed in the substrate W before etching, and a fin structure 51 having multiple fins 51a is formed on the substrate layer 50. Furthermore, a gate material 52 is deposited on the fin structure 51 in the substrate W before etching, and a mask 53 is formed on the gate material 52. In addition, the fin structure 51 is buried in the gate material 52, therefore, in Figure 2A and Figure 2B Not illustrated. The substrate 50 is a stop layer used to suppress etching of the underlying layer, and is formed, for example, of an oxide (Ox) such as a silicon oxide film. The substrate 50 can also be a metal film such as SiN, an organic film, or a tungsten film. The fin structure 51 is formed, for example, by covering the surface of the silicon layer with an oxide layer. A plurality of fins 51a of the fin structure 51 are formed side by side in one direction. The gate material 52 is formed, for example, of polysilicon. The mask 53 is formed, for example, by stacking an oxide layer 53b (Ox) on the SiN layer 53a. The mask 53 is formed such that gaps are provided side by side in a direction that intersects with one direction.

[0077] Figure 3A and Figure 3B This illustrates the etching of the gate material 52 onto the substrate W after reaching the base layer 50, using mask 53 as a mask. An example of the pressure conditions and process gas used for etching the substrate W is shown below. Furthermore, in the values ​​below, 1 sccm is approximately 1.69 × 10⁻⁶. -3 pa·m 3 / s, 1mTorr is approximately 0.133Pa.

[0078] • Pressure conditions

[0079] Pressure within plasma processing chamber 10: 50–100 mTorr

[0080] • Gas processing

[0081] Cl2 gas: 100~210sccm

[0082] HBr gas: 70–150 sccm

[0083] O2 gas: 30-60 sccm

[0084] Ar gas: 50–300 sccm

[0085] The result of etching is as follows Figure 3A and Figure 3BAs shown, in the gate material 52, the gate portion 52a directly below the mask 53 is retained, and the retained gate portion 52a can function as a gate. In the substrate W, each rectangular portion 55 surrounded by the mask 53 and the fin 51a has reached the substrate layer 50.

[0086] Next, an etching method as a reference example will be described. Furthermore, the differences from the etching method of the first embodiment will be explained below.

[0087] First, the etching method of the first reference example will be described. Etching methods that apply high-frequency electrical power as a bias to the substrate support 11 to etch the substrate W have been known for some time. For example, in the etching method of the first reference example, when etching the substrate W, a source RF signal is supplied from the first RF generation unit 31a to plasmaize the process gas in the plasma processing chamber 10. Furthermore, in the etching method of the first reference example, a bias DC signal is not supplied from the bias DC generation unit 32a, but a bias RF signal is supplied to the lower electrode of the base 1110 from the second RF generation unit 31b.

[0088] Figure 4A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the first reference example. By supplying a bias RF signal as high-frequency electrical power to the lower electrode of the substrate 1110, the potential of the substrate W changes in a sinusoidal manner in response to the variation of the bias RF signal.

[0089] Figure 4B This is a schematic diagram illustrating the movement of ions and free radicals in the plasma during the etching method of the first reference example. Figure 4B In this method, the object side to be etched, such as the substrate W, is referred to as the etch front. Ions and free radicals in the plasma are attracted to the substrate W by its potential, thus etching the substrate W. In the etching method of the first reference example, since the potential of the substrate W changes in a sinusoidal pattern, ions and free radicals are scattered, and the incident angle of ions and free radicals incident on the substrate W becomes wider. Furthermore, in the etching method of the first reference example, the energy distribution of ions and free radicals incident on the substrate W becomes wider.

[0090] Figure 4C This is a diagram illustrating an example of the energy distribution of ions in the etching method of the first reference example. Figure 4C This is an example of the result of obtaining the ion energy distribution function (IEDF) for the etching method of the first reference example. The horizontal axis represents the ion energy [eV], with higher energies further to the right. The vertical axis represents the number of ions, with more ions further up. Furthermore, in... Figure 4CIn this context, the minimum ion energy required to etch the gate material 52 is expressed as the threshold E. th Threshold E th For example, it is 25 [eV].

[0091] In the etching method of the first reference example, although the energy distribution of the ions is at the threshold E th Therefore, it is possible to etch the gate material 52, but a peak is generated on the low-energy side of the energy distribution, and the energy range of the generated peak is wide. In the etching method of the first reference example, the energy distribution of ions incident on the substrate W is extended.

[0092] Therefore, the etching method of the first reference example has low vertical processing performance. For example, when implementing the etching method of the first reference example... Figure 2A , Figure 2B , Figure 3A and Figure 3B When the substrate W shown is etched, the sidewall of the gate portion 52a is also etched, and the roughness of the sidewall of the gate portion 52a deteriorates.

[0093] Next, the etching method of the second reference example will be described. High vertical processing performance is required in the manufacture of semiconductor devices. For this purpose, an etching method is known that applies a pulsed rectangular DC voltage to the substrate support 11 to etch the substrate. For example, in the etching method of the second reference example, when etching the substrate W, a source RF signal is supplied from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10. Furthermore, in the etching method of the second reference example, instead of supplying a bias RF signal from the second RF generation unit 31b, a bias DC signal obtained by pulsed negative DC voltage is supplied from the bias DC generation unit 32a to the lower electrode of the substrate 1110.

[0094] Figure 5A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the second reference example. By supplying a bias DC signal obtained by pulsed negative DC voltage to the lower electrode of the substrate 1110, the potential of the substrate W changes in a rectangular shape accordingly with the variation of the bias DC signal.

[0095] Figure 5B This is a schematic diagram illustrating the movement of ions and free radicals in the plasma during the etching method of the second reference example. Figure 5BIn this example, the object side of the substrate W to be etched is referred to as the etch front. Ions and free radicals in the plasma are attracted to the substrate W by its potential, thus etching the substrate W. In the etching method of the second reference example, since the potential of the substrate W changes in a rectangular shape, the perpendicularity of the ions and free radicals incident on the substrate W can be improved. Furthermore, in the etching method of the second reference example, the energy distribution of the ions and free radicals incident on the substrate W becomes narrower, and the energy peak becomes higher.

[0096] Figure 5C This is a diagram illustrating an example of the energy distribution of ions in the etching method of the second reference example. Figure 5C This is a schematic diagram illustrating the ion energy distribution function (IEDF) of the etching method in the second reference example. The horizontal axis represents the ion energy [eV], with higher energies further to the right. The vertical axis represents the number of ions, with more ions further up. Furthermore, in... Figure 5C The figure shows the threshold energy E required for etching the gate material 52. th .

[0097] In the etching method of the second reference example, peaks are generated on both the high-energy and low-energy sides. On the low-energy side, the ion energy is the threshold E. th Therefore, it does not contribute to the etching of the gate material 52. On the high-energy side, the peak is higher, and the energy range for peak generation is narrower. That is, in the etching method of the second reference example, the peak on the high-energy side exhibits an acute-angled energy distribution. Consequently, the perpendicularity of ions and radicals incident on the substrate W is improved.

[0098] In the etching method of the second reference example, the perpendicularity of ions and free radicals is high, thus achieving high vertical processing performance. For example, in the etching method of the second reference example... Figure 2A , Figure 2B , Figure 3A and Figure 3B During the etching of the substrate W shown, the gate portion 52a can be etched into a vertical shape while suppressing the roughness of the sidewall of the gate portion 52a.

[0099] However, in the etching method of the second reference example, due to the improved vertical processing performance of ions, there is a situation where gate material 52 residue remains in the corner of the bottom after etching. Figure 6 This is a diagram illustrating an example of residue remaining on the etched substrate W according to the first embodiment. Figure 6 This indicates the planar shape of the etched substrate W as viewed from above. Residue 56 remains in each rectangular portion 55 of the etched substrate W.

[0100] Therefore, in the etching method of the first embodiment, when etching the substrate W, a bias DC signal obtained by pulsed negative DC voltage is supplied from the bias DC generation unit 32a to the lower electrode of the substrate 1110. Furthermore, in the etching method of the first embodiment, a bias RF signal is supplied from the second RF generation unit 31b in superimposed on the bias DC signal.

[0101] Figure 7A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the first embodiment. By supplying a bias DC signal and a bias RF signal obtained by pulsed negative DC voltage to the lower electrode of the substrate 1110, the potential of the substrate W changes in a rectangular shape in accordance with the variation of the bias DC signal and vibrates in accordance with the bias RF signal.

[0102] Figure 7B This is a diagram illustrating an example of the energy distribution of ions in the etching method of the first embodiment. Figure 7B This is a schematic diagram illustrating the ion energy distribution function (IEDF) of the etching method of the first embodiment. The horizontal axis represents the ion energy [eV], with higher energy levels towards the right. The vertical axis represents the number of ions, with higher ion numbers towards the top. Furthermore, in... Figure 7B The figure shows the threshold energy E required for etching the gate material 52. th .

[0103] In the etching method of the first embodiment, peaks are generated on both the high-energy side and the low-energy side, and the energy range for peak generation is wide. Because the etching method of the first embodiment generates peaks on the high-energy side, high vertical processing performance can be obtained. Furthermore, in the etching method of the first embodiment, the low-energy side is also at the threshold energy E. th The above, and the generation of peaks over a wide range, thus enabling the expansion of the incident angle of ions incident on the substrate W, and enabling the efficient removal of residue 56.

[0104] Next, an example will be given to verify the results of the actual etching of substrate W to verify the amount of residue 56.

[0105] In the verification, the substrate W was etched using the etching method of the first embodiment and the etching method of the first reference example. The etching method of the first embodiment consists of two steps: a residue removal step 1 and a residue removal step 2. The residue removal step 2 is performed after the residue removal step 1. The common conditions for the source RF signal, bias RF signal, and bias DC signal in the residue removal steps 1 and 2 during verification are as follows.

[0106] (Common conditions of the etching method in the first embodiment)

[0107] Conditions for residue removal step 1

[0108] Source RF signal: frequency 27MHz, power 300W

[0109] Bias RF signal: frequency 13MHz, power 400W

[0110] Bias DC signal: Frequency 400kHz, -500V, duty cycle 0~80%

[0111] Conditions for residue removal step 2

[0112] Source RF signal: frequency 27MHz, power 500W

[0113] Bias RF signal: frequency 13MHz, power 270W

[0114] Bias DC signal: Frequency 400kHz, -500V, duty cycle 0~80%

[0115] The duty cycle of the bias DC signal is the proportion of the on-time period in one cycle of turning -500V on and off. In the etching method of the first embodiment, the residue removal step 2 is performed after the residue removal step 1, and the duty cycle of the bias DC signal is changed in both the residue removal step 1 and the residue removal step 2.

[0116] First, the first verification results will be explained. In the first verification, the substrate W was etched using the etching method of the first reference example and the etching method of the first embodiment, respectively, and the amount of residue 56 on the substrate W was compared.

[0117] In the first verification, the source RF signal and the bias RF signal of the etching method of the first reference example are set as follows.

[0118] (Conditions of the etching method in the first reference example)

[0119] Source RF signal: frequency 27MHz, power 500W

[0120] Bias RF signal: frequency 13MHz, power 270W

[0121] Furthermore, in the first verification, the duty cycle of the bias DC signal for the residue removal step 1 and residue removal step 2 of the etching method of the first embodiment is set as follows.

[0122] (Conditions of the etching method in the first embodiment)

[0123] Conditions for residue removal step 1

[0124] Bias DC signal: Not applied (duty cycle 0%)

[0125] Conditions for residue removal step 2

[0126] Bias DC signal: Frequency 400kHz, -500V, Duty Cycle 80%

[0127] Figure 8A This diagram illustrates the processing conditions of the etching method for the first reference example during the first verification. Figure 8A In order to make it easier to communicate with Figure 8B The processing conditions of the etching method of the first embodiment shown are compared, and the conditions of the source RF signal, bias RF signal, and bias DC signal of the etching method of the first reference example are represented as residue removal step 1 and residue removal step 2. Figure 8A In the first reference example, corresponding to one cycle of the bias DC signal at a frequency of 400 kHz, the period during which the source RF signal and the bias RF signal are supplied is represented by a diagonal line pattern during one cycle of 400 kHz in the etching process. In the etching method of the first reference example, the source RF signal and the bias RF signal are continuously supplied during etching. Therefore, the source RF signal and the bias RF signal are represented by a diagonal line pattern during one cycle of 400 kHz, indicating that they are always on. The source RF signal and the bias RF signal are supplied as a continuous wave (CW). On the other hand, in the etching method of the first reference example, the bias DC signal is not applied in the residue removal step 1 and the residue removal step 2, so the diagonal line pattern is not represented during one cycle of 400 kHz, indicating that they are always off.

[0128] Figure 8B This diagram illustrates the processing conditions of the etching method of the first embodiment during the first verification. Figure 8A The process is divided into two steps: residue removal step 1 and residue removal step 2. The conditions for the source RF signal, bias RF signal, and bias DC signal of the etching method of the first embodiment during the first verification are shown. Figure 8B In the residue removal step 1, the conditions for the source RF signal, bias RF signal, and bias DC signal are the same as in the first reference example. In residue removal step 1, the bias DC signal is not applied, but the source RF signal and bias RF signal are supplied. In residue removal step 2, during etching, the source RF signal, bias RF signal, and bias DC signal are supplied. In residue removal step 2, the bias DC signal is supplied at 400 kHz with a duty cycle of 80%. Figure 8B In the process of removing residue in step 2, the bias RF signal is represented by a diagonal pattern during one cycle of 400kHz, indicating that 80% of the period is on.

[0129] In the first verification, the amount of residue 56 on the substrate W was 1.61 nm when using the etching method of the first reference example, and 1.45 nm when using the etching method of the first embodiment. Therefore, it can be seen that the etching method of the first embodiment can reduce the amount of residue 56 compared to the etching method of the first reference example.

[0130] Next, the second verification results will be explained. In the second verification, in the etching method of the first embodiment, the residue removal step 1 was performed under the same conditions as the first reference example, and the duty cycle of the bias DC signal in the residue removal step 2 was set to 80% and 10% respectively to perform etching of the substrate W, and the amount of residue 56 on the substrate W was compared.

[0131] Figure 9A and Figure 9B This diagram illustrates the processing conditions of the etching method of the first embodiment during the second verification. Figure 9A and Figure 9B The process is divided into two steps: residue removal step 1 and residue removal step 2. This illustrates the periods for supplying the source RF signal, bias RF signal, and bias DC signal during each 400kHz cycle of the etching process. In the second verification, in residue removal step 2, the duty cycle of the bias DC signal during etching is set to 80% (…). Figure 9A ) and 10% Figure 9B The conditions for residue removal step 1 are the same as in the first reference example.

[0132] In the second verification, the duty cycle was 80% ( Figure 9A The amount of residue 56 on substrate W under the condition of ) is 2.21 [nm], and the duty cycle is 10% ( Figure 9B In the case of ), the amount of residue 56 on substrate W is 1.67 [nm]. Therefore, it can be seen that in the etching method of the first embodiment, reducing the duty cycle of the bias DC signal can reduce the amount of residue 56. Furthermore, the reason why the amount of residue 56 differs between the first and second verifications for a duty cycle of 80% is because the structure of substrate W is slightly different in the first and second verifications.

[0133] Next, the third verification result will be explained. In the third verification, in the etching method of the first embodiment, the substrate W was etched when the duty cycle of the bias DC signal in the residue removal step 2 was set to 10%, when no bias DC signal was applied in the residue removal step 1, and when the duty cycle was set to 20%, and the amount of residue 56 was compared.

[0134] Figure 10A and Figure 10B This diagram illustrates the processing conditions of the etching method of the first embodiment during the third verification. Figure 10A and Figure 10B The process is divided into two steps: residue removal step 1 and residue removal step 2. The steps illustrate the periods for supplying the source RF signal, bias RF signal, and bias DC signal during each 400kHz cycle of the etching process. In the third verification, during residue removal step 1, the bias DC signal during etching is set to be unapplied. Figure 10A ) and 20% Figure 10B In step 2 of residue removal, the duty cycle is set to 10%.

[0135] In the third verification, during the residue removal step 1, without applying the bias DC signal during etching ( Figure 10A The amount of residue 56 on substrate W is 1.67 [nm], and the duty cycle is set to 20% ( Figure 10B In the case of ), the amount of residue 56 on substrate W is 1.1 [nm]. It can be seen that in the etching method of the first embodiment, applying a bias DC signal in the residue removal step 1 can reduce the amount of residue 56.

[0136] In the above verification, the etching method of the first embodiment is divided into two steps: a residue removal step 1 and a residue removal step 2. The residue removal step 2 is performed after the residue removal step 1 to etch the substrate W. However, the etching method of the first embodiment is not limited to this. The etching method of the first embodiment may also be divided into three or more steps. Furthermore, the etching method of the first embodiment may not be divided into steps, but the duty cycle of the bias DC signal may be maintained at a constant level during etching to etch the substrate W. The substrate W may be etched solely by the steps of the etching method of the first embodiment, or the etching method of the first embodiment may be combined with other etching methods for etching.

[0137] [flow chart]

[0138] The etching process incorporating the etching method of the present invention will be described. Figure 11 This is a flowchart illustrating an example of the processing sequence of the etching process in the first embodiment. Figure 11 The etching process is performed when the etching of the substrate W begins.

[0139] Control unit 2 controls gas supply unit 20 to start supplying processing gas from gas supply unit 20, supplying processing gas into plasma processing chamber 10 (step S10). Control unit 2 controls first RF generation unit 31a to start supplying source RF signal from first RF generation unit 31a, causing plasmaification of processing gas in plasma processing chamber 10 (step S11). Control unit 2 controls bias DC generation unit 32a to start supplying bias DC signal from bias DC generation unit 32a, supplying bias DC signal to substrate support unit 11 (step S12). Control unit 2 controls second RF generation unit 31b to start supplying bias RF signal from second RF generation unit 31b, supplying bias RF signal to substrate support unit 11 superimposed with bias DC signal (step S13). Furthermore, the order of steps S11 to S13 can be interchanged. Additionally, steps S11 to S13 can be performed as a single step, either partially or entirely.

[0140] Control unit 2 determines whether etching has ended (step S14). For example, if the predetermined conditions for ending etching are met, control unit 2 determines that etching has ended. If etching has not ended (step S14: No), the process returns to step S14. If etching has ended (step S14: Yes), control unit 2 controls the supply of processing gas, the supply of source RF signal, the supply of bias DC signal, and the supply of bias RF signal to stop respectively, and ends the process.

[0141] Therefore, the etching process of the first embodiment can achieve high vertical processing performance. Furthermore, the etching method of the first embodiment can reduce residue 56.

[0142] also, Figure 11 The etching process shown is an example and is not limited to it. The etching process may include other steps. Furthermore, the etching process may be implemented as part of other processes. For example, in the case where etching proceeds by sequentially performing multiple processes to etch the substrate W down to the stop layer, Figure 11 The etching process shown can be performed as an etching process that reaches the stop layer of the substrate W. For example, in implementing... Figure 2A , Figure 2B , Figure 3A and Figure 3B In the case of etching the substrate W shown, the control unit 2 can control the etching process when the bottom of the rectangular portion 55 of the substrate layer 50 is to be etched, so that the etching can proceed. Figure 11 The etching process shown.

[0143] (Second Implementation)

[0144] Next, the second embodiment will be described. The structure of the plasma processing system in the second embodiment is similar to... Figure 1The plasma processing system shown in the first embodiment has the same structure, so the description is omitted.

[0145] The bias DC generation unit 32a can supply a bias DC signal obtained by periodically turning on and off a negative DC voltage to pulse it.

[0146] The second RF generation unit 31b does not supply a bias RF signal when the bias DC signal is on, and supplies a bias RF signal when the bias DC signal is off.

[0147] In the etching method of the second embodiment, the bias RF signal is not superimposed during the on-time period when the DC voltage of the bias DC signal is on, and the bias RF signal is superimposed during the off-time period when the DC voltage of the bias DC signal is off.

[0148] Figure 12A This is a diagram illustrating an example of the potential change of the substrate W in the etching method of the second embodiment. By supplying a bias RF signal to the lower electrode of the substrate 1110 in superimposed with the bias DC signal during the off-period of the bias DC signal, the potential of the substrate W changes in a rectangular shape in accordance with the variation of the bias DC signal, and vibrates in accordance with the bias RF signal during the off-period.

[0149] Figure 12B This is a diagram illustrating an example of the energy distribution of ions in the etching method of the second embodiment. Figure 12B This is a schematic diagram illustrating the ion energy distribution function (IEDF) of the etching method according to the second embodiment. The horizontal axis represents the ion energy [eV], with higher energy levels towards the right. The vertical axis represents the number of ions, with higher ion numbers towards the top. Furthermore, in... Figure 12B The figure shows the threshold energy E required for etching the gate material 52. th .

[0150] In the etching method of the second embodiment, peaks are generated on the high-energy side and the low-energy side.

[0151] In the etching method of the second embodiment, the bias RF signal is not superimposed during the on-time of the bias DC signal. Therefore, the peak on the high-energy side is higher, and the energy range of the generated peak is narrower. In the etching method of the second embodiment, the peak on the high-energy side exhibits an acute-angled energy distribution. As a result, the verticality of ions and free radicals is increased in the etching method of the second embodiment, thus achieving high vertical processing performance.

[0152] Furthermore, in the etching method of the second embodiment, a bias RF signal is superimposed during the off period of the bias DC signal; therefore, the low-energy side is also the threshold E. thThe above applies, and peaks are generated over a wide range. Therefore, the etching method of the second embodiment can broaden the incident angle of ions incident on the substrate W, and can efficiently remove residue 56, thus reducing residue 56.

[0153] Furthermore, in the etching methods of the first and second embodiments described above, by changing the amplitude of the bias DC signal and the on-time of the bias DC signal, the height of the peak on the high-energy side and the energy of the peak generation can be changed independently without changing the height of the peak on the low-energy side and the energy of the peak generation.

[0154] Figure 13A This is a diagram illustrating the potential change of substrate W when the amplitude of the bias DC signal is changed. Figure 13A This illustrates the case where, in the etching method of the second embodiment, the amplitude of the bias DC signal is changed by altering the negative voltage during the on-time of the bias DC signal. Figure 13A In the middle, the further to the right, the greater the negative voltage during the switching-on period of the bias DC signal becomes. Therefore, the further to the right, the greater the change in the potential of the substrate W during the switching-on period. Figure 13B This is a graph illustrating the change in the energy distribution of ions when the amplitude of the bias DC signal is changed. Figure 13B This illustrates how, in the etching method of the second embodiment, the amplitude of the bias DC signal is changed by altering the negative voltage during the on-time of the bias DC signal. Depending on the potential of the substrate W, the energy of the ions attracted to the substrate W varies. Therefore, by changing the amplitude of the bias DC signal, the energy range of the peaks generated on the high-energy side can be altered.

[0155] Figure 14A This is a diagram illustrating the potential change of substrate W when the on-time of the bias DC signal is changed. Figure 14A This illustrates the case where the on-time of the bias DC signal is changed in the etching method of the second embodiment. Figure 14A In the middle, the further to the right, the longer the bias DC signal is on; the further to the right, the longer the period T1 during which the potential of the substrate W is negative. Figure 14B This is a graph illustrating the change in ion energy distribution when the on-time of the bias DC signal is altered. Figure 14B This illustrates the case where the on-time of the bias DC signal is varied in the etching method of the second embodiment. The longer the period during which the potential of the substrate W is negative, the more ions are attracted to the substrate W. Therefore, by changing the on-time of the bias DC signal, the height of the peak on the high-energy side can be altered.

[0156] Furthermore, in the etching methods of the first and second embodiments described above, by changing the amplitude of the bias RF signal and the off period of the bias DC signal, the height of the low-energy side peak and the range of the peak energy can be changed independently without changing the height of the high-energy side peak and the energy of the peak generation.

[0157] Figure 15A This is a diagram illustrating the potential change of substrate W when the amplitude of the bias RF signal is changed. Figure 15A This illustrates the case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. Figure 15A In the middle, the further to the right, the larger the amplitude of the bias RF signal becomes. Therefore, the further to the right, the greater the amplitude of the potential fluctuation of the substrate W during the turn-off period. Figure 15B This is a graph illustrating the change in the energy distribution of ions when the amplitude of the bias RF signal is changed. Figure 15B This illustrates the case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. The energy of the ions attracted to the substrate W changes depending on the potential of the substrate W. Therefore, by changing the amplitude of the bias RF signal, the energy range in which the low-energy peak is generated can be altered.

[0158] Figure 16A This is a diagram illustrating the potential change of substrate W when the off-time of the bias DC signal is changed. Figure 16A This illustrates the case where the off-time of the bias DC signal is changed in the etching method of the second embodiment. Figure 16A In the middle, the further to the right, the longer the off period of the bias DC signal; the further to the right, the longer the period T2 when the potential of the substrate W is near 0. Figure 16B This is a graph illustrating the change in ion energy distribution when the off-time of the bias DC signal is altered. Figure 16B This illustrates the case where the off-time of the bias DC signal is varied in the etching method of the second embodiment. The longer the period T2 when the potential of the substrate W is near 0, the more ions are attracted to the substrate W during the period T2. Therefore, by changing the off-time of the bias DC signal, the height of the peak on the low-energy side can be altered.

[0159] The on and off periods of the bias DC signal can be changed by altering its period and duty cycle. Therefore, in the etching methods of the first and second embodiments, the energy distribution of ions incident on the substrate W can be adjusted by changing the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, in the etching methods of the first and second embodiments, by changing the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal, the peak heights on the low-energy side and the energy range of the generated peaks can be adjusted, respectively.

[0160] The control unit 2 can control the period, duty cycle, and amplitude of the bias DC signal, as well as the amplitude of the bias RF signal, during the etching of the substrate W. For example, in Figure 2A , Figure 2B , Figure 3A and Figure 3B In the etching of the substrate W shown, a hole surrounded by a mask 53 and a fin 51a is formed in the gate material 52. When the hole is formed in the gate material 52 by etching, the control unit 2 controls the period, duty cycle, and amplitude of the bias DC signal, as well as the amplitude of the bias RF signal. For example, the control unit 2 controls the period, duty cycle, and amplitude of the bias DC signal, as well as the amplitude of the bias RF signal, such that before the bottom of the hole reaches the substrate layer 50, the peak on the high-energy side is higher and the peak on the low-energy side is lower. Furthermore, the control unit 2 controls the period, duty cycle, and amplitude of the bias DC signal, as well as the amplitude of the bias RF signal, such that when the bottom of the hole reaches the substrate layer 50, the peak on the low-energy side is higher, and the energy range that produces the low-energy side peak is wider. Therefore, the plasma processing apparatus 1 can obtain high vertical processing performance. In addition, the plasma processing apparatus 1 can reduce residue 56.

[0161] Furthermore, the etching methods of the first and second embodiments described above were illustrated using the case where a bias RF signal is superimposed during the entire off-period of the bias DC signal. However, they are not limited to this. The etching methods of the first and second embodiments described above may also superimpose a bias RF signal during a portion of the off-period of the bias DC signal. Figure 17 This is a graph illustrating the potential change of the substrate W when the superposition period of the superposition bias RF signal is changed. Figure 17 In the etching method of the second embodiment, the height of the low-energy side peak can be changed by the length of the superposition period T4 of the bias RF signal during the off-time T3 of the bias DC signal.

[0162] Furthermore, the etching methods of the first and second embodiments described above have been illustrated using the case where a bias RF signal is superimposed during the entire off period of the bias DC signal. However, they are not limited to this. In the case where the rectangularity of the bias DC signal is poor, the etching methods of the first and second embodiments described above can omit the superimposed bias RF signal during the transition period when the potential of the substrate W changes in accordance with the on / off state of the bias DC signal, and instead superimpose the bias RF signal after the transition period has passed. Figure 18 This diagram illustrates the potential change of substrate W as the superposition period T4 of the superimposed bias RF signal is changed. Within the potential of substrate W, period T5 is generated as the transition period from when the bias DC signal is turned off until it reaches near 0. Figure 18In this method, after the bias DC signal is turned off, the bias RF signal is also turned off during period T5 without superimposing the bias RF signal on the bias DC signal. After period T5, the bias RF signal is superimposed on the bias DC signal. In the etching methods of the first and second embodiments, when the rectangularity of the bias DC signal is poor, by not superimposing the bias RF signal during the transition period but superimposing the bias RF signal after the transition period, peaks can be generated on both the low-energy side and the high-energy side.

[0163] Furthermore, the etching methods of the first and second embodiments described above are used to etch... Figure 2A , Figure 2B The example shown is of substrate W. However, it is not limited to this. Substrate W only needs to have a target film for etching formed on the substrate layer. The target film for etching can be, for example, an oxide film such as a silicon oxide film, a SiN film, an organic film, a metal film such as a tungsten film. The substrate layer only needs to be a material from which an etch selectivity ratio can be achieved with the aforementioned target film for etching. As long as the process involves etching holes in the target film of substrate W that reach the substrate layer, the etching methods of the first and second embodiments can be applied.

[0164] (Effect)

[0165] As described above, the plasma processing system (plasma processing apparatus) of the above embodiment includes a plasma processing chamber 10, a substrate support 11, a gas supply unit 20, a first RF generation unit 31a (first high-frequency power supply), a bias DC generation unit 32a (voltage pulse source), a second RF generation unit 31b (second high-frequency power supply), and a control unit 2. The substrate support 11 is disposed within the plasma processing chamber 10 and is capable of supporting the substrate W. The gas supply unit 20 is capable of supplying processing gas into the plasma processing chamber 10. The first RF generation unit 31a is capable of supplying a source RF signal (first high-frequency electrical power) for plasmaifying the processing gas within the plasma processing chamber 10. The bias DC generation unit 32a is capable of supplying a bias DC signal (voltage pulse) obtained by pulsed DC voltage to the substrate support 11. The second RF generation unit 31b is capable of supplying a bias RF signal (second high-frequency electrical power) to the substrate support 11. The control unit 2 can control the process such that, during etching of the substrate W, a processing gas is supplied from the gas supply unit 20 into the plasma processing chamber 10, a source RF signal is supplied from the first RF generation unit 31a to plasmaize the processing gas in the plasma processing chamber 10, a bias DC signal is supplied to the substrate support unit 11 from the bias DC generation unit 32a, and a bias RF signal is supplied to the substrate support unit 11 from the second RF generation unit 31b in superimposed with the bias DC signal. Therefore, the plasma processing system of this embodiment can reduce residue.

[0166] Furthermore, the bias DC generation unit 32a can change the duty cycle of the bias DC signal by periodically turning the negative DC voltage on and off and changing the proportion of the on and off periods in one cycle. The control unit 2 can control the duty cycle of the bias DC signal to be 10% to 80%. As a result, the plasma processing system of this embodiment can reduce residue.

[0167] Furthermore, the control unit 2 can control the duty cycle of the bias DC signal to 10% to 20%. As a result, the plasma processing system of the embodiment can reduce residue.

[0168] Furthermore, a target film, which is the object to be etched, is formed on the substrate W. The control unit 2 can control the process such that the closer the bottom of the hole formed in the target film by etching is to the substrate layer, the smaller the duty cycle of the bias DC signal. As a result, the plasma processing system of this embodiment can reduce the residue at the bottom of the hole.

[0169] Furthermore, the bias DC generation unit 32a can periodically turn on and off a negative DC voltage to supply a bias DC signal. The second RF generation unit 31b can not supply a bias RF signal during the on period and supply a bias RF signal during the off period. Therefore, the plasma processing system of this embodiment can reduce residue. Furthermore, the plasma processing system of this embodiment can achieve high vertical processing performance.

[0170] Furthermore, a target film, which is the object to be etched, is formed on the substrate W. The control unit 2 can perform the aforementioned control when the bottom of the hole formed in the target film by etching is about to reach the substrate layer. As a result, the plasma processing system of this embodiment can reduce the residue at the bottom of the hole.

[0171] Furthermore, the substrate W has, sequentially on the substrate layer 50, a fin structure 51 having a plurality of fins 51a; a gate material 52 deposited on the fin structure 51; and a mask 53 on the gate material 52. The control unit 2 can perform the aforementioned control when etching the gate material 52 deposited between the plurality of fins 51a of the substrate W until the substrate layer 50 is exposed. As a result, the plasma processing system of the embodiment can reduce the residue 56 at the bottom of the hole (rectangular portion 55) exposed in the substrate layer 50.

[0172] Furthermore, the bias DC generation unit 32a can supply a bias DC signal with a frequency of 100kHz to 1200kHz. Therefore, the plasma processing system of this embodiment can achieve high vertical processing performance.

[0173] Furthermore, the gate material is polycrystalline silicon. The substrate layer is a silicon oxide film. Therefore, the plasma processing system of this embodiment can reduce residue at the bottom of the pores exposed in the silicon oxide film formed in the polycrystalline silicon. Thus, the plasma processing system of this embodiment can reduce residue.

[0174] Furthermore, the control unit 2 can control the period, duty cycle, and amplitude of the bias DC signal, as well as the amplitude of the bias RF signal, during the etching of the substrate W. Thus, the plasma processing system of this embodiment can adjust the height of the peaks on the low-energy side and the high-energy side of the ion energy distribution, and the range of peak energies, respectively.

[0175] Furthermore, a target film, which is the object to be etched, is formed on the substrate W. The control unit 2 can control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal, so that: before the bottom of the hole formed in the target film by etching reaches the substrate layer, the energy distribution of ions incident on the substrate W has a higher peak on the high-energy side and a lower peak on the low-energy side; while when the bottom of the hole reaches the substrate layer, the low-energy side peak is higher and the energy range of the low-energy side peak becomes wider. As a result, the plasma processing system of the embodiment can reduce residue. In addition, the plasma processing system of the embodiment can obtain high vertical processing performance.

[0176] The embodiments have been described above; however, the embodiments disclosed herein should be considered illustrative rather than limiting in all respects. In fact, the above embodiments can be implemented in various ways. Furthermore, the above embodiments can be omitted, substituted, or modified in various ways without departing from the claims and their spirit.

[0177] For example, in the above embodiment, the case of performing plasma etching on a semiconductor wafer serving as substrate W was described as an example, but it is not limited to this. Substrate W can be any substrate.

[0178] Furthermore, the embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. In fact, the above-described embodiments can be implemented in various ways. Moreover, the above-described embodiments can be omitted, substituted, or modified in various ways without departing from the appended claims and their spirit.

[0179] Furthermore, the following notes are further disclosed regarding the above-described embodiments.

[0180] (Note 1)

[0181] A plasma processing apparatus, characterized in that it comprises:

[0182] chamber;

[0183] A substrate support portion, disposed within the cavity, is capable of supporting the substrate;

[0184] A gas supply unit that can supply processing gas to the chamber;

[0185] A first high-frequency power supply is capable of supplying first high-frequency electrical power for plasmaizing the processing gas in the chamber.

[0186] A voltage pulse source capable of supplying voltage pulses obtained by pulsed DC voltage to the substrate support portion;

[0187] A second high-frequency power supply, capable of supplying second high-frequency electrical power to the substrate support portion; and

[0188] The control unit is capable of controlling the following to: supplying the processing gas from the gas supply unit to the chamber during etching of the substrate, supplying a first high-frequency power from the first high-frequency power source to plasmaize the processing gas in the chamber, supplying a voltage pulse from the voltage pulse source to the substrate support, and supplying a second high-frequency power from the second high-frequency power source to the substrate support in superposition with the voltage pulse.

[0189] (Note 2)

[0190] The plasma processing apparatus according to Appendix 1 is characterized in that:

[0191] The voltage pulse source can change the duty cycle of the voltage pulse by periodically turning a negative DC voltage on and off and changing the proportion of the on and off periods in one cycle.

[0192] The control unit can control the duty cycle of the voltage pulse to be 10% to 80%.

[0193] (Note 3)

[0194] The plasma processing apparatus according to Appendix 2 is characterized in that:

[0195] The control unit can control the duty cycle of the voltage pulse to be 10% to 20%.

[0196] (Note 4)

[0197] The plasma processing apparatus according to Appendix 2 or 3 is characterized in that:

[0198] The substrate has an object film formed on its base layer, which serves as the object to be etched.

[0199] The control unit is capable of controlling the voltage pulse to be smaller as the bottom of the hole formed in the target film by etching is closer to the substrate layer.

[0200] (Note 5)

[0201] The plasma processing apparatus according to any one of Appendices 1 to 4 is characterized in that:

[0202] The voltage pulse source can periodically switch on and off a negative DC voltage to supply the voltage pulse.

[0203] The second high-frequency power supply is capable of not supplying the second high-frequency power during the on-time period, but supplying the second high-frequency power during the off-time period.

[0204] (Note 6)

[0205] The plasma processing apparatus according to any one of Appendices 1 to 5 is characterized in that:

[0206] The substrate has an object film formed on its base layer, which serves as the object to be etched.

[0207] The control unit is capable of performing the control when the bottom of the hole formed in the target film by etching is about to reach the substrate layer.

[0208] (Note 7)

[0209] The plasma processing apparatus according to any one of Appendices 1 to 6 is characterized in that:

[0210] The substrate has, in sequence on a base layer: a fin structure having multiple fins; a gate material deposited on the fin structure; and a mask on the gate material.

[0211] The control unit is capable of performing the control when the gate material deposited between the plurality of fins of the substrate is etched until the substrate layer is exposed.

[0212] (Note 8)

[0213] The plasma processing apparatus according to any one of Appendices 1 to 7 is characterized in that:

[0214] The voltage pulse source can supply voltage pulses with a frequency of 100kHz to 1200kHz.

[0215] (Note 9)

[0216] The plasma processing apparatus according to Appendix 7 is characterized in that:

[0217] The gate material is polycrystalline silicon.

[0218] (Postscript 10)

[0219] The plasma processing apparatus according to Appendix 7 or 9 is characterized in that:

[0220] The substrate layer is a silicon oxide film.

[0221] (Postscript 11)

[0222] The plasma processing apparatus according to any one of Appendices 1 to 10 is characterized in that:

[0223] The control unit is able to control the period, duty cycle, and amplitude of the voltage pulse, as well as the amplitude of the second high-frequency electrical power, during the etching of the substrate.

[0224] (Postscript 12)

[0225] The plasma processing apparatus according to any one of Appendices 1 to 11 is characterized in that:

[0226] The substrate has an object film formed on its base layer, which serves as the object to be etched.

[0227] The control unit can control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal, so that: before the bottom of the hole formed in the target film by etching reaches the substrate layer, the energy distribution of the ions incident on the substrate has a higher peak on the high energy side and a lower peak on the low energy side, while when the bottom of the hole reaches the substrate layer, the low energy side peak is higher and the energy range that produces the low energy side peak becomes wider.

[0228] (Postscript 13)

[0229] An etching method, which is an etching method of a plasma processing device, is characterized by:

[0230] The plasma processing device includes:

[0231] chamber;

[0232] A substrate support portion, disposed within the cavity, is capable of supporting the substrate;

[0233] A gas supply unit that can supply processing gas to the chamber;

[0234] A first high-frequency power supply is capable of supplying first high-frequency electrical power for plasmaizing the processing gas in the chamber.

[0235] A voltage pulse source capable of supplying voltage pulses obtained by pulsed DC voltage to the substrate support; and

[0236] The second high-frequency power supply is capable of supplying second high-frequency electrical power to the substrate support portion.

[0237] The etching method includes the following steps:

[0238] During etching of the substrate, the processing gas is supplied from the gas supply section into the chamber, and a first high-frequency power is supplied from the first high-frequency power source to plasmaize the processing gas in the chamber. A voltage pulse is supplied from the voltage pulse source to the substrate support section, and a second high-frequency power is supplied from the second high-frequency power source to the substrate support section in superposition with the voltage pulse.

[0239] Explanation of reference numerals in the attached figures

[0240] 1 Plasma processing apparatus, 2 Control unit, 2a Computer, 2a1 Processing unit, 2a2 Storage unit, 2a3 Communication interface, 10 Plasma processing chamber, 11 Substrate support unit, 13 Central gas injection unit, 14 Antenna, 20 Gas supply unit, 21 Gas source, 22 Flow controller, 30 Power supply, 31 RF power supply, 31a First RF generation unit, 31b Second RF generation unit, 32 DC power supply, 32a Biased DC generation unit, 40 Exhaust system, 50 Substrate layer, 51 Fin structure, 51a Fin, 52 Gate material, 52a Gate portion, 53 Mask, 53a SiN layer, 53b Oxide layer, 55 Rectangular portion, 56 Residue, 101 Dielectric window, 102 Sidewall, 111 Main body, 112 Ring assembly, 1111 Electrostatic chuck, W Substrate.

Claims

1. A plasma processing device, characterized in that, include: chamber; A substrate support portion, disposed within the cavity, is capable of supporting the substrate; A gas supply unit that can supply processing gas to the chamber; A first high-frequency power supply is capable of supplying first high-frequency electrical power for plasmaizing the processing gas within the chamber. A voltage pulse source capable of supplying voltage pulses obtained by pulsed DC voltage to the substrate support portion; The second high-frequency power supply is capable of supplying second high-frequency electrical power to the substrate support portion; and The control unit is capable of controlling the following to: supplying the processing gas from the gas supply unit to the chamber during etching of the substrate, supplying a first high-frequency power from the first high-frequency power source to plasmaize the processing gas in the chamber, supplying a voltage pulse from the voltage pulse source to the substrate support, and supplying a second high-frequency power from the second high-frequency power source to the substrate support in superposition with the voltage pulse.

2. The plasma processing apparatus according to claim 1, characterized in that: The voltage pulse source can change the duty cycle of the voltage pulse by periodically turning a negative DC voltage on and off and changing the proportion of the on and off periods in one cycle. The control unit can control the duty cycle of the voltage pulse to be 10% to 80%.

3. The plasma processing apparatus according to claim 2, characterized in that: The control unit can control the duty cycle of the voltage pulse to be 10% to 20%.

4. The plasma processing apparatus according to claim 2, characterized in that: The substrate has an object film formed on its base layer, which serves as the object to be etched. The control unit is capable of controlling the voltage pulse to be smaller as the bottom of the hole formed in the target film by etching is closer to the substrate layer.

5. The plasma processing apparatus according to claim 1, characterized in that: The voltage pulse source can periodically switch on and off a negative DC voltage to supply the voltage pulse. The second high-frequency power supply is capable of not supplying the second high-frequency power during the on-time period, but supplying the second high-frequency power during the off-time period.

6. The plasma processing apparatus according to claim 1, characterized in that: The substrate has an object film formed on its base layer, which serves as the object to be etched. The control unit is capable of performing the control when the bottom of the hole formed in the target film by etching is about to reach the substrate layer.

7. The plasma processing apparatus according to claim 1, characterized in that: The substrate has, in sequence on a base layer: a fin structure having multiple fins; a gate material deposited on the fin structure; and a mask on the gate material. The control unit is capable of performing the control when the gate material deposited between the plurality of fins of the substrate is etched until the substrate layer is exposed.

8. The plasma processing apparatus according to claim 1, characterized in that: The voltage pulse source can supply voltage pulses with a frequency of 100kHz to 1200kHz.

9. The plasma processing apparatus according to claim 7, characterized in that: The gate material is polycrystalline silicon.

10. The plasma processing apparatus according to claim 7, characterized in that: The substrate layer is a silicon oxide film.

11. The plasma processing apparatus according to claim 1, characterized in that: The control unit is able to control the period, duty cycle, and amplitude of the voltage pulse, as well as the amplitude of the second high-frequency electrical power, during the etching of the substrate.

12. The plasma processing apparatus according to claim 1, characterized in that: The substrate has an object film formed on its base layer, which serves as the object to be etched. The control unit can control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal, so that: before the bottom of the hole formed in the target film by etching reaches the substrate layer, the energy distribution of the ions incident on the substrate has a higher peak on the high energy side and a lower peak on the low energy side, while when the bottom of the hole reaches the substrate layer, the low energy side peak is higher and the energy range that produces the low energy side peak becomes wider.

13. An etching method, which is an etching method of a plasma processing device, characterized in that: The plasma processing device includes: chamber; A substrate support portion, disposed within the cavity, is capable of supporting the substrate; A gas supply unit that can supply processing gas to the chamber; A first high-frequency power supply is capable of supplying first high-frequency electrical power for plasmaizing the processing gas within the chamber. A voltage pulse source capable of supplying voltage pulses obtained by pulsed DC voltage to the substrate support; and The second high-frequency power supply is capable of supplying second high-frequency electrical power to the substrate support portion. The etching method includes the following steps: During etching of the substrate, the processing gas is supplied from the gas supply section into the chamber, and a first high-frequency power is supplied from the first high-frequency power source to plasmaize the processing gas in the chamber. A voltage pulse is supplied from the voltage pulse source to the substrate support section, and a second high-frequency power is supplied from the second high-frequency power source to the substrate support section in superposition with the voltage pulse.

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