Light emitting element, array substrate, display device, and method of manufacturing light emitting element

Abstract

A light emitting element is provided. The light emitting element includes: a first conductive layer; a barrier layer on the first conductive layer; and a plurality of pillars spaced apart from each other by the barrier layer. Each of the plurality of pillars includes: a first semiconductor material layer on the first conductive layer; the multi-quantum well layer is located on the side, away from the first conductive layer, of the first semiconductor material layer; and the second semiconductor material layer is positioned on one side, far away from the first semiconductor material layer, of the barrier layer and the multi-quantum well layer. The light-emitting angle of the light-emitting element is within + / -20 degrees.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a light-emitting element, an array substrate, a display device, and a method for manufacturing the light-emitting element. Background Technology

[0002] In recent years, advancements in augmented reality (AR) and virtual reality (VR) technologies have driven the development of more sophisticated and efficient display systems. AR / VR devices increasingly rely on high-brightness, high-efficiency light sources to produce immersive and visually compelling experiences. These developments have paved the way for more compact, lightweight, and energy-efficient AR / VR systems that offer improved visual quality and user comfort, contributing to the widespread adoption and development of AR / VR applications. Summary of the Invention

[0003] On one hand, this disclosure provides a light-emitting element, comprising: a first conductive layer; a barrier layer located on the first conductive layer; and a plurality of pillars spaced apart from each other by the barrier layer; wherein each of the plurality of pillars comprises: a first semiconductor material layer located on the first conductive layer; a multiple quantum well layer located on the side of the first semiconductor material layer away from the first conductive layer; and a second semiconductor material layer located on the side of the barrier layer and the multiple quantum well layer away from the first semiconductor material layer; wherein the light emission angle of the light-emitting element is within ±20 degrees.

[0004] Optionally, the light-emitting element further includes an insulating layer formed into a tube configured to accommodate the plurality of pillars; wherein the inner sidewall of the insulating layer is in contact with the second semiconductor material layer.

[0005] Optionally, the light-emitting element further includes a second conductive layer located on the side of the insulating layer and the second semiconductor material layer away from the first conductive layer.

[0006] Optionally, the first conductive layer, the second conductive layer, and the insulating layer encapsulate the plurality of pillars.

[0007] Optionally, the light-emitting element further includes: a backplate; a bonding layer located on the backplate; and a first electrode layer located on the side of the bonding layer away from the backplate; wherein the first electrode layer is connected to the first conductive layer; and the first electrode layer is bonded to the backplate through the bonding layer.

[0008] Optionally, the light-emitting element further includes: a second electrode layer located on the side of the bonding layer away from the backplane; and an insulating layer located on the side of the first electrode layer and the second electrode layer away from the bonding layer; wherein the bonding layer includes a first bonding block and a second bonding block spaced apart from each other; the first electrode layer is bonded to the backplane through the first bonding block; the second electrode layer is bonded to the backplane through the second bonding block; and the second electrode layer is connected to the second semiconductor material layer through a via extending through the insulating layer.

[0009] Optionally, the light-emitting element further includes a lens; wherein the orthogonal projection of the lens onto the substrate substantially covers the orthogonal projection of the plurality of pillars onto the substrate.

[0010] Optionally, the lens is a biconvex lens.

[0011] Optionally, the lens has a first central optical axis; the light-emitting element has a second central optical axis; and the first central optical axis and the second central optical axis do not overlap with each other.

[0012] Optionally, the lens is a diffractive converging lens.

[0013] Optionally, the light-emitting element further includes: a first distributed Bragg reflector layer located on the side of the first conductive layer away from the first semiconductor material layer; and a second distributed Bragg reflector layer located on the side of the second semiconductor material layer away from the multiple quantum well layer; wherein the orthographic projection of the first distributed Bragg reflector layer on the substrate substantially covers the orthographic projection of the plurality of pillars on the substrate; and the orthographic projection of the second distributed Bragg reflector layer on the substrate substantially covers the orthographic projection of the plurality of pillars on the substrate.

[0014] Optionally, the light-emitting element further includes a reflective sidewall configured to converge light emitted from the plurality of pillars in the light-emitting element; wherein the orthographic projection of the reflective sidewall onto the substrate substantially surrounds the orthographic projection of the plurality of pillars in the light-emitting element onto the substrate.

[0015] Optionally, the light-emitting element further includes: a second conductive layer located on the side of the second semiconductor material layer away from the first semiconductor material layer, and the reflective sidewall located on the side of the second conductive layer away from the substrate; and a planarization layer located on the side of the second conductive layer away from the substrate; wherein the planarization layer fills the gap between the second conductive layer and the reflective sidewall.

[0016] Optionally, the light-emitting element further includes: a first lens; and a second lens; wherein the orthogonal projection of the first lens onto the substrate substantially covers the orthogonal projection of the plurality of pillars onto the substrate; the orthogonal projection of the second lens onto the substrate substantially covers the orthogonal projection of the plurality of pillars onto the substrate; the first lens is located on the side of the second semiconductor material layer away from the first conductive layer; the second lens is located on the side of the first lens away from the first conductive layer; the first lens is a biconvex lens; and the second lens is a diffraction deflecting lens.

[0017] Optionally, the widths of the plurality of pillars decrease sequentially along a first direction, wherein the first direction is along a plane that intersects the barrier layer, the first semiconductor material layer, the multiple quantum well layer and the second semiconductor material layer and is perpendicular to the surface of the first conductive layer.

[0018] On the other hand, this disclosure provides an array substrate comprising: a stacked structure including a plurality of light-emitting elements, wherein the plurality of light-emitting elements include light-emitting elements described herein or manufactured by the methods described herein; a plurality of first vias; a plurality of second vias; and a backplane; wherein the orthographic projections of the plurality of light-emitting elements on the backplane at least partially overlap each other; one or more first electrode layers of the plurality of light-emitting elements are electrically connected to the backplane through the plurality of first vias; and second electrode layers of the plurality of light-emitting elements are electrically connected to each other through the plurality of second vias.

[0019] On the other hand, this disclosure provides an array substrate comprising: a plurality of light-emitting elements, wherein the plurality of light-emitting elements include light-emitting elements described herein or manufactured by methods thereof; a color conversion layer configured to convert the color of light emitted from at least one light-emitting element to a different color; a transparent layer through which light emitted from at least one light-emitting element passes without color conversion; wherein the orthographic projections of the plurality of light-emitting elements on the substrate do not overlap with each other; and the plurality of light-emitting elements are configured to emit light of the same color.

[0020] On the other hand, this disclosure provides a display device including a light-emitting element described herein or manufactured by the methods described herein, and one or more integrated circuits.

[0021] Optionally, the display device includes a plurality of display panels configured to emit light of different colors, and an X-prism configured to combine light beams from the plurality of display panels; wherein each of the plurality of display panels includes a light-emitting element as described herein or manufactured by the methods described herein.

[0022] On the other hand, this disclosure provides a method for manufacturing a light-emitting element, comprising: forming a first conductive layer; forming a barrier layer on the first conductive layer; forming a plurality of pillars spaced apart from each other by the barrier layer; wherein forming each of the plurality of pillars comprises: forming a first semiconductor material layer on the first conductive layer; forming a multi-quantum well layer on the side of the first semiconductor material layer away from the first conductive layer; and forming a second semiconductor material layer on the side of the barrier layer and the multi-quantum well layer away from the first semiconductor material layer; wherein the light emission angle of the light-emitting element is within ±20 degrees. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0026] Figure 3A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 3B The converging cone angle of the respective lenses in some embodiments according to this disclosure is shown.

[0028] Figure 4 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 5 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 6 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0031] Figure 7 This is a perspective view of a diffraction converging lens according to some embodiments of the present disclosure.

[0032] Figure 8 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0033] Figure 9 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0034] Figure 10AThis is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0035] Figure 10B This is a schematic diagram illustrating the arrangement of multiple pillars in an array substrate according to some embodiments of the present disclosure.

[0036] Figure 10C This is a schematic diagram illustrating the arrangement of multiple pillars in an array substrate according to some embodiments of the present disclosure.

[0037] Figures 11A to 11I Methods for manufacturing an array substrate according to some embodiments of the present disclosure are shown.

[0038] Figure 12 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0039] Figure 13 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0040] Figure 14 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0041] Figures 15A to 15B Methods for manufacturing an array substrate according to some embodiments of the present disclosure are shown.

[0042] Figure 16 This is a schematic diagram illustrating the structure of a plurality of columns according to some embodiments of the present disclosure.

[0043] Figure 17 This is a schematic diagram illustrating the structure of a plurality of columns according to some embodiments of the present disclosure.

[0044] Figure 18 This is a schematic diagram illustrating the structure of a plurality of columns according to some embodiments of the present disclosure. Detailed Implementation

[0045] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0046] In recent years, AR / VR technology has developed rapidly, and corresponding AR / VR headsets have also been constantly evolving. Since AR / VR headsets are worn on the head, their size and weight must be minimized to ensure user comfort. As a key image output component in AR / VR headsets, the display screen's pixel size has decreased over time.

[0047] Micro-light-emitting diode (micro-LED) technology, known for its high brightness and self-emissive properties, is considered one of the most promising candidates for AR / VR head-mounted displays. However, LEDs exhibit a size effect, where reducing pixel size leads to an increase in the proportion of edge area, thereby enhancing non-radiative recombination and reducing luminous efficacy.

[0048] Furthermore, as portable devices, AR / VR headsets typically consume power in the hundreds of milliwatts, limiting the maximum brightness of the micro-LED displays. Additionally, the Lambertian radiation characteristics of micro-LEDs are poorly matched to AR / VR optical systems, causing some light to fail to reach the human eye, thus reducing the luminous efficiency of the AR / VR system.

[0049] Due to these limitations, the brightness perceived by users in AR / VR headsets is far from ideal, resulting in suboptimal display quality. Therefore, a high-efficiency micro-LED pixel structure and an AR / VR near-eye display optical system are proposed to address these challenges.

[0050] Under normal conditions, LEDs exhibit Lambertian radiation with a divergence angle of ±60°. In AR / VR optical systems, the required divergence angle for display pixels is within ±20°. Therefore, a significant amount of light does not enter the human eye. The display panel according to this disclosure controls the LED emission angle and divergence angle to match the requirements of the AR / VR optical system, effectively improving the efficiency of the AR / VR optical system.

[0051] Therefore, this disclosure particularly provides a light-emitting element, an array substrate, a display device, and a method for manufacturing a light-emitting element, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a light-emitting element. In some embodiments, the light-emitting element includes: a first conductive layer; a barrier layer located on the first conductive layer; and a plurality of pillars spaced apart from each other by the barrier layer. Optionally, each of the plurality of pillars includes: a first semiconductor material layer located on the first conductive layer; a multiple quantum well layer located on the side of the first semiconductor material layer away from the first conductive layer; and a second semiconductor material layer located on the side of the barrier layer and the multiple quantum well layer away from the first semiconductor material layer. Optionally, the light emission angle of the light-emitting element is within ±20 degrees.

[0052] As used herein, the term "column" refers to a substantially upright shaft in which the height is much greater than the width, for example, at least 1.5 times the width, at least 2 times the width, at least 2.5 times the width, at least 3 times the width, at least 3.5 times the width, at least 4 times the width, at least 4.5 times the width, at least 5 times the width, at least 5.5 times the width, at least 6 times the width, at least 6.5 times the width, at least 7 times the width, at least 7.5 times the width, at least 8 times the width, at least 8.5 times the width, at least 9 times the width, at least 9.5 times the width, or at least 10 times the width. In some embodiments, the column is a nanocolumn, such as a nanoscale column. As used herein, the term “nanoscale” refers to any structure with a width between 1 nm and 1000 nm (e.g., 1 nm to 100 nm, 100 nm to 200 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, or 900 nm to 1000 nm).

[0053] Various suitable embodiments can be practiced in this disclosure. For example, the column can have various suitable shapes. The column can be a cube or a cylinder, but for manufacturing considerations, it is generally cylindrical. In one example, the column has a cubic shape with a length less than 1 μm, a width less than 1 μm, and a height in the range of 0.1 μm to 5 μm. In another example, the column has a cylindrical shape with a diameter less than 1 μm and a height in the range of 0.1 μm to 5 μm.

[0054] In some embodiments, adjacent pillars of the plurality of pillars are spaced apart by a distance greater than 0.04 μm. In some embodiments, the total number of pillars in each light-emitting element is greater than 4. The spacing can be adjusted according to the brightness requirements of the LED device. For cylindrical nanopillars, the number of nanopillars can be calculated as the area of ​​the nanopillar divided by the square of the sum of the nanopillar diameter and the spacing.

[0055] As used herein, the term "light emission angle" refers to an angle at which the intensity of light emitted by the light-emitting element is half the intensity of light emitted by the light-emitting element along the normal direction. The term "light emission angle" does not imply that there is no light emission outside this angle.

[0056] Figure 1 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP, and a second electrode layer E2 on the side of the second conductive layer CL2 away from the backplane BP.

[0057] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second conductive layer CL2 connects the second electrode layer E2 to the second semiconductor material layer SML2.

[0058] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 1 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0059] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0060] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0061] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0062] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0063] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0064] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0065] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillar NPs. The insulating layer IN forms the sidewalls of the package. In some embodiments, the insulating layer IN forms a tube configured to accommodate the plurality of pillar NPs. Optionally, the inner sidewall of the insulating layer IN contacts a second semiconductor material layer SML2. As used herein, the term "tube" refers to a hollow structure that at least partially (e.g., completely) encloses a plurality of pillar NPs within a respective light-emitting element. The inner sidewall of the tube contacts the second semiconductor material layer SML2, thereby forming part of the overall structural and electrical isolation within the device. The primary function of the tube is to provide physical support and electrical insulation for the plurality of pillar NPs while maintaining close contact with other material layers within the respective light-emitting element. In one example, the tube has a cylindrical shape. Other examples of tube shapes include square tube shapes, rectangular tube shapes, elliptical tube shapes, triangular tube shapes, and octagonal tube shapes.

[0066] In some embodiments, the length of each light-emitting element is in the range of 1 μm to 2000 μm, the width is in the range of 1 μm to 2000 μm, and the height is in the range of 0.5 μm to 10 μm, for example, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. In one example, the height of each light-emitting element is in the range of 5 μm to 6 μm.

[0067] Figure 2 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 2 An array substrate comprising miniature light-emitting diodes with an inverted structure is depicted. (Refer to...) Figure 2 In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 and a second electrode layer E2 on the side of the bonding layer BL away from the backplane BP, an insulating layer IN on the side of the first electrode layer E1 and the second electrode layer E2 away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, and a substrate BS on the side of the second semiconductor material layer SML2 away from the backplane BP.

[0068] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second electrode layer E2 is connected to the second semiconductor material layer SML2 through a via extending through the insulating layer IN.

[0069] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 2 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0070] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0071] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0072] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0073] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0074] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0075] In some embodiments, the first conductive layer CL1 is made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 is configured to allow current diffusion.

[0076] In some embodiments, the substrate BS is made of an insulating material such as sapphire, silicon, and silicon carbide.

[0077] The inventors of this disclosure discovered that, Figure 2 The array substrate depicted in the image offers a simple manufacturing process and high luminous efficiency.

[0078] Figure 3AThis is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3A In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP, and a second electrode layer E2 on the side of the second conductive layer CL2 away from the backplane BP.

[0079] In some embodiments, the array substrate further includes a plurality of lenses. Figure 3A The diagram illustrates a corresponding lens LEN among a plurality of lenses. In some embodiments, the array substrate further includes a planarization layer PLN located on the side of the second conductive layer CL2 away from the backplane BP, a corresponding lens LEN located on the side of the planarization layer PLN away from the backplane BP, and an encapsulation layer EN located on the side of the corresponding lens LEN away from the backplane BP.

[0080] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second conductive layer CL2 connects the second electrode layer E2 to the second semiconductor material layer SML2.

[0081] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 3A The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0082] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0083] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0084] In some embodiments, the orthogonal projection of the corresponding lens LEN onto the backplane BP substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthogonal projection of the plurality of pillars NP onto the backplane BP.

[0085] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0086] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0087] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0088] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0089] In some embodiments, the individual lens elements (LENs) may be made of insulating materials, such as silicon oxide, silicon nitride, and organic adhesives. The individual lens elements (LENs) can be manufactured using processes such as exposure, thermal bonding, and etching. In some embodiments, the individual lens elements (LENs) are biconvex lenses.

[0090] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillars NP. The insulating layer IN forms the sidewalls of the package.

[0091] In some embodiments, the bottom diameter of the respective lens LEN is greater than the sum of the widths of the multiple quantum well layers (MQWs) within the respective lens LEN in the plurality of pillar NPs. In some embodiments, the sum of the widths of the multiple quantum well layers (MQWs) within the respective lens LEN in the plurality of pillar NPs is in the range of 0.5 μm to 1000 μm. In some embodiments, the bottom diameter of each lens LEN is in the range of 1 μm to 2000 μm. In some embodiments, the height of each lens LEN is in the range of 0.1 μm to 1000 μm. Figure 3B The converging cone angle of a corresponding lens according to some embodiments of the present disclosure is shown. In some embodiments, reference is made to... Figure 3B The multiple quantum well layer (MQW) is located within the convergence cone angle (CA) of the corresponding lens LEN. By placing the MQW within the convergence cone angle (CA) of the corresponding lens LEN, light can be converged to the normal viewing angle. The convergence cone angle of the corresponding lens LEN depends on the focal length of the corresponding lens LEN and ranges from 0.1 μm to 1000 μm.

[0092] Figure 4 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 4 In some embodiments, the array substrate includes a first distributed Bragg reflector layer DBR1, a first electrode layer E1 and a second electrode layer E2 located on the first distributed Bragg reflector layer DBR1, a first conductive layer CL1 located on the side of the first electrode layer E1 away from the first distributed Bragg reflector layer DBR1, a first semiconductor material layer SML1 located on the side of the first conductive layer CL1 away from the first distributed Bragg reflector layer DBR1, a multi-quantum well layer MQW located on the side of the first semiconductor material layer SML1 away from the first distributed Bragg reflector layer DBR1, a second semiconductor material layer SML2 located on the side of the multi-quantum well layer MQW away from the first distributed Bragg reflector layer DBR1, a second distributed Bragg reflector layer DBR2 located on the side of the second semiconductor material layer SML2 away from the first distributed Bragg reflector layer DBR1, and a substrate BS located on the side of the second distributed Bragg reflector layer DBR2 away from the first distributed Bragg reflector layer DBR1.

[0093] In some embodiments, the first distributed Bragg reflector layer DBR1 or the second distributed Bragg reflector layer DBR2 comprises alternating silicon oxide sublayers and titanium oxide sublayers. In one example, the number of sublayers in the first distributed Bragg reflector layer DBR1 is the same as the number of sublayers in the second distributed Bragg reflector layer DBR2. In an alternative example, the number of sublayers in the first distributed Bragg reflector layer DBR1 is different from the number of sublayers in the second distributed Bragg reflector layer DBR2. In some embodiments, the thickness of the first distributed Bragg reflector layer DBR1 or the second distributed Bragg reflector layer DBR2 is in the range of 0.5 μm to 10 μm. In some embodiments, the orthographic projection of the first distributed Bragg reflector layer DBR1 onto the backplane BP overlaps the orthographic projection of the multiple quantum well layers in the plurality of pillars onto the backplane. In some embodiments, the orthographic projection of the second distributed Bragg reflector layer DBR2 onto the backplane BP overlaps the orthographic projection of the multiple quantum well layers in the plurality of pillars onto the backplane. In some embodiments, the width of the first distributed Bragg reflector layer DBR1 is 1.5 times the distance between the two furthest sublayers in the first distributed Bragg reflector layer DBR1. In some embodiments, the width of the first distributed Bragg reflector layer DBR1 is in the range of 1 μm to 2000 μm. In some embodiments, the width of the second distributed Bragg reflector layer DBR2 is 1.5 times the distance between the two furthest sublayers in the second distributed Bragg reflector layer DBR2. In some embodiments, the width of the second distributed Bragg reflector layer DBR2 is in the range of 1 μm to 2000 μm.

[0094] In some embodiments, the array substrate further includes an insulating layer IN located on the side of the first electrode layer E1 and the second electrode layer E2 away from the first distributed Bragg reflector layer DBR1. The second electrode layer E2 is connected to the second semiconductor material layer SML2 through a via extending through the insulating layer IN.

[0095] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second electrode layer E2 is connected to the second semiconductor material layer SML2 through a via extending through the insulating layer IN.

[0096] In some embodiments, the array substrate includes a plurality of light-emitting elements. In one example... Figure 4 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0097] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0098] In some embodiments, the orthographic projection of the first distributed Bragg reflector layer DBR1 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the plurality of pillars NP onto the substrate BS. In some embodiments, the orthographic projection of the second distributed Bragg reflector layer DBR2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the plurality of pillars NP onto the substrate BS.

[0099] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0100] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0101] In some embodiments, the first electrode layer E1 and the second electrode layer E2 are made of metallic materials.

[0102] In some embodiments, the first conductive layer CL1 is made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 is configured to allow current diffusion.

[0103] In some embodiments, the first distributed Bragg reflector layer DBR1 and the second distributed Bragg reflector layer DBR2 are configured to converge light emitted from the respective light-emitting elements. The first distributed Bragg reflector layer DBR1 and the second distributed Bragg reflector layer DBR2 may be made of one or more materials including group III-V elements, silicon, nitrogen, and oxygen.

[0104] In some embodiments, the first distributed Bragg reflector layer DBR1 has a multilayer structure comprising one or more high-refractive-index sublayers and one or more low-refractive-index sublayers arranged alternately. In one example, the first distributed Bragg reflector layer DBR1 has an HL...HL structure, where H represents a sublayer with a high refractive index and L represents a sublayer with a low refractive index. Optionally, the distributed Bragg reflector is a quarter-wavelength reflector, wherein the thickness of each of the plurality of sublayers is related to one-quarter of the wavelength of the light reflected by the distributed Bragg reflector. In one example, the H sublayer comprises titanium oxide and the L sublayer comprises silicon oxide. In another example, the H sublayer comprises hafnium oxide and the L sublayer comprises silicon oxide. In another example, the H sublayer comprises gallium nitride and the L sublayer comprises aluminum nitride. In another example, the H sublayer comprises aluminum gallium nitride and the L sublayer comprises gallium nitride. In another example, the H sublayer comprises aluminum gallium arsenide and the L sublayer comprises gallium arsenide.

[0105] In some embodiments, the second distributed Bragg reflector layer DBR2 has a multilayer structure comprising one or more high-refractive-index sublayers and one or more low-refractive-index sublayers arranged alternately. In one example, the second distributed Bragg reflector layer DBR2 has an HL...HL structure, where H represents a sublayer with a high refractive index and L represents a sublayer with a low refractive index. Optionally, the distributed Bragg reflector is a quarter-wavelength reflector, wherein the thickness of each of the multiple sublayers is related to one-quarter of the wavelength of the light reflected by the distributed Bragg reflector. In one example, the H sublayer comprises titanium oxide and the L sublayer comprises silicon oxide. In another example, the H sublayer comprises hafnium oxide and the L sublayer comprises silicon oxide. In another example, the H sublayer comprises gallium nitride and the L sublayer comprises aluminum nitride. In another example, the H sublayer comprises aluminum gallium nitride and the L sublayer comprises gallium nitride. In another example, the H sublayer comprises aluminum gallium arsenide and the L sublayer comprises gallium arsenide.

[0106] Alternatively, the thickness of each sublayer in the multiple sublayers of the distributed Bragg reflector can be calculated using the following formula:

[0107] d=λ / 4η

[0108] Where d represents the thickness of the corresponding sublayer among the multiple sublayers of the distributed Bragg reflector; λ represents the dominant wavelength of the light reflected by the distributed Bragg reflector; and η is the reflectivity of the corresponding sublayer among the multiple sublayers of the distributed Bragg reflector.

[0109] For example, the dominant wavelength of light reflected by the distributed Bragg reflector is 450 nm (e.g., blue light). This distributed Bragg reflector has multiple H sublayers (with high refractive indices) and multiple L sublayers (with low refractive indices). Each H sublayer comprises titanium oxide, and each L sublayer comprises silicon oxide. The refractive index of each L sublayer comprising silicon oxide is 1.47, therefore the thickness of each L sublayer is 76.5 nm. The refractive index of each H sublayer comprising titanium oxide is 2.52, therefore the thickness of each H sublayer is 44.64 nm.

[0110] In some embodiments, the number of H sublayers in the distributed Bragg reflector is the same as the number of L sublayers. In alternative embodiments, the number of H sublayers in the distributed Bragg reflector is different from the number of L sublayers.

[0111] In some embodiments, the thickness of each H sublayer in the plurality of H sublayers is in the range of 0.5 μm to 10 μm, and the thickness of each L sublayer in the plurality of L sublayers is in the range of 0.5 μm to 10 μm.

[0112] In some embodiments, the width of the distributed Bragg reflector is greater than the width of the multi-quantum-well (MQW) layer. Optionally, the width of the distributed Bragg reflector is greater than or equal to 1.5 times the width of the MQW layer to reduce light emission from the sidewalls. In some embodiments, the width of the distributed Bragg reflector is in the range of 1 μm to 2000 μm.

[0113] Figure 5 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, and a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP. Optionally, in some embodiments, the array substrate further includes a second electrode layer on the side of the second conductive layer CL2 away from the backplane BP.

[0114] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 5 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0115] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0116] In some embodiments, the array substrate further includes a reflective sidewall RSW located on the side of the second conductive layer CL2 away from the backplane BP. The reflective sidewall RSW is configured to converge light emitted from the respective light-emitting elements. In some embodiments, the orthographic projection of the reflective sidewall RSW onto the backplane BP substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) surrounds the orthographic projection of a plurality of pillars NP in the respective light-emitting elements onto the backplane BP.

[0117] In some embodiments, the reflective sidewalls RSW are made of a metallic material.

[0118] In some embodiments, the reflective sidewall RSW is a distributed Bragg reflector. In some embodiments, the reflective sidewall RSW has a multilayer structure comprising one or more high-refractive-index sublayers and one or more low-refractive-index sublayers arranged alternately. In one example, the reflective sidewall RSW has an HL...HL structure, where H represents a sublayer with a high refractive index and L represents a sublayer with a low refractive index. Optionally, the reflective sidewall RSW is a quarter-wavelength reflector, wherein the thickness of each of the plurality of sublayers is related to one-quarter of the wavelength of the light reflected by the reflective sidewall RSW. In one example, the H sublayer comprises titanium oxide and the L sublayer comprises silicon oxide. In another example, the H sublayer comprises hafnium oxide and the L sublayer comprises silicon oxide. In another example, the H sublayer comprises gallium nitride and the L sublayer comprises aluminum nitride. In another example, the H sublayer comprises aluminum gallium nitride and the L sublayer comprises gallium nitride. In another example, the H sublayer comprises aluminum gallium arsenide and the L sublayer comprises gallium arsenide.

[0119] In some embodiments, the height of the reflective sidewall RSW is in the range of 2 μm to 10 μm. The height of the reflective sidewall RSW relative to the backplane BP is greater than the height of the multiple quantum well layer MQW relative to the backplane BP.

[0120] In some embodiments, the sidewall tilt angle of the reflective sidewall RSW is in the range of 30 degrees to 90 degrees, and optionally, in the range of 60 degrees to 80 degrees.

[0121] In some embodiments, the array substrate further includes a planarization layer PLN located on the side of the second conductive layer CL2 away from the backplane BP. Optionally, the planarization layer PLN fills the gap between the second conductive layer CL2 and the reflective sidewall RSW.

[0122] In some embodiments, a first conductive layer CL1 connects a first electrode layer E1 to a first semiconductor material layer SML1. In some embodiments, a second conductive layer CL2 connects a second electrode layer to a second semiconductor material layer SML2.

[0123] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0124] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0125] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0126] In some embodiments, the first electrode layer E1, the second electrode layer, and the bonding layer BL are made of metallic materials.

[0127] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0128] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillars NP. The insulating layer IN forms the sidewalls of the package.

[0129] Figure 6 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 6In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, and a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP. Optionally, the array substrate further includes a second electrode layer on the side of the second conductive layer CL2 away from the backplane BP.

[0130] In some embodiments, the array substrate further includes a plurality of lenses. Figure 6 The diagram shows a corresponding lens LEN among a plurality of lenses. In some embodiments, the array substrate further includes a planarization layer PLN located on the side of the second conductive layer CL2 away from the backplane BP, each lens LEN located on the side of the planarization layer PLN away from the backplane BP, and an encapsulation layer EN located on the side of each lens LEN away from the backplane BP.

[0131] In some embodiments, a first conductive layer CL1 connects a first electrode layer E1 to a first semiconductor material layer SML1. In some embodiments, a second conductive layer CL2 connects a second electrode layer to a second semiconductor material layer SML2.

[0132] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 6 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0133] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0134] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0135] In some embodiments, the orthogonal projection of the corresponding lens LEN onto the backplane BP substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthogonal projection of the plurality of pillars NP onto the backplane BP.

[0136] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0137] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0138] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0139] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0140] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillars NP. The insulating layer IN forms the sidewalls of the package.

[0141] In some embodiments, each lens (LEN) may be made of an insulating material, such as silicon oxide, silicon nitride, and organic adhesive. In some embodiments, each lens (LEN) is a diffractive converging lens. Figure 7This is a perspective view of a diffractive converging lens according to some embodiments of the present disclosure. In some embodiments, the diffractive converging lens includes a plurality of micropillars MP. Optionally, the diameter of each micropillar in the plurality of micropillars MP is less than 1000 nm. The phases of micropillars with different diameters are different. The specific micropillar diameters are configured to meet the phase requirements of a spherical lens or to meet the off-axis aberration correction phase, thereby producing a collimated beam. The diffractive converging lens can be fabricated using nanoimprint lithography or photolithography techniques.

[0142] A diffractive converging lens is an optical component that uses the principle of diffraction to focus or converge light waves to a single point or along a specific path. Similar to a conventional lens, its purpose is to direct parallel light rays to a single focal point. However, it achieves this by using microstructure patterns on its surface, which creates a phase shift in the passing light waves. These phase shifts cause the light to interfere in a way that leads to convergence.

[0143] Various suitable embodiments can be practiced in this disclosure. The plurality of micropillars (MPs) can have various suitable shapes. Examples of suitable shapes include cylindrical or rectangular. In some embodiments, the array period of the plurality of micropillars (MPs) is less than 1 μm. In some embodiments, the diameter or width of each micropillar in the plurality of micropillars (MPs) is smaller than this period. The plurality of micropillars (MPs) can be made of dielectric materials such as SiO2, SiN, Al2O3, GaN, etc.

[0144] Micropillars can be either transmission-phase or geometric-phase. Transmission-phase typically refers to the phase shift modulation experienced by light as it passes through multiple micropillars (MPs), where the MPs act as cutoff dielectric waveguides with low-reflectivity upper or lower interfaces. The phase shift can be adjusted by changing factors such as the height, cross-sectional dimensions, lattice spacing, and constituent materials of the MPs. Geometric-phase, also known as Pancharatnam-Berry phase, is generally applicable when circularly polarized light interacts with an anisotropic array of micropillars of the same size but with different orientation angles. The crossed circularly polarized components of the transmitted light will be given twice the phase modulation of the micropillars, achieved by changing the orientation angles of the MPs. The arrangement of the MPs follows a specific phase distribution, which can be a hyperbolic or complex phase distribution. In some embodiments, the phase of the MPs is represented as:

[0145]

[0146] Where f is the focal length of the metasurface, λ is the wavelength of light emitted from the corresponding light-emitting element, and (x, y) are the coordinates of the multiple micropillars MP. In some embodiments, the metasurface refers to a planar lens structure composed of multiple micropillars MP, wherein the height of the multiple micropillars MP is in the range of nanometer to micrometer scales. Macroscopically, it appears as a surface structure; under a microscope, it is a three-dimensional structure, not just a simple surface, but an collection of micropillars. The metasurface is configured to collimate light from the corresponding light-emitting element and acts as a lens with a focal length f. In one example, the focal length f of the metasurface is the distance between the multi-quantum-well layer (MQW) and the bottom surface of the multiple micropillars MP.

[0147] In some embodiments, the diameter or width of the diffractive converging lens is in the range of 1 μm to 2000 μm. In some embodiments, the number of multiple micropillars (MPs) is approximately the same as the diameter or width divided by the period. When the optical axes of the diffractive converging lens and the corresponding light-emitting element coincide, the orthographic projection of the diffractive converging lens onto the substrate at least partially overlaps with the orthographic projection of the corresponding light-emitting element onto the substrate.

[0148] Figure 8 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 8 An angle-deflected array substrate is depicted. (Refer to...) Figure 8 In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP, and a second electrode layer E2 on the side of the second conductive layer CL2 away from the backplane BP.

[0149] In some embodiments, the array substrate further includes a plurality of lenses. Figure 8 The diagram illustrates a corresponding lens LEN among a plurality of lenses. In some embodiments, the array substrate further includes a planarization layer PLN located on the side of the second conductive layer CL2 away from the backplane BP, and a corresponding lens LEN located on the side of the planarization layer PLN away from the backplane BP.

[0150] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second conductive layer CL2 connects the second electrode layer E2 to the second semiconductor material layer SML2.

[0151] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 8 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0152] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0153] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0154] In some embodiments, the orthogonal projection of the corresponding lens LEN onto the backplane BP substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthogonal projection of the plurality of pillars NP onto the backplane BP.

[0155] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0156] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0157] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0158] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0159] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillars NP. The insulating layer IN forms the sidewalls of the package.

[0160] In some embodiments, the individual lens elements (LENs) may be made of insulating materials, such as silicon oxide, silicon nitride, and organic adhesives. The individual lens elements (LENs) can be manufactured using processes such as exposure, thermal bonding, and etching. In some embodiments, the individual lens elements (LENs) are biconvex lenses.

[0161] In some embodiments, each lens LEN has a first central optical axis AX1, each light-emitting element has a second central optical axis AX2, and the first central optical axis AX1 and the second central optical axis AX2 do not overlap each other. As used herein, the term "non-overlapping" means that the first central optical axis AX1 and the second central optical axis AX2 are not parallel (e.g., at an angle greater than 5 degrees, greater than 10 degrees, greater than 15 degrees, greater than 20 degrees, or greater than 25 degrees). In one example, each lens LEN is tilted relative to its respective light-emitting element such that the first central optical axis AX1 and the second central optical axis AX2 do not overlap each other. In another example, each lens LEN is shaped in a way that redirects light so that the first central optical axis AX1 and the second central optical axis AX2 do not overlap each other.

[0162] In some embodiments, the orthographic projection of the first central optical axis AX1 onto the backplate BP and the orthographic projection of the second central optical axis AX2 onto the backplate BP are spaced apart by a distance smaller than the diameter of the corresponding lens LEN. Optionally, the orthographic projection of the first central optical axis AX1 onto the backplate BP and the orthographic projection of the second central optical axis AX2 onto the backplate BP are spaced apart by a distance smaller than half the diameter of the corresponding lens LEN. Optionally, the distance between the orthographic projection of the first central optical axis AX1 onto the backplate BP and the orthographic projection of the second central optical axis AX2 onto the backplate BP is in the range of 0.1 to 0.5 times the diameter of the corresponding lens LEN (e.g., 0.1 to 0.2 times, 0.2 to 0.3 times, 0.3 to 0.4 times, or 0.4 to 0.5 times).

[0163] When light passes through the individual lenses (LENs), the curvature and orientation of each LEN cause the light to bend. This bending is due to refraction, which is governed by Snell's law. The difference in refractive index between the lens material and the surrounding medium causes the light to change direction. The deflection mechanism allows light to be guided at a specific angle, which can be precisely controlled. By deflecting light at a controlled angle, the array substrate improves the efficiency of light utilization, ensuring that more light is directed to the desired viewing angle or optical path. This deflection reduces light loss that occurs when light is emitted in an unwanted direction, thereby improving the overall brightness and efficiency of the array substrate.

[0164] The inventors of this disclosure have discovered that the structure of the array substrate provides a simple and cost-effective way to manufacture angle-deflecting array substrates. By deflecting light at a specific angle, the array substrate ensures efficient use of more light, increasing brightness and reducing waste. The array substrate can be customized to achieve specific light patterns and angles, making this technology versatile for a wide range of applications. This method of light deflection in LEDs is particularly useful in applications where precise control of light direction is crucial (such as in AR / VR displays), where light needs to be precisely directed to the user's eyes for optimal visual experience.

[0165] Figure 9 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 9In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP, and a second electrode layer E2 on the side of the second conductive layer CL2 away from the backplane BP.

[0166] In some embodiments, the array substrate further includes a plurality of first lenses. Figure 9 The diagram illustrates a corresponding first lens LEN1 among a plurality of first lenses. In some embodiments, the array substrate further includes a planarization layer PLN located on the side of the second conductive layer CL2 away from the backplane BP, each first lens LEN1 located on the side of the planarization layer PLN away from the backplane BP, and a first encapsulation layer EN1 located on the side of each first lens LEN1 away from the backplane BP.

[0167] In some embodiments, the array substrate further includes a plurality of second lenses. Figure 9 The diagram illustrates a corresponding second lens LEN2 among a plurality of second lenses. In some embodiments, each second lens LEN2 is located on the side of the first encapsulation layer EN1 away from the backplane BP, and the second encapsulation layer EN2 is located on the side of each second lens LEN2 away from the backplane BP.

[0168] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second conductive layer CL2 connects the second electrode layer E2 to the second semiconductor material layer SML2.

[0169] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 9 The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0170] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0171] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0172] In some embodiments, the orthogonal projection of the corresponding first lens LEN1 onto the backplane BP substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthogonal projection of the plurality of pillars NP onto the backplane BP.

[0173] In some embodiments, the orthogonal projection of the corresponding second lens LEN2 onto the backplane BP substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthogonal projection of the plurality of pillars NP onto the backplane BP.

[0174] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0175] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0176] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0177] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0178] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillars NP. The insulating layer IN forms the sidewalls of the package.

[0179] In some embodiments, each first lens LEN1 or each second lens LEN2 may be made of an insulating material, such as silicon oxide, silicon nitride, and organic adhesive. Each first lens LEN1 may be manufactured using processes such as exposure, thermal bonding, and etching. In some embodiments, each first lens LEN1 is a biconvex lens. In some embodiments, each second lens LEN2 is a diffraction-deflecting lens. In some embodiments, the diffraction-deflecting lens comprises a plurality of micropillars. Optionally, the diameter of each micropillar is less than 1000 nm. Micropillars of different diameters have different phases. Specific micropillar diameters are configured to meet the phase requirements of a spherical lens or to meet off-axis aberration correction phase, thereby producing a collimated beam. The diffraction-deflecting lens may be manufactured using nanoimprint lithography or photolithography techniques.

[0180] Various suitable embodiments can be practiced in this disclosure. The plurality of micropillars can have various suitable shapes. Examples of suitable shapes include cylindrical or rectangular. In some embodiments, the array period of the plurality of micropillars is less than 1 μm. In some embodiments, the diameter or width of each micropillar in the plurality of micropillars is smaller than this period. The plurality of micropillars can be made of a dielectric material such as SiO2, SiN, Al2O3, GaN, etc.

[0181] Micropillars can be either transmission-phase or geometric-phase. Transmission-phase typically refers to the phase shift modulation experienced by light as it passes through multiple micropillars, which act as cutoff dielectric waveguides with low-reflectivity upper or lower interfaces. The phase shift can be adjusted by changing factors such as the height, cross-sectional dimensions, lattice spacing, and constituent materials of the micropillars. Geometric-phase, also known as Pancharatnam-Berry phase, is typically applied when circularly polarized light interacts with an anisotropic array of micropillars of the same size but with different orientation angles. The crossed circularly polarized components of the transmitted light will be given twice the phase modulation of the micropillars, achieved by changing the orientation angles of the micropillars. The arrangement of the micropillars follows a specific phase distribution, which can be a hyperbolic phase distribution or a complex phase distribution.

[0182] In some embodiments, the diameter or width of the diffraction deflector is in the range of 1 μm to 2000 μm. In some embodiments, the number of multiple micropillars (MPs) is approximately the same as the diameter or width divided by the period. When the optical axes of the diffraction deflector and the corresponding light-emitting element coincide, the orthographic projection of the diffraction deflector onto the substrate at least partially overlaps with the orthographic projection of the corresponding light-emitting element onto the substrate.

[0183] In some embodiments, the phase of a diffractive deflector lens is a deflection phase, configured to deflect light. A diffractive deflector lens is an optical element configured to redirect or deflect light waves through diffraction. Unlike conventional lenses that rely on refraction to change the direction of light, diffractive deflectors use microstructures, typically in the form of a series of grooves or patterns etched into a surface. These microstructures cause light to interfere constructively and destructively at specific angles, resulting in controlled deflection of the beam. Diffractive deflectors are commonly used in applications requiring precise optical manipulation, such as beam control in optical communication and laser systems.

[0184] In some embodiments, the phase distribution of the diffractive lens is:

[0185]

[0186] Where θ is the deflection angle of the metasurface, λ is the wavelength of light emitted from the corresponding light-emitting element, and x is the coordinate of the plurality of micropillars (MPs). Adjusting the phase distribution can change the deflection angle, which can be achieved by changing the diameter / side length of the micropillars. As used herein, the term deflection angle refers to the angle relative to the incident light emitted from the corresponding light-emitting element reflected by the metasurface. In some embodiments, the metasurface refers to a planar lens structure composed of a plurality of micropillars (MPs) with heights ranging from nanometers to micrometers. Macroscopically, it appears as a surface structure; microscopically, it is a three-dimensional structure, not merely a simple surface, but an assembly of micropillars. The metasurface is configured to collimate light from the corresponding light-emitting element and acts as a lens with a focal length f. In one example, the focal length f of the metasurface is the distance between the multi-quantum-well (MQW) layer and the bottom surface of the plurality of micropillars (MPs).

[0187] Figure 9The array substrate depicted uses a combination of a corresponding first lens LEN1 and a corresponding second lens LEN2. The array substrate allows for highly precise control of the beam direction. This precision is crucial for applications like AR / VR displays, where light needs to be precisely guided to the user's eyes. By focusing and then deflecting the light, the array substrate ensures that more emitted light is effectively utilized, reducing losses and improving the overall brightness and efficiency of the LED. The array substrate is relatively simple and cost-effective to manufacture. The use of the corresponding first lens LEN1 and corresponding second lens LEN2 can be integrated into existing manufacturing processes, making it suitable for mass production. The array substrate is suitable for a variety of applications requiring precise light control. The diffraction deflecting lenses can be customized to achieve different deflection angles and patterns, providing design flexibility.

[0188] Figure 10A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 10A In some embodiments, the array substrate includes a backplane BP, a bonding layer BL on the backplane BP, a first electrode layer E1 on the side of the bonding layer BL away from the backplane BP, a first conductive layer CL1 on the side of the first electrode layer E1 away from the backplane BP, a first semiconductor material layer SML1 on the side of the first conductive layer CL1 away from the backplane BP, a multi-quantum well layer MQW on the side of the first semiconductor material layer SML1 away from the backplane BP, a second semiconductor material layer SML2 on the side of the multi-quantum well layer MQW away from the backplane BP, an insulating layer IN on the side of the second semiconductor material layer SML2 away from the backplane BP, a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP, a second electrode layer E2 on the side of the second conductive layer CL2 away from the backplane BP, and a planarization layer PLN on the side of the second conductive layer CL2 away from the backplane BP.

[0189] In some embodiments, the first conductive layer CL1 connects the first electrode layer E1 to the first semiconductor material layer SML1. In some embodiments, the second conductive layer CL2 connects the second electrode layer E2 to the second semiconductor material layer SML2.

[0190] In some embodiments, the backplane (BP) includes a plurality of transistors configured to drive a plurality of light-emitting elements in the array substrate to emit light. In one example... Figure 10A The corresponding light-emitting elements among the multiple light-emitting elements in the array substrate are depicted.

[0191] In some embodiments, the bonding layer BL is configured to bond multiple light-emitting elements to the backplane BP. The bonding layer BL ensures stable connectivity and efficient transmission of electrical signals.

[0192] In some embodiments, the array substrate includes a plurality of pillars NP spaced apart from each other by a barrier layer BRL. Each pillar of the plurality of pillars NP includes a stacked structure comprising: a portion of a first semiconductor material layer SML1; a portion of a multiple quantum well layer MQW located on the portion of the first semiconductor material layer SML1; and a portion of a second semiconductor material layer SML2 located on the side of the portion of the multiple quantum well layer MQW away from the portion of the first semiconductor material layer SML1.

[0193] Various suitable embodiments can be practiced in this disclosure. For example, the column can have various suitable shapes. The column can be a cube or a cylinder, but it is usually cylindrical for manufacturing considerations. In one example, the column has a cubic shape with a length less than 1 μm, a width less than 1 μm, and a height in the range of 0.1 μm to 5 μm. In another example, the column has a cylindrical shape with a diameter less than 1 μm and a height in the range of 0.1 μm to 5 μm.

[0194] In some embodiments, adjacent pillars of the plurality of pillars are spaced apart by a distance greater than 0.04 μm. In some embodiments, the total number of pillars in each light-emitting element is greater than 4. The spacing can be adjusted according to the brightness requirements of the LED device. For cylindrical nanopillars, the number of nanopillars can be calculated as the area of ​​the nanopillar divided by the square of the sum of the nanopillar diameter and the spacing.

[0195] In some embodiments, the phase distribution of the columns among the plurality of columns is as follows:

[0196]

[0197] Where θ is the deflection angle of the metasurface, λ is the wavelength of light emitted from the corresponding light-emitting element, and x is the coordinate of the plurality of micropillars (MPs). Adjusting the phase distribution can change the deflection angle, which can be achieved by changing the diameter / side length of the pillars among the plurality of pillars. In one example, the pillars among the plurality of pillars are made of GaN, and the diameter-phase mapping is as follows: when the diameters are 40 / 60 / 80 / 100 / 120 / 160 nm, the corresponding phases are 0.163 / 0.489 / 1.022 / 1.885 / 3.137 / 4.677 / 6.198 radians, respectively. In some embodiments, the metasurface refers to a planar lens structure composed of a plurality of micropillars (MPs), wherein the height of the plurality of micropillars (MPs) is in the range of nanometer to micrometer scales. Macroscopically, it exhibits as a surface structure; under a microscope, it is a three-dimensional structure, not only a simple surface but also an collection of micropillars. The metasurface is configured to collimate light from the corresponding light-emitting element and acts as a lens with a focal length f. In one example, the focal length f of the metasurface is the distance between the multi-quantum-well layer (MQW) and the bottom surface of the multiple micropillars (MP).

[0198] Figure 10B This is a schematic diagram illustrating the arrangement of a plurality of pillars in an array substrate according to some embodiments of the present disclosure. In some embodiments, the plurality of pillars are arranged in an array having a square grid or a hexagonal grid. Figure 10B In the diagram, multiple columns are arranged in an array with square grids. Figure 10C This is a schematic diagram illustrating the arrangement of multiple pillars in an array substrate according to some embodiments of the present disclosure. Figure 10C In the diagram, multiple pillars are arranged in an array with hexagonal grids.

[0199] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0200] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0201] In some embodiments, the first electrode layer E1, the second electrode layer E2, and the bonding layer BL are made of metallic materials.

[0202] In some embodiments, the first conductive layer CL1 and the second conductive layer CL2 are made of a transparent conductive material such as indium tin oxide. The first conductive layer CL1 and the second conductive layer CL2 are configured to diffuse current.

[0203] In some embodiments, a first conductive layer CL1, a second conductive layer CL2, and an insulating layer IN encapsulate a plurality of pillars NP. The insulating layer IN forms the sidewalls of the package.

[0204] In some embodiments, the width (e.g., diameter) of the plurality of pillar NPs along a first direction DR1 decreases sequentially, wherein the first direction DR1 is a direction along a plane intersecting the surface of the barrier layer BRL, the first semiconductor material layer SML1, the multiple quantum well layer MQW, and the second semiconductor material layer SML2 and perpendicular to the backplane BP. Optionally, the first direction DR1 extends from a first side of a respective light-emitting element to a second side of the respective light-emitting element. In some embodiments, the width of the plurality of pillar NPs along the first direction DR1 gradually decreases. The plurality of pillar NPs with sequentially (e.g., gradually) decreasing widths are configured to have different deflection phases and are configured to directly emit deflected light, the different deflection phases altering the path of the light as it passes through the pillars. When light passes through the plurality of pillar NPs, the deflection phase introduced by the varying widths causes the light to be emitted at a specific angle. This results in direct light deflection without the need for additional structures.

[0205] The inventors of this disclosure have discovered that the array substrate according to this disclosure provides a simple and cost-effective way to manufacture an angle-deflecting array substrate. Multiple pillars (NPs) provide precise control over light deflection, ensuring that more light is guided in the desired direction, thereby improving efficiency. The array substrate can be used in a variety of applications requiring precise light control, such as AR / VR displays, where precise light direction enhances the visual experience.

[0206] Figures 11A to 11I Methods for manufacturing an array substrate according to some embodiments of the present disclosure are illustrated. (Refer to...) Figure 11A The method includes: forming a first layer L1 on a substrate BS, forming a second layer L2 on the side of the first layer L1 away from the substrate BS, forming a third layer L3 on the side of the second layer L2 away from the substrate BS, forming a first conductive material layer CML1 on the side of the third layer L3 away from the substrate BS, and forming a photoresist layer PR on the side of the first conductive material layer CML1 away from the substrate BS.

[0207] In some embodiments, the first layer L1 and the second layer L2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first layer L1 comprises a p-doped semiconductor material, and the second layer L2 comprises an n-doped semiconductor material. In alternative embodiments, the first layer L1 comprises an n-doped semiconductor material, and the second layer L2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0208] In some embodiments, the third layer L3 includes a stacked structure comprising multiple semiconductor material sublayers, each of which includes one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the multiple quantum well (MQW) layer to emit light.

[0209] In some embodiments, the first conductive material layer CML1 is made of a transparent conductive material such as indium tin oxide.

[0210] In some embodiments, forming the photoresist layer PR includes: nanoprinting a plurality of photoresist pillars on a first conductive material layer CML1.

[0211] Reference Figure 11B In some embodiments, the method includes: patterning a first layer, a second layer, a third layer, and a first conductive material layer using a photoresist layer as a mask to form a fourth layer L4, a fifth layer L5, a sixth layer L6, and a second conductive material layer CML2. After forming the fourth layer L4, the fifth layer L5, the sixth layer L6, and the second conductive material layer CML2, the array substrate includes a plurality of first pillars NP1. Each of the plurality of first pillars NP1 includes a portion of the fourth layer L4, a portion of the fifth layer L5, a portion of the sixth layer L6, and a portion of the second conductive material layer CML2. Optionally, the method further includes: annealing the substrate after the patterning step, and repairing the sidewalls of the plurality of first pillars NP1.

[0212] In some embodiments, the fourth layer L4 and the fifth layer L5 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the fourth layer L4 comprises a p-doped semiconductor material, and the fifth layer L5 comprises an n-doped semiconductor material. In alternative embodiments, the fourth layer L4 comprises an n-doped semiconductor material, and the fifth layer L5 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0213] In some embodiments, the sixth layer L6 includes a stacked structure comprising multiple semiconductor material sublayers, each of which includes one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the multiple quantum well (MQW) layer to emit light.

[0214] In some embodiments, the second conductive material layer CML2 is made of a transparent conductive material such as indium tin oxide.

[0215] Reference Figure 11C In some embodiments, the method further includes forming a barrier material layer BRML. The barrier material layer BRML fills the space between adjacent first posts of a plurality of first posts NP1. The barrier material layer BRML comprises an insulating material.

[0216] Reference Figure 11D In some embodiments, the method further includes: depositing a conductive material on the second conductive material layer and the barrier material layer to form a third conductive material layer CML3; and depositing an electrode material on the side of the third conductive material layer CML3 away from the substrate BS to form an electrode material layer EML.

[0217] Reference Figure 11E In some embodiments, the method further includes: providing a backplane BP comprising a plurality of thin-film transistor TFTs, providing a bonding material layer BML to bond light-emitting elements to the thin-film transistor TFTs via contact electrodes CE, and removing the substrate BS from the fourth layer L4.

[0218] Reference Figure 11FIn some embodiments, the method further includes etching a fourth layer L4, a barrier material layer BRML, a fifth layer L5, a sixth layer L6, a third conductive material layer CML3, an electrode material layer EML, and a barrier material layer BML, thereby forming a second semiconductor material layer SML2, a barrier layer BML, a multiple quantum well layer MQW, a first semiconductor material layer SML1, a first conductive layer CL1, a first electrode layer E1, and a bonding layer BL.

[0219] In some embodiments, the first semiconductor material layer SML1 and the second semiconductor material layer SML2 comprise two different materials selected from p-doped semiconductor materials and n-doped semiconductor materials. In some embodiments, the first semiconductor material layer SML1 comprises a p-doped semiconductor material, and the second semiconductor material layer SML2 comprises an n-doped semiconductor material. In alternative embodiments, the first semiconductor material layer SML1 comprises an n-doped semiconductor material, and the second semiconductor material layer SML2 comprises a p-doped semiconductor material. Examples of suitable p-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with holes. Specific examples of p-doped semiconductor materials include p-doped gallium nitride and p-doped gallium phosphide. Examples of suitable n-doped semiconductor materials include one or more of group III, group IV, and group V semiconductor elements doped with electrons. Specific examples of n-doped semiconductor materials include n-doped gallium nitride and n-doped gallium phosphide.

[0220] In some embodiments, the multiple quantum well layer (MQW) includes a stacked structure comprising multiple semiconductor material sublayers, each of which comprises one or more of group III, group IV, and group V semiconductor elements, such as indium gallium nitride or aluminum indium gallium phosphide. Electrons and holes recombine in the MQW to emit light.

[0221] In some embodiments, the first electrode layer E1 and the bonding layer BL are made of a metallic material.

[0222] In some embodiments, the first conductive layer CL1 is made of a transparent conductive material such as indium tin oxide.

[0223] Reference Figure 11G In some embodiments, the method further includes: forming an insulating layer IN that exposes a portion of a second semiconductor material layer SML2; and forming a second conductive layer CL2 on the side of the insulating layer IN away from the backplane BP, the second conductive layer CL2 being connected to the second semiconductor material layer SML2.

[0224] Reference Figure 11HIn some embodiments, the method further includes: forming a planarization layer PLN on the side of the second conductive layer CL2 away from the backplane BP, forming a lens material layer LML on the side of the planarization layer PLN away from the backplane BP, and forming a lens template TPL on the side of the lens material layer LML away from the backplane BP.

[0225] In some embodiments, forming a lens template TPL includes: nanoprinting a template material on a lens material layer LML, and performing a hot-melt process on the template material to form the lens template TPL.

[0226] In some embodiments, the method further includes: using a lens template TPL as a mask to etch a lens material layer LML, thereby forming a plurality of lenses. Figure 11I The text indicates the corresponding lens LEN among multiple lenses.

[0227] Figure 12 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 12 In some embodiments, the display device includes a plurality of display panels and an X-prism XP. Each of the plurality of display panels DP includes the array substrate described herein. In some embodiments, the X-prism XP is configured to combine light beams from the plurality of display panels. In some embodiments, the plurality of display panels are configured to emit light of different colors. In one example, a first display panel is configured to emit red light, a second display panel is configured to emit green light, and a third display panel is configured to emit blue light. The X-prism XP is configured to combine light of different colors emitted from the plurality of display panels to produce a panchromatic image.

[0228] An X-prism (XP) is a specially designed optical element for combining light beams from different light sources. It has a unique structure that allows it to efficiently guide and combine light. In one example, the surface of the X-prism (XP) can be coated with a bandpass filter for a specific color to enhance the transmission of the desired wavelength while minimizing loss. In another example, each facet of the X-prism can be coated with a bandpass filter corresponding to the color emitted by the display panel. These coatings allow only specific wavelengths to pass through, thereby improving transmission efficiency and color purity. Light from each display panel enters the X-prism (XP) and is guided by internal reflection and the bandpass coating to combine into a single beam. The combined beam includes all color information from the individual displays, thus producing a panchromatic image directed towards the observer (VE). Using an X-prism (XP) with a bandpass coating ensures high luminous efficacy. The coating enhances the transmission of the desired light while minimizing losses due to reflection or absorption. The display device according to this disclosure is easy to implement and provides high luminous efficacy, making it suitable for applications requiring bright, full-color displays.

[0229] Figure 13This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 13 In some embodiments, the array substrate includes a stacked structure comprising a plurality of light-emitting elements. Each of the plurality of light-emitting elements... Figure 13 The image is denoted as LE. In some embodiments, the orthographic projections of the plurality of light-emitting elements on the backplane BP overlap at least partially with each other. Optionally, the orthographic projections of the plurality of light-emitting elements on the backplane BP overlap at least substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with each other.

[0230] In some embodiments, the array substrate further includes a plurality of first vias V1. The array substrate includes a backplane BP, and one or more first electrode layers of a plurality of light-emitting elements are electrically connected to the backplane BP through the plurality of first vias V1. For example, the first electrode layer of a first light-emitting element is electrically connected to the backplane BP through a first relay electrode RE1, which extends through a first first via of the plurality of first vias V1 to reach the backplane BP. In another example, the first electrode layer of a second light-emitting element is electrically connected to the backplane BP through a second relay electrode RE2, which extends through a second first via V1 of the plurality of first vias to reach the backplane BP. In some embodiments, the array substrate further includes a plurality of second vias V2. The second electrode layers of the plurality of light-emitting elements are electrically connected to each other through the plurality of second vias V2. In one example, the second electrode layers of the plurality of light-emitting elements are electrically connected to each other through a third relay electrode RE3 extending through the plurality of second vias V2. In some embodiments, the array substrate further includes a plurality of lenses configured to converge light emitted from the plurality of light-emitting elements. The respective lenses of the plurality of lenses in... Figure 13 The Chinese character is represented as LEN.

[0231] In some embodiments, multiple light-emitting elements are configured to emit light of different colors. In one example, a first light-emitting element is configured to emit red light, a second light-emitting element is configured to emit green light, and a third light-emitting element is configured to emit blue light. The different colors of light emitted from the multiple light-emitting elements are combined and converged through corresponding lenses (LENs).

[0232] The vertically stacked light-emitting elements according to this disclosure allow for the integration of various light-emitting elements that emit different colors of light within a compact structure. Each light-emitting element in the stack is responsible for emitting a specific color, and when combined, they produce a full-color output. This results in a highly integrated structure that significantly reduces the overall size and weight of the display system. The compact structure also allows for smaller pixel sizes, thereby improving the resolution and image quality of the display.

[0233] Figure 14This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 14 In some embodiments, the array substrate includes a plurality of light-emitting elements. A corresponding light-emitting element among the plurality of light-emitting elements... Figure 14 The symbol is LE. In some embodiments, the orthographic projections of the multiple light-emitting elements on the backplane BP do not overlap with each other.

[0234] In some embodiments, multiple light-emitting elements are configured to emit light of the same color, such as blue. In some embodiments, the array substrate further includes a color conversion layer configured to convert the color of light emitted from at least one light-emitting element into a different color (e.g., red or green). Optionally, the array substrate further includes a transparent layer through which light emitted from at least one light-emitting element passes without color conversion.

[0235] In some embodiments, the array substrate further includes a light-shielding layer LS located in the region between adjacent light-emitting elements.

[0236] In some embodiments, the array substrate further includes a color filter CF and a black matrix located on the side of the color conversion layer CCL and the transparent layer TL away from the backplane BP.

[0237] Figures 15A to 15B Methods for manufacturing an array substrate according to some embodiments of the present disclosure are illustrated. (Refer to...) Figure 15A A backplane (BP) is provided, and a bonding layer (BL) is formed on the backplane (BP). The bonding layer (BL) comprises multiple bond blocks (BB) spaced apart from each other.

[0238] Reference Figure 15B A light-emitting substrate (LES) is provided, and the LES is bonded to a backplane (BP) via multiple bonding blocks (BBs). In the regions where the LES is bonded to the multiple bonding blocks (BBs), the LES is configured to emit light. In the regions where the LES is not bonded to the multiple bonding blocks (BBs), the LES is not configured to emit light.

[0239] Multiple columns can have a variety of suitable shapes. Figure 16 This is a schematic diagram illustrating the structure of a plurality of columns according to some embodiments of the present disclosure. (Refer to...) Figure 16 In some embodiments, each pillar in the plurality of pillars NP has a hexagonal prism shape. Figure 17 This is a schematic diagram illustrating the structure of a plurality of columns according to some embodiments of the present disclosure. (Refer to...) Figure 17 In some embodiments, each of the multiple pillars NP has a cylindrical shape.

[0240] Figure 18 This is a schematic diagram illustrating the structure of a plurality of columns according to some embodiments of the present disclosure. (Refer to...) Figure 18In some embodiments, multiple pillars (NPs) form a one-dimensional nanowire grating that emits polarized light. This makes them suitable for polarized AR / VR optical systems, such as the Pancake optical system. This configuration can double the light efficiency.

[0241] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is a miniature light-emitting diode display device.

[0242] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a first conductive layer; forming a barrier layer on the first conductive layer; forming a first semiconductor material layer on the first conductive layer; forming a multiple quantum well layer on the side of the first semiconductor material layer SML1 away from the first conductive layer; and forming a second semiconductor material layer on the side of the barrier layer and the multiple quantum well layer away from the first semiconductor material layer. Optionally, the method includes: forming a plurality of pillars spaced apart from each other by the barrier layer.

[0243] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A light-emitting element, comprising: First conductive layer; A barrier layer is located on the first conductive layer; and Multiple columns, which are spaced apart from each other by the barrier layer; Each of the plurality of columns includes: A first semiconductor material layer is located on the first conductive layer; A multiple quantum well layer, located on the side of the first semiconductor material layer away from the first conductive layer; and A second semiconductor material layer is located on the side of the barrier layer and the multiple quantum well layer away from the first semiconductor material layer; The light emission angle of the light-emitting element is within ±20 degrees.

2. The light-emitting element according to claim 1, in, The light-emitting element further includes an insulating layer that forms a tube configured to accommodate the plurality of pillars; The inner wall of the insulating layer is in contact with the second semiconductor material layer.

3. The light-emitting element according to claim 2 further includes a second conductive layer located on the side of the insulating layer and the second semiconductor material layer away from the first conductive layer.

4. The light-emitting element according to claim 3, wherein, The first conductive layer, the second conductive layer, and the insulating layer encapsulate the plurality of pillars.

5. The light-emitting element according to claim 1, further comprising: Back panel; A bonding layer located on the backplate; as well as The first electrode layer is located on the side of the bonding layer away from the backplate; Wherein, the first electrode layer is connected to the first conductive layer; and The first electrode layer is bonded to the backplate via the bonding layer.

6. The light-emitting element according to claim 5, further comprising: The second electrode layer is located on the side of the bonding layer away from the backplate; as well as An insulating layer is located on the side of the first electrode layer and the second electrode layer away from the bonding layer; The bonding layer includes a first bonding block and a second bonding block spaced apart from each other. The first electrode layer is bonded to the backplate via the first bonding block; The second electrode layer is bonded to the backplate via the second bonding block; and The second electrode layer is connected to the second semiconductor material layer through a via extending through the insulating layer.

7. The light-emitting element according to any one of claims 1 to 6, further comprising a lens; in, The orthogonal projection of the lens onto the substrate substantially covers the orthogonal projection of the plurality of pillars onto the substrate.

8. The light-emitting element according to claim 7, wherein, The lens is a biconvex lens.

9. The light-emitting element according to claim 7, wherein, The lens has a first central optical axis; The light-emitting element has a second central optical axis; and The first central optical axis and the second central optical axis do not overlap.

10. The light-emitting element according to claim 7, wherein, The lens is a diffractive converging lens.

11. The light-emitting element according to any one of claims 1 to 6, further comprising: A first distributed Bragg reflector layer is located on the side of the first conductive layer away from the first semiconductor material layer; as well as The second distributed Bragg reflector layer is located on the side of the second semiconductor material layer away from the multi-quantum well layer; Wherein, the orthogonal projection of the first distributed Bragg reflector layer on the substrate substantially covers the orthogonal projection of the plurality of pillars on the substrate; as well as The orthographic projection of the second distributed Bragg reflector layer on the substrate substantially covers the orthographic projection of the plurality of pillars on the substrate.

12. The light-emitting element according to any one of claims 1 to 6, further comprising a reflective sidewall configured to converge light emitted from the plurality of pillars in the light-emitting element; in, The orthographic projection of the reflective sidewalls onto the substrate substantially surrounds the orthographic projection of the plurality of pillars in the light-emitting element onto the substrate.

13. The light-emitting element according to claim 12, further comprising: The second conductive layer is located on the side of the second semiconductor material layer away from the first semiconductor material layer, and the reflective sidewall is located on the side of the second conductive layer away from the substrate. as well as A planarization layer is located on the side of the second conductive layer away from the substrate. The planarization layer fills the gap between the second conductive layer and the reflective sidewall.

14. The light-emitting element according to any one of claims 1 to 6, further comprising: First lens; as well as Second lens; Wherein, the orthogonal projection of the first lens onto the substrate substantially covers the orthogonal projection of the plurality of pillars onto the substrate; The orthogonal projection of the second lens onto the substrate substantially covers the orthogonal projection of the plurality of pillars onto the substrate; The first lens is located on the side of the second semiconductor material layer away from the first conductive layer; The second lens is located on the side of the first lens that is away from the first conductive layer; The first lens is a biconvex lens; and The second lens is a diffraction deflector lens.

15. The light-emitting element according to any one of claims 1 to 6, wherein, The widths of the plurality of pillars decrease sequentially along a first direction, wherein the first direction is along a plane that intersects the barrier layer, the first semiconductor material layer, the multiple quantum well layer and the second semiconductor material layer and is perpendicular to the surface of the first conductive layer.

16. An array substrate, comprising: A stacked structure comprising a plurality of light-emitting elements, wherein the plurality of light-emitting elements comprises the light-emitting elements according to any one of claims 1 to 15; Multiple first vias; Multiple second vias; and Back panel; Wherein, the orthographic projections of the plurality of light-emitting elements on the back plate at least partially overlap each other; One or more first electrode layers of the plurality of light-emitting elements are electrically connected to the backplate through the plurality of first vias; and The second electrode layers of the plurality of light-emitting elements are electrically connected to each other through the plurality of second vias.

17. An array substrate, comprising: A plurality of light-emitting elements, wherein the plurality of light-emitting elements includes the light-emitting element according to any one of claims 1 to 15; A color conversion layer is configured to convert the color of light emitted from at least one light-emitting element into different colors; A transparent layer through which light emitted from at least one light-emitting element passes without color conversion; Wherein, the orthographic projections of the plurality of light-emitting elements on the substrate do not overlap with each other; and The plurality of light-emitting elements are configured to emit light of the same color.

18. A display device comprising a light-emitting element according to any one of claims 1 to 15, and one or more integrated circuits.

19. The display device of claim 18, comprising a plurality of display panels configured to emit light of different colors respectively, and an X-prism configured to combine light beams from the plurality of display panels; in, Each of the plurality of display panels includes a light-emitting element according to any one of claims 1 to 15.

20. A method for manufacturing a light-emitting element, comprising: Form the first conductive layer; A barrier layer is formed on the first conductive layer; Multiple pillars are formed that are spaced apart from each other by the barrier layer; Each of the plurality of columns comprises: A first semiconductor material layer is formed on the first conductive layer; A multi-quantum-well layer is formed on the side of the first semiconductor material layer away from the first conductive layer; and A second semiconductor material layer is formed on the side of the barrier layer and the multiple quantum well layer away from the first semiconductor material layer; The light emission angle of the light-emitting element is within ±20 degrees.

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