Dicing wafer manufacturing method

Abstract

The invention provides a manufacturing method for cutting a wafer, and the wafer is provided with a plurality of crystal grains with non-vertical inner angles. The manufacturing method comprises the following steps that firstly, a plurality of crystal grains on a wafer are arranged, so that the edges of the crystal grains are aligned with one another and arranged into a straight line, and a separation area is formed between every two adjacent crystal grains in a surrounding mode; secondly, a plurality of calibration objects are arranged in the partition areas respectively; then, after each calibration object is positioned by the initial image, the wafer is linearly cut along the mutually aligned edges of each crystal grain. And after the wafer is rotated by an angle and each calibration object is subjected to image positioning, linearly cutting the wafer along the aligned and uncut edges of each crystal grain. And finally, repeating the previous step until all the edges of all the crystal grains are linearly cut.

Description

Technical Field

[0001] This invention relates to a method for manufacturing wafers, specifically, a method for manufacturing wafers into non-rectangular granules. Background Technology

[0002] A photosensitive chip is a photoelectric conversion component that generates a change in current or voltage when light shines on it. Photosensitive chips are widely used in various optical instruments such as optical communication, photoelectric detection, automatic brightness adjustment, spectral analysis, photosensitive circuits, photodetectors, and cameras. They are typically used to detect light intensity, measure spectra, or detect light signals. Figure 1 As shown, Figure 1 The image shows a wafer being linearly cut using a dicing saw, resulting in a common rectangular wafer shape. However, when this type of rectangular wafer is used in the photosensitive modules of recently popular wearable devices, it fails to meet the requirement of maximizing the area of ​​the sensor. Therefore, to meet the requirement of maximizing the area of ​​the photosensitive wafer, various wafer shapes have begun to be developed, such as... Figure 2 As shown, the most common type is the hexagonal grain.

[0003] Figure 2 The diagram illustrates the layout of hexagonal-shaped dies on wafer 1 in the prior art. The die 10 layout shown is a densest layout, which maximizes the usable wafer area. However, because the hexagonal die outlines cannot form a long straight line, the wafer cannot be used as described above after the die 10 growth process is completed. Figure 1 The traditional low-cost dicing method shown cannot perform wafer dicing using conventional cleaving processes, even after laser dicing. Instead, dicing can only be done using plasma etching. However, plasma etching of wafers with thicknesses of 100 micrometers (μm) to 300 micrometers (μm) presents disadvantages such as high cost, time consumption, and low yield, all of which urgently need improvement. Summary of the Invention

[0004] The main objective of this invention is to provide an innovative method for manufacturing wafers, particularly suitable for dicing non-rectangular dies on wafers. This method not only allows for the introduction of traditional linear dicing processes but also ensures consistent image recognition from different angles by placing calibration objects in the separation areas between the dies on the wafer. This improves the image positioning accuracy of the wafer dicing equipment and ensures the correctness of angle judgment by different dicing devices, thereby increasing the accuracy of wafer dicing.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a wafer dicing process, wherein the wafer has a plurality of dies with non-perpendicular interior angles. The manufacturing method includes the following steps: First, arranging the plurality of dies on the wafer such that the edges of each die are aligned with each other in a straight line, wherein a separation region surrounds adjacent dies. Second, placing a plurality of markers in each of the separation regions. Next, after initial image positioning of each marker, cutting the wafer in a straight line along the aligned edges of each die. After rotating the wafer by an angle and image positioning of each marker, cutting the wafer in a straight line along the aligned but uncut edges of each die. Finally, repeating the previous steps until all edges of each die are cut in a straight line.

[0006] In an embodiment of the wafer dicing manufacturing method of the present invention, when each grain is a grain with an interior angle of 120°, the edges of the multiple grains on the wafer are aligned and arranged into multiple first slope lines, multiple second slope lines and multiple third slope lines.

[0007] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of locating each marker in the initial image includes: after locating each first slope line to be in a horizontal state, cutting each first slope line on the wafer in a straight line.

[0008] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of rotating the wafer by an angle and positioning each calibration object includes: rotating the wafer by 60°, positioning each second slope line in a horizontal state, and then cutting each second slope line on the wafer in a straight line; and rotating the wafer by 60° again, positioning each third slope line in a horizontal state, and then cutting each third slope line on the wafer in a straight line.

[0009] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of straight-line wafer dicing includes dicing with a dicing blade.

[0010] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of setting multiple markers in each of the respective separation regions includes forming each marker in each of the respective separation regions by an exposure and development process.

[0011] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of arranging a plurality of grains on the wafer such that a separation region is formed between adjacent grains includes arranging a plurality of grains on the wafer such that a triangular region is formed between adjacent grains.

[0012] To achieve the above objectives, the present invention provides a method for manufacturing a wafer dicing process. The wafer has a plurality of hexagonal grains. The manufacturing method includes: arranging the plurality of hexagonal grains on the wafer such that the edges of each hexagonal grain are aligned to form a plurality of first slope lines, a plurality of second slope lines, and a plurality of third slope lines, wherein a separation region surrounds adjacent hexagonal grains, and the area of ​​the separation region is smaller than the area of ​​the hexagonal grain; setting a plurality of markers in each of the separation regions; initially image-positioning each marker to position the plurality of first slope lines horizontally, and then dicing the wafer along each of the first slope lines; rotating the wafer by 60° and image-positioning each marker to position the plurality of second slope lines horizontally, and then dicing the wafer along each of the second slope lines; and rotating the wafer by 60° and image-positioning each marker to position the plurality of third slope lines horizontally, and then dicing the wafer along each of the third slope lines.

[0013] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of straight-line wafer dicing includes dicing with a dicing blade.

[0014] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of setting multiple markers in each of the respective separation regions includes forming each marker in each of the respective separation regions by an exposure and development process.

[0015] In an embodiment of the wafer dicing manufacturing method of the present invention, the step of arranging a plurality of hexagonal grains on the wafer such that a separation region is formed between adjacent hexagonal grains includes arranging a plurality of hexagonal grains on the wafer such that a triangular region is formed between adjacent hexagonal grains.

[0016] Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0017] Figure 1 This is a top view of a traditional wafer layout with rectangular grains. Figure 2 This is a top view of a traditional wafer layout with hexagonal grains. Figure 3 This is a top view schematic diagram of the wafer layout of hexagonal grains in an embodiment of the present invention; Figure 4 for Figure 3 A partially enlarged schematic diagram; Figures 5A to 5C for Figure 4 Enlarged schematic diagrams of parts rotated at different angles; Figure 6This is a top view schematic diagram of the wafer layout of hexagonal grains in another embodiment of the present invention; Figures 7A to 7C for Figure 6 Enlarged schematic diagrams at different rotation angles; and Figure 8 This is a schematic diagram of the wafer cutting process of the present invention. Detailed Implementation

[0018] The following embodiments will explain the content of the present invention. These embodiments are not intended to limit the implementation of the invention to any specific environment, application, or special method as described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and drawings, elements not directly related to the present invention have been omitted and not drawn, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0019] Please refer to Figure 3 , Figure 3 A top view of wafer 50 is shown. Wafer 50 has multiple photosensitive grains before dicing, wherein adjacent grains 20 are surrounded by a separating region 30, the area of ​​which is smaller than the area of ​​each grain 20. In terms of grain appearance, grain 20 is a hexagonal grain with non-perpendicular interior angles; more precisely, grain 20 has 120° interior angles, and the separating region 30 surrounded by the hexagonal grains is a triangular region. Furthermore, as... Figure 4 The enlarged schematic diagram shown shows that two electrodes 22 are provided at the upper edge of each grain 20, which serve as the contact points for the positive and negative electrodes. Figure 3 Although the arrangement of the grains 20 on the wafer 50 shown is not the densest grain arrangement, its characteristic is that the six sides of each hexagonal grain are aligned with each other to form multiple straight lines, facilitating subsequent straight-line dicing of the wafer with a dicing blade. These straight lines are classified according to their slope and can be divided into three categories: first slope line L1, second slope line L2, and third slope line L3. Specifically, as... Figure 3 As shown, the slope of the first slope line L1 is 0, and the slope of the second slope line L2 is... The slope of the third slope line L3 is - .

[0020] Figure 3The illustrated grain arrangement allows the edges of each grain to be connected into long straight lines, facilitating straight-line cutting on the wafer by the dicing blade and reducing the process costs required for laser or plasma cutting. It should be noted that before dicing the wafer, the cutting equipment must use image positioning to identify the orientation of the grain edges. Cutting can only proceed after the image confirms the grain edge orientation is correct, to avoid incorrect cutting and resulting in cutting failure and grain damage. Please continue to refer to... Figure 4 , Figures 5A to 5C When using image positioning to locate the edge of a grain, one of the two electrodes 22 of the grain 20 can be used as a reference positioning point, such as... Figure 4 As shown in the box.

[0021] Specifically, during initial image positioning, one of the electrodes 22 of the die 20 is selected as the positioning reference point. After the image confirms that the die edge orientation is correct, horizontal straight-line cutting is performed. That is, when the image positioning is correct, the first slope line L1 is in a horizontal state with a slope of 0, and the cutting equipment can perform straight-line cutting. The aligned and connected edges of each die 20 on the wafer 50 are then cut in a straight line to form the edges of the first slope line L1. Figure 5A As shown. Next, the entire wafer 50 is rotated by an angle, for example, 60°, so that the slope of the second slope line L2 changes from its original value. After the image is positioned horizontally and the positioning is confirmed to be correct, the wafer is cut again using a cutting device in a straight line. The edges of the cut wafer 50 are aligned and connected to form the edges of the second slope straight line L2, as shown. Figure 5B As shown. Similarly, the wafer is rotated 60° again so that the third slope line L3 is horizontal after the second rotation. After the image positioning and recognition are correct, the wafer is cut into straight sections again using the dicing equipment. The diced wafer 50 is aligned and connected to form the edges of the third slope line L3, as shown. Figure 5C As shown.

[0022] While the aforementioned wafer dicing method overcomes the drawback of traditional methods requiring laser or plasma cutting for non-rectangular dies on wafers, the method of using one electrode on the die as a positioning reference point for image recognition still carries the possibility of image recognition failure. Specifically, as... Figures 5A to 5C As shown, when the calibration electrode 22 is used as a positioning reference point, when the wafer is rotated at three different angles of 0°, 60° and 120°, the orientation of each grain 20 on the wafer 50 will change accordingly. Such orientation differences will cause difficulties in image recognition. That is, the grain will produce three different images at three different orientations, causing confusion in the grayscale values ​​of image recognition, which in turn leads to misidentification and affects the accuracy of wafer cutting.

[0023] In view of this, please refer to Figure 6 , Figure 6This invention illustrates a method for dicing a wafer in a preferred embodiment. In this preferred embodiment, a marker 40 is provided in the separation region 30 between adjacent dies 20 on the wafer 50 to assist in image positioning and identification during wafer dicing. The marker 40 is formed in each separation region 30 during the wafer fabrication process using an exposure and development process. Specifically, please refer to… Figure 6 Since the center of the separation region 30 between each adjacent die 20 has a marker 40 that can serve as a positioning reference point for image recognition, when performing a wafer dicing process similar to the one described above, the image recognition images at various angles will be substantially consistent. This avoids the drawback of grayscale value confusion and difficulty in recognition in the aforementioned image recognition, thus improving the recognition accuracy of image positioning. It can also increase the accuracy of wafer rotation angle recognition in image recognition, thereby improving the accuracy of wafer dicing.

[0024] Specifically, similar to the aforementioned process, during initial image positioning, a calibrator 40 between the dies 20 is selected as a positioning reference point. After confirming the correct orientation of the die edges in the image, a horizontal straight line cut is performed. That is, the first slope line L1 at this point is horizontal with a slope of 0. The edges of each die 20 are aligned and connected on the wafer 50 to form the first slope line L1. Figure 7A As shown. Next, the entire wafer is rotated 60° to make the second slope line L2 horizontal. After the image positioning and recognition are correct, the wafer is cut again in a straight line using a dicing device. The edges of the cut wafer 50 are then aligned and connected to form the edges of the second slope line L2, as shown. Figure 7B As shown. Similarly, the wafer is rotated 60° again so that the third slope line L3 is horizontal after the second rotation. After the image positioning and recognition are correct, the wafer is cut into straight sections again using the dicing equipment. The diced wafer 50 is aligned and connected to form the edges of the third slope line L3, as shown. Figure 7C As shown. After three cuts, the edges of each die 20 on the wafer 50 can be smoothly cut in a straight line by the dicing blade. Subsequently, the non-rectangular die can be easily separated using the conventional wafer cleaving method. Moreover, the aforementioned example of a hexagonal die is only to illustrate the function of the wafer cutting manufacturing method of the present invention, and is not intended to limit the present invention to the manufacturing method of cutting hexagonal dies. In fact, the present invention can also be applied to the cutting of other shaped dies (e.g., parallelogram or octagonal dies).

[0025] Please refer to Figure 8 , Figure 8This diagram illustrates the wafer dicing process of the present invention. First, in step S01, multiple dies on the wafer are arranged so that the edges of each die are aligned in a straight line. Separating regions surround adjacent dies, and the area of ​​each separating region is smaller than the area of ​​each die. In step S02, markers are placed in each separating region. Next, in step S03, after initial image positioning of the markers, the wafer is linearly diced along the edges where the dies are aligned in a straight line. In step S04, the wafer is rotated by an angle, and after image positioning of the markers, the wafer is linearly diced along the edges where the dies are aligned in a straight line but have not yet been diced. Finally, in step S05, the previous steps are repeated until all edges of each die are linearly diced. The descriptions of related components in the aforementioned process steps are as described above and will not be repeated.

[0026] The above embodiments are merely illustrative of the present invention and to explain its technical features, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims.

[0027] [Symbol Explanation] 1 wafer 10 grains 20 grains 22 electrodes 30-section area 40 calibration materials 50 wafers L1 First slope line L2 second slope line L3 is the third slope line.

Claims

1. A method for manufacturing a wafer, the wafer having a plurality of grains with non-perpendicular interior angles, the manufacturing method comprising: The plurality of grains on the wafer are arranged such that the edges of each grain are aligned in a straight line, wherein a separation region surrounds adjacent grains and the area of ​​the separation region is smaller than the area of ​​the grain; Multiple calibration objects are set in each of the separate areas; After locating each marker using the initial image, the wafer is cut in a straight line along the edge where each grain is arranged in a straight line. After rotating the wafer by an angle and positioning the various markers using image positioning, the wafer is then linearly cut along the edge where the individual grains are arranged in a straight line and have not yet been cut; and Repeat the previous step until all the edges of each grain are cut with straight lines.

2. The wafer dicing manufacturing method as described in claim 1, wherein, When each grain is a grain with an interior angle of 120°, the edges of the plurality of grains on the wafer are aligned to form a plurality of first slope lines, a plurality of second slope lines, and a plurality of third slope lines.

3. The wafer dicing manufacturing method as described in claim 2, wherein, The initial image positioning steps for each calibration object include: after positioning each first slope line to be horizontal, cutting each first slope line on the wafer with a straight line.

4. The wafer dicing manufacturing method as described in claim 3, wherein, The steps of rotating the wafer by an angle and positioning the various calibration objects include: After rotating the wafer by 60° and positioning each of the second slope lines to the horizontal position, a straight line is cut across each of the second slope lines on the wafer; and After rotating the wafer by 60° again and positioning each of the third slope lines to be in the horizontal state, the wafer is then cut with a straight line to cut each of the third slope lines.

5. The wafer dicing manufacturing method as described in claim 1, wherein, The step of slicing the wafer in a straight line includes cutting it with a dicing blade.

6. The wafer dicing manufacturing method as described in claim 1, wherein, The step of setting the plurality of calibration objects in each of the separate areas includes forming each calibration object in each of the separate areas by an exposure and development process.

7. The wafer dicing manufacturing method as described in claim 2, wherein, The step of arranging the plurality of grains on the wafer such that adjacent grains surround the separation region includes arranging the plurality of grains on the wafer such that adjacent grains surround a triangular region.

8. A method for manufacturing a wafer, the wafer having a plurality of hexagonal grains, the manufacturing method comprising: The plurality of hexagonal grains on the wafer are arranged such that the edges of each hexagonal grain are aligned and arranged into a plurality of first slope lines, a plurality of second slope lines, and a plurality of third slope lines, wherein a separation region is formed between adjacent hexagonal grains, and the area of ​​the separation region is smaller than the area of ​​the hexagonal grain. Multiple calibration objects are set in each of the separate areas; After locating each of the initial image markers to ensure that the plurality of first slope lines are in a horizontal state, the wafer is cut along each of the first slope lines. After rotating the wafer by 60° and positioning the various markers to align the plurality of second slope lines to the horizontal position, the wafer is then cut along each of the second slope lines; and After rotating the wafer by 60° and positioning each calibration object to ensure that the plurality of third slope lines are in the horizontal state, the wafer is cut along each third slope line.

9. The wafer dicing manufacturing method as described in claim 8, wherein, The step of slicing the wafer in a straight line includes cutting it with a dicing blade.

10. The wafer dicing manufacturing method as described in claim 8, wherein, The step of setting the plurality of calibration objects in each of the separate areas includes forming each calibration object in each of the separate areas by an exposure and development process.

11. The wafer dicing manufacturing method as described in claim 8, wherein, The step of arranging the plurality of hexagonal grains on the wafer such that adjacent hexagonal grains surround the separating region includes arranging the plurality of hexagonal grains on the wafer such that adjacent hexagonal grains surround a triangular region.

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