Fault detection method and system for cryptographic chip

Abstract

The invention belongs to the technical field of integrated circuit design and information security, and particularly relates to a fault detection method and system for a cryptographic chip. The fault detection method for the cryptographic chip comprises the following steps: when the cryptographic chip runs a cryptographic algorithm, injecting a preset test vector into input data of algorithm logic; obtaining an actual output result of the algorithm logic corresponding to the test vector; comparing the actual output result with a pre-calculated expected output result under a fault-free condition; and judging whether the password chip has a fault or not according to a comparison result. The invention also correspondingly provides a system for realizing the method. According to the method, the test vector is actively injected and the output result is compared, so that the calculation error of the cryptographic chip caused by hardware faults, side channel attacks or natural aging and the like can be effectively detected, and the method has the advantages of high detection real-time performance, low hardware overhead, high universality and the like.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and information security technology, and in particular to a fault detection method and system for cryptographic chips. Background Technology

[0002] Cryptographic chips are widely used in smart cards, IoT devices, mobile payment terminals, security controllers and other scenarios, and the correctness and security of their calculations are of paramount importance. However, cryptographic chips may fail during operation due to a variety of reasons, such as: (1) environmental factors: abnormal fluctuations in voltage, temperature and clock signals; (2) natural aging: timing errors caused by transistor aging; (3) malicious attacks: fault injection attacks, which deliberately induce chip calculation errors through laser, electromagnetic, clock glitches and other means to bypass security mechanisms or steal keys.

[0003] These faults can cause cryptographic algorithms to produce incorrect outputs, leading to serious security problems such as key leakage or authentication bypass. Therefore, integrating efficient and reliable fault detection mechanisms within cryptographic chips is particularly important.

[0004] Existing fault detection techniques, such as those based on redundancy computation (dual-mode redundancy, triple-mode redundancy), while reliable, incur significant hardware resource overhead and increased power consumption, making them unsuitable for resource-constrained embedded cryptographic chips. Furthermore, some error detection code-based methods may not be able to cover all types of faults, particularly targeted attacks against specific cryptographic units (such as S-boxes).

[0005] Therefore, this application provides a fault detection method and system for cryptographic chips. Summary of the Invention

[0006] The purpose of this invention is to propose a fault detection method and system for cryptographic chips to address the problems mentioned in the background: existing technologies generally suffer from a trade-off between detection performance and resource overhead; efficient detection schemes often require significant hardware overhead, while low-overhead schemes may lack sufficient detection coverage and real-time performance. Therefore, there is an urgent need in the art for a fault detection scheme that can achieve high coverage and low latency under low overhead conditions.

[0007] To achieve the above objectives, the present invention provides a fault detection method and system for cryptographic chips, including a fault detection method for cryptographic chips comprising the following steps: Step S1: During the cryptographic operation performed by the cryptographic chip, inject at least one set of preset test vectors into the original input data of the cryptographic algorithm logic module. ; Step S2: Transfer the test vector The input is fed into the cryptographic algorithm logic module for computation, and the actual output result is obtained. ; Step S3: Output the actual results Compared to the pre-stored expected correct results corresponding to the test vectors Compare and generate comparison results ; Step S4: Based on the comparison results To determine if the cryptographic chip has a malfunction.

[0008] Preferably, in step S1, the test vector The timing of the injection is controlled by a random or pseudo-random function, defined as follows: ; in, For the injection time, Use a random seed. This is the counter for the current round of computation.

[0009] Preferably, in step S3, the expected correct result is... It is pre-computed by the cryptographic chip in a secure and trusted environment and stored in the read-only memory or one-time programmable memory on the cryptographic chip.

[0010] Preferably, in step S4, the comparison results are... Defined by the following functions: ; when When this occurs, a fault is detected, and a safety response mechanism is triggered; Security response mechanisms include: suspending the current cryptographic operation, clearing sensitive data, outputting an error flag, or resetting the chip.

[0011] A fault detection system for cryptographic chips, implementing a fault detection method for cryptographic chips, the system being integrated within the cryptographic chip, comprising: Test vector injection module: During cryptographic operations, it injects preset test vectors. Selectively compared with the original input data Mix; Cryptographic algorithm logic module: Receive test vector and raw input data Perform cryptographic operations; Expected Result Storage Module: Securely stores test vectors Corresponding expected correct result ; Result Comparison Module: Coupled to the output of the cryptographic algorithm logic module and the expected result storage module, used to compare the actual output results. Correct result as expected Perform a comparison; Fault Judgment and Control Module: Based on the output of the result comparison module, it determines whether a fault has occurred, and controls the execution of safety response operations when a fault occurs.

[0012] Preferably, the test vector injection module includes a multiplexer (MUX), and the output of the multiplexer (MUX) is... By selection signal Control, whose logical relationship satisfies: ; Among them, the selection signal It is generated by a random signal generator or timer.

[0013] Preferably, the result comparison module is a digital comparator, and the digital comparator outputs a comparison result signal. satisfy: ; in, This indicates no fault. This indicates a malfunction.

[0014] Preferably, the expected result storage module is a one-time programmable memory or a read-only memory protected by access control logic, and the expected result storage module stores the expected correct result. Once written during the chip personalization stage, it cannot be tampered with.

[0015] Therefore, the present invention employs the above-described fault detection method and system for cryptographic chips, which has the following advantages: (1) Low overhead: There is no need to make the entire cryptographic algorithm logic completely redundant. Only a small amount of injection, storage and comparison circuits are added, and the hardware overhead is significantly lower than that of traditional redundancy methods. (2) High real-time performance: The detection process is carried out synchronously with the cryptographic operation, which can detect faults in almost real time and respond quickly; (3) Highly targeted: Test vectors can be designed for the most vulnerable and critical computing units, improving the detection coverage of specific faults (especially faults induced by malicious attacks); (4) Good versatility: This method can be applied to various symmetric and asymmetric cryptographic algorithms, and only requires the corresponding test vector and expected results to be adapted.

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Fig. 1 This is a flowchart of the method steps for a fault detection method and system for cryptographic chips mentioned in an embodiment of the present invention; Fig. 2 This is a schematic diagram of the system module structure of a fault detection method and system for cryptographic chips mentioned in an embodiment of the present invention; Fig. 3 This describes the workflow of a fault detection system for a cryptographic chip in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] Example like Figs. 1-3 As shown, the present invention provides a fault detection method and system for cryptographic chips. The fault detection method for cryptographic chips includes the following steps: Step S1: During the cryptographic operation performed by the cryptographic chip, the original input data is sent to the cryptographic algorithm logic module. Inject at least one set of pre-defined test vectors. These test vectors are carefully designed for key operations in cryptographic algorithms (such as nonlinear S-box transformations and column scrambling), and can effectively expose faults in these operational units. Step S2: Transfer the test vector The input is fed into the cryptographic algorithm logic module for computation, and the actual output result is obtained. ; Step S3: Output the actual results Compared to the pre-stored expected correct results corresponding to the test vectors Compare and generate comparison results ; Step S4: Based on the comparison results To determine if the cryptographic chip has a malfunction.

[0021] In step S1, the test vector The timing of the injection is controlled by a random or pseudo-random function, defined as follows: ; in, For the injection time, Use a random seed. This is the counter for the current round of computation.

[0022] In step S3, the expected correct result is... It is pre-computed by the cryptographic chip in a secure and trusted environment and stored in the read-only memory or one-time programmable memory on the cryptographic chip.

[0023] In step S4, the comparison results are... Defined by the following functions: ; when When this occurs, a fault is detected, and a safety response mechanism is triggered; Security response mechanisms include: suspending the current cryptographic operation, clearing sensitive data, outputting an error flag, or resetting the chip.

[0024] A fault detection system for cryptographic chips, implementing a fault detection method for cryptographic chips, the system being integrated within the cryptographic chip, comprising: Test vector injection module: During cryptographic operations, it injects preset test vectors. Selectively compared with the original input data Mix; Cryptographic algorithm logic module: Receive test vector and raw input data Perform cryptographic operations; Expected Result Storage Module: Securely stores test vectors Corresponding expected correct result ; Result Comparison Module: Coupled to the output of the cryptographic algorithm logic module and the expected result storage module, used to compare the actual output results. Correct result as expected Perform a comparison; Fault Judgment and Control Module: Based on the output of the result comparison module, it determines whether a fault has occurred, and controls the execution of safety response operations when a fault occurs.

[0025] The test vector injection module includes a multiplexer (MUX), and the output of the multiplexer (MUX) is... By selection signal Control, whose logical relationship satisfies: ; Among them, the selection signal It is generated by a random signal generator or timer.

[0026] The result comparison module is a digital comparator, and the digital comparator outputs the comparison result signal. satisfy: ; in, This indicates no fault. This indicates a malfunction.

[0027] The expected result storage module is a one-time programmable memory or a read-only memory protected by access control logic. The expected result storage module stores the expected correct results. Once written during the chip personalization stage, it cannot be tampered with.

[0028] A specific implementation process is as follows: like Fig. 3 As shown, this embodiment describes in detail the specific application of the present invention in an AES-128 encryption chip, and the process is as follows: Preparation phase: During the chip design or customization phase, a set of test vectors is designed to fully test the SubBytes (S-box) transformation and MixColumns transformation in the AES algorithm, along with their corresponding expected correct results. These expected results are then stored in a small-capacity OTP (One-Time Programmable) memory within the chip.

[0029] Operation and testing phase: The fault detection system starts working when the chip receives the encryption command and begins processing the data; The control module may generate a control signal during the 5th and 10th rounds (or random rounds) of AES encryption; The signal control test vector injection module (a MUX) inputs the preset test vector (rather than the actual state data of the current round) into the round function of AES for calculation; After logical calculation by the AES algorithm, a 128-bit actual result is output. The result comparison module (a 128-bit comparator) immediately compares the actual result with the expected correct result read from the OTP; If the comparison result is "equal", the fault judgment and control module will not intervene in any way, and AES encryption will continue normally. If the comparison result is "not equal", the control module immediately triggers an emergency security response, which will force the AES state machine to stop working and trigger the clearing of intermediate states and round keys in the register.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A fault detection method for cryptographic chips, characterized in that: Includes the following steps: Step S1: During the cryptographic operation performed by the cryptographic chip, the original input data is sent to the cryptographic algorithm logic module. Inject at least one set of pre-defined test vectors. ; Step S2: Transfer the test vector The input is fed into the cryptographic algorithm logic module for computation, and the actual output result is obtained. ; Step S3: Output the actual results Compared to the pre-stored expected correct results corresponding to the test vectors Compare and generate comparison results ; Step S4: Based on the comparison results To determine if the cryptographic chip has a malfunction.

2. The fault detection method for a cryptographic chip according to claim 1, characterized in that: In step S1, the test vector The timing of the injection is controlled by a random or pseudo-random function, defined as follows: ； in, For the injection time, Use a random seed. This is the counter for the current round of computation.

3. The fault detection method for a cryptographic chip according to claim 1, characterized in that: In step S3, the expected correct result is... It is pre-computed by the cryptographic chip in a secure and trusted environment and stored in the read-only memory or one-time programmable memory on the cryptographic chip.

4. The fault detection method for a cryptographic chip according to claim 1, characterized in that: In step S4, the comparison results are... Defined by the following functions: ； when When this occurs, a fault is detected, and a safety response mechanism is triggered; Security response mechanisms include: suspending the current cryptographic operation, clearing sensitive data, outputting an error flag, or resetting the chip.

5. A fault detection system for cryptographic chips, implementing the fault detection method for cryptographic chips according to any one of claims 1-4, characterized in that: The system is integrated within the cryptographic chip, including: Test vector injection module: During cryptographic operations, it injects preset test vectors. Selectively compared with the original input data Mix; Cryptographic algorithm logic module: Receive test vector and raw input data Perform cryptographic operations; Expected Result Storage Module: Securely stores test vectors Corresponding expected correct result ; Result Comparison Module: Coupled to the output of the cryptographic algorithm logic module and the expected result storage module, used to compare the actual output results. Correct result as expected Perform a comparison; Fault Judgment and Control Module: Based on the output of the result comparison module, it determines whether a fault has occurred, and controls the execution of safety response operations when a fault occurs.

6. A fault detection system for a cryptographic chip according to claim 5, characterized in that: The test vector injection module includes a multiplexer (MUX), and the output of the multiplexer (MUX) is... By selection signal Control, whose logical relationship satisfies: ； Among them, the selection signal It is generated by a random signal generator or timer.

7. A fault detection system for a cryptographic chip according to claim 5, characterized in that: The result comparison module is a digital comparator, and the digital comparator outputs the comparison result signal. satisfy: ； in, This indicates no fault. This indicates a malfunction.

8. A fault detection system for a cryptographic chip according to claim 5, characterized in that: The expected result storage module is a one-time programmable memory or a read-only memory protected by access control logic. The expected result storage module stores the expected correct results. Once written during the chip personalization stage, it cannot be tampered with.

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