Warping simulation finite element model analysis method

Abstract

The invention provides a warping simulation finite element model analysis method, which realizes improvement of simulation efficiency under the condition of ensuring the accuracy of a warping simulation result. The method is characterized by comprising the following steps of: performing equivalent simplification reconstruction on positions, areas and mentions of lines and through holes of a metal structure of a single chip unit model; and then reconstruction and simulation of the panel-level model are carried out.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit packaging, specifically to a warpage simulation finite element model analysis method. Background Technology

[0002] With the rapid development of integrated circuit technology, fan-out semiconductor devices have become the core of the industry due to their high integration, small size and excellent electrothermal performance. These packaging structures are usually composed of multiple materials such as metals (e.g., copper) and dielectrics (e.g., EMC, PI, dry film). There is a huge mismatch in the coefficient of thermal expansion (CTE) between the materials. During packaging manufacturing and use, the thermal stress generated by drastic temperature changes causes the structure to warp.

[0003] Accurate warpage simulation can predict the degree of warpage under different design schemes before manufacturing, helping engineers optimize material selection, structural dimensions, and process flow in advance. This avoids design iterations and mass production delays caused by warpage issues, making it an indispensable part of the design phase. Current technology, in simulation analysis, typically employs the finite element method based on refined geometric models to accurately predict warpage. This involves precisely establishing geometric models of metal traces, copper foil, and dielectric materials based on design layout data, generating extremely fine finite element meshes.

[0004] However, this existing refined modeling method has significant drawbacks: 1. Large model size: The intricate wiring and copper pattern result in a huge number of model nodes and elements; Second, high computational cost: The large model consumes a lot of memory and computation time; Third, low modeling efficiency: The process from design files to generating a finite element model that can be used for calculation is cumbersome and prone to errors.

[0005] Therefore, there is an urgent need for an innovative solution that can significantly improve the efficiency of package warpage simulation while ensuring engineering accuracy. Summary of the Invention

[0006] To address the aforementioned problems, this invention provides a finite element model analysis method for warpage simulation, which improves simulation efficiency while ensuring the accuracy of warpage simulation results.

[0007] A warp simulation finite element model analysis method is characterized by first performing equivalent simplification and reconstruction of the position, area, and height of the circuits and vias of the metal structure of a single chip unit model; then performing reconstruction and simulation of the panel-level model.

[0008] Its further features are A single chip cell includes a fan-out package and a substrate. The steps for equivalent simplified reconstruction of a single chip cell model are as follows: S1 flip-chips the fan-out package onto the substrate to form a circuit connection; S2 identifies areas of trace fan-out and interconnect vias using layout data; S3 performs routing reconstruction; S4 performs interconnect reconfiguration.

[0009] The reconstruction and simulation of the panel-level model is step S5. After completing the reconstruction of all traces and vias of a single chip unit, the simplified unit model is arrayed and copied on the panel to construct a complete panel-level simulation model and calculate the warping deformation of the entire structure.

[0010] Its further characteristic is: In step S1, a pre-fabricated single fan-out integrated circuit chip is flip-chipped onto a substrate. The circuit is connected by having the active side of the integrated circuit chip face down and the solder joints directly connected to the substrate. In step S2, the areas of trace fan-out and interconnect vias are identified from the substrate stack-up design using layout data; In step S3, the chip is divided into multiple 45° sector areas around each edge. In each sector, divergent power, ground, or signal traces are identified. N traces with roughly the same direction and adjacent to each other are grouped into an equivalent trace. The cross-sectional area of ​​the equivalent trace is equal to the total cross-sectional area of ​​the original group of traces. The equivalent trace is placed on the geometric center line of the original trace group. The value of N ranges from 2 to 5; In step S4, within the fan-out region, M interconnects that are connected to the same pair of wiring layers and are adjacent on the plane are identified and grouped into a group to create an equivalent reconstruction unit. The volume of the equivalent reconstruction unit is equal to the total copper volume of the original via group, and the equivalent reconstruction unit is placed at the geometric center of the original via group. The value of M is 2-3.

[0011] By adopting this invention, the original high-density interconnected traces and vias are generated into a macroscopically simplified model according to the equivalent rules, which significantly reduces the number of finite element meshes from the root. At the same time, by strictly maintaining the macroscopic distribution characteristics of key materials, the accuracy of warpage simulation results is ensured while achieving an order-of-magnitude improvement in simulation efficiency. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of step S1 in a specific embodiment of the present invention; Figure 2 This is a diagram showing the identified wiring fan-out layout in step S2 of a specific embodiment of the present invention; Figure 3 This is a diagram showing the interconnect hole arrangement identified in step S2 of a specific embodiment of the present invention; Figure 4 This is a schematic diagram of the routing reconstruction in step S3 of a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the interconnect hole reconstruction in step S4 of a specific embodiment of the present invention; Figure 6 This is a schematic diagram of panel-level model reconstruction according to a specific embodiment of the present invention. Detailed Implementation

[0013] A warp simulation finite element model analysis method first simplifies and reconstructs the position, area, and height of the circuits and vias of the metal structure of a single chip unit model; then, it reconstructs and simulates the panel-level model.

[0014] A single chip cell includes a fan-out package and a substrate. The steps for equivalent simplified reconstruction of a single chip cell model are as follows: S1 flip-chips the fan-out package onto the substrate to form a circuit connection; S2 identifies areas of trace fan-out and interconnect vias using layout data; S3 performs routing reconstruction; S4 performs interconnect hole reconstruction to obtain a simplified cell model.

[0015] The reconstruction and simulation of the panel-level model is step S5. After completing the reconstruction of all traces and vias of a single chip unit, the simplified unit model is arrayed and copied on the panel to construct a complete panel-level simulation model and calculate the warping deformation of the entire structure.

[0016] For specific implementation examples, see Figures 1-6 It includes the following steps: In step S1 (see) Figure 1 A pre-fabricated single fan-out integrated circuit chip is flip-chipped onto a substrate, and the circuit is connected by having the active side of the integrated circuit chip face down and the solder joints directly connected to the substrate. In step S2, the areas of trace fan-out and interconnect vias are identified from the substrate's stack-up design using layout data (see...). Figure 2 , Figure 3 ); In step S3, the chip is divided into multiple 45° sector regions centered on each side. Within each sector, divergent power, ground, or signal traces are identified. Two to five traces with roughly the same direction and adjacent to each other are grouped together to form an equivalent trace, and the cross-sectional area of ​​the equivalent trace is equal to the total cross-sectional area of ​​the original group of traces. The equivalent trace is placed on the geometric center line of the original trace group, ultimately forming a... Figure 4 The equivalent routing diagram is shown below; In step S4, within the fan-out region, 2-3 interconnects that connect to the same pair of wiring layers and are adjacent on the plane are identified and grouped together to create an equivalent reconstruction unit. The volume of this equivalent reconstruction unit is equal to the total copper volume of the original via group, and the equivalent reconstruction unit is placed at the geometric center of the original via group, ultimately forming a structure as shown in the image. Figure 5 The equivalent through-hole diagram is shown below; Step S5: After completing the reconstruction of all traces and vias of a single chip cell, the simplified cell model is arrayed and copied on the panel to build a complete panel-level simulation model and calculate the warping deformation of the entire structure.

[0017] By adopting this invention, the original high-density interconnected traces and vias are generated into a macroscopically simplified model according to the equivalent rules, which significantly reduces the number of finite element meshes from the root. At the same time, by strictly maintaining the macroscopic distribution characteristics of key materials, the accuracy of warpage simulation results is ensured while achieving an order-of-magnitude improvement in simulation efficiency.

[0018] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0019] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for analyzing warpage using a finite element model, characterized in that, First, the location, area, and details of the circuits and vias of the metal structure of a single chip unit model are equivalently simplified and reconstructed; then, the panel-level model is reconstructed and simulated.

2. The method for analyzing a warpage simulation finite element model according to claim 1, characterized in that, A single chip cell includes a fan-out package and a substrate. The steps for equivalent simplified reconstruction of a single chip cell model are as follows: S1 flip-chips the fan-out package onto the substrate to form a circuit connection; S2 identifies areas of trace fan-out and interconnect vias using layout data; S3 performs routing reconstruction; S4 performs interconnect reconfiguration.

3. The warpage simulation finite element model analysis method according to claim 2, characterized in that: The reconstruction and simulation of the panel-level model is step S5. After completing the reconstruction of all traces and vias of a single chip unit, the simplified unit model is arrayed and copied on the panel to construct a complete panel-level simulation model and calculate the warping deformation of the entire structure.

4. The warpage simulation finite element model analysis method according to claim 2, characterized in that: In step S1, a pre-fabricated single fan-out integrated circuit chip is flip-chip mounted on a substrate. The circuit is connected by having the active side of the integrated circuit chip facing down and the solder joints directly connected to the substrate.

5. The method for analyzing a warpage simulation finite element model according to claim 2, characterized in that: In step S2, the areas of trace fan-out and interconnect vias are identified from the substrate stack-up design using layout data.

6. The method for analyzing a warpage simulation finite element model according to claim 2, characterized in that: In step S3, the chip is divided into multiple 45° sector areas around each edge. Within each sector, divergent power, ground, or signal traces are identified. N traces with roughly the same direction and adjacent to each other are grouped together to form an equivalent trace. The cross-sectional area of ​​the equivalent trace is equal to the total cross-sectional area of ​​the original group of traces. The equivalent trace is placed on the geometric center line of the original trace group.

7. The method for analyzing a warpage simulation finite element model according to claim 6, characterized in that: The value of N is 2-5.

8. The method for analyzing a warpage simulation finite element model according to claim 2, characterized in that: In step S4, within the fan-out region, M interconnects that are connected to the same pair of wiring layers and are adjacent on the plane are identified and grouped together to create an equivalent reconstruction unit. The volume of the equivalent reconstruction unit is equal to the total copper volume of the original via group, and the equivalent reconstruction unit is placed at the geometric center of the original via group.

9. The method for analyzing a warping simulation finite element model according to claim 8, characterized in that: The value of M is 2-3.

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