Capacitor simulation circuit and simulation method thereof

Abstract

The invention relates to a capacitor simulation circuit and a simulation method thereof. The capacitor simulation circuit comprises a main body capacitor; the upper polar plate equivalent circuit comprises an upper polar plate equivalent resistor and an upper polar plate equivalent inductor which are connected in series, one end of the upper polar plate equivalent circuit is connected with the upper polar plate end, and the other end is connected with the first end of the main capacitor; the lower polar plate equivalent circuit comprises a lower polar plate equivalent resistor and a lower polar plate equivalent inductor which are connected in series, one end of the lower polar plate equivalent circuit is connected with the lower polar plate end, and the other end is connected with the second end of the main capacitor; the first end of the dielectric layer capacitor is connected with the second end of the main body capacitor; the substrate equivalent circuit comprises a substrate capacitor and a substrate resistor which are connected in parallel, one end of the substrate equivalent circuit is connected with the substrate end, and the other end of the substrate equivalent circuit is connected with the second end of the dielectric layer capacitor; wherein the capacitance value of the dielectric layer capacitor is obtained by inputting the number of dielectric layers of the device. According to the invention, the capacitance value of the isolation capacitor of chips with different metal layers in the same process can be accurately simulated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a capacitor simulation circuit and a simulation method for the capacitor simulation circuit. Background Technology

[0002] Capacitive isolation is widely used in solar inverters, electric / hybrid vehicles, and other terminals due to its high reliability, high voltage resistance, low latency, and low cost. Ultra-high voltage capacitors are essential components for capacitive isolation. To improve integration, ultra-high voltage capacitor manufacturing processes can be added to the later stages of semiconductor processing; therefore, designers have also raised the need for models of ultra-high voltage capacitors. Summary of the Invention

[0003] Therefore, it is necessary to provide a capacitor simulation circuit and its simulation method.

[0004] A capacitor simulation circuit is applicable to an isolation capacitor formed above a device section. The device section includes a substrate, a plurality of devices on the substrate, a plurality of device dielectric layers on the devices, and a metal interconnect layer. The isolation capacitor includes a lower plate, a capacitor dielectric layer on the lower plate, and an upper plate on the capacitor dielectric layer. The capacitor simulation circuit includes: a main capacitor; an upper plate equivalent circuit, including an upper plate equivalent resistance and an upper plate equivalent inductance connected in series, one end of the upper plate equivalent circuit being connected to the upper plate end and the other end being connected to the first end of the main capacitor; and a lower plate equivalent circuit, including a lower plate equivalent resistance and an upper plate equivalent inductance connected in series. The device includes an equivalent resistance of the lower plate and an equivalent inductance of the lower plate. One end of the lower plate equivalent circuit is connected to the lower plate end, and the other end is connected to the second end of the main capacitor. The lower plate parasitic circuit includes a dielectric layer capacitor and a substrate equivalent circuit. The first end of the dielectric layer capacitor is connected to the second end of the main capacitor. The substrate equivalent circuit includes a substrate capacitor and a substrate resistor connected in parallel. One end of the substrate equivalent circuit is connected to the substrate end, and the other end is connected to the second end of the dielectric layer capacitor. The capacitance value of the dielectric layer capacitor is variable and is obtained by inputting the number of dielectric layers or the number of metal interconnect layers of the device.

[0005] The capacitor simulation circuit described above can accurately simulate the capacitance value of isolation capacitors of chips with different numbers of metal interconnect layers (corresponding to different numbers of dielectric layers) using the same process, reducing redundancy in the simulation model and improving simulation efficiency.

[0006] In one embodiment, the capacitance value of all or part of the device dielectric layer is obtained by the capacitance per unit area of ​​all or part of the device dielectric layer.

[0007] In one embodiment, the capacitance value of the dielectric layer capacitor is Mi×C. oxMi = 1 / [1 / K1 + 1 / K6] × j2 + 1 / [1 / K1 + 1 / K2 + (i-3) / K3 + 1 / K6] × (j3 + j4 + j5 + j6); where i is the number of metal interconnect layers, 1 / K1 is the normalized value of the unit area capacitance of the dielectric layer closest to the substrate for the 4Al process, 1 / K2 is the normalized value of the unit area capacitance of the second dielectric layer closest to the substrate for the 4Al process, 1 / K3 is the normalized value of the unit area capacitance of the third dielectric layer closest to the substrate for the 4Al process, 1 / K6 is the normalized value of the unit area capacitance of the top dielectric layer for the 4Al process, j2, j3, j4, j5, and j6 correspond to the switching coefficients of the 2Al, 3Al, 4Al, 5Al, and 6Al processes, respectively, and C ox The dielectric layer capacitor is a 4Al process.

[0008] In one embodiment, C ox =Ca×A+Cf×P, where Ca is the capacitance related to the area of ​​the lower plate, Cf is the capacitance related to the perimeter of the lower plate, A is the area of ​​the lower plate, and P is the perimeter of the lower plate.

[0009] A simulation method for a capacitor simulation circuit includes: obtaining simulation model parameters of the capacitor simulation circuit, wherein the simulation model parameters are related to the thickness of the capacitor dielectric layer, the length of the upper electrode, the width of the upper electrode, and the number of isolation capacitors on each chip; establishing a capacitor simulation circuit as described in any of the preceding embodiments based on the simulation model parameters; obtaining the capacitance value of each device dielectric layer based on the thickness of each device dielectric layer and the dielectric constant of each device dielectric layer in the baseline process of the isolation capacitor to be simulated; using the capacitance value of the device dielectric layer as the simulation model parameter, and inputting the number of device dielectric layers for simulation.

[0010] The above-mentioned simulation method for capacitor simulation circuits can accurately simulate the capacitance values ​​of isolation capacitors of chips with different numbers of metal interconnect layers (corresponding to different numbers of device dielectric layers) using the same process, reducing the redundancy of the simulation model and improving simulation efficiency.

[0011] In one embodiment, the method further includes: acquiring a plurality of test wafers having test structures, the test structures including a device portion and an isolation capacitor above the device portion, the device portion including a substrate, a plurality of devices on the substrate, a plurality of device dielectric layers and a metal interconnect layer on the devices, the isolation capacitor including a lower electrode, a capacitor dielectric layer on the lower electrode and an upper electrode on the capacitor dielectric layer; each test wafer including a test wafer with a capacitor dielectric layer thickness of a first thickness and a test wafer with a capacitor dielectric layer thickness of a second thickness, wherein the first thickness is not equal to the second thickness; and testing to obtain the S-parameters of each test structure; wherein the simulation model parameters are obtained based on the S-parameters.

[0012] In one embodiment, the step of obtaining the capacitance value of each device dielectric layer based on the thickness and dielectric constant of each device dielectric layer of the isolation capacitor to be simulated includes: obtaining the unit area capacitance of each device dielectric layer based on the thickness and dielectric constant of each device dielectric layer of the isolation capacitor to be simulated; the simulation method further includes: calculating the capacitance value of the variable dielectric layer capacitance based on the number of device dielectric layers and the unit area capacitance of all or part of the device dielectric layers.

[0013] In one embodiment, the step of calculating the capacitance value of the dielectric layer based on the number of dielectric layers and the capacitance per unit area of ​​all or part of the dielectric layers includes: normalizing the capacitance per unit area of ​​all or part of the dielectric layers; and using Mi×C... ox Calculate the capacitance value of the dielectric layer: Mi = 1 / [1 / K1 + 1 / K6] × j2 + 1 / [1 / K1 + 1 / K2 + (i-3) / K3 + 1 / K6] × (j3+j4+j5+j6); where i is the number of metal interconnect layers, 1 / K1 is the normalized value of the unit area capacitance of the dielectric layer closest to the substrate for the 4Al process, 1 / K2 is the normalized value of the unit area capacitance of the second dielectric layer closest to the substrate for the 4Al process, 1 / K3 is the normalized value of the unit area capacitance of the third dielectric layer closest to the substrate for the 4Al process, 1 / K6 is the normalized value of the unit area capacitance of the top dielectric layer for the 4Al process, j2, j3, j4, j5, and j6 correspond to the switching coefficients of the 2Al, 3Al, 4Al, 5Al, and 6Al processes, respectively, and C oxThe step of using the capacitance value of the device dielectric layer as a simulation model parameter and inputting the number of device dielectric layers for simulation includes: using the normalized value of the unit area capacitance of the device dielectric layer to the capacitance of the dielectric layer in the 4Al process as a simulation model parameter and inputting the number of device dielectric layers for simulation.

[0014] In one embodiment, C ox =Ca×A+Cf×P, where Ca is the capacitance related to the area of ​​the lower plate, Cf is the capacitance related to the perimeter of the lower plate, A is the area of ​​the lower plate, and P is the perimeter of the lower plate.

[0015] In one embodiment, the method further includes: setting the lower plate parasitic circuit switching parameters; and in response to the lower plate parasitic circuit switching parameters being a first value, using a preset capacitance value as the capacitance value of the substrate capacitance in the capacitor simulation circuit.

[0016] In one embodiment, different test wafers have different capacitor dielectric layer thicknesses.

[0017] In one embodiment, the test wafer is a wafer fabricated using a standard process having four metal interconnect layers in the device section.

[0018] In one embodiment, the step of obtaining several test wafers is to obtain 3 test wafers.

[0019] It is also necessary to provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0020] It is also necessary to provide a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the method described in any of the foregoing embodiments.

[0021] It is also necessary to provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the method as described in any of the foregoing embodiments. Attached Figure Description

[0022] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0023] Figure 1This is a schematic diagram of the structure of the isolation capacitor of an integrated circuit in one embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the device section of an integrated circuit in one embodiment of this application.

[0025] Figure 3 This is the equivalent circuit of the capacitor simulation circuit of the integrated circuit in one embodiment of this application.

[0026] Figure 4a This is a flowchart of a simulation method for a capacitor simulation circuit in one embodiment of this application; Figure 4b This is a flowchart of a simulation method for a capacitor simulation circuit in another embodiment of this application.

[0027] Figures 5a to 5c This is a fitting diagram of the equivalent capacitance across the two ends of an ultra-high voltage capacitor.

[0028] Figures 6a to 6e Fitting plot of equivalent capacitance at port 1 when W, L, and mf take different values. Detailed Implementation

[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0035] Isolation capacitors can be integrated into a chip containing semiconductor devices. The entire integrated circuit of the chip includes... Figure 1 The isolation capacitor 200 shown and Figure 2 The device section 100 shown has an isolation capacitor 200 formed above it. The isolation capacitor 200 includes a lower electrode 210, a capacitor dielectric layer 220 on the lower electrode 210, and an upper electrode 230 on the capacitor dielectric layer 220. The device section 100 includes a substrate Sub, a plurality of devices on the substrate Sub, a plurality of device dielectric layers on the devices, and a plurality of metal interconnect layers. Figure 2 In the illustrated embodiment, the device section 100 has six device dielectric layers, namely ILD (interlayer dielectric layer) and IMD1~IMD5 (five-layer intermetallic dielectric layers). The metal interconnect layers of the device section 100 include a first metal layer 121, a second metal layer 123, a third metal layer 125, a fourth metal layer 127, and a fifth metal layer 129. The capacitor dielectric layer 220 and the device dielectric layers can be made of silicon oxide, such as silicon dioxide. The device dielectric layers and the metal layers are stacked alternately.

[0036] The capacitor simulation circuit for integrated circuits can be used Figure 3The equivalent circuit shown includes a main capacitor Cmain, an upper plate equivalent circuit 310, a lower plate equivalent circuit 320, a variable dielectric layer capacitor Cox, and a substrate equivalent circuit 330. The main capacitor Cmain is a capacitor formed between the lower plate 210 and the upper plate 230. The upper plate equivalent circuit 310 includes an upper plate equivalent resistance r_t and an upper plate equivalent inductance ln_t connected in series. One end of the upper plate equivalent circuit 310 is connected to the upper plate terminal top, and the other end is connected to the first terminal of the main capacitor Cmain. The lower plate equivalent circuit 320 includes a lower plate equivalent resistance r_b and a lower plate equivalent inductance ln_b connected in series. One end of the lower plate equivalent circuit 320 is connected to the lower plate terminal bottom, and the other end is connected to the second terminal of the main capacitor Cmain. The first terminal of the dielectric layer capacitor Cox is connected to the second terminal of the main capacitor Cmain. The substrate equivalent circuit 330 includes a substrate capacitor csub and a substrate resistor rsub connected in parallel. One end of the substrate equivalent circuit 330 is connected to the substrate terminal sub, and the other end is connected to the second terminal of the dielectric layer capacitor Cox.

[0037] The dielectric layer capacitance Cox varies with the number of metal interconnect layers in device section 100, that is, it varies with the number of dielectric layers in the device, and therefore can be equivalent to a variable capacitor. The capacitance value of the dielectric layer capacitance Cox is calculated by inputting the number of dielectric layers or metal interconnect layers, and the capacitance value of all or part of the dielectric layers into a capacitor simulation circuit. In other words, the dielectric layer capacitance Cox is a variable capacitor that varies with the number of metal interconnect layers and the capacitance value of the dielectric layers. Figure 2 Taking the structure shown as an example, the 6 device dielectric layers consist of 5 IMD layers and 1 ILD layer. For some processes, there are cases where different device dielectric layers have the same capacitance value. Therefore, for such processes, it is not necessary to input the capacitance values ​​of all device dielectric layers into the capacitor simulation circuit. That is, for device dielectric layers with equal capacitance values, only the capacitance value of one device dielectric layer needs to be input. For example, in some processes, several IMD layers have equal capacitance values; therefore, for IMD layers with equal capacitance values, only the capacitance value of one IMD layer needs to be input into the capacitor simulation circuit.

[0038] The capacitor simulation circuit described above can accurately simulate the isolation capacitor capacitance values ​​of chips with different numbers of metal interconnect layers (corresponding to different numbers of device dielectric layers) using the same process, reducing the number of test wafers and production time required to extract the simulation model, reducing the redundancy of the simulation model, and improving simulation efficiency.

[0039] In one embodiment of this application, the capacitance value of all or part of the device dielectric layer is obtained by calculating the capacitance per unit area of ​​all or part of the device dielectric layer.

[0040] In one embodiment of this application, the capacitance value of the dielectric layer capacitor Cox is calculated by inputting the number of metal interconnect layers (or dielectric layers) of the device, the area of ​​the lower electrode, and the capacitance per unit area of ​​all or part of the device dielectric layers.

[0041] In one embodiment of this application, the capacitance value of the dielectric layer capacitor Cox is Mi×C. ox Mi = 1 / [1 / K1 + 1 / K6] × j2 + 1 / [1 / K1 + 1 / K2 + (i-3) / K3 + 1 / K6] × (j3 + j4 + j5 + j6); where 1 / K1 is the normalized value of the dielectric layer capacitance per unit area of ​​the device layer closest to the substrate for the dielectric layer capacitance of the plate parasitic circuit under the 4Al process (four-layer metal baseline), 1 / K2 is the normalized value of the dielectric layer capacitance per unit area of ​​the device layer closest to the substrate for the dielectric layer capacitance of the plate parasitic circuit under the 4Al process, and 1 / K3 is the normalized value of the dielectric layer capacitance per unit area of ​​the device layer closest to the substrate. The capacitance is the normalized value of the dielectric layer capacitance of the plate parasitic circuit under the 4Al process. 1 / K6 is the normalized value of the unit area capacitance of the uppermost device dielectric layer for the dielectric layer capacitance of the plate parasitic circuit under the 4Al process. j2, j3, j4, j5, and j6 correspond to the switching coefficients of the 2Al process (two-layer metal baseline), 3Al process (three-layer metal baseline), 4Al process (four-layer metal baseline), 5Al process (five-layer metal baseline), and 6Al process (six-layer metal baseline), respectively. C ox This refers to the dielectric layer capacitance of the parasitic circuit of the lower electrode corresponding to the 4Al process.

[0042] In one embodiment of this application, C ox =Ca×A+Cf×P, where Ca is the capacitance related to the area of ​​the lower plate, Cf is the capacitance related to the perimeter of the lower plate, A is the area of ​​the lower plate, and P is the perimeter of the lower plate. Ca and Cf can be obtained through measurement or based on experience. For example, Ca is 6.77671E-6, and Cf is 7.3129E-11.

[0043] In one embodiment of this application, the isolation capacitor 200 is an ultra-high voltage (UHV) capacitor.

[0044] This application provides a simulation method for a capacitor simulation circuit. Figure 4a This is a flowchart of a simulation method for a capacitor simulation circuit according to an embodiment of this application, including the following steps:

[0045] S310: Obtain the simulation model parameters of the capacitor simulation circuit.

[0046] The simulation model parameters are related to the size of the capacitor. In one embodiment of this application, the capacitor size includes d: capacitor dielectric layer thickness, W: upper plate width, L: upper plate length, and mf: number of isolation capacitors on each chip. The chip refers to the chip containing the isolation capacitor to be simulated (the isolation capacitor to be simulated).

[0047] S320, establishes a capacitor simulation circuit based on the simulation model parameters.

[0048] Capacitor simulation circuits can be used Figure 3 The equivalent circuit is shown below. For the fitting effect between the capacitor simulation circuit and the test data, please refer to [reference needed]. Figures 5a to 5c ,and Figures 6a to 6e . Figures 5a to 5c This is a fitting plot of the equivalent capacitance across the ultra-high voltage capacitor, where the horizontal axis represents frequency in Hz and the vertical axis represents capacitance in F. L / W / Mf / Zr / Zi=800 / 800 / 1 / 50 / 0 indicates that the upper plate length and width of the ultra-high voltage capacitor are 800 micrometers, and there is one ultra-high voltage capacitor on each chip. During testing, the real component Zr of the matching resistor connected in series at the ports of the ultra-high voltage capacitor is 50 ohms, and the imaginary component of the impedance is 0. T=25 indicates that the data was measured at 25 degrees Celsius. vp=0V, vn=-3.3V, vp and vn are the bias voltages applied across the ultra-high voltage capacitor (port 1 and port 2) during testing. C11 represents the capacitance obtained from testing port 1, C22 represents the capacitance obtained from testing port 2, and C12 represents the capacitance between ports 1 and 2 obtained from testing. Figures 6a to 6e Fitting plot of equivalent capacitance at port 1 when W, L, and mf take different values. Figures 5a to 5c , Figures 6a to 6e The discrete points in the figure are data obtained from testing, and the curves are data obtained from simulation based on the established capacitor simulation circuit.

[0049] S330: Obtain the capacitance values ​​of the dielectric layers of each component in the isolation capacitor to be simulated.

[0050] Based on the thickness and dielectric constant of each dielectric layer of the isolation capacitor to be simulated, the capacitance value of each dielectric layer can be obtained. In one embodiment of this application, step S450 involves obtaining the thickness and relative dielectric constant εs of each dielectric layer based on the back-end process parameters of the baseline process of the isolation capacitor to be simulated. Then, based on the thickness and relative dielectric constant εs of each dielectric layer, the capacitance per unit area of ​​each dielectric layer is calculated, as shown in Table 1.

[0051] Table 1

[0052]

[0053] S340: Use the capacitance value obtained in step S330 as the simulation model parameter, and input the number of dielectric layers of the device for simulation.

[0054] In one embodiment of this application, the simulation is performed using the normalized value of the dielectric layer capacitance of the 4Al process based on the unit area capacitance of each device dielectric layer. This yields more accurate simulation results. In other embodiments, the simulation can also be performed using the normalized value of the dielectric layer capacitance of processes such as 2Al and 3Al.

[0055] Figure 4b This is a flowchart of a simulation method for a capacitor simulation circuit according to another embodiment of this application, including the following steps:

[0056] S410: Obtain several test wafers with test structures.

[0057] A test wafer is also known as a golden wafer (standard wafer). In one embodiment of this application, a test wafer needs to be fabricated to simulate the isolation capacitors (isolation capacitors to be simulated) on a chip using a capacitor simulation circuit. Specifically, a test structure (Testkey) in the test wafer can be designed according to the length and width of the isolation capacitors to be simulated and the number of isolation capacitors on each chip. The test structure includes a device section and an isolation capacitor above the device section. The device section includes a substrate, several device dielectric layers on the substrate, and several metal interconnect layers. The isolation capacitor includes a lower electrode, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. Each test wafer includes a test wafer with a capacitor dielectric layer thickness of a first thickness and a test wafer with a capacitor dielectric layer thickness of a second thickness.

[0058] In one embodiment of this application, the prepared test wafers have the same number of metal interconnect layers.

[0059] In one embodiment of this application, step S410 is to obtain three test wafers with capacitor dielectric layer thicknesses of d1, d2, and d3, respectively, where d1≠d2≠d3.

[0060] In one embodiment of this application, the isolation capacitor is an ultra-high voltage capacitor.

[0061] In one embodiment of this application, the test wafer is fabricated using a standard baseline process with a critical dimension (CD) of 0.18 micrometers.

[0062] S420, the S-parameters of each test structure are obtained through testing.

[0063] S-parameters are scattering parameters.

[0064] S430 extracts the corresponding simulation model parameters from the capacitor simulation circuit based on the S-parameters.

[0065] The extracted simulation model parameters are related to the size of the capacitor. In one embodiment of this application, the size of the capacitor includes d: the thickness of the capacitor dielectric layer, W: the width of the upper plate, L: the length of the upper plate, and mf: the number of isolation capacitors on each chip.

[0066] S440, establishes a capacitor simulation circuit based on the simulation model parameters.

[0067] Capacitor simulation circuits can be used Figure 3 The equivalent circuit is shown below. For the fitting effect between the capacitor simulation circuit and the test data, please refer to [reference needed]. Figures 5a to 5c ,and Figures 6a to 6e . Figures 5a to 5c This is a fitting plot of the equivalent capacitance across the ultra-high voltage capacitor, where the horizontal axis represents frequency in Hz and the vertical axis represents capacitance in F. L / W / Mf / Zr / Zi=800 / 800 / 1 / 50 / 0 indicates that the upper plate length and width of the ultra-high voltage capacitor are 800 micrometers, and there is one ultra-high voltage capacitor on each chip. During testing, the real component Zr of the matching resistor connected in series at the ports of the ultra-high voltage capacitor is 50 ohms, and the imaginary component of the impedance is 0. T=25 indicates that the data was measured at 25 degrees Celsius. vp=0V, vn=-3.3V, vp and vn are the bias voltages applied across the ultra-high voltage capacitor (port 1 and port 2) during testing. C11 represents the capacitance obtained from testing port 1, C22 represents the capacitance obtained from testing port 2, and C12 represents the capacitance between ports 1 and 2 obtained from testing. Figures 6a to 6e Fitting plot of equivalent capacitance at port 1 when W, L, and mf take different values. Figures 5a to 5c , Figures 6a to 6e The discrete points in the figure are data obtained from testing, and the curves are data obtained from simulation based on the established capacitor simulation circuit.

[0068] In one embodiment of this application, if the capacitance value obtained by the capacitor simulation circuit deviates significantly from the capacitance test value obtained by the test wafer, the simulation model parameters need to be adjusted until the simulation model parameters are modulated to a value less than a preset range.

[0069] S450: Obtain the capacitance values ​​of the dielectric layers of each component in the isolation capacitor to be simulated.

[0070] Based on the thickness and dielectric constant of each dielectric layer of the isolation capacitor to be simulated, the capacitance value of each dielectric layer can be obtained. In one embodiment of this application, step S450 involves obtaining the thickness and relative dielectric constant εs of each dielectric layer based on the back-end process parameters of the baseline process of the isolation capacitor to be simulated. Then, based on the thickness and relative dielectric constant εs of each dielectric layer, the capacitance per unit area of ​​each dielectric layer is calculated, referring to Table 1 above.

[0071] S460, Input the capacitance value obtained in step S450 into the number of dielectric layers of the device for simulation.

[0072] In one embodiment of this application, the simulation is performed based on the normalized value of the dielectric layer capacitance of the 4Al process, according to the unit area capacitance of each device dielectric layer; in other embodiments, the simulation can also be performed based on the normalized value of the dielectric layer capacitance of processes such as 2Al and 3Al.

[0073] The above-described simulation method for capacitor simulation circuits can accurately simulate the capacitance values ​​of isolation capacitors for chips with different numbers of metal interconnect layers (corresponding to different numbers of device dielectric layers) using the same process. This reduces the number of test wafers and production time required to extract the simulation model, lowers model redundancy, and improves modeling efficiency. Step S410 only requires acquiring the test wafer with metal interconnect layer number i. By inputting the normalized value of the unit area capacitance of the device dielectric layer to the parasitic dielectric layer capacitance of the electrode under the 4Al process, and the number of metal interconnect layers / device dielectric layers, the capacitance values ​​of isolation capacitors for other metal interconnect layer processes can be simulated. The reduced number of test wafers required in step S410 significantly reduces testing and modeling time. Once the ultra-high voltage capacitor process is stable, this simulation method can directly calculate and replace the corresponding dielectric layer capacitance using the downstream process parameters of the mature process, applying the high-voltage capacitor simulation circuit to that mature process. For different processes, this simulation method can also quickly establish ultra-high voltage capacitor simulation circuits suitable for that process, shortening tape-out time and cost, and improving modeling efficiency.

[0074] In one embodiment of this application, step S450 includes: obtaining the capacitance per unit area of ​​each device dielectric layer based on the thickness and dielectric constant of each device dielectric layer of the isolation capacitor to be simulated. The simulation method further includes: calculating the capacitance value of the dielectric layer based on the number of device dielectric layers and the capacitance per unit area of ​​all or part of the device dielectric layers. Specifically, the capacitance per unit area of ​​all or part of the device dielectric layers can be normalized. The capacitance per unit area of ​​ILD~IMD5 is denoted as K1~K6 after normalization.

[0075] In one embodiment of this application, the simulation method further includes the step of calculating the capacitance per unit area of ​​the entire device dielectric layer. Specifically, the capacitance per unit area of ​​the entire device dielectric layer can be calculated based on the capacitance per unit area of ​​each device dielectric layer obtained in step S450. In one embodiment of this application, it is necessary to calculate: the overall unit area capacitance M2_Sub of the dielectric layer between M1, AT and substrate Sub in a two-metal baseline (i.e., 2Al process); the overall unit area capacitance M3_Sub of the dielectric layer between M1, M2, AT and substrate Sub in a three-metal baseline (i.e., 3Al process); the overall unit area capacitance M4_Sub of the dielectric layer between M1, M2, M3, AT and substrate Sub in a four-metal baseline (i.e., 4Al process); the overall unit area capacitance M5_Sub of the dielectric layer between M1, M2, M3, M4, AT and substrate Sub in a five-metal baseline (i.e., 5Al process); and the overall unit area capacitance M6_Sub of the dielectric layer between M1, M2, M3, M4, M5, AT and substrate Sub in a six-metal baseline (i.e., 6Al process). The overall capacitance of the device dielectric layer is equivalent to the capacitance of each device dielectric layer connected in parallel. Based on this, M2_Sub to M6_Sub can be calculated using the data in Table 1 (M1_Sub is equal to the capacitance per unit area of ​​the ILD). Taking the calculation of M2_Sub as an example, assuming its value is C, the capacitance per unit area of ​​the ILD is C1, and the capacitance per unit area of ​​IMD5 (IMD5 is the intermetallic dielectric layer below AT that is closest to AT) is C2, then C can be calculated according to 1 / C = 1 / C1 + 1 / C2.

[0076] In one embodiment of this application, the method further includes a step of normalizing the capacitance per unit area of ​​the entire device dielectric layer. M1_Sub to M6_Sub are denoted as M1 to M6 after normalization.

[0077] Define the parameter layer: layer 1 corresponds to M1_Sub (1Al process), layer 2 corresponds to M2_Sub (2Al process), ..., layer 6 corresponds to M6_Sub (6Al process).

[0078] The formula is as follows:

[0079] Mi = 1 / [1 / K1+1 / K6]×j2+1 / [1 / K1+1 / K2+1 / K3+1 / K4+1 / K5+1 / K6]×(j3+j4+j5+j6) (i=layer). In the embodiment corresponding to Table 1, K3=K4=K5. Based on this, the aforementioned formula is simplified to obtain...

[0080] Mi=1 / [1 / K1+1 / K6]×j2+1 / [1 / K1+1 / K2+(i-3) / K3+1 / K6]×(j3+j4+j5+j6)

[0081] Where j2, j3, j4, j5, and j6 correspond to the switching coefficients of the 2Al, 3Al, 4Al, 5Al, and 6Al processes, respectively.

[0082] j2=((i-3)× (i-4)× (i-5)× (i-6)) / ((2-3)× (2-4)× (2-5)× (2-6))

[0083] j3=((i-2)× (i-4)× (i-5)× (i-6)) / ((3-2)× (3-4)× (3-5)× (3-6))

[0084] j4=((i-2)× (i-3)× (i-5)× (i-6)) / ((4-2)× (4-3)× (4-5)× (4-6))

[0085] j5=((i-2)× (i-3)× (i-4)× (i-6)) / ((5-2)× (5-3)× (5-4)× (5-6))

[0086] j6=((i-2)× (i-3)× (i-4)× (i-5)) / ((6-2)× (6-3)× (6-4)× (6-5))

[0087] Based on the above explanation, we obtain Table 2.

[0088] Table 2

[0089]

[0090] Therefore, the capacitance value of the dielectric layer capacitor Cox can be characterized as Mi×C ox In one embodiment of this application, C ox For the lower electrode parasitic circuit corresponding to the 4Al process, the dielectric layer capacitance is C; in other embodiments, C ox It can also be the dielectric layer capacitor of the parasitic circuit of the lower electrode plate using processes such as 2Al and 3Al.

[0091] In one embodiment of this application, C ox =Ca×A+Cf×P, where Ca is the capacitance related to the area of ​​the lower plate, Cf is the capacitance related to the perimeter of the lower plate, A is the area of ​​the lower plate, and P is the perimeter of the lower plate.

[0092] In one embodiment of this application, the simulation method further includes setting the switching parameters of the lower electrode parasitic circuit (including dielectric layer capacitance, substrate capacitance and substrate resistance). When the lower electrode parasitic circuit is to be ignored, the dielectric layer capacitance of the lower electrode parasitic circuit is set to a preset very small value by assigning a value (a preset value, such as 0) to the parameter.

[0093] Specifically, the flag parameter coxflag can be set. When coxflag==0, a very small, negligible capacitor—for example, a capacitance value of 1e-20 (F)—is used as the dielectric layer capacitor cox of the lower plate parasitic circuit.

[0094] In one embodiment of this application, after step S460, a step is further included to confirm whether the simulation data of the capacitor simulation circuit matches the test data obtained from testing the test wafer, and then the obtained capacitor simulation circuit is solidified.

[0095] The capacitor simulation circuit of this application can be simulated using software such as HSPICE and SPECTRE. The following is an example of a capacitor simulation circuit established according to the simulation method of the capacitor simulation circuit in one embodiment of this application:

[0096] .subckt cap_uhv_at_tz_l1 top bottom sub l = 1E-4 w = 1E-4 mf = 1 i =4

[0097] .param

[0098] +d = …

[0099] + cox_a = 6.77671E-6 cox_f =7.3129E-11 cox3=1e-20

[0100] +…

[0101] +K1=4.871477 K2=3.977145 K3=3.881348 K6=3.500857

[0102] .param

[0103] +j2=((i-3)× (i-4)× (i-5)× (i-6)) / ((2-3)× (2-4)× (2-5)× (2-6))

[0104] +j3=((i-2)× (i-4)× (i-5)× (i-6)) / ((3-2)× (3-4)× (3-5)× (3-6))

[0105] +j4=((i-2)× (i-3)× (i-5)× (i-6)) / ((4-2)× (4-3)× (4-5)× (4-6))

[0106] +j5=((i-2)× (i-3)× (i-4)× (i-6)) / ((5-2)× (5-3)× (5-4)× (5-6))

[0107] +j6=((i-2)× (i-3)× (i-4)× (i-5)) / ((6-2)× (6-3)× (6-4)× (6-5))

[0108] +Mi=1 / [1 / K1+1 / K6]×j2+1 / [1 / K1+1 / K2+(i-3) / K3+1 / K6]×(j3+j4+j5+j6)

[0109] +cox = '(cox_a×area_0+cox_f×pj_0) ×Mi×mf'

[0110] rmain1 top n1 'rmain2×rctm_mimfac'

[0111] ln n1 n2 'ln_t×l_mimfac'

[0112] lp n3 n33 'ln_b×l_mimfac'

[0113] rmain2 n33 bottom 'rmain2×rctm_mimfac'

[0114] cmain2 n2 n3 'cmain2×cmim_mimfac'

[0115] .if (coxflag==1)

[0116] cox n3 sub1 'cox×cm4_mimfac'

[0117] rsub sub1 sub 'rsub / mf×rsub_mimfac'

[0118] csub sub1 sub 'csub×mf×csub_mimfac'

[0119] .elseif (coxflag==0)

[0120] cox n3 sub 'cox3×mf'

[0121] .endif

[0122] .ends cap_uhv_at_tz_l1

[0123] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0124] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0125] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0126] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the method described in any of the foregoing embodiments.

[0127] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method as described in any of the foregoing embodiments.

[0128] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A capacitor simulation circuit, characterized in that, An isolation capacitor is suitable for being formed above a device portion, the device portion including a substrate, a plurality of devices on the substrate, a plurality of device dielectric layers on the devices, and a metal interconnect layer; the isolation capacitor includes a lower electrode, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer; the capacitor simulation circuit includes: Main capacitor; The upper plate equivalent circuit includes an upper plate equivalent resistance and an upper plate equivalent inductance connected in series. One end of the upper plate equivalent circuit is connected to the upper plate end, and the other end is connected to the first end of the main capacitor. The lower plate equivalent circuit includes a lower plate equivalent resistance and a lower plate equivalent inductance connected in series. One end of the lower plate equivalent circuit is connected to the lower plate end, and the other end is connected to the second end of the main capacitor. The lower electrode parasitic circuit includes a dielectric layer capacitor and a substrate equivalent circuit. The first end of the dielectric layer capacitor is connected to the second end of the main capacitor. The substrate equivalent circuit includes a substrate capacitor and a substrate resistor connected in parallel. One end of the substrate equivalent circuit is connected to the substrate end, and the other end is connected to the second end of the dielectric layer capacitor. The capacitance value of the dielectric layer capacitor is variable and is obtained by inputting the number of dielectric layers or the number of metal interconnect layers of the device.

2. The capacitor simulation circuit according to claim 1, characterized in that, The capacitance value of the dielectric layer capacitor is also obtained by inputting the capacitance per unit area of ​​all or part of the dielectric layer of the device.

3. The capacitor simulation circuit according to claim 2, characterized in that, The capacitance value of the dielectric layer capacitor is Mi×C ox , Mi=1 / [1 / K1+1 / K6]×j2+1 / [1 / K1+1 / K2+(i-3) / K3+1 / K6]×(j3+j4+j5+j6); Where i is the number of metal interconnect layers, 1 / K1 is the normalized value of the unit area capacitance of the dielectric layer closest to the substrate for the 4Al process, 1 / K2 is the normalized value of the unit area capacitance of the second dielectric layer closest to the substrate for the 4Al process, 1 / K3 is the normalized value of the unit area capacitance of the third dielectric layer closest to the substrate for the 4Al process, 1 / K6 is the normalized value of the unit area capacitance of the top dielectric layer for the 4Al process, j2, j3, j4, j5, and j6 correspond to the switching coefficients of the 2Al, 3Al, 4Al, 5Al, and 6Al processes, respectively, and C ox The dielectric layer capacitor is a 4Al process.

4. The capacitor simulation circuit according to claim 3, characterized in that, C ox =Ca×A+Cf×P, where Ca is the capacitance related to the area of ​​the lower plate, Cf is the capacitance related to the perimeter of the lower plate, A is the area of ​​the lower plate, and P is the perimeter of the lower plate.

5. A simulation method for a capacitor simulation circuit, characterized in that, include: Obtain the simulation model parameters of the capacitor simulation circuit. The simulation model parameters are related to the capacitor dielectric layer thickness, upper plate length, upper plate width, and the number of isolation capacitors on each chip. Establish the capacitor simulation circuit as described in claim 1 based on the simulation model parameters; Based on the thickness and dielectric constant of each dielectric layer of the isolation capacitor to be simulated, the capacitance value of each dielectric layer is obtained. The capacitance value of the device's dielectric layer is used as a parameter in the simulation model, and the number of dielectric layers is input for simulation.

6. The simulation method for the capacitor simulation circuit according to claim 5, characterized in that, Also includes: A number of test wafers with test structures are obtained. The test structure includes a device section and an isolation capacitor above the device section. The device section includes a substrate, a number of devices on the substrate, a number of device dielectric layers and a metal interconnect layer on the devices. The isolation capacitor includes a lower electrode, a capacitor dielectric layer on the lower electrode and an upper electrode on the capacitor dielectric layer. Each test wafer includes a test wafer with a capacitor dielectric layer thickness of a first thickness and a test wafer with a capacitor dielectric layer thickness of a second thickness, wherein the first thickness is not equal to the second thickness. The S-parameters of each test structure were obtained through testing. The simulation model parameters are obtained based on the S-parameters.

7. The simulation method for the capacitor simulation circuit according to claim 5, characterized in that, The capacitance value of the dielectric layer of each device includes the capacitance per unit area of ​​the dielectric layer of each device. The simulation method further includes: calculating the capacitance value of the dielectric layer based on the number of dielectric layers of the device and the capacitance per unit area of ​​all or part of the dielectric layers of the device.

8. The simulation method for the capacitor simulation circuit according to claim 7, characterized in that, The step of calculating the capacitance value of the dielectric layer based on the number of dielectric layers in the device and the capacitance per unit area of ​​all or part of the dielectric layers includes: The capacitance per unit area of ​​the dielectric layer of all or part of the devices is normalized. Through Mi×C ox Calculate the capacitance value of the dielectric layer. Mi = 1 / [1 / K1 + 1 / K6] × j2 + 1 / [1 / K1 + 1 / K2 + (i-3) / K3 + 1 / K6] × (j3 + j4 + j5 + j6); where i is the number of metal interconnect layers, 1 / K1 is the normalized value of the unit area capacitance of the dielectric layer closest to the substrate for the 4Al process, 1 / K2 is the normalized value of the unit area capacitance of the second dielectric layer closest to the substrate for the 4Al process, 1 / K3 is the normalized value of the unit area capacitance of the third dielectric layer closest to the substrate for the 4Al process, 1 / K6 is the normalized value of the unit area capacitance of the top dielectric layer for the 4Al process, j2, j3, j4, j5, and j6 correspond to the switching coefficients of the 2Al, 3Al, 4Al, 5Al, and 6Al processes, respectively, and C ox The dielectric layer capacitor is a 4Al process.

9. The simulation method for the capacitor simulation circuit according to claim 8, characterized in that, C ox =Ca×A+Cf×P, where Ca is the capacitance related to the area of ​​the lower plate, Cf is the capacitance related to the perimeter of the lower plate, A is the area of ​​the lower plate, and P is the perimeter of the lower plate. The step of using the capacitance value of the device dielectric layer as a simulation model parameter and inputting the number of device dielectric layers for simulation includes: using the normalized value of the unit area capacitance of the device dielectric layer to the capacitance of the dielectric layer in the 4Al process as a simulation model parameter and inputting the number of device dielectric layers for simulation.

10. The simulation method for the capacitor simulation circuit according to claim 6, characterized in that, Different test wafers have different capacitor dielectric layer thicknesses; and / or The test wafer is prepared using a standard process that includes four metal interconnect layers in the device section.

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