A gate driving circuit and a display panel
By setting forward and reverse scanning modules in the gate drive circuit and performing pre-charge voltage processing on the drive control node, the problem of poor bidirectional scanning stability is solved, and a stable bidirectional scanning effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2026-04-14
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, bidirectional scanning has poor stability, especially when switching power polarity, which may cause transient shocks and flickering.
By setting forward and reverse scan modules in the gate drive circuit, the drive control node is pre-charged to generate forward and reverse pre-charge voltages, and forward and reverse scans are independently controlled to avoid changes in power supply polarity and ensure the stability of the scan process.
It achieves stability in the bidirectional scanning process, avoids problems such as transient impacts and flicker, and ensures stable display on the display panel.
Smart Images
Figure CN122050282B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, specifically relating to a gate driving circuit and a display panel. Background Technology
[0002] As display panels evolve towards higher resolution, narrower bezels, and larger sizes, external gate-level driver circuits struggle to meet the requirements of wiring area, cost, and high-speed scanning. Consequently, display panels employing Gate Driver on Array (GOA) technology are gradually becoming mainstream. In related technologies, GOA circuits achieve scanning in both top-down and bottom-up directions by switching power supply polarity. However, switching power supply polarity can cause transient shocks and flickering, leading to decreased display stability.
[0003] Therefore, how to achieve stability in bidirectional scanning is an urgent problem to be solved. Summary of the Invention
[0004] This application provides a gate driving circuit and a display panel that solves the problem of poor stability in bidirectional scanning.
[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit comprising: N cascaded gate driving units, each gate driving unit comprising: a forward scan module, a reverse scan module, and an output module connected to a driving control node; the forward scan module has a forward scan control node, and the reverse scan module has a reverse scan control node; when the gate driving unit is the nth stage, the nth stage is an intermediate stage among the N gate driving units; the forward scan module is configured to receive the nith stage cascade signal output by the nith stage output module and the nd stage forward scan control signal output by the nd stage forward scan control node. The signal is used to precharge the drive control node to obtain the forward scan precharge voltage; where d is less than i; the reverse scan module is configured to precharge the drive control node to obtain the reverse scan precharge voltage based on the (n+i)th stage transmission signal output by the (n+i)th stage output module and the (n+d)th stage reverse scan control signal output by the (n+d)th stage reverse scan control node; the output module is connected to the nth stage clock signal line and is configured to output the forward scan drive signal based on the nth stage clock signal and the forward scan precharge voltage, and output the reverse scan drive signal based on the nth stage clock signal and the reverse scan precharge voltage.
[0006] Optionally, when the gate driving unit is the -i-th stage, the -i-th stage is the first stage among the N gate driving units; the forward scan module is configured to pre-charge the drive control node according to the forward scan start signal to obtain a forward scan pre-charge voltage; the output module is connected to the clock signal line of the -i-th stage and is configured to output a forward scan drive signal according to the clock signal of the -i-th stage and the forward scan pre-charge voltage; when the gate driving unit is the M+i-th stage, the M+i-th stage is the last stage among the N gate driving units; the reverse scan module is configured to pre-charge the drive control node according to the reverse scan start signal to obtain a reverse scan pre-charge voltage; the output module is also configured to output a reverse scan drive signal according to the clock signal of the M+i-th stage and the reverse scan pre-charge voltage; wherein, during the scanning process, the voltage polarities of the forward scan start signal and the reverse scan start signal are opposite.
[0007] Optionally, the forward scan module is further configured to pull the drive control node low based on the (n+i)th stage transmission signal output by the (n+i)th stage output module and the nth stage forward scan control signal output by the forward scan control node.
[0008] Optionally, the forward scan module includes: a first transistor, a first capacitor, a second transistor, and a third transistor; the control terminal of the first transistor is connected to the nd-th stage forward scan control node, the first terminal of the first transistor is connected to a high-level terminal, and the second terminal of the first transistor, the first terminal of the first capacitor, and the control terminal of the second transistor are connected to the forward scan control node; the second terminal of the first capacitor is connected to a low-level terminal; the first terminal of the second transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the second transistor is connected to the control terminal of the third transistor; the first terminal of the third transistor is connected to the high-level terminal, and the second terminal of the third transistor is connected to the drive control node.
[0009] Optionally, the forward scan module further includes: a fourth transistor and a fifth transistor; the control terminal of the fourth transistor is connected to the nth-level forward scan control node, the first terminal of the fourth transistor is connected to the stage transmission output terminal of the (n+i)th-level output module, and the second terminal of the fourth transistor is connected to the control terminal of the fifth transistor; the first terminal of the fifth transistor is connected to the drive control node, and the second terminal of the fifth transistor is connected to the low-level terminal.
[0010] Optionally, the backscan module is further configured to pull the drive control node low based on the nith stage transmission signal output by the nith stage output module and the nth stage backscan control signal output by the backscan control node.
[0011] Optionally, the reverse scan module includes: a sixth transistor, a second capacitor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the control terminal of the sixth transistor is connected to the (n+d)th stage reverse scan control node, the first terminal of the sixth transistor is connected to a high-level terminal, and the second terminal of the sixth transistor, the first terminal of the second capacitor, and the control terminal of the seventh transistor are connected to the reverse scan control node; the first terminal of the seventh transistor is connected to the stage output terminal of the nith stage output module, and the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor; the first terminal of the eighth transistor is connected to the drive control node, and the second terminal of the eighth transistor is connected to a low-level terminal; the control terminal of the ninth transistor is connected to the nth stage reverse scan control node, the first terminal of the ninth transistor is connected to the stage output terminal of the (n+i)th stage output module, and the second terminal of the ninth transistor is connected to the control terminal of the tenth transistor; the first terminal of the tenth transistor is connected to a high-level terminal, and the second terminal of the tenth transistor is connected to the drive control node.
[0012] Optionally, the forward scan module includes: a first transistor, a first capacitor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the control terminal of the first transistor is connected to the nd-th stage forward scan control node, the first terminal of the first transistor is connected to a high-level terminal, and the second terminal of the first transistor, the first terminal of the first capacitor, the first terminal of the second transistor, and the first terminal of the third transistor are connected to the forward scan control node; the second terminal of the first capacitor, the second terminal of the second transistor, and the second terminal of the fourth transistor are connected to a low-level terminal; the control terminal of the second transistor is connected to the first terminal of the fourth transistor and the second terminal of the fifth transistor; the control terminal of the third transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the third transistor is connected to the drive control node; the control terminal of the fourth transistor is connected to the forward scan control node; the control terminal and the first terminal of the fifth transistor are connected to the high-level terminal.
[0013] Optionally, the reverse scan module includes: a sixth transistor, a seventh transistor, a second capacitor, an eighth transistor, a ninth transistor, and a tenth transistor; the control terminal of the sixth transistor is connected to the stage output terminal of the (n+i)th stage output module; the first terminal of the sixth transistor, the second terminal of the seventh transistor, the first terminal of the second capacitor, and the first terminal of the eighth transistor are connected to the reverse scan control node; the second terminal of the sixth transistor is connected to the drive control node; the control terminal of the seventh transistor is connected to the (n+d)th stage reverse scan control node; the first terminal of the seventh transistor is connected to a high-level terminal; the second terminal of the second capacitor, the second terminal of the eighth transistor, and the second terminal of the ninth transistor are connected to a low-level terminal; the control terminal of the eighth transistor is connected to the first terminal of the ninth transistor and the second terminal of the tenth transistor; the control terminal of the ninth transistor is connected to the reverse scan control node; the control terminal and the first terminal of the tenth transistor are connected to the high-level terminal.
[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.
[0015] The technical solution provided in this application has at least the following beneficial effects:
[0016] By setting up a forward scan module to precharge the drive control node and generate a forward precharge voltage, and a reverse scan module to precharge the drive control node and generate a reverse precharge voltage, the drive control node is connected to the output module. When the output module receives the nth-level clock signal and the forward precharge voltage, it outputs a forward scan drive signal; and when the transmission module receives the nth-level clock signal and the reverse precharge voltage, it outputs a reverse scan signal, thereby realizing independent control of forward and reverse scans without changing the power supply polarity. This avoids transient impacts and flickering in the gate drive unit, thus ensuring the stability of the bidirectional scan process. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0018] Figure 1 A schematic diagram of a gate driving circuit provided in an embodiment of this application is shown.
[0019] Figure 2A circuit diagram of a -i-th stage gate drive unit provided in an embodiment of this application is shown.
[0020] Figure 3 A circuit diagram of an nth-stage gate drive unit provided in an embodiment of this application is shown.
[0021] Figure 4 The diagram shows a circuit diagram of a gate driving unit of the M+ith stage provided in an embodiment of this application.
[0022] Figure 5 The diagram shows a waveform of a forward scan process provided in an embodiment of this application.
[0023] Figure 6 The diagram shows a waveform of a reverse scan process provided in an embodiment of this application.
[0024] Figure 7 A circuit diagram of another -i-th stage gate drive unit provided in an embodiment of this application is shown.
[0025] Figure 8 A circuit diagram of another nth-stage gate drive unit provided in an embodiment of this application is shown.
[0026] Figure 9 A circuit diagram of another M+i-th stage gate drive unit provided in an embodiment of this application is shown.
[0027] Figure 10 The diagram shows a waveform of another forward scan process provided in an embodiment of this application.
[0028] Figure 11 The diagram shows a waveform of another reverse scan process provided in an embodiment of this application.
[0029] Explanation of reference numerals in the attached figures:
[0030] 100. Gate driving unit; 110. Forward scan module; 120. Reverse scan module; 130. Output module; 140. Reset module; 150. Noise reduction module; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor; T11. Eleventh transistor; T12. Twelfth transistor; T13. Tenth transistor; Three transistors; T14, the fourteenth transistor; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; VDD, the high-level terminal; VSS, the low-level terminal; CK, the clock signal line; Q, the drive control node; A, the forward scan control node; B, the reverse scan control node; C, the forward scan interlock node; D, the reverse scan interlock node; STV1, the output terminal of the forward scan start signal; STV2, the output terminal of the reverse scan start signal; Reset, the output terminal of the reset signal; LC1 / LC2, the output terminals of the noise reduction signal. Detailed Implementation
[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.
[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.
[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.
[0034] Figure 1 A schematic diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1As shown, the gate drive circuit includes N cascaded gate drive units 100. Each gate drive unit 100 includes a forward scan module 110, a reverse scan module 120, and an output module 130 connected to the drive control node Q (commonly known as the Q point). The forward scan module 110 has a forward scan control node A, and the reverse scan module 120 has a reverse scan control node B.
[0035] In some embodiments, the N cascaded gate driving units 100 include: i first-stage gate driving units, M intermediate-stage gate driving units, and i last-stage gate driving units; the i first-stage gate driving units and the i last-stage gate driving units are dummy stages, i.e., virtual stages. For example, when the display has 1080 stages and the cascading architecture is -2 / 2, i is 2 and M is 1080. Where d is less than i; when i is 2, d can be 1, enabling the step-by-step transmission of forward scan control signals or reverse scan control signals.
[0036] For example, when i is 2, it indicates that there are two first-stage gate driving units and two last-stage gate driving units. The two first-stage gate driving units include the -2nd stage and the -1st stage, and the two last-stage gate driving units include the 1080+1th stage and the 1080+2nd stage. The figure shows an embodiment where i is 2 and d is 1. When n is 1, the nith stage is the -2nd stage, and the ndth stage is the -1st stage.
[0037] In the diagram, CK1···CKx-1, CKx, CKx+1···CKy represent clock signal lines. In this embodiment, an 8CK clock signal can be used. B(n+d) represents the output terminal of point B in the (n+d)th stage. F(-i) represents the stage transmission output terminal of the (-i)th stage output module. G(-i) represents the drive output terminal of the (-i)th stage output module. F(ni) represents the stage transmission output terminal of the nith stage output module. A(nd) represents the output terminal of point A in the ndth stage. F(nd) represents the stage transmission output terminal of the ndth stage output module. F(n+i) represents the stage transmission output terminal of the (n+i)th stage output module. F(n) represents the stage transmission output terminal of the nth stage output module. G(n) represents the drive output terminal of the nth stage output module. A(M+id) represents the output terminal of point A in the (M+id)th stage. G(M+i) represents the drive output terminal of the (m+i)th stage output module. F(M+i) represents the stage transmission output terminal of the (M+i)th stage output module.
[0038] When the gate driving unit 100 is the nth stage, the nth stage is the intermediate stage of the N gate driving units 100.
[0039] In some embodiments, the forward scan module 110 is configured to precharge the drive control node Q to obtain the forward scan precharge voltage based on the nith stage transmission signal output by the nith stage output module 130 and the nd stage forward scan control signal output by the nd stage forward scan control node A.
[0040] For example, when the forward scanning module 110 receives the ni-th level transmission signal to limit the scanning direction, it receives the nd-th level forward scanning control signal to precharge the drive control node Q, so that the drive control node Q generates a forward scanning precharge voltage, thereby realizing transmission and precharging in the forward scanning direction.
[0041] In some embodiments, the backscan module 120 is configured to precharge the drive control node Q to obtain the backscan precharge voltage based on the n+i-th stage transmission signal output by the n+i-th stage output module 130 and the n+d-th stage backscan control signal output by the n+d-th stage backscan control node B.
[0042] For example, when the backscan module 120 receives the (n+i)th level transmission signal to limit the scanning direction, it receives the (n+d)th level backscan control signal to precharge the drive control node Q, so that the drive control node Q generates a backscan precharge voltage, thereby realizing transmission and precharging in the backscan direction.
[0043] In some embodiments, the output module 130 is connected to the nth-level clock signal line and is configured to output a forward scan drive signal according to the nth-level clock signal and the forward scan precharge voltage, and to output a reverse scan drive signal according to the nth-level clock signal and the reverse scan precharge voltage.
[0044] For example, by pre-charging the drive control node Q, which is connected to the output module 130, when the output module 130 receives the nth-level clock signal and the forward pre-charge voltage, it outputs a forward scan drive signal; and when the output module 130 receives the nth-level clock signal and the reverse pre-charge voltage, it outputs a reverse scan signal, thereby realizing independent control of forward and reverse scans without changing the power supply polarity. This avoids transient impacts and flickering in the gate drive unit 100, thus ensuring the stability of the bidirectional scan process.
[0045] Please see Figure 1As shown, when the gate driving unit 100 is the -ith stage, the -ith stage is the first stage among the N gate driving units 100; the forward scan module 110 is configured to precharge the drive control node Q according to the forward scan start signal to obtain the forward scan precharge voltage; the output module 130 is connected to the clock signal line of the -ith stage and is configured to output the forward scan drive signal according to the clock signal of the -ith stage and the forward scan precharge voltage; when the gate driving unit 100 is the M+ith stage, the M+ith stage is the last stage among the N gate driving units 100; the reverse scan module 120 is configured to precharge the drive control node Q according to the reverse scan start signal to obtain the reverse scan precharge voltage; the output module 130 is also configured to output the reverse scan drive signal according to the clock signal of the M+ith stage and the reverse scan precharge voltage; wherein, during the scanning process, the voltage polarities of the forward scan start signal and the reverse scan start signal are opposite.
[0046] In some embodiments, when the gate driving unit 100 is at the -ith stage, the forward scan module 110 precharges the drive control node Q according to the forward scan start signal; when the gate driving unit 100 is at the M+ith stage, the reverse scan module 120 precharges the drive control node Q according to the reverse scan start signal. During the scanning process, by setting the voltage polarities of the forward scan start signal and the reverse scan start signal to be opposite, the forward scan process and the reverse scan process are interlocked. During the forward scan process, the reverse scan cannot be started, and during the reverse scan process, the forward scan cannot be started.
[0047] For example, when the forward scan start signal is high, the forward scan process will be started; when the reverse scan start signal is high, the reverse scan process will be started. When the forward scan process is started, the forward scan start signal is set to high and the reverse scan start signal is set to low; when the reverse scan process is started, the reverse scan start signal is set to high and the forward scan start signal is set to low, thereby achieving interlocking between the forward scan and reverse scan processes.
[0048] In some embodiments, the forward scan module 110 is further configured to pull the drive control node Q low based on the (n+i)th stage transmission signal output by the (n+i)th stage output module 130 and the nth stage forward scan control signal output by the forward scan control node A.
[0049] For example, after the output module 130 of this stage outputs the gate drive signal, the voltage of the drive control node Q needs to be pulled low so that the drive control node Q can be pre-charged again at the beginning of the next frame scan cycle; the forward scan module 110 determines that the drive control node Q of this stage has been pre-charged by receiving the control of the nth stage forward scan control signal; and determines that the output module 130 has output the gate drive signal for a sufficient time by receiving the control of the (n+i)th stage cascade signal, so that the drive control node Q is pulled low when the (n+i)th stage cascade signal and the nth stage forward scan control signal are received.
[0050] In some embodiments, the backscan module 120 is further configured to pull the drive control node Q low based on the ni-th stage transmission signal output by the ni-th stage output module 130 and the n-th stage backscan control signal output by the backscan control node B.
[0051] For example, the reverse scan module 120 determines that the current drive control node Q has been pre-charged by receiving the control signal of the nth stage forward scan; and determines that the output module 130 has output the gate drive signal for a sufficient time by receiving the control signal of the nith stage cascade; thereby pulling the drive control node Q low when the nith stage cascade signal and the nth stage reverse scan control signal are received.
[0052] Figure 2 This paper shows a circuit diagram of a -i-th stage gate driving unit according to an embodiment of the present application. Figure 3 This paper shows a circuit diagram of an nth-stage gate driving unit according to an embodiment of this application. Figure 4 This paper shows a circuit diagram of a gate driving unit at the M+i level according to an embodiment of this application. Please refer to [link / reference]. Figure 2 , Figure 3 and Figure 4 As shown, the forward scan module 110 of each gate drive unit 100 includes: a first transistor T1, a first capacitor C1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5; the first terminal of the first transistor T1 is connected to the high-level terminal VDD, and the second terminal of the first transistor T1, the first terminal of the first capacitor C1, and the control terminal of the second transistor T2 are connected to the forward scan control node A; the second terminal of the first capacitor C1 is connected to the low-level terminal VSS; the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3; the first terminal of the third transistor T3 is connected to the high-level terminal VDD, and the second terminal of the third transistor T3 is connected to the drive control node Q; the second terminal of the fourth transistor T4 is connected to the control terminal of the fifth transistor T5; the first terminal of the fifth transistor T5 is connected to the drive control node Q, and the second terminal of the fifth transistor T5 is connected to the low-level terminal VSS.
[0053] In the diagram, A(-2) represents the output terminal of point A in the -2nd stage; Reset represents the output terminal of the reset signal; LC1 / LC2 represents the output terminal of the noise reduction low-frequency control signal; B(-1) represents the output terminal of point B in the -1st stage; B(-2) represents the output terminal of point B in the -2nd stage; F(1) represents the stage transmission output terminal of the 1st stage output module; G(-2) represents the drive output terminal of the -2nd stage output module; F(n-2) represents the stage transmission output terminal of the (n-2)th stage output module; F(n-1) represents the (n-1)th stage... The output module's stage transmission output terminal; B(n-1) represents the output terminal of point B in the (n-1)th stage; A(1081) represents the output terminal of point A in the 1081st stage; A(1082) represents the output terminal of point A in the 1082nd stage; F(1082) represents the stage transmission output terminal of the 1082nd stage output module; F(1080) represents the stage transmission output terminal of the 1080th stage output module; G(1082) represents the drive output terminal of the 1082nd stage output module; B(1082) represents the output terminal of point B in the 1082nd stage.
[0054] Please see Figure 2 As shown, when the gate driving unit 100 is the -ith stage, the control terminal of the first transistor T1 is connected to the output terminal of the forward scan start signal, the first terminal of the second transistor T2 is connected to the output terminal of the forward scan start signal, the control terminal of the fourth transistor T4 is connected to the -ith stage forward scan control node A, and the first terminal of the fourth transistor T4 is connected to the stage transmission output terminal of the first stage output module 130.
[0055] For example, the output of the forward scan start signal can be the output of an external timing controller. When the forward scan start signal is a high-level signal, the first transistor T1 is turned on, the high-level terminal VDD charges the first capacitor C1, and the control terminal of the second transistor T2 receives the high-level signal output from the high-level terminal VDD and turns on. Consequently, the control terminal of the third transistor T3 receives the high-level signal and turns on. The high-level terminal VDD pre-charges the drive control node Q to obtain the forward scan pre-charge voltage, thereby starting the forward scan process. The first capacitor C1 is used to store the forward scan control signal of the forward scan control node A for cascading transmission of the forward scan control signal.
[0056] The pull-down process of the drive control node Q is as follows: When the control terminal of the fourth transistor T4 receives the -i-th stage forward scan drive signal, such as the -2-th stage forward scan drive signal, the control terminal of the fourth transistor T4 receives the first stage transmission signal, which is a high-level signal; the fourth transistor T4 will turn on, and the control terminal of the fifth transistor T5 will receive the high-level signal and turn on. The drive control node Q connected to the second terminal of the fifth transistor T5 will be connected to the low-level terminal VSS, thereby pulling the drive control node Q low after outputting the current stage forward scan drive signal. It should be noted that the pull-down process of the n-th stage gate drive unit 100 works in the same way as the -i-th stage, and will not be described again later.
[0057] Figure 5 The diagram shows a waveform of a forward scan process according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 5 As shown, when the gate driving unit 100 is the nth stage, the control terminal of the first transistor T1 is connected to the nd-th stage forward scan control node A, the first terminal of the second transistor T2 is connected to the stage transmission output terminal of the ni-th stage output module 130, the control terminal of the fourth transistor T4 is connected to the n-th stage forward scan control node A, and the first terminal of the fourth transistor T4 is connected to the stage transmission output terminal of the (n+i)-th stage output module 130.
[0058] For example, during the forward scan, the first terminal of the second transistor T2 will receive the ni-th stage transmission signal, such as the (n-2)-th stage transmission signal, i.e., a high-level signal. The control terminal of the first transistor T1 will receive the ni-th stage forward scan control signal, i.e., a high-level signal, and the first transistor T1 will turn on. The first terminal of the first transistor T1 will receive the high-level signal and transmit it to the control terminal of the second transistor T2. After receiving the high-level signal, the control terminal of the second transistor T2 will turn on. The control terminal of the third transistor T3 will receive the ni-th stage transmission signal, and the high-level terminal VDD will precharge the drive control node Q to obtain the forward scan precharge voltage.
[0059] Please see Figure 4 As shown, when the gate driving unit 100 is at the M+i level, the control terminal of the first transistor T1 is connected to the forward scan control node A of the M+id level, the first terminal of the second transistor T2 is connected to the stage transmission output terminal of the M-level output module 130, the control terminal of the fourth transistor T4 is connected to the forward scan control node A of the M+i level, and the first terminal of the fourth transistor T4 is connected to the output terminal of the forward scan start signal.
[0060] For example, when the control terminal of the fourth transistor T4 receives the M+i-th level reverse scan control signal, such as the 1082-th level reverse scan control signal, the first terminal of the fourth transistor T4 is always the forward scan start signal. After the fourth transistor T4 is turned on, it transmits the forward scan start signal to the control terminal of the fifth transistor T5. The fifth transistor T5 will then be turned on, thereby pulling the drive control node Q down to the low level terminal VSS. The third transistor T3 will then be unable to charge the drive control node Q, thus ending the forward scan.
[0061] Please see Figure 2 , Figure 3 , Figure 4 and Figure 5 The forward scan module 110 also includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the output terminal of the reset signal. The first terminal of the eleventh transistor T11 is connected to the forward scan control node A, and the second terminal of the eleventh transistor T11 is connected to the low-level terminal VSS.
[0062] For example, during the scanning of N gate driving units 100, the forward scan control node A is kept at a high potential. At the end of the first scan signal, that is, when the N gate driving units 100 are scanned, a reset signal is sent to the control terminal of the eleventh transistor T11. The reset signal is a high-level signal, which turns on the eleventh transistor T11 and pulls the forward scan control node A down to the low-level terminal VSS to discharge the forward scan control node A.
[0063] Please see Figure 2 , Figure 3 and Figure 4 As shown, the reverse scan module 120 of each gate drive unit 100 includes: a sixth transistor T6, a second capacitor C2, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the first terminal of the sixth transistor T6 is connected to the high-level terminal VDD, and the second terminal of the sixth transistor T6, the first terminal of the second capacitor C2, and the control terminal of the seventh transistor T7 are connected to the reverse scan control node B; the second terminal of the seventh transistor T7 is connected to the control terminal of the eighth transistor T8; the first terminal of the eighth transistor T8 is connected to the drive control node Q, and the second terminal of the eighth transistor T8 is connected to the low-level terminal VSS; the second terminal of the ninth transistor T9 is connected to the control terminal of the tenth transistor T10, the first terminal of the tenth transistor T10 is connected to the high-level terminal VDD, and the terminal of the tenth transistor T10 is connected to the drive control node Q.
[0064] Please see Figure 4As shown, when the gate drive unit 100 is at the M+i level, the control terminal of the sixth transistor T6 is connected to the output terminal of the reverse scan start signal, the first terminal of the seventh transistor T7 is connected to the transmission output terminal of the Mi level, the control terminal of the ninth transistor T9 is connected to the reverse scan control node B of the M+i level, and the second terminal of the ninth transistor T9 is connected to the output terminal of the reverse scan start signal.
[0065] For example, the output of the backscan start signal can be the output of an external timing controller. When the backscan start signal is a high-level signal, the sixth transistor T6 turns on to charge the second capacitor C2 and generates a backscan control signal on the backscan control node B. The control terminal of the ninth transistor T9 receives the cascade signal output from the backscan control node B and turns on. The control terminal of the tenth transistor T10 receives the backscan start signal through the first terminal of the ninth transistor T9 and turns on, thereby pre-charging the drive control node Q to obtain the backscan pre-charge voltage and starting the backscan process. The backscan control signal of the backscan control node B is stored through the second capacitor C2, thereby enabling the backscan control signal to be cascaded.
[0066] The pull-down process works as follows: When the control terminal of the seventh transistor T7 receives the backscan control signal generated by the backscan control node B and is turned on, and when the control terminal of the seventh transistor T7 receives the stage transmission signal of the (n+i)th stage, the stage transmission signal of the (n+i)th stage is a high-level signal, the eighth transistor T8 will be turned on, and the drive control node Q will be connected to the low-level terminal VSS, thereby pulling the drive control node Q low. It should be noted that the working principle of the pull-down process of the nth stage gate drive unit 100 is the same as that of the (-i)th stage, and will not be described again hereafter.
[0067] Figure 6 The diagram shows a waveform of a reverse scan process according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 6 As shown, when the gate drive unit 100 is the nth stage, the control terminal of the sixth transistor T6 is connected to the reverse sweep control node B of the (n+d)th stage, the first terminal of the seventh transistor T7 is connected to the stage transmission output terminal of the nith stage, and the first terminal of the ninth transistor T9 is connected to the stage transmission output terminal of the (n+i)th stage output module 130.
[0068] For example, during the reverse scan process, the control terminal of the sixth transistor T6 receives the reverse scan control signal of the (n+d)th stage. The reverse scan control signal of the (n+d)th stage is a high-level signal. The sixth transistor T6 is turned on to charge the second reverse scan capacitor C2 and generates a reverse scan control signal at the reverse scan control node B. The control terminal of the ninth transistor T9 will receive the reverse scan control signal output by the reverse scan control node B of this stage and be turned on. The control terminal of the tenth transistor T10 will be turned on through the (n+i)th stage transmission signal received by the first terminal of the ninth transistor T9, thereby pre-charging the drive control node Q to obtain the reverse scan pre-charge voltage.
[0069] Please see Figure 2 As shown, when the gate drive unit 100 is at the -i level, the control terminal of the sixth transistor T6 is connected to the -i+d level reverse scan control node B, the first terminal of the seventh transistor T7 is connected to the output terminal of the reverse scan start signal, the control terminal of the ninth transistor T9 is connected to the -i level reverse scan control node B, and the first terminal of the ninth transistor T9 is connected to the output terminal of the first level transmission output module 130.
[0070] For example, when the control terminal of the sixth transistor T6 receives the -i+d level reverse scan control signal, i.e., a high-level signal, the sixth transistor T6 will turn on. The first terminal of the seventh transistor T7 always receives the reverse scan start signal. When the reverse scan start signal is a high-level signal, the control terminal of the seventh transistor T7 will receive the high-level signal transmitted from the first terminal of the sixth transistor and turn on. The control terminal of the eighth transistor T8 will receive the reverse scan start signal output from the first terminal of the seventh transistor T7 and turn on to pull the drive control node Q low. The ninth transistor T9 and the tenth transistor T10 will not precharge the drive control node Q, thereby ending the reverse scan.
[0071] Please see Figure 2 , Figure 3 and Figure 4 As shown, the reverse scan module 120 also includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is connected to the output terminal of the reset signal. The first terminal of the twelfth transistor T12 is connected to the reverse scan control node B. The second terminal of the twelfth transistor T12 is connected to the low-level terminal VSS.
[0072] For example, during the scanning process of N gate driving units 100, the reverse scan control node B is kept at a high potential. At the end of the first scan signal, that is, when the N gate driving units 100 are reverse scanned, a reset signal is sent to the control terminal of the twelfth transistor T12. The reset signal is a high-level signal, which controls the twelfth transistor T12 to turn on. The reverse scan control node B is pulled down to the low-level terminal VSS to discharge the reverse scan control node B.
[0073] Figure 7This paper shows a circuit diagram of another -i-th stage gate drive unit provided in an embodiment of this application. Figure 8 The diagram shows another circuit diagram of the nth stage gate drive unit provided in an embodiment of this application. Figure 9 This paper shows a circuit diagram of another M+i-th stage gate drive unit provided in an embodiment of this application. Please refer to [link / reference]. Figure 7 , Figure 8 and Figure 9 As shown, the forward scan module 110 includes: a first transistor T1, a first capacitor C1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5; the first terminal of the first transistor T1 is connected to the high-level terminal VDD, and the second terminals of the first transistor T1, the first terminals of the first capacitor C1, the second transistor T2, and the third transistor T3 are connected to the forward scan control node A; the second terminals of the first capacitor C1, the second transistor T2, and the fourth transistor T4 are connected to the low-level terminal VSS; the control terminal of the second transistor T2 is connected to the first terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5; the second terminal of the third transistor T3 is connected to the drive control node Q; the control terminal of the fourth transistor T4 is connected to the forward scan control node A; and the control terminal and the first terminal of the fifth transistor T5 are connected to the high-level terminal VDD.
[0074] Please see Figure 7 , Figure 8 and Figure 9 As shown, the reverse scan module 120 includes: a sixth transistor T6, a seventh transistor T7, a second capacitor C2, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the first terminal of the sixth transistor T6, the second terminal of the seventh transistor T7, the first terminal of the second capacitor C2, and the first terminal of the eighth transistor T8 are connected to the reverse scan control node B, and the second terminal of the sixth transistor T6 is connected to the drive control node Q; the first terminal of the seventh transistor T7 is connected to the high-level terminal VDD; the second terminal of the second capacitor C2, the second terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9 are connected to the low-level terminal VSS; the control terminal of the eighth transistor T8 is connected to the first terminal of the ninth transistor T9 and the second terminal of the tenth transistor T10; the control terminal of the ninth transistor T9 is connected to the reverse scan control node B; the control terminal and the first terminal of the tenth transistor T10 are connected to the high-level terminal VDD.
[0075] Please see Figure 7 , Figure 8 and Figure 9 As shown, the forward scan module 110 also includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the stage transmission output terminal of the (n+i)th stage output module 130. The first terminal of the eleventh transistor T11 is connected to the forward scan control node A, and the second terminal of the eleventh transistor T11 is connected to the low-level terminal VSS.
[0076] For example, when the control terminal of the eleventh transistor T11 receives the (n+i)th stage transmission signal, which is a high-level signal, the eleventh transistor T11 will be turned on, pulling the forward scan control node A down to the low-level terminal VSS, thus discharging the forward scan control node A.
[0077] Please see Figure 7 , Figure 8 and Figure 9 As shown, the reverse scan module 120 also includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is connected to the stage output terminal of the ni-th stage output module 130. The first terminal of the twelfth transistor T12 is connected to the reverse scan control node B, and the second terminal of the twelfth transistor T12 is connected to the low-level terminal VSS.
[0078] For example, when the control terminal of the twelfth transistor T12 sends the nith stage transmission signal, which is a high-level signal, the twelfth transistor T12 will be turned on, pulling the reverse scan control node B down to the low-level terminal VSS, thus discharging the reverse scan control node B.
[0079] Please see Figure 7 As shown, when the gate driving unit 100 is at the -ith stage, the control terminal of the first transistor T1 is connected to the output terminal of the forward scan start signal, the control terminal of the third transistor T3 is connected to the output terminal of the forward scan start signal, the control terminal of the eleventh transistor T11 is connected to the stage transmission output terminal of the first stage output module 130, the control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the first stage output module 130, the control terminal of the seventh transistor T7 is connected to the -i+dth stage reverse scan control node B, and the control terminal of the twelfth transistor T12 is connected to the output terminal of the reverse scan start signal.
[0080] For example, during the forward scan process, when the forward scan start signal is a high-level signal, the first transistor T1 is turned on, which will charge the first capacitor C1 and generate a forward scan control signal at the forward scan control node A. The control terminal of the third transistor T3 receives the forward scan start signal, and the first terminal of the third transistor T3 is connected to the high-level terminal VDD through the first terminal of the first transistor T1, which will precharge the drive control node Q to generate a forward scan precharge voltage, thereby starting the forward scan process.
[0081] It should be noted that when the forward scan start signal is high, the forward scan control signal output by forward scan control node A will control the fourth transistor T4 to turn on, thereby pulling forward scan control node A low and charging it. During reverse scan, when the forward scan start signal is low, the control terminal and the first terminal of the fifth transistor T5 will receive a high-level signal. The forward scan interlock node will also receive a high-level signal, controlling the second transistor T2 to turn on, pulling forward scan control node A low, preventing the forward scan process from starting. This prevents erroneous input of the forward scan start signal during reverse scan.
[0082] In some embodiments, during the forward scan process, after the transmission module outputs the gate drive signal of this stage according to the forward scan precharge voltage, the control terminal of the sixth transistor T6 receives the first stage transmission signal, and the control terminal and the first terminal of the eighth transistor T8 receive a high-level signal, making the eighth transistor T8 in a conducting state. The second terminal of the sixth transistor T6 is connected to the low-level terminal VSS through the eighth transistor T8, which can pull down the drive control node Q to the low-level terminal VSS. It should be noted that when the gate drive unit 100 is the nth stage, the working principle of the pull-down process of the drive control node Q is the same as that of the i-th stage gate drive unit 100, and will not be described again hereafter.
[0083] Figure 10 The following is a waveform diagram of another forward scan process provided in an embodiment of this application. Please refer to [link / reference]. Figure 8 and Figure 10 As shown, when the gate driving unit 100 is the nth stage, the control terminal of the first transistor T1 is connected to the forward scan control node A of the nd stage, the control terminal of the third transistor T3 is connected to the stage transmission output terminal of the nith stage output module 130, the control terminal of the eleventh transistor T11 is connected to the stage transmission output terminal of the (n+i)th stage output module 130, the control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the (n+i)th stage output module 130, the control terminal of the seventh transistor T7 is connected to the reverse scan control node B of the (n+d)th stage, and the control terminal of the twelfth transistor T12 is connected to the stage transmission output terminal of the nith stage output module 130.
[0084] For example, when the control terminal of the first transistor T1 receives the nd-th stage forward scan control signal, the first transistor T1 is turned on, charging the first capacitor C1 and generating a forward scan control signal at the forward scan control node A. The control terminal of the third transistor T3 receives the ni-th stage transmission signal, and the first terminal of the third transistor T3 is connected to the high-level terminal VDD through the first terminal of the first transistor T1, pre-charging the drive control node Q to generate a forward scan pre-charge voltage, thereby starting the forward scan process.
[0085] It should be noted that when the first transistor T1 receives the nd-th level forward scan control signal, the forward scan control signal output by the forward scan control node A will control the fourth transistor T4 to turn on, thereby pulling the forward scan interlock node low and enabling charging of the forward scan control node A. When the first transistor T1 does not receive the nd-th level forward scan control signal, the control terminal and the first terminal of the fifth transistor T5 will receive a high-level signal, the forward scan interlock node will receive a high-level signal, controlling the second transistor T2 to turn on, pulling the forward scan control node A low.
[0086] Please see Figure 9 As shown, when the gate driving unit 100 is at the M+i level, the control terminal of the first transistor T1 is connected to the forward scan control node A of the M+id level, the control terminal of the third transistor T3 is connected to the stage transmission output terminal of the M-level output module 130, the control terminal of the eleventh transistor T11 is connected to the output terminal of the forward scan start signal, the control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the M+i level output module 130, the control terminal of the seventh transistor T7 is connected to the reverse scan control node B of the M+id level, and the control terminal of the twelfth transistor T12 is connected to the stage transmission output terminal of the M-level output module 130.
[0087] For example, when the forward scan start signal is a high-level signal, the forward scan control node A is pulled down to the low-level terminal VSS, and the M+i-th level forward scan control node A will not be able to be charged, thus ending the forward scan process.
[0088] Figure 11 The waveform diagram of another reverse scan process provided in this application embodiment is shown below. Please refer to [link / reference]. Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 As shown, the reverse scan process will scan from the M+ith level to the -ith level. The circuit structure and working principle of the reverse scan module 120 are the same as those of the forward scan module 110, and will not be described again here.
[0089] In some embodiments, the output module 130 of each gate drive unit 100 includes: a thirteenth transistor T13, a fourteenth transistor T14, and a third capacitor C3; the control terminal of the thirteenth transistor T13, the control terminal of the fourteenth transistor T14, and the first terminal of the third capacitor C3 are connected to the drive control node Q; the first terminal of the thirteenth transistor T13 is connected to the clock signal line of the current stage, the second terminal of the thirteenth transistor T13 is the stage output terminal, the first terminal of the fourteenth transistor T14 is connected to the clock signal line of the current stage, and the second terminal of the fourteenth transistor T14 is connected to the second terminal of the second capacitor C2 and serves as the drive output terminal.
[0090] For example, when the thirteenth transistor T13 and the fourteenth transistor T14 receive the forward scan precharge voltage or the reverse scan precharge voltage, the first terminal of the thirteenth transistor T13 and the first terminal of the fourteenth transistor T14 receive the clock signal of this stage, the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the stage transmission output terminal of the thirteenth transistor T13 outputs the stage transmission signal, and the drive output terminal of the fourteenth transistor T14 outputs the forward scan drive signal or the reverse scan drive signal.
[0091] In some embodiments of this application, each gate drive unit 100 further includes a reset control module and a noise reduction module 150 connected to the drive control node Q. The reset module 140 is configured to reset the drive control node Q according to a reset signal; the noise reduction control module is configured to reduce noise in the drive control node Q according to a noise reduction signal.
[0092] In some embodiments of this application, a display panel is also provided, including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit provided in any of the above embodiments. The output module 130 of the gate driving circuit is connected to at least one scan line.
[0093] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0094] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0095] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.
Claims
1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, each gate driving unit including a forward scan module, a reverse scan module and an output module connected to the driving control node; the forward scan module has a forward scan control node and the reverse scan module has a reverse scan control node; when the gate driving unit is the nth stage, the nth stage is the intermediate stage of the N gate driving units; The forward scanning module is configured to precharge the drive control node to obtain the forward scanning precharge voltage based on the ni-th stage transmission signal output by the ni-th stage output module and the nd-th stage forward scanning control signal output by the nd-th stage forward scanning control node; where d is less than i. The backscan module is configured to precharge the drive control node to obtain the backscan precharge voltage based on the (n+i)th stage transmission signal output by the (n+i)th stage output module and the (n+d)th stage backscan control signal output by the (n+d)th stage backscan control node. The output module is connected to the nth-level clock signal line and is configured to output a forward scan drive signal according to the nth-level clock signal and the forward scan precharge voltage, and to output a reverse scan drive signal according to the nth-level clock signal and the reverse scan precharge voltage.
2. The gate driving circuit according to claim 1, characterized in that, When the gate driving unit is the -ith stage, the -ith stage is the first stage among the N gate driving units; The forward scanning module is configured to pre-charge the drive control node according to the forward scanning start signal to obtain the forward scanning pre-charge voltage; The output module is connected to the -ith stage clock signal line and is configured to output a forward scan drive signal according to the -ith stage clock signal and the forward scan precharge voltage. When the gate driving unit is the M+ith stage, the M+ith stage is the tail stage among the N gate driving units; The backscan module is configured to precharge the drive control node according to the backscan start signal to obtain the backscan precharge voltage; The output module is also configured to output a backscan drive signal according to the M+ith level clock signal and the backscan precharge voltage; During the scanning process, the voltage polarity of the forward scan start signal and the reverse scan start signal are opposite.
3. The gate driving circuit according to claim 1, characterized in that, The forward scan module is further configured to pull the drive control node low based on the (n+i)th stage transmission signal output by the (n+i)th stage output module and the nth stage forward scan control signal output by the forward scan control node.
4. The gate driving circuit according to claim 1, characterized in that, The forward scanning module includes: a first transistor, a first capacitor, a second transistor, and a third transistor; The control terminal of the first transistor is connected to the nd-th forward scan control node, the first terminal of the first transistor is connected to the high-level terminal, and the second terminal of the first transistor, the first terminal of the first capacitor, and the control terminal of the second transistor are connected to the forward scan control node. The second terminal of the first capacitor is connected to the low-level terminal; The first terminal of the second transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the second transistor is connected to the control terminal of the third transistor. The first terminal of the third transistor is connected to the high-level terminal, and the second terminal of the third transistor is connected to the drive control node.
5. The gate driving circuit according to claim 4, characterized in that, The forward scanning module further includes: a fourth transistor and a fifth transistor; The control terminal of the fourth transistor is connected to the nth stage forward scan control node, the first terminal of the fourth transistor is connected to the stage transmission output terminal of the (n+i)th stage output module, and the second terminal of the fourth transistor is connected to the control terminal of the fifth transistor. The first terminal of the fifth transistor is connected to the drive control node, and the second terminal of the fifth transistor is connected to the low-level terminal.
6. The gate driving circuit according to claim 1, characterized in that, The backscan module is further configured to pull the drive control node low based on the ni-th stage transmission signal output by the ni-th stage output module and the n-th stage backscan control signal output by the backscan control node.
7. The gate driving circuit according to claim 1, characterized in that, The reverse scan module includes: a sixth transistor, a second capacitor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The control terminal of the sixth transistor is connected to the (n+d)th stage reverse scan control node, the first terminal of the sixth transistor is connected to the high-level terminal, and the second terminal of the sixth transistor, the first terminal of the second capacitor, and the control terminal of the seventh transistor are connected to the reverse scan control node. The first terminal of the seventh transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor. The first terminal of the eighth transistor is connected to the drive control node, and the second terminal of the eighth transistor is connected to the low-level terminal. The control terminal of the ninth transistor is connected to the nth stage reverse scan control node, the first terminal of the ninth transistor is connected to the stage transmission output terminal of the (n+i)th stage output module, and the second terminal of the ninth transistor is connected to the control terminal of the tenth transistor. The first terminal of the tenth transistor is connected to the high-level terminal, and the second terminal of the tenth transistor is connected to the drive control node.
8. The gate driving circuit according to claim 1, characterized in that, The forward scan module includes: a first transistor, a first capacitor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The control terminal of the first transistor is connected to the nd-th forward scan control node, the first terminal of the first transistor is connected to the high-level terminal, and the second terminal of the first transistor, the first terminal of the first capacitor, the first terminal of the second transistor, and the first terminal of the third transistor are connected to the forward scan control node. The second terminal of the first capacitor, the second terminal of the second transistor, and the second terminal of the fourth transistor are connected to the low-level terminal; The control terminal of the second transistor is connected to the first terminal of the fourth transistor and the second terminal of the fifth transistor; The control terminal of the third transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the third transistor is connected to the drive control node. The control terminal of the fourth transistor is connected to the forward scan control node; The control terminal and the first terminal of the fifth transistor are connected to the high-level terminal.
9. The gate driving circuit according to claim 1, characterized in that, The reverse scan module includes: a sixth transistor, a seventh transistor, a second capacitor, an eighth transistor, a ninth transistor, and a tenth transistor; The control terminal of the sixth transistor is connected to the stage output terminal of the (n+i)th stage output module. The first terminal of the sixth transistor, the second terminal of the seventh transistor, the first terminal of the second capacitor, and the first terminal of the eighth transistor are connected to the reverse scan control node. The second terminal of the sixth transistor is connected to the drive control node. The control terminal of the seventh transistor is connected to the (n+d)th stage reverse scan control node, and the first terminal of the seventh transistor is connected to the high-level terminal. The second terminal of the second capacitor, the second terminal of the eighth transistor, and the second terminal of the ninth transistor are connected to the low-level terminal; The control terminal of the eighth transistor is connected to the first terminal of the ninth transistor and the second terminal of the tenth transistor; The control terminal of the ninth transistor is connected to the reverse scan control node; The control terminal and the first terminal of the tenth transistor are connected to the high-level terminal.
10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.