Display panel, driving method thereof and display device

Abstract

The invention discloses a display panel, a driving method thereof and a display device. The display panel comprises a pixel driving circuit, and the pixel driving circuit comprises a driving transistor, a first reset transistor, a threshold compensation transistor and a data writing transistor. In the first reset stage, the first enable level of the first scanning signal controls the first reset transistor to be switched on, the second enable level of the second scanning signal controls the threshold compensation transistor to be switched on, and the duration of the first enable level is larger than that of the second enable level. According to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the enabling time of the first scanning signal is prolonged, so that the driving transistor can be subjected to sufficient and lasting composite action of conduction bias stress (OBS) and negative bias stress (NBS), the ghosting problem of the display panel is improved, and the display effect of the display panel is improved. Meanwhile, thorough resetting of the first node, the second node and the third node of the driving transistor is achieved, and the problem that the brightness of the first frame is abnormal during picture switching is solved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the rapid development of display technology, active-matrix display panels (such as OLED and Micro LED) have been widely used in smartphones, tablets and wearable devices due to their excellent characteristics such as self-illumination, high contrast and fast response.

[0003] However, existing display panels suffer from image retention and abnormal brightness in the first frame, which severely affects the display performance. Summary of the Invention

[0004] This invention provides a display panel and its driving method, as well as a display device, to solve the problems of image retention and abnormal brightness in the first frame.

[0005] According to one aspect of the present invention, a display panel is provided, including a pixel driving circuit, the pixel driving circuit comprising: A driving transistor, wherein the driving transistor and the light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line; A first reset transistor, wherein the gate of the first reset transistor is electrically connected to a first scan signal line providing a first scan signal, the first terminal of the first reset transistor is electrically connected to a first reference voltage signal line providing a first reference voltage, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor at a third node; A threshold compensation transistor, wherein the gate of the threshold compensation transistor is electrically connected to a second scan signal line that provides a second scan signal, the first terminal of the threshold compensation transistor is connected to the gate of the driving transistor at a first node, and the second terminal of the threshold compensation transistor is connected to the third node; A data writing transistor, wherein the gate of the data writing transistor is electrically connected to a third scan signal line that provides a third scan signal, the first terminal of the data writing transistor is electrically connected to a data voltage signal line that provides a data voltage, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor at a second node; The operation of the display panel includes a first reset phase. In the first reset phase, the first scan signal has a first enable level that controls the first reset transistor to turn on. During the time covered by the first enable level, the second scan signal has a second enable level that controls the threshold compensation transistor to turn on. The duration of the first enable level is greater than the duration of the second enable level.

[0006] According to another aspect of the present invention, based on the same inventive concept, a driving method for a display panel is provided, the display panel including a pixel driving circuit, the pixel driving circuit comprising: A driving transistor, wherein the driving transistor and the light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line; A first reset transistor, wherein the gate of the first reset transistor is electrically connected to a first scan signal line providing a first scan signal, the first terminal of the first reset transistor is electrically connected to a first reference voltage signal line providing a first reference voltage, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor at a third node; A threshold compensation transistor, wherein the gate of the threshold compensation transistor is electrically connected to a second scan signal line that provides a second scan signal, the first terminal of the threshold compensation transistor is connected to the gate of the driving transistor at a first node, and the second terminal of the threshold compensation transistor is connected to the third node; A data writing transistor, wherein the gate of the data writing transistor is electrically connected to a third scan signal line that provides a third scan signal, the first terminal of the data writing transistor is electrically connected to a data voltage signal line that provides a data voltage, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor at a second node; The driving method includes: In the first reset phase, the first scan signal is controlled to output a first enable level that controls the first reset transistor to turn on; and within the time covered by the first enable level, the second scan signal is controlled to output a second enable level that controls the threshold compensation transistor to turn on; wherein the duration of the first enable level is greater than the duration of the second enable level.

[0007] According to another aspect of the present invention, based on the same inventive concept, a display device is provided, comprising the display panel described in the first aspect.

[0008] The display panel, driving method, and display device provided in this invention decouple the reset control and data voltage writing control of the pixel driving circuit in the circuit architecture. In the first reset phase, a first scan signal and a second scan signal are provided respectively. The duration of the first enable level of the first scan signal is lengthened in the driving timing configuration, allowing the driving transistor to be subjected to a sufficient and sustained combined effect of on-bias stress (OBS) and negative bias stress (NBS). This strong electric field stress resets the charge distribution inside the driving transistor, eliminating the hysteresis effect accumulated by the driving transistor due to different light emission states in the previous frame, thus improving the image retention problem of the display panel. Simultaneously, by lengthening the duration of a single first enable level, the first, second, and third nodes of the driving transistor are completely reset, eliminating residual charge and potential pulling interference between nodes. This ensures that the abnormal brightness problem of the first frame during screen switching is improved with fewer driving pulses. This solution not only avoids interference caused by the preceding row data voltage during virtual writing and solves the abnormal display problem of "black text with bright bars" at the boundary between light and dark areas, but also reduces the overall operating power consumption of the driving IC.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies; Figure 2 This is a schematic diagram of a pixel driving circuit in related technologies; Figure 3 This is a signal timing diagram of a pixel driving circuit in related technologies; Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the A-A' direction; Figure 6 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention; Figure 7 A signal timing diagram of a pixel driving circuit provided in an embodiment of the present invention; Figure 8 Signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 9 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 10 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of a second shifting unit provided in an embodiment of the present invention; Figure 13 for Figure 12 A corresponding signal timing diagram; Figure 14 This is a schematic diagram of the structure of a first shifting unit provided in an embodiment of the present invention; Figure 15 for Figure 14 A corresponding signal timing diagram; Figure 16 This is a schematic diagram of another first shift unit provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention; Figure 19 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Various modifications and variations can be made to this invention without departing from the spirit or scope of the invention, which will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations of the invention that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0014] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies. Figure 2 This is a schematic diagram of the structure of a pixel driving circuit in related technologies, such as... Figure 1 and Figure 2 As shown, the display panel includes multiple pixel driving circuits 10' arranged in an array. Each pixel driving circuit 10' includes a driving transistor T1', a first reset transistor T2', a threshold compensation transistor T3', a data writing transistor T4', and a first light-emitting control transistor T5'.

[0015] The gate of the first reset transistor T2' is connected to the scan signal scan1', one end of which is connected to the first reference voltage VREF1', and the other end is connected to the gate of the drive transistor T1'.

[0016] The gate of the data writing transistor T4' is connected to the scan signal scan2', one end of which is connected to the data voltage data', and the other end is connected to the first terminal of the driving transistor T1'.

[0017] The gate of the threshold compensation transistor T3' is connected to the scan signal scan2', one end of which is connected to the gate of the driving transistor T1', and the other end is connected to the second electrode of the driving transistor T1'.

[0018] The first light-emitting control transistor T5' is connected in series between the second terminal of the driving transistor T1' and the light-emitting element 20', and its gate is connected to the light-emitting control signal EMIT'.

[0019] The pixel driving circuit 10' is controlled by the same set of shift registers 50' during the reset phase and the data writing phase.

[0020] For example, see Figure 1 The shift register 50' includes multiple cascaded shift units 501'. One shift unit 501' is simultaneously electrically connected to two adjacent rows of pixel driving circuits. By controlling the shift unit 501' to output multiple pulses, the scan signals scan1' and scan2' can be driven by multiple pulses.

[0021] In other configurations, the display panel may also include at least two sets of shift registers, one set of which provides the scan signal scan1' and the other set of which provides the scan signal scan2'.

[0022] The inventors discovered that during grayscale switching in a display panel, due to the inherent hysteresis effect of the driving transistor T1', a large amount of trapped charge (positive or negative charge) accumulates at the channel and interface of the driving transistor T1' when it emits light in the previous frame. This causes the threshold voltage of the driving transistor T1' to drift. Even though a reset process occurs before the data voltage is written, the threshold voltage of the driving transistor T1' cannot fully recover to its initial state due to the short reset time. This results in brightness differences, leading to short-term image retention on the display panel. Furthermore, with the continuous improvement of display panel resolution and the application requirements of low-cost, ramless architectures, the reset time has been further compressed, exacerbating the image retention problem under the current driving architecture.

[0023] Meanwhile, due to the parasitic capacitance between the electrodes of the driving transistor T1, before entering the data writing stage, the electrodes of the driving transistor T1 are in an uncertain state because they retain the potential of the previous frame's light-emitting stage. Therefore, at the instant of circuit state switching, the potential of the electrodes of the driving transistor T1 will affect the gate potential of the driving transistor T1 through capacitive coupling effect, resulting in a potential pull phenomenon between nodes. This potential pull will cause the initial potential of the gate of the driving transistor T1 to be inaccurate, thus causing a significant difference between the brightness of the first frame after the screen switch and the brightness of subsequent frames.

[0024] To improve the aforementioned issue of abnormal brightness in the first frame Figure 3 This is a signal timing diagram of a pixel driving circuit in related technologies, such as... Figure 3As shown, the related technology employs a multi-pulse (e.g., three-pulse) driving timing. Specifically, during the phase when the light-emitting control signal EMIT' controls the light-emitting element 20' to not emit light, a scan signal containing multiple effective pulses is applied to the data writing transistor T4' and the threshold compensation transistor T3'. For example, during the time covered by a high level in the light-emitting control signal EMIT', both the scan signals scan1' and scan2' are driven by three pulses. The above driving method aims to use the preceding pulses to repeatedly reset the driving transistor T1' and write virtual data voltage before the actual data voltage is written, thereby improving the brightness of the first frame to some extent by repeatedly resetting the node potential.

[0025] However, in practical applications, the inventors further discovered that the aforementioned multi-pulse driving method can trigger new display anomalies. Specifically, during the initial resets and virtual data voltage writes to the driving transistor T1' of the current pixel driving circuit row, the data transmitted on the data lines is actually the data voltage used for the preceding pixel driving circuit row. Only when the last pulse arrives is the data voltage of the current pixel driving circuit row itself written. Therefore, the data voltage write of the current pixel driving circuit row is affected by the display image of the preceding pixel driving circuit row.

[0026] For example, when the display transitions from dark to bright (e.g., the previous pixel driving circuit row is black, and the current pixel driving circuit row is white), the data voltage corresponding to the previous pixel driving circuit row is higher (e.g., 7V), while the data voltage corresponding to the current pixel driving circuit row is lower (e.g., 3V). When the driving transistor T1' of the current pixel driving circuit row performs virtual data voltage writing, it will be written with a higher black screen data voltage. This will cause an excessively large gate-source voltage difference in the driving transistor T1', subjecting it to severe negative bias stress (NBS). This negative bias state will disrupt the charge balance inside the transistor, causing the threshold voltage of the driving transistor T1' to drift. Therefore, when the last pulse arrives and writes the lower data voltage (e.g., 3V) corresponding to this pixel driving circuit row, because the characteristics of the driving transistor T1' have already drifted, the data voltage of the current pixel driving circuit row will be insufficiently written, resulting in an excessively high actual brightness. This manifests as an abnormal "bright black bar" phenomenon at the boundary between the black and white display areas.

[0027] Meanwhile, multi-pulse driving means that the scan signal needs to frequently switch between high and low levels multiple times within a very short period of a single cycle. Since the scan lines in the display panel array run through the entire display area, they themselves have large parasitic capacitance and parasitic resistance (RC load). Each pulse switch of the scan signal requires the integrated circuit (IC) and shift register to charge and discharge the entire scan line. This high-frequency charging and discharging process generates a large amount of dynamic switching power consumption, which significantly increases the power consumption of the driver IC.

[0028] Based on the above-mentioned technical problems, the present invention provides a display panel and driving method with a novel pixel driving circuit to solve the problems of image retention and abnormal brightness of the first frame caused by the limited reset time in related technologies, and at the same time overcome the black text bright bar phenomenon and high power consumption problem caused by multi-pulse timing.

[0029] Specifically, Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the A-A' direction. Figure 6 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. Figure 7 A signal timing diagram of a pixel driving circuit provided in an embodiment of the present invention, such as... Figures 4-7 As shown, the display panel provided in this embodiment of the invention includes a pixel driving circuit 10, which includes: A driving transistor T1 and a light-emitting element 20 are connected in series between the first power supply voltage signal line 31 and the second power supply voltage signal line 32.

[0030] The first reset transistor T2 has its gate T20 electrically connected to the first scan signal line 33 that provides the first scan signal SN, its first terminal T21 electrically connected to the first reference voltage signal line 34 that provides the first reference voltage VREF1, and its second terminal T22 connected to the second terminal T12 of the driving transistor T1 at the third node N3.

[0031] Threshold compensation transistor T3, the gate T30 of threshold compensation transistor T3 is electrically connected to the second scan signal line 35 that provides the second scan signal scan1, the first terminal T31 of threshold compensation transistor T3 is connected to the gate T10 of driving transistor T1 at the first node N1, and the second terminal T32 of threshold compensation transistor T3 is connected to the third node N3.

[0032] The data writing transistor T4 has its gate T40 electrically connected to the third scan signal line 36 that provides the third scan signal scan2, its first terminal T41 electrically connected to the data voltage signal line 37 that provides the data voltage data, and its second terminal T42 connected to the first terminal T11 of the driving transistor T1 at the second node N2.

[0033] The operation of the display panel includes a first reset phase T10. In the first reset phase T10, the first scan signal SN has a first enable level V11 that controls the first reset transistor T2 to turn on. During the time covered by the first enable level SN1, the second scan signal scan1 has a second enable level V21 that controls the threshold compensation transistor T3 to turn on. The duration of the first enable level V11 is greater than the duration of the second enable level V21.

[0034] Specifically, such as Figures 4-7 As shown, the display panel includes a display area AA and a non-display area NAA located on at least one side of the display area AA. Multiple sub-pixels PX are arranged in an array in the display area AA, and the multiple sub-pixels PX are disposed on the same side of the substrate 40. Figure 4 This example only illustrates the standard RGB arrangement of multiple sub-pixels PX on a display panel. In other embodiments, the multiple sub-pixels PX may be arranged in other ways. Furthermore, the shape of the light-emitting area of ​​the sub-pixel PX includes, but is not limited to, […]. Figure 4 The rectangle shown in the figure can be used in other embodiments, and the shape of the light-emitting area of ​​the sub-pixel PX can also be designed according to actual needs. This embodiment of the invention does not impose specific limitations on this.

[0035] Furthermore, the sub-pixel PX includes a pixel driving circuit 10 and a light-emitting element 20 that are electrically connected to each other. The pixel driving circuit 10 is used to transmit driving current to the light-emitting element 20 under the action of signals from driving signal lines (such as scan signal lines, data voltage signal lines, power supply voltage signal lines and reference voltage signal lines) on the display panel, thereby driving the light-emitting element 20 to emit light.

[0036] In some embodiments, such as Figure 5 As shown, taking an organic light-emitting diode (OLED) as an example, the light-emitting element 23 can be described as follows: the light-emitting element 20 may include an anode 201, a light-emitting layer 202, and a cathode 203 stacked together. When electrons and holes are injected into the light-emitting layer 202 from the cathode 203 and the anode 201, respectively, excitons are formed in the light-emitting layer 202, exciting the light-emitting molecules and causing the light-emitting layer 202 to emit visible light. Different colors of visible light can be emitted by using different materials for the light-emitting layer 202.

[0037] It should be noted that the light-emitting element 20 is not limited to organic light-emitting diodes. In other embodiments, the light-emitting element 20 may also be other types of light-emitting devices, and the embodiments of the present invention do not make specific limitations on this.

[0038] In some embodiments, such as Figure 5 As shown, the light-emitting layers 202 of each light-emitting element 20 are separated by a pixel definition layer 41, wherein the pixel definition layer 41 includes multiple openings, at least a portion of the light-emitting layers 202 are located within the openings, and the area where the openings of the pixel definition layer 41 are located forms the light-emitting area of ​​the sub-pixel PX.

[0039] In some embodiments, the light-emitting element 20 may include at least two light-emitting elements of different colors. For example, the light-emitting element 20 may include a red light-emitting element, a green light-emitting element, and a blue light-emitting element, so that the sub-pixel PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, thereby realizing color image display.

[0040] In some embodiments, such as Figure 5 As shown, the pixel driving circuit 10 may include at least one thin film transistor T. The thin film transistor T may include an active layer 1, a gate 2, and source / drain electrodes 3 (including a first electrode and a second electrode) stacked on one side of the substrate 40.

[0041] In some embodiments, such as Figure 5 As shown, a gate insulating layer 42 is disposed between the active layer 1 and the gate 2, an interlayer insulating layer 43 is disposed between the gate 2 and the source / drain electrode 3, and a planarization layer 44 is disposed between the source / drain electrode 3 and the anode 201, so as to isolate each conductive film layer and avoid short circuit between adjacent conductive film layers.

[0042] Furthermore, such as Figure 6 As shown, the pixel driving circuit 10 specifically includes a driving transistor T1. The driving transistor T1 and the light-emitting element 20 are connected in series between the first power supply voltage signal line 31 and the second power supply voltage signal line 32. The first power supply voltage signal line 31 is used to transmit the first power supply voltage PVDD, and the second power supply signal line PVEE is used to transmit the second power supply voltage PVEE. The first power supply voltage PVDD is higher than the second power supply voltage PVEE.

[0043] The driving transistor T1 can be turned on according to the voltage of its gate T10, and the driving current generated by its conduction is used to drive the light-emitting element 20 to emit light. It can be understood that the gate voltage of the driving transistor T1 determines the magnitude of the driving current generated by its conduction. Therefore, the brightness of the light-emitting element 20 can be adjusted by controlling the gate voltage of the driving transistor T1, thereby controlling the grayscale.

[0044] like Figure 6As shown, the pixel driving circuit 10 also includes a first reset transistor T2. The first reset transistor T2 is connected in series between the second terminal T12 (i.e., the third node N3) of the driving transistor T1 and the first reference voltage signal line 34. The gate T20 of the first reset transistor T2 is electrically connected to the first scan signal line 33. The first reset transistor T2 is used to turn on under the control of the first scan signal SN to transmit the first reference voltage VREF1 to the third node N3, thereby resetting the third node N3.

[0045] like Figure 6 As shown, the pixel driving circuit 10 also includes a threshold compensation transistor T3. The threshold compensation transistor T3 is connected in series between the gate T10 (i.e., the first node N1) and the second terminal T12 (i.e., the third node N3) of the driving transistor T1. The gate T30 of the threshold compensation transistor T3 is electrically connected to the second scan signal line 35. The threshold compensation transistor T3 is used to conduct under the control of the second scan signal scan1, so that the first node N1 and the third node N3 are connected.

[0046] like Figure 6 As shown, the pixel driving circuit 10 also includes a data writing transistor T4. The data writing transistor T4 is connected in series between the first terminal T11 (i.e., the second node N2) of the driving transistor T1 and the data voltage signal line 37. The gate T40 of the data writing transistor T4 is electrically connected to the third scan signal line 36. The data writing transistor T4 is used to be turned on under the control of the third scan signal scan2 to write the data voltage data to the second node N2.

[0047] Furthermore, such as Figure 7 As shown, the operation of the display panel includes a first reset stage T10. In the first reset stage T10, the first scan signal SN has a first enable level V11 that controls the first reset transistor T2 to turn on. At this time, the first reset transistor T2 is turned on and transmits the first reference voltage VREF1 (e.g., -3.5V) provided by the first reference voltage signal line 34 to the third node N3, thereby resetting the third node N3 (i.e., the second electrode T12 of the driving transistor T1). Since a negative reference voltage is applied to the electrode of the driving transistor T1, the driving transistor T1 is subjected to negative bias stress (NBS).

[0048] During this process, within the time period covered by the first enable level V11, the second scan signal scan1 provided by the second scan signal line 35 has a second enable level V21, which is used to control the threshold compensation transistor T3 to turn on. Since the threshold compensation transistor T3 is turned on, the first node N1 (i.e., the gate T10 of the driving transistor T1) is connected to the third node N3, so that the first node N1 is reset to the negative potential of the first reference voltage VREF1.

[0049] At this time, a first reference voltage VREF1 is applied to both the gate T10 and the second terminal T12 of the driving transistor T1, causing the driving transistor T1 to be fully turned on, thus placing it in a strong on-bias stress (OBS) state. By placing the driving transistor T1 in this OBS state, a strong electric field can be used to reset its internal charge distribution, making the charge reset of the semiconductor channel and the insulating layer interface of the driving transistor T1 more consistent. This physical process effectively eliminates the hysteresis effect accumulated by the driving transistor T1 due to different light emission states in the previous frame, allowing the driving transistor T1 to quickly recover its state, thereby improving the image retention problem of the display panel.

[0050] Meanwhile, during the conduction of the driving transistor T1, its first electrode T11 (i.e., the second node N2) is connected to the third node N3, so that the second node N2 is also reset to the potential of the first reference voltage VREF1. This effectively clears the uncertain charge remaining in the second node N2 from the previous frame's light emission stage, ensuring that the initial potential of each electrode of the driving transistor T1 is in a stable and known reference state before entering the data writing stage. This eliminates the potential pull (capacitive coupling interference) between the first node N1 and the second node N2, thereby improving the problem of abnormal brightness in the first frame during screen switching without using a multi-pulse driving scheme.

[0051] It should be noted that the first enable level V11 refers to the voltage potential in the first scan signal SN that enables the first reset transistor T2 to conduct. In the actual pixel driving circuit, if the first reset transistor T2 is a P-type thin-film transistor, then the first enable level V11 is low; if the first reset transistor T2 is an N-type thin-film transistor, then the first enable level V11 is high, and its function is to act as a switch control signal to open the path for the transmission of the first reference voltage VREF1 to the third node N3.

[0052] The second enable level V21 refers to the voltage potential in the second scan signal scan1 that enables the threshold compensation transistor T3 to conduct. Similarly, if the threshold compensation transistor T3 is a P-type thin film transistor, the second enable level V21 is low; if the threshold compensation transistor T3 is an N-type thin film transistor, the second enable level V21 is high. Its function is to act as a switch control signal to control the threshold compensation transistor T3 to turn on, so that the gate T10 (i.e., the first node N1) of the driving transistor T1 (i.e., the second terminal T12 (i.e., the third node N3)) is connected, thereby transmitting the reset potential at the third node N3 to the first node N1.

[0053] The first reference voltage VREF1 is a DC reference potential used to initialize key nodes (such as the third node N3 and the first node N1) in the pixel driving circuit. In this embodiment, the first reference voltage VREF1 is configured as a negative voltage (e.g., it can be set to -3.5V). By applying this negative first reference voltage VREF1 to the driving transistor T1, the driving transistor T1 can be fully turned on, thereby forming a strong on-bias stress (OBS) effect inside it. Under the action of the on-bias stress, the charge distribution at the interface between the semiconductor channel and the insulating layer of the driving transistor T1 can be forced to reset, so that the reset state of the channel and interface charge is fully consistent, thereby effectively clearing the charge remaining in the driving transistor T1 due to carrier capture in the previous frame emission stage, reducing the threshold voltage drift of the thin film transistor T1, and ensuring that the driving transistor T1 returns to the standard initial operating state.

[0054] Furthermore, in this embodiment of the invention, the duration of the first enable level V11 is configured to be greater than the duration of the second enable level V21. Specifically, the pulse width of the first scan signal SN that controls the first reset transistor T2 to turn on is greater than the pulse width of the second scan signal scan1 that controls the threshold compensation transistor T3 to turn on.

[0055] By extending the timing design of this embodiment, the duration of the first enable level V11 is increased, thereby prolonging the reset time of the third node N3 and the first node N1 connected through the threshold compensation transistor T3. During this extended reset time, the time for applying negative bias stress (NBS) to the driving transistor T1 is increased, allowing the driving transistor T1 to experience a stronger and more sustained on-bias stress (OBS) effect. Under the influence of this strong electric field stress, the charge distribution inside the driving transistor T1 can be effectively reset, resulting in a more thorough reset of the charge at the interface between the semiconductor channel and the insulating layer of the driving transistor T1. It is understood that, with the aforementioned extended reset time design, this embodiment can reduce brightness differences caused by the characteristic drift of the driving transistor T1, thereby improving the image retention problem of the display panel.

[0056] Meanwhile, this embodiment enhances the reset effect of the first node N1, the second node N2, and the third node N3 by directly lengthening the effective level (i.e., the first enable level V11) of a single reset signal (i.e., the first scan signal SN), thereby achieving a deep reset of the first node N1, the second node N2, and the third node N3. This improves the problem of abnormal brightness in the first frame without the need for virtual write data voltage. At the same time, the "black text with bright bars" phenomenon is avoided because the interference of the preceding row data voltage is isolated.

[0057] In addition, the reduction in the number of scanning pulses reduces the switching losses caused by high-frequency switching, thereby reducing the overall operating power consumption of the driver IC and display panel.

[0058] In summary, the display panel provided by this embodiment of the invention decouples the reset control and data voltage write control of the pixel driving circuit in the circuit architecture. During the first reset phase, a first scan signal and a second scan signal are provided respectively. The duration of the first enable level of the first scan signal is extended in the driving timing configuration, allowing the driving transistor to be subjected to a sufficient and sustained combined effect of on-bias stress (OBS) and negative bias stress (NBS). This strong electric field stress resets the charge distribution inside the driving transistor, eliminating the hysteresis effect accumulated by the driving transistor due to different light emission states in the previous frame, thus improving the image retention problem of the display panel. Simultaneously, by extending the duration of a single first enable level, the first, second, and third nodes of the driving transistor are completely reset, eliminating residual charge and potential pulling interference between nodes. This ensures that the abnormal brightness problem of the first frame during screen switching is improved with fewer driving pulses. This solution not only avoids interference caused by the preceding row data voltage during virtual writing and solves the abnormal display problem of "black text with bright bars" at the boundary between light and dark areas, but also reduces the overall operating power consumption of the driving IC.

[0059] Optional, such as Figure 7 As shown, during the first reset phase T10, the first scan signal SN has only one first enable level V11. During the time covered by the first enable level V11, the second scan signal scan1 has only one second enable level V21.

[0060] Specifically, during the first reset phase T10, the first scan signal SN controlling the first reset transistor T2 only transitions from the disabled level to the first enabled level V11 once, and after a relatively long period of time, it returns to the disabled level. During this long period, no repeated level switching occurs.

[0061] Meanwhile, during the first reset phase T10, the second scan signal scan1 of the control threshold compensation transistor T3 also only jumps from the disabled level to the second enabled level V21 once, and after a period of time, it returns to the disabled level, that is, the first node N1 and the third node N3 are connected only once.

[0062] In the first reset stage T10, which resets the pixel driving circuit 10, a single-pulse (single-enable) driving timing is adopted so that the driving transistor T1 undergoes only one continuous and relatively long reset process before entering the formal data voltage writing stage. This reduces the level switching action by using the fewest pulses of the first scan signal SN and the second scan signal scan1, and minimizes the dynamic charging and discharging frequency of parasitic capacitance and parasitic resistance on the first scan signal line 33 and the second scan signal line 35, thereby further reducing the overall power consumption of the driving IC.

[0063] It should be noted that the duration (i.e., pulse width) of the first enable level V11 can be flexibly adjusted according to actual needs.

[0064] Understandably, if the duration of the first enable level V11 is too short, although the driving transistor T1 can enter the bias stress (OBS) state, due to insufficient reset time, the residual charge in its semiconductor channel and interface cannot be completely reset in time, resulting in the hysteresis characteristic of the transistor not being completely eliminated. When switching screens, a slight short-term afterimage may still remain, and the problem of abnormal brightness in the first frame caused by the pull between the first node N1 and the second node N2 cannot be completely solved.

[0065] However, if the duration of the first enable level V11 is too long, the excessively long reset time will excessively occupy the display driving time of the entire frame, which is not conducive to the timing settings of high refresh rate display panels.

[0066] In some embodiments, the duration of the first enable level V11 is configured to be between 6H and 18H, where H is a horizontal time in the display panel driving timing, i.e., the time required to scan one row of pixels. By limiting the duration of the first enable level V11 to the range of 6H to 18H, it is ensured that the driving transistor T1 can receive sufficient and sustained reset, improving ghosting and abnormal brightness in the first frame, while also maintaining the overall compactness of the driving timing, which is beneficial for achieving a high refresh rate.

[0067] like Figure 7 As shown, optionally, in the first reset phase T10, the start time of the first enable level V11 is earlier than the start time of the second enable level V21.

[0068] Specifically, Figure 8 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention, such as... Figure 8 As shown, in the initial stage of the transition from the disabled level to the first enabled level V11, due to the parasitic RC load effect on the first scan signal line 33, the first enabled level V11 has a small voltage fluctuation or requires a certain setting time to reach the ideal stable level.

[0069] In this embodiment, during the first reset phase T10, the first enable level V11 of the first scan signal SN is output before the second enable level V21 of the second scan signal scan1, thus reserving a voltage stabilization buffer time in the timing. During this buffer time, the first reset transistor T2 is turned on first, allowing the third node N3 to be reset preferentially and to drop sufficiently and stably to the potential of the first reference voltage VREF1. After the first scan signal SN has passed the initial fluctuation period and the potential of the third node N3 has reached a stable state, the threshold compensation transistor T3 is then turned on. This prevents unstable voltage or noise of the first scan signal SN during the initial transition period from being coupled to the gate T10 of the driving transistor T1 (i.e., the first node N1) through the turned-on threshold compensation transistor T3. This ensures that the gate T10 of the driving transistor T1 can receive a more stable first reference voltage VREF1 when it is connected to the reset path, thereby entering the conduction bias stress (OBS) state more smoothly and further improving the stability of the pixel driving circuit during the reset process.

[0070] In an optional embodiment, such as Figure 7 As shown, the interval t10 between the start time of the first enable level V11 and the start time of the second enable level V21 is configured to be 3H to 5H, where H is a row scan cycle in the display panel driving timing.

[0071] Understandably, if the interval t10 is too short (e.g., less than 3 line scan cycles), due to the unavoidable large parasitic RC load (parasitic resistance and parasitic capacitance) on the scan signal lines in the display panel, the level transition of the first scan signal SN and the potential drop of the third node N3 both require a certain settling time. If the settling time is insufficient, the potential of the third node N3 has not yet smoothly dropped to the target first reference voltage VREF1. If the threshold compensation transistor T3 is turned on too early at this time, the voltage fluctuations and noise during the transition period can easily be directly coupled to the gate T10 of the driving transistor T1 (i.e., the first node N1), resulting in inaccurate gate initialization potential and thus affecting subsequent display uniformity.

[0072] On the other hand, if the interval time t10 is too long (e.g., more than 5 row scan cycles), although the potential of the third node N3 can be stabilized, the total duration of the first enable level V11 is limited (e.g., 6H to 18H as mentioned above). The excessively long interval time t10 will severely compress the effective overlap time of the first reset transistor T2 and the threshold compensation transistor T3 being turned on at the same time, resulting in insufficient time for the internal charge reset of the driving transistor T1, weakening the effect of improving the afterimage, and also being detrimental to the overall compactness of the driving timing.

[0073] In this embodiment, the interval time t10 is limited to the range of 3H to 5H, which not only provides sufficient voltage stabilization buffer period for the level transition of the first scanning signal SN, isolates the coupling interference of the initial voltage noise to the first node N1, but also ensures the time for the driving transistor T1 to perform OBS reset, thus ensuring the improvement effect on afterimage and abnormal brightness of the first frame.

[0074] Optional, such as Figure 7 As shown, in the first reset phase T10, the end time of the first enable level V11 is later than the end time of the second enable level V21.

[0075] Specifically, in the first reset phase T10, the second scan signal scan1 controlling the threshold compensation transistor T3 switches back to the disabled level first (i.e., the threshold compensation transistor T3 turns off first), while the first scan signal SN controlling the first reset transistor T2 remains at the first enabled level V11 (i.e., the first reset transistor T2 remains on).

[0076] In this process, after the threshold compensation transistor T3 is turned off, although the first node N1 (the gate of the driving transistor T1) is disconnected from the third node N3, it remains stably maintained at the first reference voltage VREF1 due to the capacitance retention effect. Simultaneously, the still-on first enable level V11 causes the first reset transistor T2 to continue supplying the first reference voltage VREF1 to the third node N3, thereby extending the reset time of the third node N3. This state allows the driving transistor T1 to remain in the on-bias stress (OBS) state until the first enable level V11 ends, further extending the reset time of the driving transistor T1 and improving the reduction of ghosting and first frame brightness anomalies.

[0077] Simultaneously, at the instant the thin-film transistor is turned off, charge injection and clock feedthrough effects occur, causing voltage fluctuations in local nodes. Since the threshold compensation transistor T3 turns off before the first reset transistor T2 in this embodiment, when the first reset transistor T2 finally turns off and causes a small voltage jump or noise in the third node N3, the path to the first node N1 (i.e., the threshold compensation transistor T3) has been completely turned off. This blocks the coupling of the turn-off noise of the first reset transistor T2 to the gate of the driving transistor T1, ensuring a stable reset of the first node N1.

[0078] In an optional embodiment, such as Figure 7 As shown, the time interval t2 between the end time of the first enable level V11 and the end time of the second enable level V21 is 1H to 5H, where H is a row scan cycle in the display panel driving timing.

[0079] If the interval t2 is too short (e.g., less than one row scan cycle), the threshold compensation transistor T3 may not have reached a stable cutoff state before the turn-off process of the thin-film transistor requires a certain response time. If the first reset transistor T2 turns off too early, the clock feedthrough and channel charge injection effects generated during its level transition may couple to the first node N1 through the channel of the threshold compensation transistor T3 or its parasitic capacitance. In this embodiment, maintaining the interval t2 at 1H or more allows sufficient turn-off stabilization period for the threshold compensation transistor T3, ensuring its complete cutoff and cutting off the path of the turn-off noise of the first reset transistor T2 coupling to the gate of the driving transistor T1, thus ensuring the stability of the initial gate potential of the driving transistor T1. At the same time, this interval t2 allows the third node N3 to continue receiving the regulated reset of the first reference voltage VREF1 after the threshold compensation transistor T3 turns off, ensuring the reset state of the third node N3.

[0080] On the other hand, if the interval time t2 is too long (e.g., more than 5 line scan cycles), since the total pulse width of the first enable level V11 has an upper limit (e.g., 6H to 18H as mentioned above), the excessively long interval time t2 will compress the effective overlap time of the first reset transistor T2 and the threshold compensation transistor T3 being turned on at the same time, resulting in insufficient time for the internal charge reset of the driving transistor T1, weakening the effect of improving the afterimage, and also being detrimental to the overall compactness of the driving timing.

[0081] Figure 9 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention, such as... Figure 9 As shown, optionally, in the first reset phase T10, the start time of the first enable level V11 is earlier than the start time of the second enable level V21, and the end time of the first enable level V11 is later than the end time of the second enable level V21. The time interval between the start time of the first enable level V11 and the start time of the second enable level V21 is t1, and the time interval between the end time of the first enable level V11 and the end time of the second enable level V21 is t2, where t1 < t2.

[0082] Specifically, such as Figure 8 and Figure 9 As shown, the first reset stage T10 is divided into three consecutive working sub-stages in terms of timing, specifically including the first reset sub-stage T101, the second reset sub-stage T102, and the third reset sub-stage T103, which are performed sequentially.

[0083] During the first reset stage T101, the first scan signal SN transitions to the first enable level V11, while the second scan signal scan1 remains at the disabled level. At this time, the first reset transistor T2 is turned on, and the threshold compensation transistor T3 is turned off. During the first reset stage T101 in which the threshold compensation transistor T3 remains off, the potential of the third node N3 is first pulled down to the first reference voltage VREF1, thus avoiding voltage fluctuations and clock feedthrough effects generated when the first scan signal SN transitions from coupling to the gate T10 (first node N1) of the driving transistor T1.

[0084] During the second reset phase T102, the first scan signal SN maintains the first enable level V11, while the second scan signal scan1 transitions to the second enable level V21. At this time, the first reset transistor T2 and the threshold compensation transistor T3 are simultaneously turned on. The first node N1 is connected to the third node N3 and synchronously receives the first reference voltage VREF1. Because a stable first reference voltage VREF1 is applied to the gate T10 of the driving transistor T1, the driving transistor T1 is fully turned on and enters the on-bias stress (OBS) state. During this period, the second node N2 also synchronously undergoes a reset process through the turned-on driving transistor T1.

[0085] During the third reset phase T103, the second scan signal scan1 is the first to return to the disabled level, while the first scan signal SN remains at the first enabled level V11. At this time, the threshold compensation transistor T3 is turned off early, while the first reset transistor T2 remains on. With the turn-off of the threshold compensation transistor T3, the first node N1 is locked to the first reference voltage VREF1, blocking possible subsequent turn-off noise interference. Simultaneously, the first reset transistor T2 continuously applies the first reference voltage VREF1 to the third node N3 (and the connected second node N2). Under the premise that the gate potential of the driving transistor T1 remains stable, the source / drain nodes are continuously reset, so that the driving transistor T1 remains in the OBS state until the first enabled level V11 ends, thereby resetting the residual charge in its semiconductor channel to a greater extent.

[0086] Furthermore, the time interval between the start time of the first enable level V11 and the start time of the second enable level V21 is defined as t1, which is the duration of the first reset sub-stage T101. The time interval between the end time of the first enable level V11 and the end time of the second enable level V21 is defined as t2, which is the duration of the third reset sub-stage T103.

[0087] like Figure 9 As shown, the function of t1 is to provide a voltage stabilization buffer period for the transition of the first scan signal SN. Since it is only necessary to wait for the voltage fluctuation on the first scan signal line 33 to subside, t1 is kept to a short duration, which is sufficient to prevent the noise generated when the first scan signal SN transitions from coupling to the gate T10 (first node N1) of the driving transistor T1, while also taking into account the overall compactness of the driving timing.

[0088] The function of t2 is to further reset the source / drain nodes (i.e., the second node N2 and the third node N3) of the driving transistor T1. By configuring t2 to be greater than t1, while avoiding noise interference to the first node N1, the second node N2 and the third node N3 can be reset more persistently, thereby further eliminating the residual charge on the second node N2 and the third node N3 due to the light emission of the previous frame, and ensuring the complete reset of the driving transistor T1.

[0089] Optional, such as Figure 7 As shown, in the first reset phase T10, the start time of the first enable level V11 is earlier than the start time of the second enable level V21, and the end time of the first enable level V11 is later than the end time of the second enable level V21. The time interval between the start time of the first enable level V11 and the start time of the second enable level V21 is t1, and the time interval between the end time of the first enable level V11 and the end time of the second enable level V21 is t2, where t1 ≥ t2.

[0090] The first scan signal line 33, which transmits the first scan signal SN, typically spans the entire display area of ​​the display panel and has a large parasitic RC load (parasitic resistance and parasitic capacitance). When the first scan signal SN transitions from the disabled level to the first enabled level V11, it will experience a relatively long period of instability.

[0091] In this embodiment, by setting t1 to a longer time period greater than or equal to t2, sufficient voltage regulation buffer period is reserved for the first scan signal SN. Only after the first scan signal SN has completely passed the unstable stage of the initial transition and ensured that the third node N3 has been smoothly reduced to the first reference voltage VREF1 will the threshold compensation transistor T3 be turned on (i.e. the second scan signal scan1 transitions to the second enable level V21). This ensures that the conduction stage of the threshold compensation transistor T3 completely avoids the unstable stage of the first scan signal SN, preventing noise generated when the first scan signal SN transitions from coupling to the gate T10 of the driving transistor T1.

[0092] Optionally, the first reference voltage is VREF1, and during the first reset phase T10, -4.5V≤VREF1≤-3V.

[0093] If the voltage value of the first reference voltage VREF1 is higher than -3V (i.e., the absolute value of the negative bias is small, for example, set to -2V or closer to 0V), the negative voltage applied to the gate of the driving transistor T1 will be insufficient, causing the driving transistor T1 to fail to be fully turned on, and the on-bias stress (OBS) effect it induces will be weak. Under the action of weak electric field stress, the residual charge trapped at the channel and interface of the driving transistor T1 is difficult to be completely removed, and the hysteresis characteristic of the driving transistor T1 cannot be completely eliminated, thereby weakening the improvement effect on image retention and first frame brightness deviation.

[0094] If the first reference voltage VREF1 is lower than -4.5V (i.e., the absolute value of the negative bias is too large, for example, set to -6V), although a very strong reset electric field can be generated, it will cause the driving transistor T1 to be subjected to excessively high negative bias stress, resulting in damage to the semiconductor lattice structure of the driving transistor T1. This will induce an irreversible and permanent drift in the threshold voltage of the driving transistor T1, shortening the long-term lifespan of the display panel. In addition, providing an excessively low negative reference voltage will also increase the voltage output swing of the power management chip (PMIC), increasing the static power consumption of the display panel.

[0095] Therefore, in this embodiment, the first reference voltage VREF1 is limited to -4.5V to -3V, which ensures that there is sufficient on-bias stress (OBS) to achieve sufficient reset and solve the problems of ghosting and abnormal brightness in the first frame, while avoiding irreversible overvoltage damage to the driving transistor T1.

[0096] It should be noted that this embodiment uses a P-type thin-film transistor (e.g., PMOS) as an example of a driving transistor T1 in a pixel driving circuit, but it is not limited to this.

[0097] In other alternative embodiments, the driving transistor T1 can also be configured as an N-type thin-film transistor (e.g., NMOS). When the driving transistor T1 is an N-type thin-film transistor, since the turn-on polarity of the N-type transistor is opposite to that of the P-type transistor, the first reference voltage VREF1 can be configured as a positive voltage. Specifically, to ensure that the N-type driving transistor can be fully turned on in the first reset phase T10, the first reference voltage VREF1 needs to be adjusted from the aforementioned negative voltage to a positive DC voltage. The specific positive value range of the first reference voltage VREF1 is not limited to the aforementioned embodiments. Those skilled in the art can make adaptive matches based on the inherent threshold voltage drift characteristics, channel turn-on capability, and long-term reliability requirements of the N-type thin-film transistor used, as long as the N-type driving transistor T1 can be fully turned on in the first reset phase T10 and generate a forward conduction bias stress that can eliminate its threshold voltage drift.

[0098] Optional, such as Figure 7 and Figure 9 As shown, the operation of the display panel also includes a data writing phase T20 following the first reset phase T10. In the data writing phase T20, the second scan signal scan1 has a third enable level V31 that controls the threshold compensation transistor T3 to turn on, and the third scan signal scan2 has a fourth enable level V41 that controls the data writing transistor T4 to turn on, with the third enable level V31 and the fourth enable level V41 overlapping. Within one frame, the display panel operation only has one data writing phase T20.

[0099] Specifically, such as Figure 7 and Figure 9 As shown, the operation of the display panel within one frame cycle includes a first reset stage T10 and a data writing stage T20 executed sequentially. The data writing stage T20 is used to complete threshold voltage compensation and data voltage writing for the pixel driving circuit.

[0100] During the data writing stage T20, the second scan signal scan1 is applied at a third enable level V31. The third enable level V31 refers to the voltage potential in the second scan signal scan1 that enables the threshold compensation transistor T3 to conduct. In the actual pixel driving circuit, if the threshold compensation transistor T3 is a P-type thin-film transistor, the third enable level V31 is low; if the threshold compensation transistor T3 is an N-type thin-film transistor, the third enable level V31 is high. Its function is to act as a switch control signal to control the threshold compensation transistor T3 to turn on, so that the gate T10 (i.e., the first node N1) of the driving transistor T1 and the second terminal T12 (i.e., the third node N3) are connected.

[0101] During the data writing phase T20, the third scan signal scan2 is applied at the fourth enable level V41. The fourth enable level V41 refers to the voltage potential in the third scan signal scan2 that enables the data writing transistor T4 to conduct. Similarly, if the data writing transistor T4 is a P-type thin-film transistor, the fourth enable level V41 is low; if the data writing transistor T4 is an N-type thin-film transistor, the fourth enable level V41 is high. Its function is to act as a switch control signal, controlling the turning on of the data writing transistor T4, thus opening the path for the data voltage data to be transmitted to the second node N2.

[0102] During the data writing phase T20, the third enable level V31 and the fourth enable level V41 overlap in time. During this overlap period, the threshold compensation transistor T3 and the data writing transistor T4 are both in the on state. At this time, the data voltage on the data voltage signal line 37 is transmitted to the first terminal T11 (i.e., the second node N2) of the driving transistor T1 through the conducting data writing transistor T4. At the same time, the threshold compensation transistor T3 is turned on, and the gate T10 (i.e., the first node N1) of the driving transistor T1 is connected to the second terminal T12 (i.e., the third node N3), so that the driving transistor T1 is in a diode-connected state. The data voltage charges the first node N1 until the potential of the first node N1 reaches a level that includes the data voltage and the threshold voltage information of the driving transistor T1 itself, thereby completing the writing of the data voltage and the self-compensation of the threshold voltage of the driving transistor T1. This compensation mechanism ensures that even if there are differences in the threshold voltage of the driving transistor T1 between different pixels, the driving current flowing through the light-emitting element 20 is still determined only by the data voltage, so as to improve the uniformity of the screen brightness.

[0103] Furthermore, within one frame, thanks to the relatively long single-pulse reset design used in the first reset stage T10, each node of the driving transistor T1 (such as the first node N1, the second node N2, and the third node N3) has been fully reset, and there is no need to rely on multiple pulses to write virtual data voltage. Therefore, in this embodiment, only one data writing stage T20 needs to be executed within one frame to achieve accurate grayscale brightness display.

[0104] Understandably, the above-mentioned single-pulse (1 pulse) data voltage writing scheme, while ensuring the brightness accuracy of the first frame and improving afterimages, isolates the coupling interference of the preceding row data voltage, avoiding the "black text with bright bar" phenomenon; and by reducing the number of scanning pulse flips, it further reduces the dynamic power consumption of the driver IC and the panel.

[0105] It should be noted that the above frame time refers to the time period required for the display panel to complete one full screen refresh, that is, the time interval between the start of scanning and writing a certain pixel row and the refresh of the same position in the next frame.

[0106] Optional, such as Figure 7 and Figure 9 As shown, the time interval between the end time of the second enable level V21 and the start time of the third enable level V31 is t3, where t3 ≥ 2H; H is the row scan period.

[0107] The line scan period H refers to the scan time allocated to a single row of pixels within a frame, and its value can be equal to the frame period divided by the total number of scanned rows.

[0108] The end of the second enable level V21 signifies that the threshold compensation transistor T3 switches from the on state to the off state, thereby cutting off the connection between the gate T10 (i.e., the first node N1) and the second terminal T12 (i.e., the third node N3) of the driving transistor T1. At the moment of turn-off, the threshold compensation transistor T3 induces channel charge injection and clock feedthrough effects, causing a small transient voltage jump in the first node N1, which has just completed its reset. In this embodiment, the time interval t3 between the end of the second enable level V21 and the start of the third enable level V31 is limited to no less than two row scan cycles, providing sufficient buffer time for the first node N1 to ensure that the voltage fluctuation on the gate T10 of the driving transistor T1 has subsided and the potentials of each terminal of the driving transistor T1 have reached a stable state before the threshold compensation transistor T3 is turned on for data voltage writing.

[0109] Meanwhile, the data voltage signal line 37 typically runs through the entire display area and has a large parasitic RC load. Before entering the formal data writing stage T20 for this row, the driver IC needs to switch the data voltage signal line 37 from the data voltage of the previous row to the data voltage of the current row. This voltage switching and charging / discharging process takes a certain amount of time. Limiting the time interval t3 to no less than two row scan cycles provides sufficient pre-charging time for the driver IC, ensuring that when the second scan signal scan1 transitions to the third enable level V31, the potential on the data voltage signal line 37 is a stable data voltage for the current row, thereby avoiding writing errors caused by the data voltage signal line 37 not being regulated.

[0110] Figure 10 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention, such as... Figure 10 As shown, optionally, the operation of the display panel also includes a second reset stage T30 following the data writing stage T20. In the second reset stage T30, the third scan signal scan2 has a fifth enable level V51 that controls the data writing transistor T4 to turn on.

[0111] During the second reset phase T30, the data write transistor T4 is turned on again due to the effect of the fifth enable level V51. At this time, the data voltage on the data voltage signal line 37 is transmitted to the first terminal T11 (i.e., the second node N2) of the drive transistor T1.

[0112] Taking the driving transistor T1 as a P-type transistor as an example, the data voltage on the data voltage signal line 37 is configured as a positive voltage, and the gate T10 (i.e. the first node N1) of the driving transistor T1 is at a relatively low potential after experiencing the pre-reset and data writing stages. At this time, a large negative voltage difference is formed between the first terminal T11 and the second terminal T12 of the driving transistor T1. This negative voltage causes the driving transistor T1 to be in a conduction bias stress (OBS) state. This stress can induce a negative shift in the threshold voltage of the driving transistor T1.

[0113] This embodiment aims to compensate for the positive shift in threshold voltage caused by the prolonged conduction of the driving transistor T1 during the previous frame's emission phase. Specifically, during the continuous operation of the display panel, the driving transistor T1 continuously endures specific operating stress during the long emission phase of the previous frame, which often leads to a slow, trending shift in its threshold voltage (e.g., a positive shift). This embodiment inserts a second reset phase T30 after the data writing phase T20 and before the formal emission phase, and applies negative stress based on the positive data voltage to guide a controllable negative shift in the threshold voltage of the driving transistor T1. This counteracts the threshold shift accumulated in the previous frame, ensuring that the charge state and threshold characteristics of the driving transistor T1 before the formal emission phase in each frame can be calibrated to a consistent reference level, thereby improving pixel driving stability and suppressing ghosting and brightness unevenness.

[0114] Optional, such as Figure 10 As shown, the time interval between the end time of the second enable level V21 and the start time of the third enable level V31 is t3, and the time interval between the end time of the fourth enable level V41 and the start time of the fifth enable level V51 is t4, where t4 = t3.

[0115] The scan signal is typically generated by a vertical shift register (VSR) integrated in the bezel area (non-display area) of the display panel.

[0116] In this embodiment, as Figure 10 As shown, the second scan signal scan1 exhibits a double-pulse waveform characteristic, which outputs the second enable level V21 once, and then outputs the third enable level V31 again at an interval of t3.

[0117] The third scan signal, scan2, also exhibits a double-pulse waveform characteristic, outputting the fourth enable level V41 once, followed by an interval of t4 time, and then outputting the fifth enable level V51 again.

[0118] This indicates that the second scan signal scan1 and the third scan signal scan2 have essentially the same pulse interval, and the only difference between them is a certain phase shift on the time axis.

[0119] Based on the consistency of the waveform characteristics mentioned above, when designing the peripheral shift registers of the display panel, the shift registers that output the second scan signal scan1 and the third scan signal scan2 can adopt the same output timing configuration, without the need to design and deploy complex VSR circuits with different pulse intervals for each scan signal.

[0120] Furthermore, under a specific wiring design, the third scan signal scan2 can be directly multiplexed to generate the shift register of the second scan signal scan1 with delay outputs at different levels. This simplifies the number of transistors in the shift registers around the display panel, effectively reducing the overall power consumption and failure rate of the shift registers. It also reduces the area occupied by the shift register circuit on the display panel, which is beneficial for achieving a narrow bezel design and improving the overall screen ratio.

[0121] Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, such as... Figure 11 As shown, optionally, the display panel also includes: The first shift register 51 includes a plurality of first shift units 511 arranged in cascade, and the first shift units 511 are electrically connected to the first scan signal line 33.

[0122] The second shift register 52 includes a plurality of cascaded second shift units 521, which are electrically connected to the second scan signal line 35 and the third scan signal line 36.

[0123] Specifically, such as Figure 11 As shown, a first shift register 51 and a second shift register 52 are integrated in the non-display area NAA around the display panel.

[0124] The first shift register 51 is composed of multiple first shift units 511 cascaded together. The output terminal of each first shift unit 511 is electrically connected to the corresponding first scan signal line 33 to generate and output the first scan signal SN line by line to control the first reset transistor T2 to turn on or off.

[0125] The second shift register 52 is composed of multiple second shift units 521 cascaded together. The output of each second shift unit 521 is simultaneously electrically connected to the corresponding second scan signal line 35 and third scan signal line 36 to generate the second scan signal scan1 and the third scan signal scan2.

[0126] In a conventional pixel-driven architecture, the reset phase and the data write phase are usually controlled by the same set of shift registers. Due to the circuit characteristics of conventional shift registers, the pulse width of their output is limited by the data scan time of a single line (usually one line scan cycle, i.e., 1H), which means that the pulse width of the reset scan signal cannot be independently extended.

[0127] This embodiment decouples the reset control and data write control of the driving transistor T1 in the driving architecture, and assigns the scan signals of the two to two independent shift registers for separate control.

[0128] Specifically, as mentioned earlier, in order to completely clear the residual charge inside the driving transistor T1 and apply a sufficiently strong on-bias stress (OBS) to regulate the threshold voltage of the driving transistor T1, the first scan signal SN needs to output a wide pulse enable level (i.e., the first enable level V11) with a duration of 6H to 18H; while the second scan signal scan1 and the third scan signal scan2 are mainly used for threshold compensation and data writing, and their effective pulse width is usually only a narrow pulse enable level of about 1H (such as the second enable level V21). To ensure that the duration of the first enable level V11 is longer than the duration of the second enable level V21, the first scan signal line 33 providing the first scan signal SN and the second scan signal line 35 providing the second scan signal scan1 are electrically connected to different vertical shift register (VSR) circuits, that is, the first shift register 51 that generates the first scan signal SN and the second shift register 52 that generates the second scan signal scan1 and the third scan signal scan2 are independently arranged in separate areas within the non-display area NAA.

[0129] The second shift register 52 used to generate the second scan signal scan1 can adopt a conventional scan shift register architecture to output a narrower scan pulse (such as the second enable level V21) and make the pulse waveform exhibit a steeper rising edge and falling edge.

[0130] Figure 12 This is a schematic diagram of the structure of a second shifting unit provided in an embodiment of the present invention. Figure 13 for Figure 12 A corresponding signal timing diagram, such as Figure 12 and Figure 13 As shown, exemplarily, the second shifting unit 521 includes: The first transistor M1 has its gate electrically connected to the first clock line CK1, and its first terminal is electrically connected to the output terminal OUT1(i-1) of the second shift unit 521 of the previous stage.

[0131] The second transistor M2 has its gate electrically connected to the first clock line CK1, its first terminal electrically connected to the second terminal of the first transistor M1, and its second terminal electrically connected to the fourth node N4.

[0132] The third transistor M3 has its gate electrically connected to the fourth node N4, its first terminal electrically connected to the first clock line CK1, and its second terminal electrically connected to the fifth node N5.

[0133] The fourth transistor M4 has its gate electrically connected to the first clock line CK1, its first terminal electrically connected to the low-potential signal line VGL, and its second terminal electrically connected to the fifth node N5.

[0134] The fifth transistor M5 has its gate electrically connected to the fifth node N5, and its first terminal is electrically connected to the high-potential signal line VGH.

[0135] The sixth transistor M6 has its gate electrically connected to the second clock line CK2, its first terminal electrically connected to the second terminal of the fifth transistor M5, and its second terminal electrically connected to the fourth node N4.

[0136] The seventh transistor M7 has its gate electrically connected to the low-potential signal line VGL, its first terminal electrically connected to the fourth node N4, and its second terminal electrically connected to the sixth node N6.

[0137] The eighth transistor M8 has its gate electrically connected to the sixth node N6, its first terminal electrically connected to the second clock line CK2, and its second terminal electrically connected to the output terminal OUT1(i).

[0138] The ninth transistor M9 has its gate electrically connected to the fifth node N5, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the output terminal OUT1(i).

[0139] The first capacitor C1 has its first plate electrically connected to the sixth node N6, and its second plate electrically connected to the output terminal OUT1(i).

[0140] The second capacitor C2 has its first plate electrically connected to the fifth node N5, and its second plate electrically connected to the high-potential signal line VGH.

[0141] It should be noted that, Figure 12 This is just one example of the structure of the second shift unit 521. In other optional embodiments of the present invention, other structures of the second shift unit 521 may also be used to output the signal waveforms required by the second scan signal line 35 and the third scan signal line 36 (such as the second scan signal scan1 and the third scan signal scan2) through the output terminal OUT1(i).

[0142] Furthermore, the first shift register 51 used to generate the first scan signal SN can adopt an architecture adapted to a large duty cycle working mode. Its circuit structure can be borrowed from the shift register circuit that generates the light emission control signal (such as the EmissionVoltage Shift Register, Emit VSR) to break through the hardware limitation that the traditional scan shift register circuit can only output short pulses. This allows for flexible adjustment and stable output of the first enable level V11, which is much wider than the conventional scan pulse (for example, its pulse width can be configured to 6H to 18H), thus achieving a full reset of the driving transistor T1.

[0143] Figure 14 This is a schematic diagram of the structure of a first shifting unit provided in an embodiment of the present invention. Figure 15 for Figure 14 A corresponding signal timing diagram, such as Figure 14 and Figure 15 As shown, exemplarily, the first shifting unit 511 includes: The tenth transistor M10 has its gate electrically connected to the third clock line CK3, its first terminal electrically connected to the output terminal Out2(i-1) of the first shift unit 511 of the previous stage, and its second terminal electrically connected to the seventh node N7.

[0144] The eleventh transistor M11 has its gate electrically connected to the third clock line CK3, its first terminal electrically connected to the low-potential signal line VGL, and its second terminal electrically connected to the eighth node N8.

[0145] The twelfth transistor M12 has its gate electrically connected to the seventh node N7, its first terminal electrically connected to the third clock line CK3, and its second terminal electrically connected to the eighth node N8.

[0146] The thirteenth transistor M13 has its gate electrically connected to the low-potential signal line VGL, and its first terminal is electrically connected to the eighth node N8.

[0147] The fourteenth transistor M14 has its gate electrically connected to the second terminal of the thirteenth transistor M13, and its first terminal is electrically connected to the fourth clock line CK4.

[0148] The fifteenth transistor M15 has its gate electrically connected to the fourth clock line CK4, its first terminal electrically connected to the second terminal of the fourteenth transistor M14, and its second terminal electrically connected to the ninth node N9.

[0149] The sixteenth transistor M16 has its gate electrically connected to the seventh node N7, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the ninth node N9.

[0150] The seventeenth transistor M17 has its gate electrically connected to the eighth node N8, and its first terminal is electrically connected to the high-potential signal line VGH.

[0151] The eighteenth transistor M18 has its gate electrically connected to the low-potential signal line VGL, its first terminal electrically connected to the seventh node N7, and its second terminal electrically connected to the tenth node N10.

[0152] The nineteenth transistor M19 has its gate electrically connected to the tenth node N10, its first terminal electrically connected to the fourth clock line CK4, and its second terminal electrically connected to the second terminal of the seventeenth transistor M17.

[0153] The twentieth transistor M20 has its gate electrically connected to the control line Reset, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the seventh node N7.

[0154] The twenty-first transistor M21 has its gate electrically connected to the ninth node N9, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the output terminal Out1(i).

[0155] The gate of the twenty-second transistor M22 is electrically connected to the tenth node N10, its first terminal is electrically connected to the low-potential signal line VGL, and its second terminal is electrically connected to the output terminal Out2(i).

[0156] The third capacitor C3 has its first plate electrically connected to the gate of the fourteenth transistor M14, and its second plate electrically connected to the second plate of the fourteenth transistor M14.

[0157] The fourth capacitor C4 has its first plate electrically connected to the second plate of the nineteenth transistor M19, and its second plate is electrically connected to the tenth node N10.

[0158] The fifth capacitor C5 has its first plate electrically connected to the ninth node N9, and its second plate electrically connected to the high-potential signal line VGH.

[0159] Figure 16 This is a schematic diagram of another first shift unit provided in an embodiment of the present invention, as shown below. Figure 16 As shown, exemplarily, the first shifting unit 511 includes: The gate of the twenty-third transistor M23 is electrically connected to the fifth clock line CK5, its first terminal is electrically connected to the output terminal Out2(i-1) of the first shift unit 511 of the previous stage, and its second terminal is connected to the eleventh node N11.

[0160] The twenty-fourth transistor M24 has its gate connected to the eleventh node N11, its first terminal electrically connected to the twelfth node N12, and its second terminal electrically connected to the fifth clock line CK5.

[0161] The 25th transistor M25 has its gate electrically connected to the fifth clock line CK5, its first terminal electrically connected to the low-potential signal line VGL, and its second terminal electrically connected to the 12th node N12.

[0162] The gate of the twenty-sixth transistor M26 is electrically connected to the twelfth node N12, its first terminal is connected to the high-potential signal line VGH, and its second terminal is electrically connected to the first terminal of the twenty-seventh transistor M27.

[0163] The twenty-eighth transistor M28 has its gate electrically connected to the low-potential signal line VGL, its first terminal connected to the eleventh node N11, and its second terminal connected to the thirteenth node N13.

[0164] The twenty-seventh transistor M27 has its gate electrically connected to the thirteenth node N13, its first terminal electrically connected to the fourteenth node N14, and its second terminal electrically connected to the sixth clock line CK6.

[0165] The gate of the twenty-eighth transistor M28 is electrically connected to the low-potential signal line VGL, its first terminal is electrically connected to the twelfth node N12, and its second terminal is electrically connected to the gate of the twenty-ninth transistor M29.

[0166] The gate of the twenty-ninth transistor M29 is electrically connected to the first plate of the sixth capacitor C6, its first plate is electrically connected to the second plate of the sixth capacitor C6, and its second plate is electrically connected to the sixth clock line CK6.

[0167] The thirtieth transistor M30 has its gate electrically connected to the sixth clock line CK6, its first terminal electrically connected to the first terminal of the twenty-ninth transistor M29, and its second terminal electrically connected to the fifteenth node N15.

[0168] The thirty-first transistor M31 has its gate electrically connected to the eleventh node N11, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the fifteenth node N15.

[0169] The gate of the thirty-second transistor M32 is electrically connected to the fifteenth node N15, its first terminal is electrically connected to the high-potential signal line VGH, and its second terminal is electrically connected to the output terminal OUT2(i).

[0170] The gate of the thirty-third transistor M33 is electrically connected to the thirteenth node N13, its first terminal is electrically connected to the low-potential signal line VGL, and its second terminal is electrically connected to the output terminal OUT2(i).

[0171] The sixth capacitor C6 has its first plate electrically connected to the second plate of the twenty-eighth transistor M28, and its second plate is electrically connected to the first plate of the thirtieth transistor M30.

[0172] The seventh capacitor C7 has its first plate electrically connected to the high-potential signal line VGH, and its second plate electrically connected to the fifteenth node N15.

[0173] The eighth capacitor C8 has its first plate electrically connected to the thirteenth node N13, and its second plate electrically connected to the fourteenth node N14.

[0174] It should be noted that, Figure 14 and Figure 16 This is merely a structural example of the first shift unit 511. In other optional embodiments of the present invention, other structures of the first shift unit 511 may be used to output the signal waveform (i.e., the first scan signal SN) required by the first scan signal line 33 through the output terminal Out2(i).

[0175] Furthermore, the above embodiments are only illustrated using the example of all transistors being P-type thin-film transistors, but are not limited to this.

[0176] In this embodiment, by independently setting the first shift register 51 and the second shift register 52, the reset duration and data writing timing can be independently adjusted, thereby achieving a sufficient extension of the reset time of the driving transistor T1.

[0177] Furthermore, the same second shift unit 521 simultaneously provides the required scan signals (i.e., second scan signal scan1 and third scan signal scan2) to the second scan signal line 35 and the third scan signal line 36. Through specific routing design, two signals that meet the timing requirements of the second scan signal scan1 and the third scan signal scan2 of the same second shift unit 521 can be output simultaneously from different output nodes within the same second shift unit 521 (e.g., by leading out the cascaded output terminal and the scan output terminal of the current stage respectively), or from the output nodes of several adjacent cascaded second shift units 521, by making simple logical combination connections. These two signals are then output to the corresponding second scan signal line 35 and third scan signal line 36 respectively. This avoids the need to add a separate set of shift registers for the third scan signal line 36, reduces the number of thin-film transistors in the non-display area NAA, reduces the overall power consumption of the shift register, and reduces the space occupied by the shift register in the display panel bezel area, achieving a narrow bezel effect.

[0178] Optional, such as Figure 11 As shown, the display panel also includes multiple rows 10R of pixel driving circuits arranged along the column direction Y, and each row 10R includes multiple pixel driving circuits 10 arranged along the row direction X. The second scan signal line 35 connected to the nth row of pixel driving circuits 10R is electrically connected to the nth stage second shift unit 521. The third scan signal line 36 connected to the nth row of pixel driving circuits 10R is electrically connected to the (n+k)th stage second shift unit 521. Here, n is a positive integer greater than 0, and k is a positive integer greater than 1.

[0179] The second shift register 52 is composed of multiple cascaded second shift units 521. The input terminal of the i-th stage second shift unit 521 (i is a positive integer greater than 1) is electrically connected to the output terminal of the (i-1)-th stage second shift unit 521, thereby realizing the step-by-step shifting and transmission of the scan signal.

[0180] In a conventional pixel-driven architecture, in order to output the second scan signal scan1 and the third scan signal scan2 with different timings, two independent shift register circuits are usually arranged in the non-display area NAA (i.e., the bezel area) of the display panel, which occupies a lot of bezel wiring space.

[0181] In this embodiment, the second scan signal scan1 and the third scan signal scan2 applied to the same row of pixel driving circuit row 10R are generated by two different second shift units 521 that are k levels apart in the second shift register 52, so that the pulse of the third scan signal scan2 has a fixed delay relative to the pulse of the second scan signal scan1, which corresponds to k row scan cycles.

[0182] Through the above connection method, a single second shift register 52 can be used to generate two sets of scan signals with precise timing offsets (second scan signal scan1 and third scan signal scan2), which are used to control different transistors in the pixel driving circuit 10 (data writing transistor T4 and threshold compensation transistor T3), thereby simplifying the number of transistors in the shift registers around the display panel. This not only effectively reduces the overall operating power consumption and failure rate of the shift registers, but also reduces the area occupied by the shift register circuit on the display panel, which is conducive to achieving a narrow bezel design and improving the overall screen ratio.

[0183] Where k is a positive integer greater than 1, and its specific value can be set according to the actual driving timing requirements of the display panel. For example, k can be 2, 3, 4, 5 or larger values ​​to stagger the enable levels of the second scan signal scan1 and the third scan signal scan2 in time.

[0184] Optional, such as Figure 11 As shown, the display panel also includes a display area AA. The display panel includes two second shift registers 52, one of which is located on the same side of the display area AA as the first shift register 51, and the other is located on the opposite side of the display area AA as the first shift register 51.

[0185] Specifically, such as Figure 11 As shown, the display panel includes a display area AA, which has multiple pixel driving circuits 10 arranged in an array along the row direction X and the column direction Y for displaying images. A non-display area NAA surrounds the display area AA.

[0186] In this embodiment, a first shift register 51 and two second shift registers 52 are arranged in the non-display area NAA. One of the second shift registers 52 is arranged on the same side of the display area AA (e.g., the right border) along with the first shift register 51; while the other second shift register 52 is arranged separately on the opposite side of the display area AA (e.g., the left border). In this case, the second shift register 52 adopts a dual-sided arrangement (dual-sided drive) structure.

[0187] As mentioned earlier, the second shift register 52 is used to output the second scan signal scan1 and the third scan signal scan2. The effective pulse width of these signals during the data writing phase T20 (i.e., the third enable level V31 and the fourth enable level V41) is relatively narrow. In large-size or high-resolution panels, the second scan signal line 35 and the third scan signal line 36, which span the entire display area AA, will generate a large parasitic RC load (resistance-capacitance delay), causing the third enable level V31 and the fourth enable level V41 to be distorted and delayed at the far end.

[0188] In this embodiment, the two second shift registers 52 are arranged on opposite sides of the display area AA, forming a bilateral driving architecture. The third enable level V31 and the fourth enable level V41 are connected to the pixel driving circuit row 10R from different sides, which can significantly reduce the RC delay difference between the second scan signal line 35 and the third scan signal line 36, reduce the uneven brightness caused by inconsistent signal delay, and improve the uniformity of the entire display. At the same time, this layout is also conducive to the realization of narrow bezel design, increasing the screen-to-body ratio of the display panel.

[0189] Optional, such as Figure 6 , Figure 7 , Figure 9 and Figure 10 As shown, the pixel driving circuit 10 also includes a light-emitting control transistor T5. The gate of the light-emitting control transistor T5 is electrically connected to the light-emitting control signal line 38 that provides the light-emitting scan signal EMIT. The light-emitting control transistor T5, the driving transistor T1, and the light-emitting element 20 are connected in series between the first power supply voltage signal line 31 and the second power supply voltage signal line 32. The operation of the display panel includes a light-emitting stage T100 and a non-light-emitting stage T200. In the light-emitting stage T100, the light-emitting control transistor T5 has a light-emitting enable level V61 that controls the light-emitting control transistor T5 to be turned on. In the non-light-emitting stage T200, the light-emitting control transistor T5 has a non-light-emitting enable level V62 that controls the light-emitting control transistor T5 to be turned off. The first reset stage T10 is located within the non-light-emitting stage T200.

[0190] Specifically, the display panel is divided into a light-emitting stage T100 and a non-light-emitting stage T200 in each frame of operation. In the light-emitting stage T100, the light-emitting control signal line 38 outputs a light-emitting enable level V61. The light-emitting enable level V61 is configured to control the light-emitting control transistor T5 to be turned on, so that the light-emitting control transistor T5 is in the on state, thereby allowing the driving current to be transmitted to the light-emitting element 20 through the on-state driving transistor T1 and the light-emitting control transistor T5, driving the light-emitting element 20 to emit light.

[0191] During the non-light-emitting stage T200, the light-emitting control signal line 38 outputs a non-light-emitting enable level V62. The non-light-emitting enable level V62 is configured to control the light-emitting control transistor T5 to turn off, so that the light-emitting control transistor T5 switches to the off state, thereby cutting off the current path flowing through the light-emitting element 20 and stopping it from emitting light.

[0192] Furthermore, the first reset stage T10, the data writing stage T20, and the second reset stage T30 are all fully configured within the non-light-emitting stage T200, ensuring that the light-emitting control transistor T5 is always in the off state during the first reset stage T10, the data writing stage T20, and the second reset stage T30. This effectively avoids unexpected light emission (such as dark-state light leakage) caused by leakage current during the reset or data writing process, thereby improving display contrast and image quality.

[0193] In some embodiments, such as Figure 6 As shown, the light-emitting control transistor T5 includes a first light-emitting control transistor T51 and a second light-emitting control transistor T52. The first light-emitting control transistor T51 is connected in series between the first power supply voltage signal line 31 and the first terminal T11 of the driving transistor T1. The second light-emitting control transistor T52 is connected in series between the second terminal T12 of the driving transistor T1 and the light-emitting element 20. During the non-light-emitting stage T200, the light-emitting control signal line 38 outputs a non-light-emitting enable level V62, controlling the first light-emitting control transistor T51 and the second light-emitting control transistor T52 to be turned off simultaneously. This effectively blocks the current path from the first power supply voltage signal line 31 to the light-emitting element 20, avoiding dark-state leakage caused by leakage current of a single light-emitting control transistor T5 or incomplete turn-off, thus improving display contrast.

[0194] Optional, such as Figure 7 , Figure 9 and Figure 10 As shown, the time interval between the start time of the non-light emission enable level V62 and the start time of the first enable level V11 is t5, where t5 ≥ H; H is the row scan period.

[0195] In the driving timing of the display panel, a predetermined time interval t5 is set between the start time of the non-light-emitting enable level V62 (used to control the light-emitting control transistor T5 to turn off) and the start time of the first enable level V11 (used to control the first reset transistor T2 to turn on).

[0196] In this embodiment, the time interval t5 satisfies t5≥H, where H is a row scan cycle (i.e., the time interval between two adjacent rows of pixels being scanned sequentially, usually equal to one frame time divided by the total number of rows).

[0197] This timing design ensures that the light-emitting control transistor T5 is stably in the off state before initiating a reset operation (e.g., node reset in the first reset phase T10). Specifically, since the time interval t5 is not less than one complete row scan cycle, even considering factors such as signal transmission delay, transistor turn-off transient response, or process variations, it can be fully guaranteed that the channel current of the light-emitting control transistor T5 has decayed to a negligible level, thereby completely cutting off the path flowing through the light-emitting element 20.

[0198] Based on this, the subsequent first enable level V11 is then used to perform a reset operation (such as resetting the gate, first terminal, and second terminal of the driving transistor T1). This effectively avoids the reset charge being bypassed by the branch where the light-emitting element is located or the generation of unexpected weak light emission due to the light-emitting control transistor T5 not being completely turned off during the reset process, thus improving the reset accuracy and dark display effect.

[0199] Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 17 As shown, optionally, the display panel also includes: The first shift register 51 includes a plurality of first shift units 511 arranged in cascade, and the first shift units 511 are electrically connected to the first scan signal line 33.

[0200] The third shift register 53 includes multiple cascaded third shift units 531, and the third shift units 531 are electrically connected to the light emission control signal line 38.

[0201] The display panel also includes a display area AA, with the first shift register 51 and the third shift register 53 located on opposite sides of the display area AA.

[0202] Specifically, such as Figure 17 As shown, the display panel includes a display area AA, which has multiple pixel driving circuits 10 arranged in an array along the row direction X and the column direction Y for displaying images. A non-display area NAA surrounds the display area AA.

[0203] In this embodiment, a first shift register 51 and a third shift register 53 are arranged within the non-display area (NAA). The first shift register 51 includes multiple cascaded first shift units 511, the output of each first shift unit 511 being electrically connected to a corresponding first scan signal line 33, for providing a first scan signal SN to the pixel driving circuit 10. The third shift register 53 includes multiple cascaded third shift units 531, each third shift unit 531 being electrically connected to a corresponding light emission control signal line 38, for providing a light emission scan signal EMIT to the light emission control transistor T5 in the pixel driving circuit 10.

[0204] In terms of physical layout, the first shift register 51 and the third shift register 53 are configured independently and placed on opposite sides of the display area AA, respectively. For example, as Figure 17 As shown, the first shift register 51 can be located on the right (or left) side of the display area AA, while the third shift register 53 is located on the left (or right) side of the display area AA. This allows the display area AA to share the area pressure of bezel routing and transistor stacking with the non-display areas NAA on both sides, avoiding the problem of a wider bezel on that side due to excessive concentration of shift registers on one side of the display panel.

[0205] Meanwhile, by using a large display area AA as a physical isolation zone, placing the first shift register 51 and the third shift register 53 at opposite ends of the display panel, it is also beneficial to reduce signal crosstalk between the first shift register 51 and the third shift register 53 and improve the stability of the display panel's brightness.

[0206] Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 19 A signal timing diagram of another pixel driving circuit provided in an embodiment of the present invention, such as... Figure 18 and Figure 19 As shown, optionally, the display panel also includes multiple rows 10R of pixel driving circuits arranged along the column direction Y, and the rows 10R of pixel driving circuits include multiple pixel driving circuits 10 arranged along the row direction X. A first shift unit 511 is electrically connected to the first scan signal lines 33 corresponding to the m rows 10R of pixel driving circuits, and a third shift unit 531 is electrically connected to the light emission control signal lines 38 corresponding to the m rows 10R of pixel driving circuits, where m is a positive integer greater than 1.

[0207] Specifically, the display panel has multiple rows 10R of pixel driving circuits arranged along the column direction Y in the display area AA. Each row 10R of pixel driving circuits is composed of multiple pixel driving circuits 10 arranged along the row direction X, thereby forming a two-dimensional pixel array.

[0208] The output terminal of a first shift unit 511 (used to output the first scan signal SN) is electrically connected to the first scan signal line 33 corresponding to m adjacent pixel driving circuit rows 10R.

[0209] The output of a third shift unit 531 (used to output the light emission scanning signal EMIT) is electrically connected to the light emission control signal line 38 corresponding to the adjacent m pixel driving circuit row 10R.

[0210] Where m is a positive integer greater than 1, that is, each first shift unit 511 simultaneously drives the first scan signal line 33 corresponding to the multi-row pixel driving circuit 10, and each third shift unit 531 simultaneously drives the light emission control signal line 38 corresponding to the multi-row pixel driving circuit 10.

[0211] like Figure 19 As shown, taking m=2 as an example, the working timing of the two adjacent rows of pixel driving circuits 10 is explained. scan1(i) and scan2(i) are defined as the second scan signal scan1 and the third scan signal scan2 input to the i-th row pixel driving circuit 10; scan1(i+1) and scan2(i+1) are defined as the second scan signal scan1 and the third scan signal scan2 input to the (i+1)-th row pixel driving circuit 10.

[0212] The first scanning signal line 33 corresponding to the pixel driving circuit 10 of the i-th row and the (i+1)-th row is electrically connected to the same first shift unit 511; the light emission control signal line 38 corresponding to the pixel driving circuit 10 of the i-th row and the (i+1)-th row is electrically connected to the same third shift unit 531.

[0213] The shared light emission control signal EMIT outputs a light emission enable level V61 during the light emission phase T100 and a non-light emission enable level V62 during the non-light emission phase T200. The non-light emission phase T200 covers not only all the reset and data writing operations of the i-th row pixel driving circuit 10 (first reset phase T10, data writing phase T20, and second reset phase T30) in terms of time span, but also the reset and data writing operations corresponding to the (i+1)-th row pixel driving circuit 10 that are executed later due to cascading delay. This allows the two rows of pixel driving circuits 10 to share the same light emission scan signal EMIT even when their timing is misaligned, thereby reducing the number of third shift units 531 in the non-display area NAA.

[0214] Simultaneously, during the first reset phase T10, the shared first scan signal SN outputs a first enable level V11 with a relatively long duration. The second scan signal scan1(i) of the i-th row first outputs a second enable level V21 during this period; after a delay of one row scan cycle (1H), the second scan signal scan1(i+1) of the i+1-th row subsequently outputs its corresponding second enable level V21. Because the duration of the first enable level V11 is relatively long, a single first enable level V11 can cover the two second enable levels V21 of the i-th and i+1-th rows, thereby allowing the two row pixel driving circuits 10 to share the same first scan signal SN even when their timing is misaligned, thus reducing the number of first shift units 511 in the non-display area NAA.

[0215] In this embodiment, the above-described scheme is adopted, and the total number of cascaded units required for the first shift register 51 and the third shift register 53 can be reduced to 1 / m of the total number of rows, thereby reducing the number of the first shift unit 511 and the third shift unit 531 in the non-display area NAA (border area), which is beneficial to achieving a narrow border design.

[0216] It should be noted that the above embodiment is only illustrated with m=2 as an example. Under the condition that the resolution or timing allows, the value of m can also be set to 3 or 4 to further reduce the number of the first shift unit 511 and the third shift unit 531 in the non-display area NAA (border area), thereby further compressing the border width and reducing the cost.

[0217] Optional, such as Figure 6 As shown, the display panel also includes: Anode reset transistor T6 has its gate T60 electrically connected to the fourth scan signal line 39, its first terminal T61 electrically connected to the second reference voltage line 70, and its second terminal T60 electrically connected to the anode of the light-emitting element 20. The fourth scan signal line 39 is the same signal line as one of the first scan signal line 33, the second scan signal line 35, and the third scan signal line 36.

[0218] In particular, after the non-light-emitting phase T200 of the previous frame ends, there will be residual charge on the parasitic capacitance inherent in the anode of the light-emitting element 20. These residual charges will be superimposed with the new driving current in the light-emitting phase T100 of the current frame, resulting in unexpected dim brightness or flickering, affecting the display uniformity of the display panel under low brightness and low grayscale.

[0219] In this embodiment, by setting the anode reset transistor T6, before entering the light emission stage T100 of the current frame, the enable level output by the fourth scan signal line 39 is used to control the anode reset transistor T6 to be turned on, so that the second reference voltage VREF2 on the second reference voltage line 70 is transmitted to the anode of the light emission element 20, thereby initializing and resetting the anode of the light emission element 20 to eliminate the residual charge of the previous frame and improve grayscale accuracy and display uniformity.

[0220] Furthermore, the fourth scan signal line 39 is the same signal line as one of the first scan signal line 33, the second scan signal line 35, and the third scan signal line 36.

[0221] In some embodiments, the fourth scan signal line 39 and the first scan signal line 33 share the same scan signal line. The scan signal on the fourth scan signal line 39 is the first scan signal SN. At this time, the anode reset transistor T6 is controlled by the first scan signal SN and is turned on in the first reset stage T10 to complete the reset of the anode of the light-emitting element 20.

[0222] In some embodiments, the fourth scan signal line 39 and the second scan signal line 35 share the same scan signal line. The scan signal on the fourth scan signal line 39 is the second scan signal scan1. At this time, the anode reset transistor T6 is controlled by the second scan signal scan1 and is turned on in the second reset stage T102 to complete the reset of the anode of the light-emitting element 20.

[0223] In some embodiments, the fourth scan signal line 39 and the third scan signal line 36 share the same scan signal line. The scan signal on the fourth scan signal line 39 is the third scan signal scan2. At this time, the anode reset transistor T6 is controlled by the third scan signal scan2. In the second reset stage, T30 is turned on to complete the reset of the anode of the light-emitting element 20.

[0224] With the above reuse design, there is no need to add an additional independent scan signal line for the anode reset transistor T6, which can reduce wiring density, simplify driving timing, and improve the integration and yield of the display panel.

[0225] Optional, such as Figure 6 As shown, the pixel driving circuit 10 also includes a storage capacitor Cst, which is connected in series between the first power supply voltage signal line 31 and the gate T10 (i.e., the first node N1) of the driving transistor T1, and is used to store the signal transmitted to the gate T10 (i.e., the first node N1) of the driving transistor T1.

[0226] Optional, such as Figure 6 As shown, both the first reset transistor T2 and the threshold compensation transistor T3 are dual-gate transistors to reduce the leakage current of the first reset transistor T2 and the threshold compensation transistor T3 in the off state, avoid the leakage current from affecting the node potential of the driving transistor T1, and improve the compensation accuracy of the threshold voltage of the driving transistor T1.

[0227] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a display panel. This driving method can be used to drive any of the display panels provided in the above embodiments, wherein the display panel includes a pixel driving circuit, and the pixel driving circuit includes: A driving transistor and a light-emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line.

[0228] The first reset transistor has its gate electrically connected to a first scan signal line that provides a first scan signal, its first terminal electrically connected to a first reference voltage signal line that provides a first reference voltage, and its second terminal connected to the second terminal of the driving transistor at a third node.

[0229] A threshold compensation transistor has its gate electrically connected to a second scan signal line that provides a second scan signal. The first terminal of the threshold compensation transistor is connected to the gate of the driving transistor at a first node, and the second terminal of the threshold compensation transistor is connected to a third node.

[0230] The data writing transistor has its gate electrically connected to the third scan signal line that provides the third scan signal, its first terminal electrically connected to the data voltage signal line that provides the data voltage, and its second terminal connected to the first terminal of the driving transistor at the second node.

[0231] The structural description of the display panel and the explanation of the terminology described above can be found in any of the above embodiments, and will not be repeated here.

[0232] Furthermore, the driving method includes: In the first reset phase, the first scan signal is controlled to output a first enable level that controls the first reset transistor to turn on; and within the time covered by the first enable level, the second scan signal is controlled to output a second enable level that controls the threshold compensation transistor to turn on; wherein the duration of the first enable level is greater than the duration of the second enable level.

[0233] The display panel driving method provided in this invention decouples the reset control of the pixel driving circuit from the data voltage writing control in the circuit architecture. During the first reset phase, a first scan signal and a second scan signal are provided respectively. The duration of the first enable level of the first scan signal is lengthened in the driving timing configuration, allowing the driving transistor to be subjected to a sufficient and sustained combined effect of on-bias stress (OBS) and negative bias stress (NBS). This strong electric field stress resets the charge distribution inside the driving transistor, eliminating the hysteresis effect accumulated by the driving transistor due to different light emission states in the previous frame, thus improving the image retention problem of the display panel. Simultaneously, by lengthening the duration of a single first enable level, the first, second, and third nodes of the driving transistor are completely reset, eliminating residual charge and potential pulling interference between nodes. This ensures that the abnormal brightness problem of the first frame during screen switching is improved with fewer driving pulses. This solution not only avoids interference caused by the preceding row data voltage during virtual writing and solves the abnormal display problem of "black text with bright bars" at the boundary between light and dark areas, but also reduces the overall operating power consumption of the driving IC.

[0234] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 20 As shown, the display device 80 includes the display panel 81 described in any embodiment of the present invention. Therefore, the display device 80 provided by the embodiments of the present invention has the technical effects of the technical solutions in any of the above embodiments. The explanations of the same or corresponding structures and terms as described in the above embodiments will not be repeated here.

[0235] The display device 80 provided in this embodiment of the invention can be Figure 20 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0236] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0237] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, Includes a pixel driving circuit, the pixel driving circuit comprising: A driving transistor, wherein the driving transistor and the light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line; A first reset transistor, wherein the gate of the first reset transistor is electrically connected to a first scan signal line providing a first scan signal, the first terminal of the first reset transistor is electrically connected to a first reference voltage signal line providing a first reference voltage, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor at a third node; A threshold compensation transistor, wherein the gate of the threshold compensation transistor is electrically connected to a second scan signal line that provides a second scan signal, the first terminal of the threshold compensation transistor is connected to the gate of the driving transistor at a first node, and the second terminal of the threshold compensation transistor is connected to the third node; A data writing transistor, wherein the gate of the data writing transistor is electrically connected to a third scan signal line that provides a third scan signal, the first terminal of the data writing transistor is electrically connected to a data voltage signal line that provides a data voltage, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor at a second node; The operation of the display panel includes a first reset phase. In the first reset phase, the first scan signal has a first enable level that controls the first reset transistor to turn on. During the time covered by the first enable level, the second scan signal has a second enable level that controls the threshold compensation transistor to turn on. The duration of the first enable level is greater than the duration of the second enable level.

2. The display panel according to claim 1, characterized in that, During the first reset phase, the first scan signal has only one first enable level; During the time covered by the first enable level, the second scan signal has only one second enable level.

3. The display panel according to claim 1, characterized in that, During the first reset phase, the start time of the first enable level is earlier than the start time of the second enable level.

4. The display panel according to claim 1, characterized in that, During the first reset phase, the end time of the first enable level is later than the end time of the second enable level.

5. The display panel according to claim 1, characterized in that, During the first reset phase, the start time of the first enable level is earlier than the start time of the second enable level, and the end time of the first enable level is later than the end time of the second enable level. The time interval between the start time of the first enable level and the start time of the second enable level is t1, and the time interval between the end time of the first enable level and the end time of the second enable level is t2, where t1 < t2.

6. The display panel according to claim 1, characterized in that, During the first reset phase, the start time of the first enable level is earlier than the start time of the second enable level, and the end time of the first enable level is later than the end time of the second enable level. The time interval between the start time of the first enable level and the start time of the second enable level is t1, and the time interval between the end time of the first enable level and the end time of the second enable level is t2, where t1 ≥ t2.

7. The display panel according to claim 1, characterized in that, The first reference voltage is VREF1; During the first reset phase, -4.5V ≤ VREF1 ≤ -3V.

8. The display panel according to claim 1, characterized in that, The operation of the display panel also includes a data writing phase following the first reset phase; During the data writing phase, the second scan signal has a third enable level that controls the threshold compensation transistor to turn on, the third scan signal has a fourth enable level that controls the data writing transistor to turn on, and the third enable level and the fourth enable level have an overlapping period. Within one frame, the operation of the display panel consists of only one data writing phase.

9. The display panel according to claim 8, characterized in that, The time interval between the end time of the second enable level and the start time of the third enable level is t3, where t3 ≥ 2H; H represents the row scan cycle.

10. The display panel according to claim 8, characterized in that, The operation of the display panel also includes a second reset phase following the data writing phase; During the second reset phase, the third scan signal has a fifth enable level that controls the data write transistor to turn on.

11. The display panel according to claim 10, characterized in that, The time interval between the end time of the second enable level and the start time of the third enable level is t3, and the time interval between the end time of the fourth enable level and the start time of the fifth enable level is t4, where t4 = t3.

12. The display panel according to claim 1, characterized in that, The display panel also includes: The first shift register includes a plurality of cascaded first shift units, and the first shift units are electrically connected to the first scan signal line; The second shift register includes a plurality of cascaded second shift units, which are electrically connected to the second scan signal line and the third scan signal line.

13. The display panel according to claim 12, characterized in that, The display panel further includes multiple rows of pixel driving circuits arranged along the column direction, and each row of pixel driving circuits includes multiple pixel driving circuits arranged along the row direction. The second scan signal line connected to the pixel driving circuit in the nth row is electrically connected to the second shift unit in the nth stage. The third scan signal line connected to the pixel driving circuit row in the nth row is electrically connected to the second shift unit of the (n+k)th stage. Where n is a positive integer greater than 0, and k is a positive integer greater than 1.

14. The display panel according to claim 12, characterized in that, The display panel also includes a display area; The display panel includes two second shift registers, one of which is located on the same side of the display area as the first shift register, and the other of which is located on the opposite side of the display area as the first shift register.

15. The display panel according to claim 1, characterized in that, The pixel driving circuit further includes a light-emitting control transistor, the gate of which is electrically connected to a light-emitting control signal line that provides a light-emitting scanning signal, and the light-emitting control transistor, the driving transistor, and the light-emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line. The operation of the display panel includes a light-emitting stage and a non-light-emitting stage; During the light-emitting phase, the light-emitting control transistor has a light-emitting enable level that controls the conduction of the light-emitting control transistor; During the non-light-emitting phase, the light-emitting control transistor has a non-light-emitting enable level that controls the light-emitting control transistor to be turned off; The first reset phase is located within the non-light-emitting phase.

16. The display panel according to claim 15, characterized in that, The time interval between the start time of the non-light-emitting enable level and the start time of the first enable level is t5, where t5 ≥ H; H represents the row scan cycle.

17. The display panel according to claim 15, characterized in that, The display panel also includes: The first shift register includes a plurality of cascaded first shift units, and the first shift units are electrically connected to the first scan signal line; The third shift register includes multiple cascaded third shift units, and the third shift units are electrically connected to the light emission control signal line; The display panel also includes a display area; The first shift register and the third shift register are located on opposite sides of the display area.

18. The display panel according to claim 17, characterized in that, The display panel further includes multiple rows of pixel driving circuits arranged along the column direction, and each row of pixel driving circuits includes multiple pixel driving circuits arranged along the row direction. Wherein, one of the first shift units is electrically connected to the first scan signal lines corresponding to the m rows of the pixel driving circuits, and one of the third shift units is electrically connected to the light emission control signal lines corresponding to the m rows of the pixel driving circuits, where m is a positive integer greater than 1.

19. The display panel according to claim 1, characterized in that, The display panel also includes: An anode reset transistor, wherein the gate of the anode reset transistor is electrically connected to a fourth scan signal line, the first terminal of the anode reset transistor is electrically connected to a second reference voltage line, and the second terminal of the anode reset transistor is electrically connected to the anode of the light-emitting element; The fourth scan signal line is the same as one of the first scan signal line, the second scan signal line, and the third scan signal line.

20. A driving method for a display panel, characterized in that, The display panel includes a pixel driving circuit, which includes: A driving transistor, wherein the driving transistor and the light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line; A first reset transistor, wherein the gate of the first reset transistor is electrically connected to a first scan signal line providing a first scan signal, the first terminal of the first reset transistor is electrically connected to a first reference voltage signal line providing a first reference voltage, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor at a third node; A threshold compensation transistor, wherein the gate of the threshold compensation transistor is electrically connected to a second scan signal line that provides a second scan signal, the first terminal of the threshold compensation transistor is connected to the gate of the driving transistor at a first node, and the second terminal of the threshold compensation transistor is connected to the third node; A data writing transistor, wherein the gate of the data writing transistor is electrically connected to a third scan signal line that provides a third scan signal, the first terminal of the data writing transistor is electrically connected to a data voltage signal line that provides a data voltage, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor at a second node; The driving method includes: In the first reset phase, the first scan signal is controlled to output a first enable level that controls the first reset transistor to turn on; and within the time covered by the first enable level, the second scan signal is controlled to output a second enable level that controls the threshold compensation transistor to turn on; wherein the duration of the first enable level is greater than the duration of the second enable level.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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