A V 2 Three-level buck-boost converter with COT control

Abstract

The application belongs to the technical field of power management circuit, and particularly relates to a three-level buck-boost converter adopting V 2 COT control. The three-level buck-boost converter comprises: a power stage module, which is used for converting an input voltage into a stable output voltage by controlling the conduction and turn-off of a power switch tube according to a driving signal output by a digital control module; an analog control module, which is used for generating a first control signal according to the difference between the output voltage and a reference voltage, and comparing the first control signal with a feedback output voltage after being superimposed with a ramp signal to generate a second control signal input to the digital control module; and the digital control module, which is used for determining that the system works in a Buck mode, a Boost mode or a detection mode according to the second control signal and a mode selection signal generated by a finite state machine. The application realizes fast transient response and good stability, and simultaneously considers the smoothness of multi-mode switching and the voltage balance of a flying capacitor.

Description

Technical Field

[0001] This invention belongs to the field of power management circuit technology, and specifically relates to a power management circuit using V 2 COT-controlled three-level buck-boost converter. Background Technology

[0002] With the rapid development of portable mobile electronic devices, battery-powered systems are placing increasingly stringent performance requirements on power management chips (PMICs). Core modules such as RF power amplifiers, LED drivers, and CPUs / GPUs not only need DC-DC converters to adapt to the wide input voltage range of lithium batteries (2.7V~4.2V), but also need to meet requirements such as dynamic voltage scaling (DVS) and transient switching under large loads. Among these, the BUCK-BOOST converter, with its ability to operate in buck, buck-boost, and boost modes, has become the core topology for wide input and output voltage scenarios. Regarding control mode selection, in addition to traditional voltage-mode control and current-mode control, ripple-based constant on-time (COT) control, with its inherently high control bandwidth, excellent light-load efficiency, and fast transient response, has become one of the mainstream control solutions for DC-DC converters in lithium battery-powered applications.

[0003] like Figure 1 The diagram shows the circuit structure of a non-reverse conventional four-switch BUCK-BOOST converter (CBB), including input voltage VIN, output voltage VOUT, switches S1~S4, inductor L, and load capacitor C. L Inductor current, current I flowing through switch S4 D and load current I LOAD In this circuit structure, the inductor current is greater than the load current I in boost mode. LOADThe CBB (Converterless Buck-Bulk) topology suffers from issues such as right-half-plane zeros and switching between boost, buck, and buck modes in both BOOST and BUCK-BOOST modes. To address these problems, scholars both domestically and internationally have conducted extensive research on topology optimization. Among these, the three-level BUCK-BOOST topology overcomes many of the problems of CBB by leveraging the three-level switching characteristics introduced by the flying capacitor. However, the three-level BUCK-BOOST topology still suffers from level switching issues, similar to CBB. Existing technologies include a hysteresis current control scheme that abandons the BUCK-BOOST mode and determines the operating mode based on the relationship between inductor current and the hysteresis window. However, its drawback is a large operating frequency variation and significant electromagnetic interference (EMI) problems. Another existing technology proposes a control scheme using an analog multiplier, employing a simplified multiplier and comparator to achieve dual-mode control. This scheme achieves smooth mode switching and fast transient response using a small area, but its control accuracy is highly dependent on multiplier matching and is only suitable for small load applications.

[0004] Therefore, this invention urgently needs to develop a method using V 2 A COT-controlled three-level buck-boost converter is used to overcome the above-mentioned technical defects. Summary of the Invention

[0005] The purpose of this invention is to provide a method using V 2 The COT-controlled three-level buck-boost converter of this invention can simplify the control loop design, achieve fast transient response and good stability, and at the same time take into account the smoothness of multi-mode switching and the voltage balance of the flying capacitor, while making full use of the advantages of the three-level topology.

[0006] To solve the above-mentioned technical problems, the present invention provides a method using V 2 The COT-controlled three-level buck-boost converter includes:

[0007] The power stage module is used to control the on and off of power switching transistors Q1 to Q5 according to the drive signals VQ1 to VQ5 output by the digital control module, thereby converting the input voltage VIN into a stable output voltage VOUT.

[0008] The analog control module is used to generate a first control signal Vc1 based on the difference between the output voltage VOUT and the reference voltage VREF, and then superimpose it with the slope signal Slope and compare it with the feedback output voltage VOUT to generate a second control signal Vc2 input to the digital control module.

[0009] The digital control module is used to determine whether the system operates in Buck mode, Boost mode or detection mode based on the second control signal Vc2 and the mode selection signal MODE generated by the finite state machine FSM, and to generate a constant on-time pulse Ton to control the on and off of power switches Q1~Q5.

[0010] Preferably, the power stage module includes: input voltage VIN, power switching transistors Q1~Q5, inductor L, and capacitor C. F Capacitor C L Resistance R CO and resistance R L The positive terminal of the input voltage VIN is connected to the source of power switches Q1 and Q5, and the negative terminal of the input voltage VIN is grounded; the drain of power switch Q1 is connected to the source of power switch Q2 and capacitor C. F One end of the power switch Q2; the drain of the power switch Q2 is connected to the drain of the power switch Q3 and one end of the inductor L; the source of the power switch Q3 is connected to the drain of the power switches Q4~Q5 and the capacitor C. F The other end; the source of the power switch Q4 is grounded; the gates of the power switches Q1~Q5 are respectively connected to drive signals VQ1~VQ5; the other end of the inductor L is connected to resistor R. CO One end and the grounded resistor R L And generate an output voltage VOUT; the resistor R CO The other end is connected to the grounded capacitor C L .

[0011] Preferably, the simulation control module includes:

[0012] Error amplifier A1 has a reference voltage VREF connected to its positive input terminal, an output voltage VOUT connected to its negative input terminal, and outputs the first control signal Vc1 at its output terminal.

[0013] The slope compensation module is used to generate the slope signal.

[0014] Comparator A2 has its positive input terminal connected to the output voltage VOUT, its negative input terminal connected to the superimposed first control signal Vc1 and the slope signal Slope, and its output terminal outputting the second control signal Vc2.

[0015] Preferably, the slope compensation module includes: a DC voltage Vdc, a transconductance amplifier A3, control switches SW1~SW3, and capacitors C1~C2; the positive terminal of the DC voltage Vdc is connected to the positive input terminal of the transconductance amplifier A3, and the negative terminal of the DC voltage Vdc is grounded; the negative input terminal of the transconductance amplifier A3 is grounded, and the output terminal of the transconductance amplifier A3 is connected to one end of the control switches SW1~SW3 and outputs the slope signal Slope; the other ends of the control switches SW1 and SW3 are sequentially connected to the grounded capacitor C1, the grounded terminal, and the grounded capacitor C2.

[0016] Preferably, it also includes an adder / subtractor, the control terminal of which is used to connect to the mode selection signal MODE to control the adder / subtractor to dynamically switch between addition and subtraction; the two input terminals of the adder / subtractor are respectively connected to the first control signal Vc1 and the ramp signal Slope, and the output terminal of the adder / subtractor outputs the sum of the first control signal Vc1 and the ramp signal Slope.

[0017] Preferably, the digital control module includes:

[0018] The working mode selection module is used to receive the second control signal Vc2 and the mode selection signal MODE output by the finite state machine FSM to determine whether the system works in Buck mode, Boost mode or detection mode, and output signals A and B.

[0019] The constant on-time module is used to generate a constant on-time pulse Ton based on the mode selection signal MODE output by the finite state machine (FSM) and the input voltage VIN, thereby controlling the on-time of power switches Q1~Q5.

[0020] A finite state machine (FSM) is used to generate drive signals VQ1~VQ5 based on the constant on-time pulse Ton generated by the constant on-time module and signals A and B generated by the operating mode selection module, thereby controlling the on and off of the power switches Q1~Q5.

[0021] Preferably, the working mode selection module includes: AND gates AND1 to AND2, inverters INV1 to INV2, an OR gate OR1, and a NOR gate NOR1; the second control signal Vc2 is connected to the first input ends of the AND gate AND1 and the OR gate OR1, and the mode selection signal MODE is connected to the second input ends of the AND gate AND1 and the OR gate OR1; the output end of the AND gate AND1 is connected to the input end of the inverter INV1 and the first input end of the AND gate AND2, the output end of the inverter INV1 is connected to the second input end of the AND gate AND2, and the output end of the AND gate AND2 outputs a signal B; the output end of the OR gate OR1 is connected to the input end of the inverter INV2 and the first input end of the NOR gate NOR1, the output end of the inverter INV2 is connected to the second input end of the NOR gate NOR1, and the output end of the NOR gate NOR1 outputs a signal A.

[0022] Preferably, when the second control signal Vc2 is at the rising edge, the signal A jumps to high level, otherwise the signal B jumps to high level, thereby determining that the system operates in the Buck mode, Boost mode, or detection mode.

[0023] Preferably, when the system is in the Boost mode, it is at the level Φ1 stage, the power switch Q5 and the power switch Q2 are turned on, and the inductor L is charged through the power switch Q5, the capacitor C F and the power switch Q2, and at this time, the voltage drop across the inductor L is 2VIN - VOUT;

[0024] When the system is in the detection mode, it is at the level Φ2 stage, the power switches Q1 to Q2 and the power switch Q4 are turned on. When VIN > VOUT, the inductor L is charged through the power switches Q1 to Q2; when VIN < VOUT, the inductor L discharges through the power switch Q2, the capacitor C F and the power switch Q4, and at this time, the voltage drop across the inductor L is VIN - VOUT;

[0025] When the system is in the Buck mode, it is at the level Φ3 stage, the power switch Q1 and the power switches Q3 to Q4 are turned on, and the inductor L discharges through the power switches Q3 to Q4, and at this time, the voltage drop across the inductor L is -VOUT.

[0026] Preferably, when the system is in the Boost mode, the control switch SW1 is turned on, and the transconductance amplifier A3 outputs a current to charge the capacitor C1 to generate a ramp signal Slope, which is used as the compensation of the system in the Boost mode;

[0027] When the system is in the detection mode, no ramp compensation is generated;

[0028] When the system is in Buck mode, the transconductance amplifier A3 outputs a current to charge capacitor C2, generating a slope signal Slope that is different from the slope when charging capacitor C1, as compensation for the system in Buck mode.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] This invention utilizes V²COT control to achieve a higher loop bandwidth than current-mode COT control, while the characteristics and state detection features of the three-level Buck-Boost converter (TLBB) enable dual-mode control of the system. Furthermore, compensation is designed to address the issue of subharmonic oscillations in the system when using low-ESR ceramic capacitors, achieving good loop stability in both boost and buck modes. Attached Figure Description

[0031] Figure 1 This is a circuit diagram of a common non-reverse conventional four-switch Buck-Boost converter (CBB) in existing technology.

[0032] Figure 2 This is an embodiment of the invention that uses V 2 Structure diagram of a COT-controlled three-level buck-boost converter.

[0033] Figure 3 This is an embodiment of the invention that uses V 2 The inductor current path diagrams of the COT-controlled three-level buck-boost converter under different operating modes are shown below; (a) is the inductor current path diagram of Φ1 stage; (b) is the inductor current path diagram of Φ2 stage; (c) is the inductor current path diagram of Φ3 stage; and (d) is the equivalent schematic diagram of Φ1~Φ3 stages.

[0034] Figure 4 This is a circuit diagram of the working mode selection module provided in an embodiment of the present invention.

[0035] Figure 5 This is a circuit diagram of the slope compensation module provided in an embodiment of the present invention.

[0036] Figure 6 This is a logic diagram showing the relationship between mode selection, output voltage VOUT, and first control signal Vc1 provided in an embodiment of the present invention; wherein (a) is a logic diagram of the second control signal Vc2 being a falling edge when A=1; and (b) is a logic diagram of the second control signal Vc2 being a rising edge when B=1. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] like Figure 2 As shown, an embodiment of the present invention provides a method using V 2 The COT-controlled three-level buck-boost converter specifically includes: a power stage module, an analog control module, and a digital control module;

[0039] The power stage module is used to control the on and off of five power switching transistors Q1~Q5 according to the output signal of the digital control module, and convert the input voltage VIN into a stable output voltage VOUT.

[0040] The analog control module generates a first control signal Vc1 based on the difference between the output voltage VOUT and the reference voltage VREF. This signal is then added to the ramp signal generated by the ramp compensation module and compared with the feedback signal (output voltage VOUT) in a comparator to generate a second control signal Vc2, which serves as the input to the digital control module.

[0041] The digital control module is used to determine whether the system operates in Buck mode, Boost mode or detection mode based on the second control signal Vc2 and the mode selection signal MODE generated by the finite state machine FSM, and generates a constant on-time to control the on and off of the five power switches Q1~Q5.

[0042] Specifically, the power stage module is used to convert the input voltage VIN into a stable output voltage VOUT based on the on and off states of the power switching transistors.

[0043] The analog control module is used to process the error between the feedback output voltage VOUT and the reference voltage VREF, output the second control signal Vc2, and input it into the digital control module.

[0044] The digital control module is used to generate five drive signals VQ1~VQ5 in the finite state machine FSM based on the second control signal Vc2 generated by the analog control module and signals A and B generated by the working mode selection module. These signals are used to control the on and off of the power switching transistors Q1~Q5.

[0045] Furthermore, such as Figure 2 As shown, the power stage module includes: input power supply VIN, power switching transistors Q1~Q5, inductor L, and capacitor C. F C L Resistance R CO R L ;

[0046] The negative terminal of the input power supply VIN is grounded, and the positive terminal is connected to the source of power switch Q1 and the source of power switch Q5.

[0047] The gate of power switch Q1 receives the gate drive signal VQ1, and the drain of power switch Q1 is connected to the source of power switch Q2 and capacitor C. F The upper electrode plate;

[0048] The gate of power switch Q2 receives the gate drive signal VQ2, and the drain of power switch Q2 is connected to the drain of power switch Q3 and the left end of the inductor.

[0049] The gate of power switch Q3 receives the gate drive signal VQ3, and the source of power switch Q3 is connected to the drain of power switch Q4 and capacitor C. F The lower electrode plate;

[0050] The gate of power switch Q4 receives the gate drive signal VQ4, and the source of power switch Q4 is grounded.

[0051] The gate of power switch Q5 receives the gate drive signal VQ5. The source of power switch Q5 is connected to the positive terminal of the input power supply VIN and the source of power switch Q1. The drain of power switch Q5 is connected to capacitor C. F The lower electrode plate, the source of power switch Q3, and the drain of power switch Q4;

[0052] Capacitor C F The upper plate is connected to the drain of power switch Q1 and the source of power switch Q2;

[0053] The left end of the inductor is connected to the drain of power switching transistors Q2 and Q3, and the right end of the inductor is connected to resistor R. CO and resistance R L One end;

[0054] resistor R CO One end is connected to the right end of the inductor, and the other end is connected to the capacitor C. L The upper electrode plate;

[0055] Capacitor C L The lower electrode plate is grounded;

[0056] resistor R L One end is connected to the negative input terminal of error amplifier A1 and the positive input terminal of comparator A2, and resistor R... L The other end is grounded.

[0057] Furthermore, based on the on and off states of power switching transistors Q1~Q5, the output voltage VOUT is generated;

[0058] Specifically, as Figure 3 shown, when the system is in Buck mode, that is, Figure 3 in the Φ3 stage in , power switch tubes Q1, Q3, and Q4 are turned on, and capacitor C F is charged through power switch tube Q1 until the voltage VIN, and inductor L discharges through power switch tubes Q3 and Q4. At this time, the voltage drop across inductor L is -VOUT, and it is in the discharging state; when the system is in the detection mode, that is, Figure 3 in the Φ2 stage in , power switch tubes Q1, Q2, and Q4 are turned on, and capacitor C F is charged through Q1 until the voltage VIN. When VIN > VOUT, inductor L is charged through power switch tubes Q1 and Q2. When VIN < VOUT, inductor L discharges through power switch tubes Q2, capacitor C F and power switch tube Q4. At this time, the voltage drop across inductor L is VIN - VOUT; when the system is in Boost mode, that is, Figure 3 in the Φ1 stage in , power switch tubes Q5 and Q2 are turned on. Since the voltage across capacitor C F cannot change suddenly, the voltage on its upper plate is 2VIN. Inductor L is charged through power switch tube Q5, capacitor C F and power switch tube Q2. At this time, the voltage drop across inductor L is 2VIN - VOUT.

[0059] Furthermore, as Figure 2 shown, the analog control module is used to process the error amount between the feedback output voltage VOUT and the reference voltage VREF, output the second control signal Vc2, and input it into the digital control module, including: an error amplifier A1, a comparator A2, and a ramp compensation module. <​​​​​​​​​​​​The positive terminal of the DC voltage Vdc is connected to the positive input terminal of the transconductance amplifier A3, and the negative terminal is connected to GND; the negative input terminal of the transconductance amplifier A3 is connected to GND, and the output terminal is connected to the upper terminals of control switches SW1, SW2, and SW3; the lower terminal of control switch SW1 is connected to the upper plate of capacitor C1; the lower terminal of control switch SW2 is connected to GND; the lower terminal of control switch SW3 is connected to the upper plate of capacitor C2; the lower plate of capacitor C1 is connected to GND; the lower plate of capacitor C2 is connected to GND.

[0064] Specifically, when the buck-boost converter is operating in the Φ1 stage (Boost stage), the slope compensation module turns on switch SW1, and the transconductance amplifier A3 outputs a current to charge capacitor C1, generating a slope that is used as compensation for the buck-boost converter operating in the Boost stage. When the buck-boost converter is operating in the Φ2 stage (Detection stage), no slope compensation is generated. When the buck-boost converter is operating in the Φ3 stage (Buck stage), the transconductance amplifier A3 outputs a current to charge capacitor C2, generating a slope different from that when charging capacitor C1, which is used as compensation for the buck-boost converter operating in the Buck stage.

[0065] Specifically, the output of error amplifier A1 generates the error between the output voltage VOUT and the reference voltage VREF, i.e., the first control signal Vc1. This error signal Vc1 enters comparator A2, is added to the ramp signal, and then compared with the output voltage VOUT to generate the second control signal Vc2. This determines the on / off state and duty cycle of the power switches Q1~Q5. The larger the error, the larger the duty cycle is usually.

[0066] Furthermore, such as Figure 2 As shown, the digital control module includes: a working mode selection module, a constant on-time module, and a finite state machine (FSM);

[0067] The working mode selection module receives the second control signal Vc2 from the analog control module. If Vc2 is a rising edge, signal A jumps to high, otherwise signal B jumps to high, thus determining whether the buck-boost converter works in Buck mode, Boost mode or detection mode.

[0068] The constant on-time module is used to generate a constant on-time pulse Ton based on the mode signal MODE output by the finite state machine (FSM) and the input voltage VIN, so as to control the on-time of power switches Q1~Q5.

[0069] The finite state machine (FSM) is used to generate five drive signals VQ1~VQ5 based on the constant on-time pulse Ton generated by the constant on-time module and the signals A and B output by the operating mode selection module. This controls the on and off of the five power switches Q1~Q5, directly determining whether the buck-boost converter operates in Buck mode, Boost mode, or detection mode.

[0070] Furthermore, such as Figure 4 As shown, the working mode selection module includes: AND gates AND1 and AND2, inverters INV1 and INV2, OR gate OR1 and NOR gate NOR1;

[0071] One end of the AND gate AND1 is connected to the second control signal Vc2, and the other end is connected to the mode selection signal MODE.

[0072] The input of inverter INV1 is connected to the output of AND gate AND1, and the output of inverter INV1 is connected to one input of AND gate AND2.

[0073] The other input of AND gate AND2 is connected to the output of AND gate AND1, and the output of AND gate AND2 outputs signal B.

[0074] One end of the OR gate OR1 is connected to the mode selection signal MODE, and the other end is connected to the second control signal Vc2.

[0075] The input of inverter INV2 is connected to the output of OR gate OR1, and the output of inverter INV2 is connected to one input of NOR gate NOR1.

[0076] The other input of NOR1 is connected to the output of OR1, and the output of NOR1 outputs signal A.

[0077] Specifically, such as Figure 6As shown, the specific operating mode is as follows: if signal A=1, then the second control signal Vc2 is a falling edge; if signal B=1, then the second control signal Vc2 is a rising edge. The MODE signal is used to select and detect rising / falling edges. If MODE=1, signal A is always 0, and the operating mode selection module can only detect the rising edge of the second control signal Vc2; if MODE=0, signal B is always 0, and the operating mode selection module can only detect the falling edge of the second control signal Vc2. Φ2, used for state detection, employs constant-time control. After this time, the mode selection module connected to the output of comparator A2 will sample the second control signal Vc2. If it is high, the system needs to enter Buck mode; if it is low, the system needs to enter Boost mode. After the phase switch, the mode selection module will detect the edge transition of the second control signal Vc2 and wait for the corresponding rising / falling edge signal based on the different modes the system entered in the previous cycle: if the system entered BUCK mode in the previous cycle, then MODE=0, and wait for the falling edge of the second control signal Vc2. Once the edge signal arrives, the system will re-enter Φ2; if the system entered Boost mode in the previous cycle, then MODE=1, and wait for the rising edge of the second control signal Vc2. Once the edge signal arrives, the system will re-enter Φ2.

[0078] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method using V 2 A COT-controlled three-level buck-boost converter, characterized in that... include: The power stage module is used to control the on and off of power switching transistors Q1 to Q5 according to the drive signals VQ1 to VQ5 output by the digital control module, thereby converting the input voltage VIN into a stable output voltage VOUT. The analog control module is used to generate a first control signal Vc1 based on the difference between the output voltage VOUT and the reference voltage VREF, and then superimpose it with the slope signal Slope and compare it with the feedback output voltage VOUT to generate a second control signal Vc2 input to the digital control module. The digital control module is used to determine whether the system operates in Buck mode, Boost mode or detection mode based on the second control signal Vc2 and the mode selection signal MODE generated by the finite state machine FSM, and to generate a constant on-time pulse Ton to control the on and off of power switching transistors Q1~Q5. The power stage module includes: input voltage VIN, power switching transistors Q1~Q5, inductor L, and capacitor C. F Capacitor C L Resistance R CO and resistance R L The positive terminal of the input voltage VIN is connected to the source of power switches Q1 and Q5, and the negative terminal of the input voltage VIN is grounded; the drain of power switch Q1 is connected to the source of power switch Q2 and capacitor C. F One end of the power switch Q2; the drain of the power switch Q2 is connected to the drain of the power switch Q3 and one end of the inductor L; the source of the power switch Q3 is connected to the drain of the power switches Q4~Q5 and the capacitor C. F The other end; the source of the power switch Q4 is grounded; the gates of the power switches Q1~Q5 are respectively connected to drive signals VQ1~VQ5; the other end of the inductor L is connected to resistor R. CO One end and the grounded resistor R L And generate an output voltage VOUT; the resistor R CO The other end is connected to the grounded capacitor C L ; The digital control module includes: The working mode selection module is used to receive the second control signal Vc2 and the mode selection signal MODE output by the finite state machine FSM to determine whether the system works in Buck mode, Boost mode or detection mode, and output signals A and B. The working mode selection module includes: AND gates AND1~AND2, inverters INV1~INV2, OR gate OR1, and NOR gate NOR1; the second control signal Vc2 is connected to the first input terminal of AND gate AND1 and OR gate OR1, and the mode selection signal MODE is connected to the second input terminal of AND gate AND1 and OR gate OR1; the output terminal of AND gate AND1 is connected to the input terminal of inverter INV1 and the first input terminal of AND gate AND2, the output terminal of inverter INV1 is connected to the second input terminal of AND gate AND2, and the output terminal of AND gate AND2 outputs signal B; the output terminal of OR gate OR1 is connected to the input terminal of inverter INV2 and the first input terminal of NOR gate NOR1, the output terminal of inverter INV2 is connected to the second input terminal of NOR gate NOR1, and the output terminal of NOR gate NOR1 outputs signal A; When the second control signal Vc2 is a rising edge, signal A jumps high, and vice versa, signal B jumps high, thereby determining whether the system works in Buck mode, Boost mode or detection mode. If signal A=1, then the second control signal Vc2 is a falling edge; if signal B=1, then the second control signal Vc2 is a rising edge. If MODE=1, then signal A is always 0, and the working mode selection module can only detect the rising edge of the second control signal Vc2; if MODE=0, then signal B is always 0, and the working mode selection module can only detect the falling edge of the second control signal Vc2. After the system enters the detection mode, if the second control signal Vc2 is high, it enters the Buck mode; if the second control signal Vc2 is low, it enters the Boost mode. If the system entered Buck mode in the previous cycle, then set MODE=0 and wait for the falling edge of the second control signal Vc2; once the falling edge is detected, the system enters detection mode again. If the system entered Boost mode in the previous cycle, then MODE=1 is set, and the system waits for the rising edge of the second control signal Vc2; once the rising edge is detected, the system re-enters detection mode.

2. A method using V as described in claim 1 2 A COT-controlled three-level buck-boost converter, characterized in that... The simulation control module includes: Error amplifier A1 has a reference voltage VREF connected to its positive input terminal, an output voltage VOUT connected to its negative input terminal, and outputs the first control signal Vc1 at its output terminal. The slope compensation module is used to generate the slope signal. Comparator A2 has its positive input terminal connected to the output voltage VOUT, its negative input terminal connected to the superimposed first control signal Vc1 and the slope signal Slope, and its output terminal outputting the second control signal Vc2.

3. A method using V as described in claim 2 2 A COT-controlled three-level buck-boost converter, characterized in that... The slope compensation module includes: a DC voltage Vdc, a transconductance amplifier A3, control switches SW1~SW3, and capacitors C1~C2; the positive terminal of the DC voltage Vdc is connected to the positive input terminal of the transconductance amplifier A3, and the negative terminal of the DC voltage Vdc is grounded; the negative input terminal of the transconductance amplifier A3 is grounded, and the output terminal of the transconductance amplifier A3 is connected to one end of the control switches SW1~SW3 and outputs the slope signal Slope; the other ends of the control switches SW1 and SW3 are connected in sequence to the grounded capacitor C1, the grounded terminal, and the grounded capacitor C2.

4. A method using V as described in claim 2 2 A COT-controlled three-level buck-boost converter, characterized in that... It also includes an adder / subtractor, the control terminal of which is used to connect to the mode selection signal MODE to control the adder / subtractor to dynamically switch between addition and subtraction; the two input terminals of the adder / subtractor are respectively connected to the first control signal Vc1 and the ramp signal Slope, and the output terminal of the adder / subtractor outputs the sum of the first control signal Vc1 and the ramp signal Slope.

5. A method using V as described in claim 1 2 A COT-controlled three-level buck-boost converter, characterized in that... The digital control module also includes: The constant on-time module is used to generate a constant on-time pulse Ton based on the mode selection signal MODE output by the finite state machine (FSM) and the input voltage VIN, thereby controlling the on-time of power switches Q1~Q5. A finite state machine (FSM) is used to generate drive signals VQ1~VQ5 based on the constant on-time pulse Ton generated by the constant on-time module and signals A and B generated by the operating mode selection module, thereby controlling the on and off of the power switches Q1~Q5.

6. A method using V as described in claim 1 2 A COT-controlled three-level buck-boost converter, characterized in that... When the system is in Boost mode, it is at level Φ1. Power switches Q5 and Q2 are turned on, and inductor L flows through power switch Q5 and capacitor C. F When the power switch Q2 is charged, the voltage drop across the inductor L is 2VIN-VOUT. When the system is in the detection mode, it is at the level Φ2 stage. The power switching transistors Q1 - Q2 and the power switching transistor Q4 are turned on. When VIN > VOUT, the inductor L is charged through the power switching transistors Q1 - Q2. When VIN < VOUT, the inductor L discharges through the power switching transistor Q2, the capacitor C F and the power switching transistor Q4. At this time, the voltage drop across the inductor L is VIN - VOUT; When the system is in Buck mode, it is at level Φ3. Power switches Q1 and Q3~Q4 are turned on, and inductor L discharges through power switches Q3~Q4. At this time, the voltage drop across inductor L is -VOUT.

7. A method using V as described in claim 3 2 A COT-controlled three-level buck-boost converter, characterized in that... When the system is in Boost mode, the control switch SW1 is turned on, and the transconductance amplifier A3 outputs a current to charge the capacitor C1 to generate a slope signal as compensation for the system in Boost mode. When the system is in detection mode, no slope compensation is generated; When the system is in Buck mode, the transconductance amplifier A3 outputs a current to charge capacitor C2, generating a slope signal Slope that is different from the slope when charging capacitor C1, as compensation for the system in Buck mode.

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