Radio frequency broadband high-power frequency doubler

Abstract

The invention discloses a radio frequency broadband high-power frequency doubler, which comprises an input phase shift power division network, a driving frequency multiplication amplification network, a final-stage frequency multiplication amplification network and an output matching power supply network, and is characterized in that the driving frequency multiplication amplification network and the final-stage frequency multiplication amplification network are adopted as a core architecture to realize high power and high gain in a microwave frequency band; and meanwhile, the self-adaptive linearization feedback network is used for adjusting the linearity component of the stacked transistors at the bottom layer of the self-bias negative feedback amplification network, so that the whole radio frequency broadband high-power frequency doubler obtains good high gain, high linearity and high power output capability.

Description

Technical Field

[0001] This invention relates to the fields of radio frequency microwave frequency multipliers and integrated circuits, and in particular to a radio frequency broadband high-power frequency doubler designed to improve output power and simplify circuit design. Background Technology

[0002] With the rapid development of wireless communication systems and RF microwave circuits, RF front-end transceivers are also evolving towards high performance, high integration, and low power consumption. Therefore, the market urgently needs RF broadband high-power frequency doublers for transmitters with high output power, high gain, high efficiency, and low cost. Integrated circuits are a key technology that is expected to meet this market demand. Meanwhile, in 5G-A communication systems, RF broadband high-power frequency doublers have evolved from traditional frequency conversion units into strategic components that enhance system performance, efficiency, and flexibility. By efficiently expanding frequency coverage, enabling linearization technology, and simplifying system architecture, they directly support the core requirements of 5G-A in millimeter wave, large bandwidth, and high power. With advancements in semiconductor processes and circuit design technologies, their performance will continue to improve, and their application scope will extend from infrastructure to high-end terminal equipment, laying a solid hardware foundation for the evolution of future mobile communication networks.

[0003] However, when using integrated circuit technology to design and implement RF broadband high-power frequency doubler circuits, their performance and cost are subject to certain limitations, mainly in the following aspects: (1) Limited high power and high efficiency capabilities: Traditional frequency multipliers have small voltage swing and low single-tube output power. They often need to adopt a multi-channel parallel structure or a distributed structure. The synthesis efficiency of these two structures is limited, resulting in some power loss in the synthesis network, which limits the high power and high efficiency capabilities.

[0004] (2) Limitations on linearity: The bias circuit of a typical frequency multiplier network is often designed in a relatively simple way, which cannot meet the improvement of linearity. It often requires additional linearization circuits, which brings complexity to the system application.

[0005] There are many common circuit structures for high-gain, high-power frequency multipliers, the most typical being multi-stage, multi-channel synthesized single-ended frequency multipliers. However, it is very difficult for traditional multi-stage, multi-channel synthesized single-ended frequency multipliers to meet the requirements of various parameters at the same time. This is mainly because the output impedance of traditional multi-stage, multi-channel synthesized single-ended frequency multipliers is low when multiple channels are combined in parallel. Therefore, the output synthesis network needs to achieve impedance matching with a high impedance transformation ratio, which often requires sacrificing the gain of the frequency multiplier and reducing the power, thus limiting the high power and high efficiency capabilities.

[0006] In addition, typical traditional stacked field-effect transistors often have a linearized bias network added to the bottom bias network. This setting has limited improvement on the linearity of the stacked field-effect transistor, ignoring the linearity limitations imposed by the bias circuit of the stacked field-effect transistor above.

[0007] This shows that the design challenges of high-gain, high-power frequency multipliers based on integrated circuit technology are high power and high efficiency, while traditional stacked field-effect transistors have limitations in linearity bias network design. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a high-power frequency doubler with wideband radio frequency, which combines the advantages of field-effect transistor stacking technology and adaptive linearization technology, and has the advantages of high power, high gain and low cost in microwave band.

[0009] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: a radio frequency broadband high-power frequency doubler, characterized in that it includes an input phase-shifting power divider network, a driving frequency doubler amplification network, a final-stage frequency doubler amplification network, and an output matching power supply network; The input terminal RF of the phase-shifting power divider network in The first and second outputs of the entire RF broadband high-power frequency doubler are connected to the first and second inputs of the driving frequency multiplier network, respectively. The first and second outputs of the driving frequency multiplier amplifier network are connected to the first and second inputs of the final stage frequency multiplier amplifier network; The output of the final stage frequency multiplier amplifier network is connected to the input of the output matching power supply network; The output of the matching power supply network is the output of the entire RF broadband high-power frequency doubler.

[0010] The beneficial effects of the technical solution of the present invention are: the self-biased negative feedback amplification network has high power and high gain characteristics, and the adaptive linearization feedback network is used to adjust the linearity component of the bottom stacked transistors in the self-biased negative feedback amplification network for large signal power amplification, so that the entire frequency doubler obtains good high gain, high linearity and high power output capability.

[0011] Furthermore, the input terminal RF of the phase-shifting power divider network in This is the input terminal of the entire RF broadband high-power frequency doubler, and the input terminal of the phase-shifting power divider network. inConnect microstrip line TL1. Connect one end of microstrip line TL1 to microstrip line TL2. Connect the other end of microstrip line TL2 to grounding resistor R1. Microstrip line TL1 and microstrip line TL3 are coupled together. Connect one end of microstrip line TL3 to grounding resistor R3. Connect the other end of microstrip line TL3 to capacitor C1. Connect the other end of capacitor C1 to inductor L1. Connect the other end of inductor L1 to the first output terminal of the input phase-shifting power divider network. Connect microstrip line TL2 and microstrip line TL4. Connect one end of microstrip line TL4 to grounding resistor R2. Connect the other end of microstrip line TL4 to capacitor C2. Connect the other end of capacitor C2 to inductor L2. Connect the other end of inductor L2 to the second output terminal of the input phase-shifting power divider network.

[0012] The beneficial effects of the above-mentioned further solutions are: in addition to achieving impedance matching, the input phase-shifting power divider network used in this invention can also improve the low-frequency stability of the circuit.

[0013] Furthermore, the first output terminal of the input phase-shifting power divider network is connected to the first input terminal of the driving frequency multiplier amplifier network. The first input terminal of the driving frequency multiplier amplifier network is connected to microstrip line TL5. The other end of microstrip line TL5 is connected to ground capacitor C3, resistor R4, and microstrip line TL7. The other end of resistor R4 is connected to resistor R6, and the other end of resistor R6 is connected to bias voltage V. g1 The microstrip line TL7 is connected to the gate of field-effect transistor M1, with its source grounded. The drain of M1 is connected to microstrip line TL9, and the other end of TL9 is connected to the source of field-effect transistor M3. The gate of M3 is connected to grounded capacitor C5 and resistor R7. The other end of resistor R7 is connected to grounded resistor R8 and resistor R9. The other end of resistor R9 is connected to the first output terminal of the driving frequency multiplier network. The drain of M3 is connected to inductor L3, grounded capacitor C8, and the first output terminal of the driving frequency multiplier network. The second output terminal of the input phase-shifting power divider network is connected to the second input terminal of the driving frequency multiplier network. The second input terminal of the driving frequency multiplier network is connected to microstrip line TL6. The other end of microstrip line TL6 is connected to grounded capacitor C4, resistor R5, and microstrip line TL8. The other end of resistor R5 is connected to resistor R6, and the other end of resistor R6 is connected to the bias voltage V. g1 The other end of the microstrip line TL8 is connected to the gate of the field-effect transistor M2, the source of the field-effect transistor M2 is grounded, and the drain of the field-effect transistor M2 is connected to the microstrip line TL8. 10 microstrip line TL 10 The other end is connected to the source of the field-effect transistor M4, and the gate of the field-effect transistor M4 is connected to ground, capacitor C6, and resistor R. 10 resistance R 10 The other end is connected to the grounding resistor R 12 and resistance R11 resistance R 11 The other end is connected to the second output terminal of the driving frequency multiplier amplifier network. The drain of the field effect transistor M4 is connected to the inductor L3, the ground capacitor C9 and the second output terminal of the driving frequency multiplier amplifier network.

[0014] The beneficial effects of the above-mentioned further solutions are: the adaptive linearization feedback network of the present invention can adjust the linearity component of each stacked transistor in the self-biased negative feedback amplification network when performing large signal power amplification, so that the entire frequency doubler obtains good high gain, high linearity and high power output capability.

[0015] Furthermore, the first output terminal of the driving frequency multiplier network is connected to the first input terminal of the final stage frequency multiplier network, the first input terminal of the final stage frequency multiplier network is connected to inductor L4, and the other end of inductor L4 is connected to resistor R. 13 and capacitor C 12 resistance R 13 The other end is connected to the grounding capacitor C 10 and microstrip lines TL 11 Capacitor C 12 The other end is connected to resistor R 15 and microstrip lines TL 11 resistance R 15 The other end is connected to resistor R 17 resistance R 17 The other end is connected to the bias voltage V g2 and grounding capacitor C 14 microstrip line TL 11 The other end is connected to the gate of field-effect transistor M5, the source of field-effect transistor M5 is grounded, and the drain of field-effect transistor M5 is connected to microstrip line TL. 13 microstrip line TL 13 The other end is connected to the source of the field-effect transistor M7, and the gate of the field-effect transistor M7 is connected to the ground capacitor C. 15 and resistance R 19 resistance R 19 The other end is connected to the grounding resistor R 18 and resistance R 22 resistance R 22 The other end of the circuit and the drain of the field-effect transistor M7 are connected to the output of the final stage frequency multiplier network; the second output of the driving frequency multiplier network is connected to the second input of the final stage frequency multiplier network, the second input of the final stage frequency multiplier network is connected to inductor L5, and the other end of inductor L5 is connected to resistor R. 14 and capacitor C 13 resistance R 14 The other end is connected to the grounding capacitor C 11 and microstrip lines TL 12 Capacitor C13 The other end is connected to resistor R 16 and microstrip lines TL 12 resistance R 16 The other end is connected to resistor R 17 resistance R 17 The other end is connected to the bias voltage V g2 and grounding capacitor C 14 microstrip line TL 12 The other end is connected to the gate of the field-effect transistor M6, the source of the field-effect transistor M6 is grounded, and the drain of the field-effect transistor M6 is connected to the microstrip line TL. 14 microstrip line TL 14 The other end is connected to the source of the field-effect transistor M8, and the gate of the field-effect transistor M8 is connected to the ground capacitor C. 16 and resistance R 21 resistance R 21 The other end is connected to the grounding resistor R 20 and resistance R 23 resistance R 23 The other end and the drain of the field-effect transistor M8 are connected to the output of the final stage frequency multiplier amplifier network.

[0016] The beneficial effects of the above-mentioned further solutions are: the self-biased negative feedback amplification network used in this invention can increase the voltage swing of the frequency doubler, improve the power output capability and output impedance, and improve output matching. At the same time, the self-biased structure of the frequency doubler simplifies the power supply bias network.

[0017] Furthermore, the output of the final stage frequency multiplier network is connected to the input of the output matching power supply network, the input of the output matching power supply network is connected to inductor L6, the other end of inductor L6 is connected to inductors L7 and L8, and the other end of inductor L7 is connected to the bias voltage V. dd Grounding capacitor C 18 and capacitor C 17 Capacitor C 17 The other end is connected to the grounding resistor R 24 The other end of inductor L8 is connected to ground capacitor C. 20 and C 19 C 19 The other end is connected to the output of the entire RF broadband high-power frequency doubler. out .

[0018] The beneficial effects of the above-mentioned further solutions are: the high-efficiency output matching network based on parasitic parameter compensation used in this invention can compensate for the equivalent output drain-source parasitic capacitance of the stacked frequency doubler structure, realize waveform shaping of the output signal, thereby improving the efficiency of the frequency doubler and reducing the insertion loss of the matching network, while also having the function of DC blocking of radio frequency signals. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating the principle of the radio frequency broadband high-power frequency doubler of the present invention. Figure 2 This is a circuit diagram of the radio frequency broadband high-power frequency doubler of the present invention. Detailed Implementation

[0020] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, and are not intended to limit the scope of the invention.

[0021] This invention provides a radio frequency broadband high-power frequency doubler, including an input phase-shifting power divider network, a driving frequency doubler amplifier network, a final-stage frequency doubler amplifier network, and an output matching power supply network.

[0022] like Figure 1 As shown, the input terminal RF of the phase-shifting power divider network in The first and second outputs of the entire RF broadband high-power frequency doubler are connected to the first and second inputs of the driving frequency multiplier network, respectively. The first and second outputs of the driving frequency multiplier amplifier network are connected to the first and second inputs of the final stage frequency multiplier amplifier network; The output of the final stage frequency multiplier amplifier network is connected to the input of the output matching power supply network; The output of the matching power supply network is the output of the entire RF broadband high-power frequency doubler.

[0023] like Figure 2 As shown, the input terminal RF of the phase-shifting power divider network in This is the input terminal of the entire RF broadband high-power frequency doubler, and the input terminal of the phase-shifting power divider network. in Connect microstrip line TL1. Connect one end of microstrip line TL1 to microstrip line TL2. Connect the other end of microstrip line TL2 to grounding resistor R1. Microstrip line TL1 and microstrip line TL3 are coupled together. Connect one end of microstrip line TL3 to grounding resistor R3. Connect the other end of microstrip line TL3 to capacitor C1. Connect the other end of capacitor C1 to inductor L1. Connect the other end of inductor L1 to the first output terminal of the input phase-shifting power divider network. Connect microstrip line TL2 and microstrip line TL4. Connect one end of microstrip line TL4 to grounding resistor R2. Connect the other end of microstrip line TL4 to capacitor C2. Connect the other end of capacitor C2 to inductor L2. Connect the other end of inductor L2 to the second output terminal of the input phase-shifting power divider network.

[0024] The first output terminal of the input phase-shifting power divider network is connected to the first input terminal of the driving frequency multiplier amplifier network. The first input terminal of the driving frequency multiplier amplifier network is connected to microstrip line TL5. The other end of microstrip line TL5 is connected to ground capacitor C3, resistor R4, and microstrip line TL7. The other end of resistor R4 is connected to resistor R6, and the other end of resistor R6 is connected to the bias voltage V. g1 The microstrip line TL7 is connected to the gate of field-effect transistor M1, with its source grounded. The drain of M1 is connected to microstrip line TL9, and the other end of TL9 is connected to the source of field-effect transistor M3. The gate of M3 is connected to grounded capacitor C5 and resistor R7. The other end of resistor R7 is connected to grounded resistor R8 and resistor R9. The other end of resistor R9 is connected to the first output terminal of the driving frequency multiplier network. The drain of M3 is connected to inductor L3, grounded capacitor C8, and the first output terminal of the driving frequency multiplier network. The second output terminal of the input phase-shifting power divider network is connected to the second input terminal of the driving frequency multiplier network. The second input terminal of the driving frequency multiplier network is connected to microstrip line TL6. The other end of microstrip line TL6 is connected to grounded capacitor C4, resistor R5, and microstrip line TL8. The other end of resistor R5 is connected to resistor R6, and the other end of resistor R6 is connected to the bias voltage V. g1 The other end of the microstrip line TL8 is connected to the gate of the field-effect transistor M2, the source of the field-effect transistor M2 is grounded, and the drain of the field-effect transistor M2 is connected to the microstrip line TL8. 10 microstrip line TL 10 The other end is connected to the source of the field-effect transistor M4, and the gate of the field-effect transistor M4 is connected to ground, capacitor C6, and resistor R. 10 resistance R 10 The other end is connected to the grounding resistor R 12 and resistance R 11 resistance R 11 The other end is connected to the second output terminal of the driving frequency multiplier amplifier network. The drain of the field effect transistor M4 is connected to the inductor L3, the ground capacitor C9 and the second output terminal of the driving frequency multiplier amplifier network.

[0025] The first output of the driving frequency multiplier network is connected to the first input of the final stage frequency multiplier network. The first input of the final stage frequency multiplier network is connected to inductor L4, and the other end of inductor L4 is connected to resistor R. 13 and capacitor C 12 resistance R 13 The other end is connected to the grounding capacitor C 10 and microstrip lines TL 11 Capacitor C 12 The other end is connected to resistor R 15 and microstrip lines TL 11 resistance R 15The other end is connected to resistor R 17 resistance R 17 The other end is connected to the bias voltage V g2 and grounding capacitor C 14 microstrip line TL 11 The other end is connected to the gate of field-effect transistor M5, the source of field-effect transistor M5 is grounded, and the drain of field-effect transistor M5 is connected to microstrip line TL. 13 microstrip line TL 13 The other end is connected to the source of the field-effect transistor M7, and the gate of the field-effect transistor M7 is connected to the ground capacitor C. 15 and resistance R 19 resistance R 19 The other end is connected to the grounding resistor R 18 and resistance R 22 resistance R 22 The other end of the circuit and the drain of the field-effect transistor M7 are connected to the output of the final stage frequency multiplier network; the second output of the driving frequency multiplier network is connected to the second input of the final stage frequency multiplier network, the second input of the final stage frequency multiplier network is connected to inductor L5, and the other end of inductor L5 is connected to resistor R. 14 and capacitor C 13 resistance R 14 The other end is connected to the grounding capacitor C 11 and microstrip lines TL 12 Capacitor C 13 The other end is connected to resistor R 16 and microstrip lines TL 12 resistance R 16 The other end is connected to resistor R 17 resistance R 17 The other end is connected to the bias voltage V g2 and grounding capacitor C 14 microstrip line TL 12 The other end is connected to the gate of the field-effect transistor M6, the source of the field-effect transistor M6 is grounded, and the drain of the field-effect transistor M6 is connected to the microstrip line TL. 14 microstrip line TL 14 The other end is connected to the source of the field-effect transistor M8, and the gate of the field-effect transistor M8 is connected to the ground capacitor C. 16 and resistance R 21 resistance R 21 The other end is connected to the grounding resistor R 20 and resistance R 23 resistance R 23 The other end and the drain of the field-effect transistor M8 are connected to the output of the final stage frequency multiplier amplifier network.

[0026] The output of the final stage frequency multiplier network is connected to the input of the output matching power supply network. The input of the output matching power supply network is connected to inductor L6. The other end of inductor L6 is connected to inductors L7 and L8. The other end of inductor L7 is connected to the bias voltage V. dd Grounding capacitor C 18 and capacitor C 17 Capacitor C 17 The other end is connected to the grounding resistor R 24 The other end of inductor L8 is connected to ground capacitor C. 20 and C 19 C 19 The other end is connected to the output of the entire RF broadband high-power frequency doubler. out .

[0027] The following is combined Figure 2 The specific working principle and process of this invention are described below: RF input signal through input terminal RF in The input signal enters the circuit, and after phase correction by the phase-shifting power divider network, it is output from the first and second output terminals of the input phase-shifting power divider network, respectively. These outputs then enter the first and second input terminals of the driving frequency multiplier network, where the frequency is amplified. The outputs from the first and second output terminals of the driving frequency multiplier network, respectively, then enter the first and second input terminals of the final stage frequency multiplier network, where the frequency is amplified again. Finally, the output signal is output from the final stage frequency multiplier network, and after matching by the output matching power supply network, it exits from the RF output terminal. out Output. Simultaneously, the first and second input terminals of the adaptive linearization feedback network receive the drain voltage signals from transistors M1 and M2 in the biased negative feedback amplifier network, and form feedback linearization voltage signals. These signals are then transmitted to the gates of M1 and M2 in the biased negative feedback amplifier network through the first and second output terminals of the adaptive linearization feedback network, thereby adjusting the linearization index of the frequency multiplier and providing a suitable linearization operating state for the circuit.

[0028] Based on the above circuit analysis, the RF broadband high-power frequency doubler proposed in this invention differs from previous frequency doubler structures based on integrated circuit technology in that its core architecture employs a two-stage frequency multiplication amplification network. The self-biased negative feedback amplification network differs from traditional Cascode transistors in that the stacked gate compensation capacitor of the common-source transistor in a traditional Cascode transistor has a large capacitance value, used to achieve AC grounding of the gate, while the stacked gate compensation capacitor of the three stacked field-effect transistors in the self-biased negative feedback amplification network has a very small capacitance value, used to achieve AC synchronous oscillation of the gate, without AC grounding.

[0029] In the entire RF broadband high-power frequency doubler, the size of the transistors and the values ​​of other resistors and capacitors are determined after comprehensively considering various indicators such as the gain, bandwidth and output power of the entire circuit. Through subsequent layout design and reasonable arrangement, the required indicators can be better achieved, realizing high power output capability, high power gain and good input-output matching characteristics.

[0030] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A radio frequency broadband high-power frequency doubler, characterized in that, This includes an input phase-shifting power divider network, a driving frequency multiplier network, a final-stage frequency multiplier network, and an output matching power supply network. The input terminal RF of the input phase-shifting power divider network in The first and second output terminals are respectively connected to the first and second input terminals of the driving frequency multiplier network; The first and second output terminals of the driving frequency multiplier amplifier network are connected to the first and second input terminals of the final stage frequency multiplier amplifier network; The output of the final stage frequency multiplier network is connected to the input of the output matching power supply network; The output terminal of the output matching power supply network is the output terminal of the entire radio frequency broadband high-power frequency doubler.

2. The radio frequency broadband high-power frequency doubler according to claim 1, characterized in that, The input terminal RF of the input phase-shifting power divider network in This is the input terminal of the entire RF broadband high-power frequency doubler, and the input terminal of the phase-shifting power divider network. in Connect microstrip line TL1. Connect one end of microstrip line TL1 to microstrip line TL2. Connect the other end of microstrip line TL2 to grounding resistor R1. Microstrip line TL1 and microstrip line TL3 are coupled together. Connect one end of microstrip line TL3 to grounding resistor R3. Connect the other end of microstrip line TL3 to capacitor C1. Connect the other end of capacitor C1 to inductor L1. Connect the other end of inductor L1 to the first output terminal of the input phase-shifting power divider network. Connect microstrip line TL2 and microstrip line TL4. Connect one end of microstrip line TL4 to grounding resistor R2. Connect the other end of microstrip line TL4 to capacitor C2. Connect the other end of capacitor C2 to inductor L2. Connect the other end of inductor L2 to the second output terminal of the input phase-shifting power divider network.

3. The radio frequency broadband high-power frequency doubler according to claim 1, characterized in that, The first input terminal of the driving frequency multiplier amplification network is connected to microstrip line TL5. The other end of microstrip line TL5 is connected to ground capacitor C3, resistor R4 and microstrip line TL7. The other end of resistor R4 is connected to resistor R6. The other end of resistor R6 is connected to bias voltage V. g1 The microstrip line TL7 is connected to the gate of the field-effect transistor M1, with its source grounded. The drain of M1 is connected to the microstrip line TL9, and the other end of TL9 is connected to the source of the field-effect transistor M3. The gate of M3 is connected to the grounding capacitor C5 and resistor R7. The other end of resistor R7 is connected to the grounding resistor R8 and resistor R9. The other end of resistor R9 is connected to the first output terminal of the driving frequency multiplier network. The drain of M3 is connected to the inductor L3, the grounding capacitor C8, and the first output terminal of the driving frequency multiplier network. The second input terminal of the driving frequency multiplier network is connected to the microstrip line TL6. The other end of TL6 is connected to the grounding capacitor C4, resistor R5, and microstrip line TL8. The other end of resistor R5 is connected to resistor R6, and the other end of resistor R6 is connected to the bias voltage V. g1 The other end of the microstrip line TL8 is connected to the gate of the field-effect transistor M2, the source of the field-effect transistor M2 is grounded, and the drain of the field-effect transistor M2 is connected to the microstrip line TL8. 10 microstrip line TL 10 The other end is connected to the source of the field-effect transistor M4, and the gate of the field-effect transistor M4 is connected to ground, capacitor C6, and resistor R. 10 resistance R 10 The other end is connected to the grounding resistor R 12 and resistance R 11 resistance R 11 The other end is connected to the second output terminal of the driving frequency multiplier amplifier network. The drain of the field effect transistor M4 is connected to the inductor L3, the ground capacitor C9 and the second output terminal of the driving frequency multiplier amplifier network.

4. The radio frequency broadband high-power frequency doubler according to claim 1, characterized in that, The first input terminal of the final-stage frequency multiplier amplifier network is connected to inductor L4, and the other end of inductor L4 is connected to resistor R. 13 and capacitor C 12 resistance R 13 The other end is connected to the grounding capacitor C 10 and microstrip lines TL 11 Capacitor C 12 The other end is connected to resistor R 15 and microstrip lines TL 11 resistance R 15 The other end is connected to resistor R 17 resistance R 17 The other end is connected to the bias voltage V g2 and grounding capacitor C 14 microstrip line TL 11 The other end is connected to the gate of field-effect transistor M5, the source of field-effect transistor M5 is grounded, and the drain of field-effect transistor M5 is connected to microstrip line TL. 13 microstrip line TL 13 The other end is connected to the source of the field-effect transistor M7, and the gate of the field-effect transistor M7 is connected to the ground capacitor C. 15 and resistance R 19 resistance R 19 The other end is connected to the grounding resistor R 18 and resistance R 22 resistance R 22 The other end of the circuit and the drain of the field-effect transistor M7 are connected to the output of the final stage frequency multiplier amplifier network; the second input of the final stage frequency multiplier amplifier network is connected to inductor L5, and the other end of inductor L5 is connected to resistor R. 14 and capacitor C 13 resistance R 14 The other end is connected to the grounding capacitor C 11 and microstrip lines TL 12 Capacitor C 13 The other end is connected to resistor R 16 and microstrip lines TL 12 resistance R 16 The other end is connected to resistor R 17 resistance R 17 The other end is connected to the bias voltage V g2 and grounding capacitor C 14 microstrip line TL 12 The other end is connected to the gate of the field-effect transistor M6, the source of the field-effect transistor M6 is grounded, and the drain of the field-effect transistor M6 is connected to the microstrip line TL. 14 microstrip line TL 14 The other end is connected to the source of the field-effect transistor M8, and the gate of the field-effect transistor M8 is connected to the ground capacitor C. 16 and resistance R 21 resistance R 21 The other end is connected to the grounding resistor R 20 and resistance R 23 resistance R 23 The other end and the drain of the field-effect transistor M8 are connected to the output of the final stage frequency multiplier amplifier network.

5. The radio frequency broadband high-power frequency doubler according to claim 1, characterized in that, The input terminal of the output matching power supply network is connected to inductor L6, the other end of inductor L6 is connected to inductors L7 and L8, and the other end of inductor L7 is connected to the bias voltage V. dd Grounding capacitor C 18 and capacitor C 17 Capacitor C 17 The other end is connected to the grounding resistor R 24 The other end of inductor L8 is connected to ground capacitor C. 20 and C 19 C 19 The other end is connected to the output of the entire RF broadband high-power frequency doubler. out .

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