Digital signal generation method and device
By generating Gaussian noise signals of arbitrary bandwidth using linear feedback shift registers and interpolation, the problem of poor bandwidth flexibility in existing technologies is solved, realizing an efficient and flexible digital circuit generation method suitable for high-performance arbitrary wave generators.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING AEROSPACE MEASUREMENT & CONTROL TECH
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-15
Smart Images
Figure CN122052701A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal testing and measurement technology, and in particular to a method and apparatus for digital signal generation. Background Technology
[0002] In signal testing and measurement systems, Gaussian noise is an important signal, often used as an additive noise model for inputs to systems such as communication and control systems to test various system performance indicators. Gaussian noise is an ideal random signal with a constant power spectral density across all frequencies, and its instantaneous amplitude follows a Gaussian distribution. In practical applications, band-limited Gaussian noise is often used as an approximation of Gaussian noise within a certain bandwidth. Compared to pure Gaussian noise, its power spectral density remains constant within a specified frequency range, representing the result of Gaussian noise passing through a low-pass filter.
[0003] Traditional digital generation methods for band-limited Gaussian noise require first generating full-bandwidth Gaussian noise, then designing a corresponding filter based on the given noise bandwidth, and finally passing the full-bandwidth Gaussian noise through the filter to obtain band-limited Gaussian noise.
[0004] However, the drawback of the above method is that changing the noise bandwidth requires redesigning the filter coefficients. Filters with different bandwidths often have different orders and implementation structures. Usually, only a few pre-designed noise bandwidth levels are provided for selection based on a fixed order and implementation structure, which is inflexible and does not have the ability to generate Gaussian noise of arbitrary bandwidth in real time. Summary of the Invention
[0005] This application provides a digital signal generation method and apparatus to solve the problem that the prior art has poor flexibility in changing noise bandwidth and lacks the ability to generate Gaussian noise of arbitrary bandwidth in real time.
[0006] In a first aspect, this application provides a method for digitally generating a signal, comprising: N-channel M-bit uniformly distributed noise signals are generated in parallel using a linear feedback shift register; The N-channel M-bit uniformly distributed noise signals are summed using an adder to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; Invert the most significant bit of the sum signal to convert it into a signed number, and obtain a full-bandwidth Gaussian noise signal. The full-bandwidth Gaussian noise signal was processed by Sinc interpolation, and the relative positions of the interpolation point phase and the original sample point phase were recorded. Obtain the interpolation coefficients, and based on the interpolation coefficients, the interpolation point, and the original sample point, obtain the interpolation point amplitude, and output the interpolation point amplitude.
[0007] In one possible implementation, the parallel generation of N-channel M-bit uniformly distributed noise signals using a linear feedback shift register includes: M-bit uniformly distributed noise signals are generated by using M linear feedback shift registers through the target primitive polynomial row; According to the central limit theorem, the sum of N uniformly distributed noise signals yields N M-bit uniformly distributed noise signals.
[0008] In one possible implementation, the addition of the N-channel M-bit uniformly distributed noise signals to obtain a sum signal includes: The N-channel M-bit uniformly distributed noise signals are input in parallel to the adder; The adder adds the N-channel M-bit uniformly distributed noise signals pairwise, increasing the bit width by one at each stage to obtain the sum signal.
[0009] In one possible implementation, the step of inverting the most significant bit of the sum signal to convert it into a signed number, thereby obtaining a full-bandwidth Gaussian noise signal, includes: Obtain the most significant bit of the sum signal; Invert the highest bit to convert the sum signal into a signed number, thus obtaining a full-bandwidth Gaussian noise signal.
[0010] In one possible implementation, the step of performing Sinc interpolation on the full-bandwidth Gaussian noise signal and recording the relative positions of the interpolation point phase and the original sample point phase includes: Obtain the preset phase counter; The phase counter increments by a phase increment at each preset clock cycle to accumulate the phase. When the most significant bit of the phase counter flips once, an interpolation point is generated; The phase counter records the relative position of the interpolation point phase and the original sample point phase.
[0011] In one possible implementation, obtaining the interpolation coefficients, obtaining the interpolation point amplitude based on the interpolation coefficients, the interpolation point, and the original sample points, and outputting the interpolation point amplitude includes: Match the interpolation coefficients corresponding to the interpolation point from the pre-stored set of interpolation coefficients; The interpolation coefficients, the interpolation points, and the original sample points are processed to obtain the interpolation point amplitude, and the interpolation point amplitude is output.
[0012] Secondly, this application provides a digital signal generation apparatus, comprising: The generation module is used to generate N-channel M-bit uniformly distributed noise signals in parallel using a linear feedback shift register; The summing module is used to add the N-channel M-bit uniformly distributed noise signals using an adder to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; The conversion module is used to invert the most significant bit of the sum signal and convert it into a signed number to obtain a full-bandwidth Gaussian noise signal; The interpolation module is used to perform Sinc interpolation on the full-bandwidth Gaussian noise signal using the interpolation method, and to record the relative position of the interpolation point phase and the original sample point phase. The acquisition module is used to acquire interpolation coefficients, obtain the interpolation point amplitude based on the interpolation coefficients, the interpolation point and the original sample points, and output the interpolation point amplitude.
[0013] In one possible implementation, the interpolation module is specifically used to acquire a preset phase counter; the phase counter is incremented by a phase increment at each preset clock cycle to accumulate the phase; when the most significant bit of the phase counter flips once, an interpolation point is generated; the phase counter records the relative position of the interpolation point phase and the original sample phase.
[0014] In one possible implementation, the interpolation module is specifically used to match the interpolation coefficients corresponding to the interpolation point from a pre-stored set of interpolation coefficients; process the interpolation coefficients, the interpolation point, and the original sample points to obtain the interpolation point amplitude; and output the interpolation point amplitude.
[0015] Compared with the prior art, the technical solution provided in this application has the following advantages: The method provided in this application generates N M-bit uniformly distributed noise signals in parallel using a linear feedback shift register; an adder is used to add the N M-bit uniformly distributed noise signals to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; the most significant bit of the sum signal is inverted to convert it into a signed number to obtain a full-bandwidth Gaussian noise signal; an interpolation method is used to perform Sinc interpolation processing on the full-bandwidth Gaussian noise signal, and the relative position of the interpolation point phase and the original sample phase is recorded; interpolation coefficients are obtained, and the interpolation point amplitude is obtained based on the interpolation coefficients, the interpolation point, and the original sample, and the interpolation point amplitude is output. This method enables the real-time generation of band-limited Gaussian noise signals of arbitrary bandwidth using digital circuits, has a unified structure, high flexibility and scalability; and has high real-time performance and strong portability, and can be directly applied to high-performance arbitrary wave generator products. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0019] Figure 1 A flowchart illustrating an embodiment of a digital signal generation method provided in this application; Figure 2 A flowchart illustrating an embodiment of another digital signal generation method provided in this application; Figure 3 A schematic diagram illustrating the generation of a 16-bit uniformly distributed random signal based on PRBS31, provided in an embodiment of this application; Figure 4 This application provides a schematic diagram of the step-by-step addition of 16 channels of uniformly distributed noise in an embodiment. Figure 5 A schematic diagram illustrating the relationship between a 64-bit phase accumulation value, an initial phase value, and a phase output value, provided in an embodiment of this application; Figure 6 A spectrum of generated full-bandwidth Gaussian noise provided in an embodiment of this application; Figure 7 A spectrum of generated band-limited Gaussian noise provided in an embodiment of this application; Figure 8 This is a block diagram illustrating an embodiment of a digital signal generation device provided in this application. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0021] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.
[0022] To address the technical problems of poor flexibility in changing noise bandwidth and lack of real-time generation capability of Gaussian noise with arbitrary bandwidth in existing technologies, this application provides a digital signal generation method that can generate band-limited Gaussian noise signals with arbitrary bandwidth in real time through digital circuits. It has a single structure, high flexibility and scalability, and also has high real-time performance and strong portability, and can be directly applied to high-performance arbitrary wave generator products.
[0023] Figure 1 This is a flowchart illustrating an embodiment of a digital signal generation method provided in this application. Figure 1 As shown, the method includes the following steps: S101. Use a linear feedback shift register to generate N channels of M-bit uniformly distributed noise signals in parallel.
[0024] This application is applied to the generation stage of Gaussian noise in a signal testing and measurement system. It generates band-limited Gaussian noise signals of arbitrary bandwidth in real time through digital circuits, and the noise bandwidth can be changed at any time as needed.
[0025] In this embodiment, the LFSR (linear feedback shift register) can generate a 1-bit PRBS (pseudo-random binary sequence), and can be used to generate N M-bit uniformly distributed noise signals in parallel. Specifically, M LFSRs can be used to generate one M-bit uniformly distributed noise signal in parallel, resulting in a total of N M-bit uniformly distributed noise signals.
[0026] S102. Use an adder to add the N channels of M-bit uniformly distributed noise signals to obtain a sum signal, wherein the sum signal follows a Gaussian distribution.
[0027] In this embodiment, after obtaining N M-bit uniformly distributed noise signals, an adder is used to sum these N M-bit uniformly distributed noise signals to obtain a total signal. Specifically, the N M-bit uniformly distributed noise signals are input into the adder in parallel. The adder aligns each data signal bit by bit, adding them bit by bit starting from the least significant bit, with carry propagated step by step to the most significant bit. The final output is the total signal. Since each noise signal is independent and uniform, the accumulated result (total signal) follows a Gaussian distribution.
[0028] In one example, since PRBS has statistical randomness, the M-bit signal generated in parallel by M LFSRs can be considered to obey... The sum of N independent random variables, all uniformly distributed, can be considered to follow a Gaussian distribution as N approaches infinity. Furthermore, according to the Levi-Lindeberg central limit theorem, the sum of N independent random variables, all uniformly distributed, can be considered to follow a Gaussian distribution, whose mean and variance are N times those of the uniform distribution. That is:
[0029] Where a and b are the lower and upper limits of a uniform distribution, respectively. and Let be the mean and variance of the Gaussian distribution.
[0030] S103. Invert the highest bit of the sum signal to convert it into a signed number, and obtain the full-bandwidth Gaussian noise signal.
[0031] In this embodiment, after obtaining the sum signal, the most significant bit of the sum signal is obtained and inverted. For example, the binary value of the most significant bit, which originally represents "0" or "1", is directly inverted. The sum signal after inversion is converted from an unsigned number to a signed number, resulting in a full-bandwidth Gaussian noise signal. This full-bandwidth Gaussian noise signal is then used as the original sample for subsequent interpolation operations. After the above-mentioned most significant bit inversion operation, the sum signal is converted from an unsigned code that can only represent positive numbers to a signed code that can represent both positive and negative numbers, while maintaining the relative order of the sum signal values.
[0032] S104. The full-bandwidth Gaussian noise signal is processed by Sinc interpolation, and the relative position of the interpolation point phase and the original sample point phase is recorded.
[0033] In this embodiment, Sinc interpolation is used to perform band-limited operation on the full-bandwidth Gaussian noise signal. Specifically, a phase counter with pre-set precision controls the output rate of the full-bandwidth Gaussian noise signal and records the relative position between the phase of the current interpolation point and the phase of the original sample point. Sinc interpolation only requires two original data points (one before and one after) to calculate the current interpolation point, resulting in fast calculation speed and low resource consumption.
[0034] In practical applications, due to the system's sampling rate Since the value is finite, the upper limit of the bandwidth of the generated full-bandwidth Gaussian noise is... ,in Let be the sampling rate of the system. After interpolating the full-bandwidth Gaussian noise by a factor of n using the Sinc interpolation operation, the bandwidth of the noise is... It will become:
[0035] Where k is the bandwidth compensation factor for Sinc interpolation. The actual rate of the signal after n-fold interpolation for:
[0036] Combining the above two equations, we can obtain the relationship between the bandwidth of the band-limited noise and the rate of the band-limited noise:
[0037] Therefore, it can be seen that the noise bandwidth can be changed by altering the interpolated signal rate. In this application, the actual rate of the noise signal can be changed by altering the phase accumulation value of the interpolated noise signal. This enables real-time changes in noise bandwidth.
[0038] S105. Obtain the interpolation coefficients, and based on the interpolation coefficients, interpolation points, and original sample points, obtain the interpolation point amplitude and output the interpolation point amplitude.
[0039] In this embodiment, when performing Sinc interpolation to generate a new interpolation point, the corresponding interpolation coefficients are read from the BRAM (Block Random Access Memory) based on the fractional part of the phase counter. The read interpolation coefficients are then processed with the interpolation point and the original sample points to obtain the interpolation point amplitude. The interpolation point amplitude is then output, thereby realizing the real-time generation of Gaussian noise with arbitrary bandwidth.
[0040] The technical solution provided in this application utilizes a linear feedback shift register to generate N M-bit uniformly distributed noise signals in parallel; an adder is used to sum the N M-bit uniformly distributed noise signals to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; the most significant bit of the sum signal is inverted to convert it into a signed number, resulting in a full-bandwidth Gaussian noise signal; Sinc interpolation is performed on the full-bandwidth Gaussian noise signal, and the relative position of the interpolation point phase and the original sample phase is recorded; interpolation coefficients are obtained, and the interpolation point amplitude is obtained based on the interpolation coefficients, the interpolation point, and the original sample, and the interpolation point amplitude is output. This enables the real-time generation of band-limited Gaussian noise signals of arbitrary bandwidth through digital circuits, has a unified structure, high flexibility and scalability; and possesses high real-time performance and strong portability, making it directly applicable to high-performance arbitrary wave generator products.
[0041] Figure 2 A flowchart illustrating an embodiment of another digital signal generation method provided in this application. Figure 2 The process shown includes the following steps: S201. Use M linear feedback shift registers to generate an M-bit uniformly distributed noise signal through the target primitive polynomial row.
[0042] This application is applied to the generation stage of Gaussian noise in a signal testing and measurement system. It generates band-limited Gaussian noise signals of arbitrary bandwidth in real time through digital circuits, and the noise bandwidth can be changed at any time as needed.
[0043] In this embodiment, the LFSR can generate a 1-bit PRBS, and an M-bit uniformly distributed noise signal can be generated in parallel by M LFSRs. Since the PRBS is statistically random, the M-bit signal generated in parallel by M LFSRs can be considered to follow [0, 2M]. Uniform distribution on 1].
[0044] S202. According to the central limit theorem, the N uniformly distributed noise signals are added together to obtain N M-bit uniformly distributed noise signals.
[0045] In this embodiment, N channels of uniformly distributed noise signals of the aforementioned M bits can be generated using an LFSR, and then summed to obtain N channels of uniformly distributed noise signals of M bits. According to the Levi-Lindeberg central limit theorem, when N approaches infinity, the sum of N independent random variables, all of which follow a uniform distribution, can be considered to follow a Gaussian distribution, thus yielding N channels of uniformly distributed noise signals of M bits.
[0046] In one example, taking the real-time generation of arbitrary bandwidth Gaussian noise signals implemented on an FPGA with a clock frequency of 250 MHz as an example, 16 channels of 16-bit uniformly distributed noise signals are generated in parallel using a linear feedback shift register. These 16 channels of 16-bit uniformly distributed noise signals are then summed. Each channel of uniformly distributed noise is composed of 16 PRBS31 signals, each generated by an LFSR. The primitive polynomial is: The LFSR taps are located in registers 28 and 31, as follows: Figure 3 As shown.
[0047] S203. Input the N-channel M-bit uniformly distributed noise signals in parallel to the adder.
[0048] In this embodiment, after obtaining N channels of M-bit uniformly distributed noise signals, these signals are input in parallel to an adder for addition. Using an adder to perform the addition of the N channels of uniformly distributed noise signals improves computational efficiency while ensuring the dynamic range and accuracy of the noise signals.
[0049] In one example, taking the real-time generation of arbitrary bandwidth Gaussian noise signals implemented on an FPGA with a clock frequency of 250 MHz as an example, the generated 16 channels of 16-bit uniformly distributed noise signals are processed by a 4-stage adder. These 16 channels of 16-bit uniformly distributed noise signals are input in parallel to the 4-stage adder. Using the 4-stage adder, the 16 signal data are reduced pairwise, achieving the most compact tree structure for adding the 16 channels of 16-bit uniformly distributed noise signals, thus obtaining the subsequent sum signal.
[0050] S204. The adder adds the N-channel M-bit uniformly distributed noise signals in pairs, increasing the bit width by one at each stage to obtain the sum signal.
[0051] In this embodiment, after the adder obtains the aforementioned N-channel M-bit uniformly distributed noise signal, it aligns each data channel bit by bit, adds them pairwise starting from the least significant bit, increases the bit width by one level at each level, and propagates the carry to the most significant bit, finally outputting the sum signal. Since each noise channel in the aforementioned N-channel M-bit uniformly distributed noise signal is independent and uniform, according to the Levi-Lindeberg central limit theorem, when N approaches infinity, the sum of N independent random variables that all follow a uniform distribution can be considered to follow a Gaussian distribution, that is, the cumulative result (sum signal) follows a Gaussian distribution.
[0052] In one example, taking the real-time generation of arbitrary bandwidth Gaussian noise signals implemented on an FPGA with a clock frequency of 250 MHz as an example, the above-mentioned four-stage adder adds the acquired 16 channels of 16-bit uniformly distributed noise signals pairwise, increasing the bit width by one at each stage, and propagating the carry to the most significant bit at each stage, finally outputting a 20-bit sum signal. Figure 4 As shown in the figure, n1~n16 are 16 channels of uniformly distributed noise, and r1-x, r2-x, r3-x and r4-x represent the results of the 1st, 2nd, 3rd and 4th stage adders, respectively.
[0053] S205, Obtain the highest bit of the sum signal.
[0054] S206. Invert the most significant bit to convert the sum signal into a signed number, resulting in a full-bandwidth Gaussian noise signal.
[0055] The following is a unified discussion of S205-S206.
[0056] In this embodiment, after obtaining the sum signal, it is converted into a signed number by inverting the most significant bit. Specifically, the most significant bit of the sum signal is first obtained, and then inverted. After inversion, the sum signal is converted from an unsigned number to a signed number, resulting in a full-bandwidth Gaussian noise signal. Through the aforementioned most significant bit inversion operation, the sum signal is converted from an unsigned code that can only represent positive numbers to a signed code that can represent both positive and negative numbers, while maintaining the relative order of the sum signal values.
[0057] In one example, taking the real-time generation of an arbitrary bandwidth Gaussian noise signal implemented on an FPGA with a clock frequency of 250 MHz as an example, the highest bit of the 20-bit sum signal is obtained, and the highest bit of the 20-bit sum signal is inverted to convert it into a signed number, resulting in a full-bandwidth Gaussian noise signal with a mean of 0 and a variance of 75674.45. Then, this signal is used as the original sample point for Sinc interpolation.
[0058] S207. Obtain the preset phase counter.
[0059] In this embodiment, an interpolation method is used to perform Sinc interpolation on the full-bandwidth Gaussian noise signal. The noise signal rate is changed by altering the phase accumulation value of the interpolated noise signal. This enables band-limited operation of full-bandwidth Gaussian noise. A phase counter is set to control the rate at which the full-bandwidth Gaussian noise signal is output, while simultaneously recording the relative position between the current interpolation point phase and the original sample phase.
[0060] In one example, taking the real-time generation of an arbitrary bandwidth Gaussian noise signal implemented on an FPGA with a clock frequency of 250 MHz as an example, after obtaining the full bandwidth Gaussian noise signal, a phase counter with an accuracy of u (64, 63) is set to control the rate of outputting the full bandwidth Gaussian noise signal, while recording the relative position between the current interpolation point phase and the original sample phase.
[0061] S208. The phase counter increments by a phase increment at each preset clock cycle to accumulate the phase.
[0062] In this embodiment, the initial state of the phase counter is the initial phase configured by the host computer. The phase counter increments by a phase increment P in each preset clock cycle for phase accumulation. After implementing band-limiting operation for full-bandwidth Gaussian noise using the Sinc interpolation method, the noise bandwidth is changed in real time by altering the phase accumulation of the interpolated noise signal, thus improving the real-time performance of band-limited Gaussian noise generation.
[0063] In one example, taking the real-time generation of an arbitrary bandwidth Gaussian noise signal implemented on an FPGA with a clock frequency of 250 MHz as an example, the phase counter increments by a phase increment P at each preset clock cycle to perform phase accumulation processing. The relationship between the phase quantities is as follows: Figure 5 As shown. The value of the phase increment P is determined by the following formula:
[0064] S209. When the highest bit of the phase counter flips once, an interpolation point is generated.
[0065] S210, the phase counter records the relative position of the interpolation point phase and the original sample point phase.
[0066] The following is a unified discussion of S209-S210.
[0067] In this embodiment, during phase accumulation processing, a new noise interpolation point is generated when the most significant bit of the phase counter flips once. A new interpolation point is generated, and its relative position to the phases of the two preceding and following original samples is recorded. The noise signal rate is changed in real time by altering the phase accumulation of the full-bandwidth Gaussian noise signal after Sinc interpolation. Furthermore, calculating the current interpolation point only requires data from two preceding and following original points, resulting in fast computation and low resource consumption.
[0068] In one example, taking the real-time generation of an arbitrary bandwidth Gaussian noise signal implemented on an FPGA with a clock frequency of 250 MHz as an example, when performing phase accumulation processing, when the highest bit of the phase counter changes (i.e., when a flip occurs), a new interpolation point is generated, and the relative position of the interpolation point with the phase of the two original sample points before and after is recorded by the last 63 bits of the phase counter so that the amplitude can be output in subsequent processing.
[0069] S211. Match the interpolation coefficients corresponding to the interpolation point from the pre-stored set of interpolation coefficients.
[0070] S212. Process the interpolation coefficients, interpolation points, and original sample points to obtain the interpolation point amplitude, and output the interpolation point amplitude.
[0071] The following is a unified discussion of S211-S212.
[0072] In this embodiment, when performing Sinc interpolation to generate a new interpolation point, the interpolation coefficient corresponding to the interpolation point is matched from the pre-stored interpolation coefficient set based on the fractional part of the phase counter. After obtaining the interpolation coefficient, a weighted sum is calculated between the interpolation point and the two original samples before and after the interpolation point to obtain the interpolation point amplitude of the phase, and the interpolation point amplitude is output. The interpolation point amplitude may include a time-domain waveform and a spectrum.
[0073] In one example, taking the real-time generation of an arbitrary bandwidth Gaussian noise signal implemented on an FPGA with a clock frequency of 250 MHz as an example, Sinc interpolation with 10-bit precision and a roll-off factor of 0.3 is used for processing. When generating a new interpolation point through Sinc interpolation, the first 10 digits of the fractional part of the phase counter are matched against a pre-stored set of interpolation coefficients to obtain the interpolation coefficients corresponding to that interpolation point. This set of interpolation coefficients contains 1024 pre-calculated groups, each with 16 coefficients, and can be stored in BRAM. Using the obtained interpolation coefficients, the interpolation point amplitude is calculated with the interpolation point and the two original samples before and after the interpolation point to obtain the interpolation point amplitude for that phase, and the interpolation point amplitude is output. Figure 6 The image shows the spectrum of the generated full-bandwidth Gaussian noise. Figure 7 The image shows the spectrum of the generated band-limited Gaussian noise.
[0074] Figure 2The illustrated process provides another digital signal generation method. It uses M LFSRs to generate an M-bit uniformly distributed noise signal in parallel, and then adds the N uniformly distributed noise signals to obtain a full-bandwidth Gaussian noise signal. The Sinc interpolation method is used to achieve band-limiting of the full-bandwidth Gaussian noise, and the noise bandwidth is changed in real time by adjusting the phase accumulation of the interpolated noise signal. This method enables direct generation of Gaussian noise in digital circuits without the need for related analog components. It eliminates the need to redesign filters during band-limited Gaussian noise generation, and the bandwidth of the band-limited Gaussian noise is arbitrarily variable, offering high flexibility and scalability. The system responds immediately to changes in the relevant parameters of the band-limited Gaussian noise, demonstrating high real-time performance. It can be directly applied to high-performance arbitrary wave generator products, and can be used alone or combined with other functions to achieve more complex functions (such as noise modulation, outputting noisy signals, etc.), exhibiting strong portability.
[0075] Figure 8 This is a block diagram illustrating an embodiment of a digital signal generation device provided in this application. Figure 8 As shown, the device includes: The generation module 801 is used to generate N-channel M-bit uniformly distributed noise signals in parallel using a linear feedback shift register; The summing module 802 is used to add the N-channel M-bit uniformly distributed noise signals using an adder to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; The conversion module 803 is used to invert the most significant bit of the sum signal and convert it into a signed number to obtain a full-bandwidth Gaussian noise signal; Interpolation module 804 is used to perform Sinc interpolation processing on the full-bandwidth Gaussian noise signal using the interpolation method, and record the relative position of the interpolation point phase and the original sample point phase; The acquisition module 805 is used to acquire interpolation coefficients, obtain the interpolation point amplitude based on the interpolation coefficients, the interpolation point and the original sample points, and output the interpolation point amplitude.
[0076] In one possible implementation, the generation module 801 is specifically used to generate an M-bit uniformly distributed noise signal in parallel using M linear feedback shift registers through a target primitive polynomial; and to add the N uniformly distributed noise signals together according to the central limit theorem to obtain an N-bit uniformly distributed noise signal.
[0077] In one possible implementation, the summing module 802 is specifically used to input the N-channel M-bit uniformly distributed noise signals in parallel to the adder; the adder adds the N-channel M-bit uniformly distributed noise signals pairwise step by step, increasing the bit width by one step by step, to obtain the sum signal.
[0078] In one possible implementation, the conversion module 803 is specifically used to obtain the most significant bit of the sum signal; invert the most significant bit to convert the sum signal into a signed number, thereby obtaining a full-bandwidth Gaussian noise signal.
[0079] In one possible implementation, the interpolation module 804 is specifically used to acquire a preset phase counter; the phase counter is incremented by a phase increment at each preset clock cycle to accumulate the phase; when the most significant bit of the phase counter flips once, an interpolation point is generated; the phase counter records the relative position of the interpolation point phase and the original sample phase.
[0080] In one possible implementation, the acquisition module 805 is specifically used to match the interpolation coefficients corresponding to the interpolation point from a pre-stored set of interpolation coefficients; process the interpolation coefficients, the interpolation point, and the original sample points to obtain the interpolation point amplitude, and output the interpolation point amplitude.
[0081] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0082] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0083] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.
[0084] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A method for digitally generating a signal, characterized in that, The method includes: N-channel M-bit uniformly distributed noise signals are generated in parallel using a linear feedback shift register; The N-channel M-bit uniformly distributed noise signals are summed using an adder to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; Invert the most significant bit of the sum signal to convert it into a signed number, and obtain a full-bandwidth Gaussian noise signal. The full-bandwidth Gaussian noise signal was processed by Sinc interpolation, and the relative positions of the interpolation point phase and the original sample point phase were recorded. Obtain the interpolation coefficients, and based on the interpolation coefficients, the interpolation point, and the original sample point, obtain the interpolation point amplitude, and output the interpolation point amplitude.
2. The method according to claim 1, characterized in that, The method of generating N-channel M-bit uniformly distributed noise signals in parallel using a linear feedback shift register includes: M-bit uniformly distributed noise signals are generated in parallel using M linear feedback shift registers through the target primitive polynomial; According to the central limit theorem, the sum of N uniformly distributed noise signals yields N M-bit uniformly distributed noise signals.
3. The method according to claim 1, characterized in that, The method of adding the N-channel M-bit uniformly distributed noise signals using an adder to obtain a sum signal includes: The N-channel M-bit uniformly distributed noise signals are input in parallel to the adder; The adder adds the N-channel M-bit uniformly distributed noise signals pairwise, increasing the bit width by one at each stage to obtain the sum signal.
4. The method according to claim 1, characterized in that, The step of inverting the most significant bit of the sum signal to convert it into a signed number, thereby obtaining a full-bandwidth Gaussian noise signal, includes: Obtain the most significant bit of the sum signal; Invert the highest bit to convert the sum signal into a signed number, thus obtaining a full-bandwidth Gaussian noise signal.
5. The method according to claim 1, characterized in that, The step of performing Sinc interpolation on the full-bandwidth Gaussian noise signal and recording the relative positions of the interpolation point phase and the original sample point phase includes: Obtain the preset phase counter; The phase counter increments by a phase increment at each preset clock cycle to accumulate the phase. When the most significant bit of the phase counter flips once, an interpolation point is generated; The phase counter records the relative position of the interpolation point phase and the original sample point phase.
6. The method according to claim 5, characterized in that, The process of obtaining interpolation coefficients, obtaining interpolation point amplitudes based on the interpolation coefficients, the interpolation points, and the original sample points, and outputting the interpolation point amplitudes includes: Match the interpolation coefficients corresponding to the interpolation point from the pre-stored set of interpolation coefficients; The interpolation coefficients, the interpolation points, and the original sample points are processed to obtain the interpolation point amplitude, and the interpolation point amplitude is output.
7. A digital signal generation device, characterized in that, The device includes: The generation module is used to generate N-channel M-bit uniformly distributed noise signals in parallel using a linear feedback shift register; The summing module is used to add the N-channel M-bit uniformly distributed noise signals using an adder to obtain a sum signal, wherein the sum signal follows a Gaussian distribution; The conversion module is used to invert the most significant bit of the sum signal and convert it into a signed number to obtain a full-bandwidth Gaussian noise signal; The interpolation module is used to perform Sinc interpolation on the full-bandwidth Gaussian noise signal using the interpolation method, and to record the relative position of the interpolation point phase and the original sample point phase. The acquisition module is used to acquire interpolation coefficients, obtain the interpolation point amplitude based on the interpolation coefficients, the interpolation point and the original sample points, and output the interpolation point amplitude.
8. The apparatus according to claim 7, characterized in that, The interpolation module is specifically used to acquire a preset phase counter; the phase counter is incremented by a phase increment at each preset clock cycle to accumulate the phase; when the highest bit of the phase counter flips once, an interpolation point is generated; the phase counter records the relative position of the interpolation point phase and the original sample phase.
9. The apparatus according to claim 7, characterized in that, The interpolation module is specifically used to match the interpolation coefficients corresponding to the interpolation point from a pre-stored set of interpolation coefficients; process the interpolation coefficients, the interpolation point, and the original sample points to obtain the interpolation point amplitude; and output the interpolation point amplitude.