Ultra-compact parallel Doherty power amplifier based on three-coil transformer

Abstract

The invention discloses an ultra-compact parallel Doherty power amplifier based on a three-coil transformer. Each of an integrated phase compensation input matching network and an integrated load modulation output matching network comprises a multi-coil transformer; the integrated phase compensation input matching network performs differential conversion, power distribution, phase compensation and impedance conversion processing on a radio frequency input signal, and outputs a main power amplifier input signal and an auxiliary power amplifier input signal; the main power amplifier processes a main power amplifier input signal and outputs a first amplified signal; the auxiliary power amplifier processes the auxiliary power amplifier input signal and outputs a second amplified signal; and the integrated load modulation output matching network performs load modulation and impedance conversion processing on the first amplification signal and the second amplification signal, and outputs a radio frequency output signal. The Doherty power amplifier disclosed by the invention is highly compact in structure and extremely small in chip area.

Description

Technical Field

[0001] This invention belongs to the field of power amplifier technology, specifically relating to an ultra-compact parallel Doherty power amplifier based on a three-coil transformer. Background Technology

[0002] In modern wireless communication systems (such as 5G and future 6G), complex modulation techniques (such as OFDM) used to improve spectral efficiency result in signals with very high peak-to-average power ratios (PARs). This necessitates that power amplifiers located at the RF front-end maintain high efficiency simultaneously in both the high-power saturation region and the low-power backoff region. Among numerous high-efficiency architectures, the Doherty Power Amplifier (DPA) stands out as a highly attractive solution for the millimeter-wave band due to its ability to effectively improve efficiency by 6dB or even higher backoff points and its clear conceptual design.

[0003] However, when operating frequencies are increased to the millimeter-wave band, the quarter-wavelength transmission lines relied upon in traditional Doherty power amplifiers become incompatible with chip integration principles due to their enormous physical size. Therefore, research has shifted to how to utilize lumped components and transformers to achieve compact, fully integrated millimeter-wave Doherty power amplifiers.

[0004] To achieve a compact parallel Doherty power amplifier, existing solutions primarily focus on optimizing the output matching network. Two common parallel Doherty power amplifier output matching schemes exist. Scheme one involves connecting the outputs of both the main and auxiliary amplifiers to a transformer first, achieving impedance transformation and absorbing the parasitic capacitance of the transistors. Subsequently, a CLC-based impedance inverter network is connected in series with the main amplifier branch, and then connected in parallel with the auxiliary amplifier branch, combining to reach the RF output. This impedance inverter is a key component for achieving Doherty load modulation; it modulates the load impedance seen by the main amplifier, allowing the amplifier to maintain high efficiency in the high-power back-off range. Scheme two connects a CLC network to the output of the main amplifier. This network acts as a quarter-wavelength impedance inverter to achieve load modulation. In this scheme, the capacitance of the impedance inverter network is not entirely introduced independently, but rather partially or entirely utilizes the output parasitic capacitance of the main and auxiliary amplifiers themselves, thus absorbing these parasitic parameters and converting them into an effective component of the impedance inverter. Subsequently, the two signals are connected in parallel to a shared, highly optimized single transformer, which simultaneously performs impedance transformation and power combining functions.

[0005] For input matching, existing technologies mostly employ the following two schemes. Scheme one uses a fully differential architecture. The RF input signal is first converted to a differential signal by a balun, and then split into two paths by a Wilson power divider: one path directly undergoes impedance transformation via a transformer to drive the main power amplifier; the other path first passes through a phase compensation network composed of differential CLCs, and then is transformed by a transformer to drive the auxiliary power amplifier. The differential inductors in the phase compensation network use a reverse magnetic coupling design to reduce area. This structure maintains good symmetry and compactness while achieving power distribution, phase compensation, and impedance transformation. Scheme two uses an LC quadrature coupler to simultaneously achieve single-slip and power distribution functions. The resulting two output signals are then impedance transformed by independent transformers to match the input impedances of the main and auxiliary power amplifiers.

[0006] However, the existing output matching schemes mentioned above, Scheme 1, employs a "dual transformer + CLC" structure, resulting in significant area overhead. While Scheme 2 reduces the area to a single transformer and CLC network combination, it still occupies relatively large layout resources. Furthermore, this scheme relies on the CLC network to absorb the transistor's output parasitic capacitance, requiring the transistor's parasitic capacitance to be less than or equal to the designed capacitance value in the network. This stringent condition severely limits its applicability in advanced processes or various transistor topologies with large output capacitances, resulting in low design freedom and insufficient versatility and robustness. Meanwhile, existing input matching schemes, while achieving signal distribution and impedance transformation, often come with significant chip area overhead, hindering high-integration designs. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides an ultra-compact parallel Doherty power amplifier based on a three-coil transformer.

[0008] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides an ultra-compact parallel Doherty power amplifier based on a three-coil transformer, comprising an integrated phase compensation input matching network, a main power amplifier, an auxiliary power amplifier, and an integrated load modulation output matching network; both the integrated phase compensation input matching network and the integrated load modulation output matching network include multi-coil transformers; An integrated phase-compensated input matching network is used to perform differential conversion, power distribution, phase compensation, and impedance transformation on the input RF signal, and output the main power amplifier input signal and the auxiliary power amplifier input signal. The main power amplifier and the auxiliary power amplifier are connected to the output of the integrated phase compensation input matching network. The main power amplifier processes the input signal of the main power amplifier and outputs the first amplified signal; the auxiliary power amplifier processes the input signal of the auxiliary power amplifier and outputs the second amplified signal. An integrated load modulation output matching network is connected to the output of the main power amplifier and the output of the auxiliary power amplifier. It is used to perform load modulation and impedance transformation on the first and second amplified signals and output an RF output signal.

[0009] This invention provides an ultra-compact parallel Doherty power amplifier based on a three-coil transformer. Both the integrated phase-compensation input matching network and the integrated load-modulation output matching network are centered around the three-coil transformer, condensing the functions of multiple independent passive modules (single slip / power distribution / phase compensation / impedance transformation / power combining / load modulation) in traditional solutions into two highly compact transformers. This results in an extremely small chip area. Furthermore, the integrated load-modulation output matching network of this invention inherently absorbs the parasitic capacitance of the power amplifier output through its coils connected in parallel with the amplifier, regardless of the size of the output parasitic capacitance. It is suitable for various power amplifier structures.

[0010] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a circuit diagram of an ultra-compact parallel Doherty power amplifier based on a three-coil transformer provided in an embodiment of the present invention; Figure 2 This is a circuit diagram of the integrated phase compensation input matching network provided in an embodiment of the present invention; Figure 3 This is a circuit diagram of the integrated load modulation output matching network provided in an embodiment of the present invention; Figure 4 This is a circuit diagram of the main power amplifier and auxiliary power amplifier provided in an embodiment of the present invention; Figure 5 This is a circuit diagram of the adaptive bias circuit provided in an embodiment of the present invention; Figure 6 This is a simulation diagram of the S-parameters of the Doherty power amplifier provided in an embodiment of the present invention; Figure 7 This is a schematic diagram showing the simulation results of the output power-power-added efficiency of the Doherty power amplifier provided in the embodiment of the present invention. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0013] See Figure 1 This invention provides an ultra-compact parallel Doherty power amplifier based on a three-coil transformer, comprising an integrated phase-compensated input matching network, a main power amplifier, an auxiliary power amplifier, and an integrated load modulation output matching network. Both the integrated phase-compensated input matching network and the integrated load modulation output matching network include multi-coil transformers.

[0014] The integrated phase-compensated input matching network is used to perform differential conversion, power distribution, phase compensation, and impedance transformation on the input RF signal, and output the main power amplifier input signal and the auxiliary power amplifier input signal.

[0015] The main power amplifier and the auxiliary power amplifier are connected to the output of the integrated phase compensation input matching network. The main power amplifier processes the input signal of the main power amplifier and outputs the first amplified signal; the auxiliary power amplifier processes the input signal of the auxiliary power amplifier and outputs the second amplified signal.

[0016] An integrated load modulation output matching network is connected to the output of the main power amplifier and the output of the auxiliary power amplifier. It is used to perform load modulation and impedance transformation on the first and second amplified signals and output an RF output signal.

[0017] Specifically, the millimeter-wave Doherty power amplifier of this invention adopts a differential single-stage structure. The input end employs an integrated phase-compensated input matching network to simultaneously achieve single-slip, power distribution, phase compensation, and impedance transformation functions. The output end employs an integrated load-modulated output matching network to simultaneously achieve load modulation and impedance transformation functions.

[0018] In one alternative embodiment, the integrated phase-compensated input matching network includes a first three-coil transformer and an adaptive bias circuit; the first three-coil transformer consists of a first inductor L. i1 Second inductor L i2 With the third inductor L i3 Magnetic coupling in three-dimensional space constitutes the first inductor L; i1 One end of the inductor is used to receive radio frequency input signals, and the other end is grounded; the second inductor L i2 Both ends of the inductor are connected to the differential input ports of the main power amplifier, and its center tap is connected to the DC bias voltage; the third inductor L i3 The two ends are connected to the differential input port of the auxiliary power amplifier; the input of the adaptive bias circuit is used to receive the RF input signal, and the output is connected to the third inductor L. i3 The center tap.

[0019] Specifically, refer to Figure 2The integrated phase-compensated input matching network includes a three-coil transformer (the first three-coil transformer) and an adaptive bias circuit. The first three-coil transformer consists of a first inductor (L... i1 ), second inductor (L i2 ) and the third inductor (L i3 ) are magnetically coupled in three-dimensional space; wherein the first inductor (L i1 The primary winding is connected to the RF input signal; the second inductor (L) i2 As the primary winding, through the coupling coefficient k i12 With L i1 The coupling is connected at both ends to the differential input port of the main power amplifier, and its center tap is connected to the DC bias voltage to provide a fixed bias voltage for the main power amplifier (i.e., the main power amplifier); the third inductor (L i3 As the second-stage winding, through the coupling coefficient k i13 With L i1 The first inductor is coupled to the differential input port of the auxiliary power amplifier at both ends. There is also coupling between the second and third inductors, with a coupling coefficient of k. i23 The input of the adaptive bias circuit is connected to the RF input signal, and its output is connected to the third inductor (L). i3 The center tap of the amplifier provides a bias voltage that dynamically varies with the input power for the auxiliary power amplifier (i.e., the auxiliary power amplifier).

[0020] During operation, the RF input signal is distributed to the main and auxiliary power amplifier paths through the magnetic coupling of the first three-coil transformer, simultaneously achieving broadband matching from the system input impedance to the power amplifier input impedance. Furthermore, based on the specific coupling relationship of the three coils, this input matching network introduces an approximately 90° phase difference between the auxiliary and main power amplifier paths to satisfy the phase combining conditions of the Doherty architecture. The adaptive bias circuit adjusts the bias state of the auxiliary power amplifier in real time according to the input power level: in the low-power region, the auxiliary power amplifier is nearly turned off; as the power increases, its bias is dynamically increased to turn it on and participate in power combining.

[0021] The integrated phase-compensated input matching network structure in this embodiment occupies the area of ​​a single transformer, thus simultaneously realizing four functions: single-ended to differential conversion, power distribution, 90° phase compensation, and impedance transformation. Compared with the aforementioned traditional input matching scheme one, the chip area can be reduced by more than 83%; compared with the aforementioned traditional input matching scheme two, the area can also be reduced by approximately 67%.

[0022] In one alternative embodiment, the adaptive bias circuit includes a fifth transistor M5, a sixth transistor M6, a DC blocking capacitor C5, and a first bias voltage V. th Second bias voltage V D1 Third bias voltage VG1 The circuit includes a first bias resistor R1, a second bias resistor R2, and a third bias resistor R3; one end of the DC blocking capacitor C5 is used to receive the RF input signal, and the other end is connected to the gate of the fifth transistor M5; the source of the fifth transistor M5 is grounded, and its drain is connected to the gate of the sixth transistor M6; the source of the sixth transistor M6 is grounded, and its drain serves as the output of the adaptive bias circuit; and the first bias voltage V... th The first bias resistor R1 is connected to the gate of the fifth transistor M5; the second bias voltage V D1 The second bias resistor R2 is connected to the gate of the sixth transistor M6; the third bias voltage V G1 The third bias resistor R3 is connected to the output of the adaptive bias circuit.

[0023] Specifically, refer to Figure 5 The adaptive bias circuit includes a fifth transistor (M5), a sixth transistor (M6), a DC blocking capacitor (C5), and first to third bias voltage sources (V). th V D1 V G1 ) and the corresponding bias resistors (R1, R2, R3).

[0024] One end of the DC blocking capacitor (C5) is connected to the RF input signal, and the other end is connected to the gate of the fifth transistor (M5). The source of the fifth transistor (M5) is grounded, and its drain is connected to the gate of the sixth transistor (M6). The source of the sixth transistor (M6) is grounded, and its drain serves as the output of the adaptive bias circuit, used to provide a bias voltage to the auxiliary power amplifier. The first bias voltage (V...) th The first bias resistor R1 is connected to the gate of the fifth transistor (M5) to set its turn-on threshold. The second bias voltage (V) D1 The third bias voltage (V) is connected to the gate of the sixth transistor (M6) through the second bias resistor R2. G1 It is connected to the output of the adaptive bias circuit through the third bias resistor R3.

[0025] The working principle of the adaptive bias circuit is as follows: When a small signal is input, the first bias voltage (V) th When the voltage is low, the first transistor (M5) is turned off; due to the second bias voltage (V... D1 When the signal is high, the second transistor (M6) turns on, the circuit outputs 0V, and the auxiliary power amplifier is completely off. When a large signal is input, if the RF input power is sufficient to turn on the first transistor (M5), the gate of the second transistor (M6) is pulled low to ground and turns off, and the circuit outputs a third bias voltage (V). G1 The auxiliary power amplifier is fully turned on and biased.

[0026] In one alternative embodiment, both the main power amplifier and the auxiliary power amplifier adopt a differential cascode structure and use transistors of the same size.

[0027] In one optional embodiment, the differential cascode structure includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the gates of the first transistor M1 and the second transistor M2 are interconnected as differential input ports, and the sources of the first transistor M1 and the second transistor M2 are interconnected and grounded; the gates of the third transistor M3 and the fourth transistor M4 are interconnected and connected to a DC bias voltage; the drains of the third transistor M3 and the fourth transistor M4 are interconnected. As a differential output port; the drain of the first transistor M1 is connected to the source of the third transistor M3; the drain of the second transistor M2 is connected to the source of the fourth transistor M4; the first capacitor C1 is connected between the drain of the first transistor M1 and the gate of the second transistor M2; the second capacitor C2 is connected between the drain of the second transistor M2 and the gate of the first transistor M1; the third capacitor C3 is connected between the drain of the second transistor M2 and the drain of the third transistor M3; and the fourth capacitor C4 is connected between the drain of the first transistor M1 and the drain of the fourth transistor M4.

[0028] Specifically, refer to Figure 4 The main power amplifier and the auxiliary power amplifier use the exact same circuit architecture and transistor size. Both the main power amplifier and the auxiliary power amplifier are implemented using a differential cascode structure.

[0029] The differential cascode structure includes first to fourth transistors (M1, M2, M3, M4) and first to fourth capacitors (C1, C2, C3, C4), and is integrated using CMOS technology.

[0030] The first transistor (M1) and the second transistor (M2) form a common-source differential input pair. Their gates are interconnected, serving as a differential input port to receive the differential input signal (i.e., the main power amplifier input signal or the auxiliary power amplifier input signal) and the DC bias voltage of the common-source differential pair; their sources are interconnected and grounded. The DC bias voltage of the main power amplifier's common-source differential pair is determined by the second inductor L. i2 The center tap is supplied with the external power supply voltage, and the bias voltage of the common-source differential pair of the auxiliary power amplifier is provided by the third inductor L. i3 The center tap connection provides an adaptive bias circuit.

[0031] The third transistor (M3) and the fourth transistor (M4) form a common-gate differential amplifier pair. Their gates are interconnected to receive the DC bias voltage of the common-gate differential pair (provided by the external power supply voltage); their drains are interconnected to serve as the differential output port.

[0032] The drain of the first transistor (M1) is connected to the source of the third transistor (M3); the drain of the second transistor (M2) is connected to the source of the fourth transistor (M4).

[0033] The first capacitor (C1) is connected between the drain of the first transistor (M1) and the gate of the second transistor (M2); the second capacitor (C2) is connected between the drain of the second transistor (M2) and the gate of the first transistor (M1); the third capacitor (C3) is connected between the drain of the second transistor (M2) and the drain of the third transistor (M3); and the fourth capacitor (C4) is connected between the drain of the first transistor (M1) and the drain of the fourth transistor (M4).

[0034] The first to fourth capacitors (C1, C2, C3, C4) together form a cross-coupled feedback network to improve the gain and stability of the circuit.

[0035] In addition, the common-source differential pair of the main power amplifier is biased in Class AB to balance linearity and efficiency, while the common-source differential pair of the auxiliary power amplifier is connected to an adaptive bias to improve back-off efficiency. The auxiliary power amplifier has the same bias voltage as the main power amplifier after being turned on.

[0036] In one alternative embodiment, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all NMOS transistors.

[0037] In one alternative embodiment, the integrated load modulation output matching network includes a second three-coil transformer, the second three-coil transformer being formed by a first inductor L. o1 Second inductor L o2 With the third inductor L o3 Magnetic coupling in three-dimensional space constitutes the first inductor L; o1 The two ends of the first inductor are connected to the differential output port of the main power amplifier; the second inductor L o2 The two ends of the inductor are respectively connected to the differential output port of the auxiliary power amplifier; the third inductor L o3 One end of the inductor is used to output the radio frequency output signal, and the other end is grounded; the first inductor L o1 The center tap is connected to the power supply voltage, and the second inductor L o2 The center tap is connected to the power supply voltage.

[0038] Specifically, refer to Figure 3 The integrated load modulation output matching network is implemented based on a three-coil transformer (the second three-coil transformer). The second three-coil transformer consists of a first inductor (L... o1 ), second inductor (L o2 ) and the third inductor (L o3 It is constructed using a three-dimensional magnetic coupling method. The first inductor (L...)o1 The first primary winding is connected at both ends to the differential output ports of the main power amplifier; the second inductor (L...) o2 ) as the second primary winding, and the first inductor (L) o1 There is a coupling coefficient k between them. o12 Its two ends are connected to the differential output port of the auxiliary power amplifier; the third inductor (L o3 As a secondary winding, through the coupling coefficient k o13 With L o1 Coupled, and through the coupling coefficient k o23 With L o2 The coupling is such that its output is connected to the system load (outputting the RF signal), and the other end is grounded. The DC power supplies for the main power amplifier and the auxiliary power amplifier can be respectively supplied through the first inductor (L...). o1 ) and the second inductor (L o2 The center tap or corresponding node provides this.

[0039] During operation, the first amplified signal output by the main power amplifier and the second amplified signal output by the auxiliary power amplifier are respectively injected into the first inductor (L). o1 ) and second inductor (L o2 Through three sets of coupling coefficients (k) o12 k o13 k o23 Through precise design, this integrated load modulation output matching network achieves power combining and efficient output of two signals. When the auxiliary power amplifier is off, the network can modulate the load impedance of the main power amplifier, enabling it to maintain high efficiency in both high-power and backoff states. Simultaneously, the entire integrated load modulation output matching network structure completes the three core functions of load modulation, impedance transformation, and power combining within a single magnetic component.

[0040] The integrated load modulation output matching network of this embodiment saves a significant amount of area compared to the traditional discrete matching structure: the chip area is reduced by about 60% compared to the aforementioned traditional output matching scheme one; and the area is also reduced by about 50% compared to the aforementioned traditional output matching scheme two.

[0041] at last, Figure 6 The figure shows the S-parameter simulation diagram of the Doherty power amplifier in this embodiment. As shown in the figure, the gain of the filter power amplifier in this embodiment exceeds 15dB in the frequency range of 22GHz to 35.2GHz, and the highest gain reaches 18.2dB. Figure 7The diagram illustrates the simulation results of the output power-power-added efficiency of the Doherty power amplifier in this embodiment. As shown, this embodiment achieves a saturated output power of 21.92 dBm, a saturated power-added efficiency of 28.55%, and a 6 dB back-off power-added efficiency of 19.12% at 26 GHz; a saturated output power of 22.70 dBm, a saturated power-added efficiency of 28.91%, and a 6 dB back-off power-added efficiency of 21.02% at 27 GHz; a saturated output power of 22.71 dBm, a saturated power-added efficiency of 30.04%, and a 6 dB back-off power-added efficiency of 20.85% at 28 GHz; and a saturated output power of 22.22 dBm, a saturated power-added efficiency of 28.20%, and a 6 dB back-off power-added efficiency of 19.11% at 29 GHz.

[0042] The ultra-compact parallel Doherty power amplifier based on a three-coil transformer in this embodiment has the following advantages: 1. Achieve ultimate compactness and deep integration of the output network: By integrating the load modulation output matching network and using a multi-coil transformer, the functions of load modulation, impedance transformation and power synthesis are deeply integrated, fundamentally eliminating the area waste caused by multiple discrete transformers and components, and achieving a breakthrough reduction in the output side area.

[0043] 2. Overcoming the design limitations of parasitic capacitance absorption, improving compatibility and performance: The integrated load modulation output matching network can effectively absorb or cancel the parasitic capacitance of the transistor output. This eliminates the stringent constraint of "parasitic capacitance ≤ impedance inverter capacitance" in existing solutions, thereby improving the compatibility and design freedom of the solution with different semiconductor processes and various power amplifier architectures.

[0044] 3. Achieve multi-functional integration and area minimization of the input network: The integrated phase-compensated input matching network organically integrates necessary functions such as power distribution, accurate phase compensation, single-ended to differential conversion, and input impedance matching into a shared passive physical structure, thereby significantly reducing the total chip area occupied by the input network.

[0045] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0046] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0047] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0048] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An ultra-compact parallel Doherty power amplifier based on a three-coil transformer, characterized in that, It includes an integrated phase-compensated input matching network, a main power amplifier, an auxiliary power amplifier, and an integrated load modulation output matching network; both the integrated phase-compensated input matching network and the integrated load modulation output matching network contain multi-coil transformers; The integrated phase-compensated input matching network is used to perform differential conversion, power distribution, phase compensation and impedance transformation on the input RF input signal, and output the main power amplifier input signal and the auxiliary power amplifier input signal. The main power amplifier and the auxiliary power amplifier are connected to the output of the integrated phase compensation input matching network. The main power amplifier processes the input signal of the main power amplifier and outputs a first amplified signal. The auxiliary power amplifier processes the input signal of the auxiliary power amplifier and outputs a second amplified signal. The integrated load modulation output matching network is connected to the output of the main power amplifier and the output of the auxiliary power amplifier, and is used to perform load modulation and impedance transformation processing on the first amplified signal and the second amplified signal to output a radio frequency output signal.

2. The ultra-compact parallel Doherty power amplifier based on a three-coil transformer according to claim 1, characterized in that, The integrated phase compensation input matching network includes a first three-coil transformer and an adaptive bias circuit; the first three-coil transformer consists of a first inductor L. i1 Second inductor L i2 With the third inductor L i3 Magnetic coupling is formed in three-dimensional space; The first inductor L i1 One end of the inductor is used to receive the radio frequency input signal, and the other end is grounded; the second inductor L i2 Both ends of the third inductor L are connected to the differential input port of the main power amplifier, and its center tap is connected to the DC bias voltage; i3 Both ends are connected to the differential input port of the auxiliary power amplifier; The input terminal of the adaptive bias circuit is used to receive the radio frequency input signal, and the output terminal is connected to the third inductor L. i3 The center tap.

3. The ultra-compact parallel Doherty power amplifier based on a three-coil transformer according to claim 1, characterized in that, The integrated load modulation output matching network includes a second three-coil transformer, which is composed of a first inductor L. o1 Second inductor L o2 With the third inductor L o3 Magnetic coupling is formed in three-dimensional space; The first inductor L o1 The two ends of the second inductor L are respectively connected to the differential output port of the main power amplifier; o2 The two ends of the third inductor L are respectively connected to the differential output port of the auxiliary power amplifier; o3 One end is used to output the radio frequency output signal, and the other end is grounded; The first inductor L o1 The center tap is connected to the power supply voltage, and the second inductor L o2 The center tap is connected to the power supply voltage.

4. The ultra-compact parallel Doherty power amplifier based on a three-coil transformer according to claim 1, characterized in that, Both the main power amplifier and the auxiliary power amplifier adopt a differential common source common gate structure and use transistors of the same size.

5. The ultra-compact parallel Doherty power amplifier based on a three-coil transformer according to claim 4, characterized in that, The differential common source common gate structure includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The gates of the first transistor M1 and the second transistor M2 are interconnected to serve as a differential input port, and the sources of the first transistor M1 and the second transistor M2 are interconnected and grounded. The gates of the third transistor M3 and the fourth transistor M4 are interconnected and connected to a DC bias voltage; the drains of the third transistor M3 and the fourth transistor M4 are interconnected to serve as a differential output port. The drain of the first transistor M1 is connected to the source of the third transistor M3; the drain of the second transistor M2 is connected to the source of the fourth transistor M4. The first capacitor C1 is connected between the drain of the first transistor M1 and the gate of the second transistor M2; the second capacitor C2 is connected between the drain of the second transistor M2 and the gate of the first transistor M1; the third capacitor C3 is connected between the drain of the second transistor M2 and the drain of the third transistor M3; and the fourth capacitor C4 is connected between the drain of the first transistor M1 and the drain of the fourth transistor M4.

6. The ultra-compact parallel Doherty power amplifier based on a three-coil transformer according to claim 5, characterized in that, The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all NMOS transistors.

7. The ultra-compact parallel Doherty power amplifier based on a three-coil transformer according to claim 2, characterized in that, The adaptive bias circuit includes a fifth transistor M5, a sixth transistor M6, a DC blocking capacitor C5, and a first bias voltage V. th Second bias voltage V D1 Third bias voltage V G1 And the first bias resistor R1, the second bias resistor R2, and the third bias resistor R3; One end of the DC blocking capacitor C5 is used to receive the radio frequency input signal, and the other end is connected to the gate of the fifth transistor M5; The source of the fifth transistor M5 is grounded, and its drain is connected to the gate of the sixth transistor M6. The source of the sixth transistor M6 is grounded, and its drain is used as the output terminal of the adaptive bias circuit. The first bias voltage V th The first bias resistor R1 is connected to the gate of the fifth transistor M5; The second bias voltage V D1 The second bias resistor R2 is connected to the gate of the sixth transistor M6; The third bias voltage V G1 The third bias resistor R3 is connected to the output of the adaptive bias circuit.

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