Stress-resistant semiconductor device and level shifter

Abstract

A stress resistant semiconductor device, a level shifter including the stress resistant semiconductor device, and a power switch controlled by the level shifter are provided. A stress resistant semiconductor device includes a source terminal, a gate terminal, a gate control terminal, and a drain terminal. The first transistor has a source connected to the source terminal, a gate connected to the gate terminal, and a drain. The second transistor has a source connected to the drain of the first transistor, a gate connected to the gate control terminal, and a drain. A third transistor has a source connected to the drain of the second transistor, a drain connected to the drain terminal, and a gate. The fourth transistor has a drain connected to the gate control terminal, a gate connected to the drain terminal, and a source. The fifth transistor includes a source connected to the source of the fourth transistor, a gate connected to the gate control terminal, and a drain connected to the drain terminal. The conductivity type of the first transistor, the second transistor, and the third transistor is opposite to the conductivity type of the fourth transistor and the fifth transistor.

Description

Technical Field

[0001] This disclosure relates to stress-resistant semiconductor devices and level shifters. More specifically, but not exclusively, this disclosure relates to stress-resistant MOS devices and stress-resistant level shifters including said devices. Background Technology

[0002] Semiconductor processes used in the digital domain have been scaled down to meet high-speed and low-power requirements. The supply voltage (VDD) and voltage tolerance of such devices have been correspondingly reduced. However, for legacy and compatibility reasons, today's system-on-a-chip (SoC) designs still need to support voltage (nVDD) interfaces that are higher than the voltages supported by the manufacturing process. For reliability (lifespan) considerations, designs for analog control should be stress-resistant when using standard VDD digital processes. As an example, 1.8V input / output (I / O) devices are widely used, while higher voltage interfaces such as 3V / 5V are important for some applications.

[0003] Level shifters are used to intersect and control different voltage domains, and as a critical building block, they must balance reliability, compatibility, flexibility, and performance. Complex systems may require hundreds of level shifters, making die size and leakage current important.

[0004] While stress-resistant level shifters are available, all of them support a mode where a logic "0" signal is transitioned from GND to (n-1)VDD and a logic "1" signal is transitioned from VDD to nVDD. However, none of them support a mode where a logic "0" signal is transitioned from GND to GND and a logic "1" signal is transitioned from VDD to nVDD. ADC bootstrap switches are an important family, but they require clock control and differ from this disclosure in both mechanism level and application. Summary of the Invention

[0005] The features of the invention are set forth in the appended claims.

[0006] According to a first aspect, a stress-resistant semiconductor device is provided, comprising: a source terminal, a gate terminal, a gate control terminal, and a drain terminal; a first transistor having a source terminal connected to the source terminal of the stress-resistant device, a gate terminal connected to the gate terminal of the stress-resistant device, and a drain terminal; a second transistor having a source terminal connected to the drain terminal of the first transistor, a gate terminal connected to the gate control terminal of the stress-resistant device, and a drain terminal; a third transistor having a source terminal connected to the drain terminal of the second transistor, a drain terminal connected to the drain terminal of the stress-resistant device, and a gate terminal; a fourth transistor having a drain terminal connected to the gate control terminal of the stress-resistant device, a gate terminal connected to the drain terminal of the stress-resistant device, and a source terminal; and a fifth transistor comprising a source terminal connected to the source terminal of the fourth transistor, a gate terminal connected to the gate control terminal of the stress-resistant device, and a drain terminal connected to the drain terminal of the stress-resistant device; wherein the conductivity types of the first transistor, the second transistor, and the third transistor are opposite to the conductivity types of the fourth transistor and the fifth transistor.

[0007] In some embodiments, the first, second, and third transistors of the stress-resistant device are PMOS transistors, and the fourth and fifth transistors of the stress-resistant device are NMOS transistors.

[0008] In some embodiments, the first, second, and third transistors of the stress-resistant device are NMOS transistors, and the fourth and fifth transistors of the stress-resistant device are PMOS transistors.

[0009] According to a second aspect of the invention, a level shifter is provided, comprising at least one stress-resistant semiconductor device according to the first aspect as defined above.

[0010] In some embodiments, the level shifter may include: two input nodes; two first output nodes; two second output nodes; a first pair of cross-coupled semiconductor devices, each having a source terminal coupled to a high-voltage supply line, a drain terminal coupled to a corresponding one of the two first output nodes, and a gate terminal coupled to a corresponding other of the two first output nodes; a second pair of semiconductor devices, each having a source terminal coupled to a corresponding one of the two first output nodes, a gate terminal coupled to a gate terminal of the other of the second pair of semiconductor devices, and a drain terminal coupled to a corresponding one of the two second output nodes; and a third pair of semiconductor devices, each having a drain terminal coupled to a corresponding one of the two second output nodes, a source terminal coupled to a reference potential, and a gate terminal coupled to a corresponding one of the two input nodes; wherein each of the second pair of semiconductor devices and each of the third pair of semiconductor devices includes a stress-resistant device according to the first aspect defined above.

[0011] In some embodiments, the level shifter may include: two input nodes; two first output nodes; two second output nodes; a first pair of cross-coupled semiconductor devices, each having a source terminal coupled to a high voltage supply, a drain terminal coupled to a corresponding one of the two first output nodes, and a gate terminal coupled to a corresponding other of the two first output nodes; a second pair of semiconductor devices, each having a source terminal coupled to a corresponding one of the two first output nodes, and a drain terminal coupled to a corresponding one of the two second output nodes; and a third pair of semiconductor devices, each having a drain terminal coupled to a corresponding one of the two second output nodes, a source terminal coupled to a reference potential, and a gate terminal coupled to a corresponding one of the two input nodes; wherein each of the second pair of semiconductor devices and each of the third pair of semiconductor devices includes at least one stress-resistant device according to the first aspect defined above.

[0012] In some embodiments, each of the second pair of semiconductor devices includes a plurality of stress-resistant devices according to the first aspect.

[0013] In some embodiments, the drain terminal of each of the second pair of semiconductor devices is provided by the drain terminal of the first of the respective plurality of stress-resistant devices; the drain terminal of each of the respective plurality of stress-resistant devices is coupled to the source terminal of the respective preceding one of the respective plurality of stress-resistant devices; and the source terminal of each of the second pair of semiconductor devices is provided by the source terminal of the last of the respective plurality of stress-resistant devices.

[0014] In some embodiments, the gate terminal of each of the at least one stress-resistant device in each of the second pair of semiconductor devices is coupled to the gate control terminal of the corresponding stress-resistant device.

[0015] In some embodiments, the gate terminal of each of the at least one stress-resistant device in one of the second pair of semiconductor devices is coupled to the gate terminal of the corresponding stress-resistant device in the other of the second pair of semiconductor devices.

[0016] In some embodiments, the first transistor, the second transistor, and the third transistor of each stress-resistant device of the second pair of semiconductor devices are PMOS transistors, and the fourth transistor and the fifth transistor of each stress-resistant device of the second pair of semiconductor devices are NMOS transistors.

[0017] In some embodiments, the first transistor, the second transistor, and the third transistor of each of the stress-resistant devices of the third pair of semiconductor devices are NMOS transistors, and the fourth transistor and the fifth transistor of each of the stress-resistant devices are PMOS transistors.

[0018] In some embodiments, each of the first pair of semiconductor devices includes a stress-resistant device according to a first aspect as defined above.

[0019] In some embodiments, the first transistor, the second transistor, and the third transistor of each stress-resistant device of the first pair of semiconductor devices are PMOS transistors, and the fourth transistor and the fifth transistor of each stress-resistant device of the first pair of semiconductor devices are NMOS transistors.

[0020] In some embodiments, each of the first pair of semiconductor devices is a PMOS transistor.

[0021] In some embodiments, the level shifter further includes at least one output coupled to a corresponding one of the two first output nodes or a corresponding one of the two second output nodes.

[0022] In some embodiments, the level shifter further includes: an input circuit coupled between a low-voltage supply and a reference potential, configured to receive a first input signal having a first state of a potential corresponding to the reference potential and a second state of a potential corresponding to the low-voltage supply line, and to generate a second input signal having a corresponding first state of a potential corresponding to the low-voltage supply and a corresponding second state of a potential corresponding to the reference potential; wherein one of the two input nodes is arranged to receive the first input signal, and the other of the two input nodes is configured to receive the second input signal.

[0023] In some embodiments, the level shifter further includes control circuitry for generating one or more control voltages, wherein a respective gate control terminal of each of the stress-resistant semiconductor devices is arranged to receive one or more of the control voltages.

[0024] In some embodiments, the level shifter further includes a multiplexer arranged to receive the one or more control voltages and output a corresponding selected one of the one or more control voltages to the corresponding gate control terminal of each of the stress-resistant semiconductor devices.

[0025] In some embodiments, the gate control terminal of each of the first pair of semiconductor devices is arranged to receive a voltage corresponding to the difference between the voltage of the high voltage supply and the voltage of the low voltage supply.

[0026] In some embodiments, the gate control terminal of each of the first pair of semiconductor devices is arranged to receive a voltage corresponding to half the voltage of the high voltage supply.

[0027] In some embodiments, the respective gate control terminal of each of the third pair of semiconductor devices is arranged to receive a voltage corresponding to the low voltage supply.

[0028] In some embodiments, each of the second pair of semiconductor devices includes a plurality of stress-resistant devices according to the first aspect, wherein the gate control terminal of the first of the plurality of stress-resistant devices is arranged to receive a voltage corresponding to a low voltage supply; and / or the gate control terminal of the last of the plurality of stress-resistant devices is arranged to receive a voltage corresponding to the difference between a high voltage supply and a low voltage supply. In some embodiments, a respective gate control terminal of each of the second pair of semiconductor devices and / or the third pair of semiconductor devices is arranged to receive a voltage corresponding to the low voltage supply.

[0029] In some embodiments, the level shifter further includes a respective gate control terminal of each of a first pair of semiconductor devices and / or at least one gate control terminal of each of a second pair of semiconductor devices coupled to a reference potential, and / or wherein a respective gate control terminal of a third pair of semiconductor devices and / or each of a third pair of semiconductor devices is arranged to receive a voltage corresponding to the low voltage supply.

[0030] According to a third aspect of this disclosure, a power switch is provided, comprising: an NMOS power transistor; and a level shifter according to the second aspect as defined above; wherein the gate of the power transistor is coupled to one of two second output nodes. Attached Figure Description

[0031] A more complete understanding of the subject matter can be obtained by referring to the specific embodiments and claims considered in conjunction with the following figures, wherein the same reference numerals refer to similar elements throughout the figures.

[0032] Figure 1 An exemplary level shifter is schematically shown;

[0033] Figure 2 Another exemplary level shifter is illustrated schematically;

[0034] Figure 3 A stress-resistant NMOS semiconductor device is schematically illustrated according to an exemplary embodiment of the present disclosure;

[0035] Figure 4 A stress-resistant PMOS semiconductor device is schematically illustrated according to an exemplary embodiment of the present disclosure;

[0036] Figure 5 A level shifter according to an exemplary embodiment of the present disclosure is schematically illustrated;

[0037] Figure 6 A level shifter according to another exemplary embodiment of the present disclosure is schematically illustrated;

[0038] Figure 7 A level shifter according to yet another exemplary embodiment of the present disclosure is schematically illustrated; and

[0039] Figure 8 The illustration schematically depicts an exemplary embodiment of the present disclosure. Figure 5 , 6 Or a power switch controlled by a level shifter in any of the diagrams in 7. Detailed Implementation

[0040] The following detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the terms "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or illustrative should not necessarily be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any express or implied theory present in the foregoing technical field, background art, or the detailed description below.

[0041] Figure 1An exemplary level shifter 100 is shown for understanding this disclosure, used to level-shift an input signal IN_VDD from a low-voltage (VDD) domain to an output signal OUT1_nVDD in a high-voltage (nVDD) domain. The level shift is implemented via a block LS_CORE in the high-voltage (nVDD) domain. The supply voltage in the low-voltage (VDD) domain has a value VDD. The supply voltage in the high-voltage (nVDD) domain has a value nVDD = n*VDD. The input signal IN_VDD has a logic "0" value of 0 (i.e., ground GND or reference potential) and a logic "1" value of VDD, while the output signal OUT1_VDD of the level shifter 100 has a logic "0" value of m*VDD + Δ and a logic "1" value of nVDD, where Δ represents the permissible variation of the supply voltage. In this prior art example, n > m, n ≥ 2, and nm ≥ 1. The mode control block is used to control the operating mode of the level shifter 100, such as power-on reset (POR) mode, isolation (ISO) mode, voltage clamping mode, etc.

[0042] It should be noted that "VDD" and "nVDD" represent specified voltages for the low and high voltage domains, respectively, rather than actual voltages.

[0043] Figure 2 Show as Figure 1Another level shifter 200 is an example of the block LS_CORE. In this example, the high voltage nVDD is taken as 2VDD, i.e., 2*VDD. Level shifter 200 includes a first pair of cross-coupled PMOS transistors P1, P2, each having a source connected to the high voltage supply line 2VDD, a drain connected to a corresponding one of the two output nodes OUT1B, OUT1, and a gate connected to the other of the two first output nodes OUT1, OUT1B. Level shifter 200 further includes a second pair of PMOS transistors P3, P4, each having a source connected to a corresponding one of the two first output nodes OUT1, OUT1B, and a gate connected to the other of the second pair of PMOS transistors P3, P4 and connected to the gate of the control voltage VCG2. The drain of each of the second pair of PMOS transistors P3, P4 is coupled to the corresponding additional output node OUT2B, OUT2 via a corresponding diode. The level shifter 200 further includes a first pair of NMOS transistors N3 and N4, each having a drain coupled to a corresponding one of the two additional output nodes OUT2B and OUT2 via a corresponding additional diode, and a gate connected to the other of the first pair of NMOS transistors N3 and N4 and connected to the gate of the control voltage VCG1. The level shifter 200 further includes a second pair of NMOS transistors N1 and N2, each having a drain connected to the source of a corresponding one of the first pair of NMOS transistors N3 and N4, a source connected to ground GND, and a gate coupled to a corresponding one of the two input nodes IN and INB.

[0044] The level shifter 200 further includes input circuitry comprising a PMOS transistor P5 and an NMOS transistor N5. The PMOS transistor P5 has a source coupled to a low-voltage supply line VDD, a gate coupled to receive an input signal from a first input node IN, and a drain coupled to a second input node INB. The NMOS transistor N5 has a drain coupled to the second input node INB, a source coupled to ground GND, and a gate coupled to receive an input signal from the first input node IN.

[0045] In the first state (e.g., logic level "0"), the first input node IN is at ground GND, and the second input node is therefore at a low supply voltage VDD. Thus, NMOS transistors N2 and N4 are turned on. PMOS transistor P4 acts as a voltage clamp, such that the voltage at the first output node OUT1 is VCG2+|VTH_P|. The first output node OUT1 is connected to the gate of PMOS transistor P1, so transistor P1 is turned on, and therefore the drain of transistor P1 (and thus at the other output node OUT1B) is pulled up to a high supply voltage 2VDD.

[0046] In the second state (e.g., logic level "1"), the first input node IN is at a low supply voltage potential VDD, and the second input node is therefore at ground potential GND. Thus, NMOS transistors N1 and N3 are turned on. PMOS transistor P3 acts as a voltage clamp, such that the voltage at the second output node OUT1B is VCG2+|VTH_P|. The second output node OUT1B is connected to the gate of PMOS transistor P2, so transistor P2 is turned on, and the drain of transistor P2 (and therefore at the first output node OUT1) is pulled up to a high supply voltage potential 2VDD.

[0047] Figure 2 The level shifter 200 shown has some limitations. For a specified value of VDD, the actual voltage VDD is allowed to vary by up to 10%. Therefore, for a nominal "VDD" of 1.8V, the actual voltage VDD will have a value in the range of 1.71V to 1.98V, while for a nominal "2VDD" of 3.0V or 3.3V, the actual voltage 2VDD will be in the range of 2.7V to 3.63V. Considering the "worst-case" PVT (stress, voltage, temperature) conditions, i.e., small voltage differences (e.g., VDD = 1.98V, 2VDD = 2.7V), SS corners, and cold temperatures, the pull-up capability of the PMOS transistors in the LS_CORE 110, 200 is extremely weak. Therefore, the level shifter may fail itself (note that the PMOS transistors require a threshold voltage Vth_P to operate) or the switching time may be extremely long. Alternatively, if level shifter 200 is used to control an external PMOS transistor, the external PMOS transistor may fail to turn on. This is because the selected PMOS transistor requires an additional VTH_P (PMOS threshold voltage) to turn on, and the worst-case value of 2VDD-VDD is 2.7-1.98 = 0.72V, which is insufficient to meet the two VTH_P requirements. Therefore, under certain conditions, level shifter 200 has been found to malfunction (i.e., voltage conversion function failure) or fail to control the external PMOS device.

[0048] To overcome the aforementioned problems, a low threshold voltage device could be considered for use in the level shifter 200. However, under conditions of large voltage differences (e.g., VDD = 1.71V, 2VDD = 3.63V), FF corners, and high temperatures, the level shifter 200 will experience high leakage current, which is undesirable in low-power designs.

[0049] Another issue is that, in order to reduce design costs, the design should be reusable in a wide range of applications. This is important because level shifters can be critical control components, and some products may contain many level shifters. However, level shifter 200 only supports large voltage differences and can only support VDD to nVDD cases where n>1. That is, level shifter 200 cannot be used in designs where n=1, such as designs with "VDD=2VDD in the range of 1.71 to 1.98V".

[0050] Finally, level shifter 200 only supports the mode where logic "0" is transitioned from GND to VDD and logic "1" is transitioned from VDD to 2VDD. Level shifter 200 cannot support the mode where logic "0" is transitioned from GND to GND and logic "1" is transitioned from VDD to 2VDD, as will be explained. Considering voltage VCG2, it is necessary to balance device voltage tolerance and design functional / performance requirements. If VCG2 is set such that VCG2 = VDD, then for the level shifter to work, the condition 2*|VTH_P| < VDD - Δ must be satisfied for all PVT (process, voltage, and temperature conditions), which is extremely difficult to guarantee. For this reason, VCG2 must be lower than VDD, for example, VCG = VDD - |VTH_P|. However, if OUT2 = 2VDD, the gate-drain voltage Vgs_P4 of the PMOS transistor P4 will be Vgd_P4 = VDD - |VTH_P| - 2VDD = -(VDD + |VTH_P|), which will damage the PMOS transistor P4. For this reason, a complex "voltage shift" is involved, represented here by a diode rather than a real circuit. Assuming the diode junction voltage is Δ, the voltage range supported by OUT2 and OUT2B is only from GND + Δ to 2VDD - Δ. This voltage range is not useful due to the large leakage current and large on-resistance. Therefore, it can be seen that level shifter 200 can only support the mode where a logic "0" signal transitions from GND to (n-1)VDD and a logic "1" signal transitions from VDD to nVDD. However, level shifter 200 cannot support the mode where a logic "0" signal transitions from GND to GND and a logic "1" signal transitions from VDD to nVDD.

[0051] Figure 3This illustration shows a stress-resistant semiconductor device 300 in the form of a stress-resistant NMOS semiconductor device 300 according to an exemplary embodiment of the present disclosure. The stress-resistant NMOS semiconductor device 300 (hereinafter referred to as a "ST-NMOS device") includes a source terminal S 302, a gate terminal G 304, a gate control terminal CG 306, and a drain terminal D 308. The ST-NMOS device 300 further includes a first transistor 310, a second transistor 312, and a third transistor 314, each in the form of an NMOS transistor. The ST-NMOS device 300 further includes a fourth transistor 316 and a fifth transistor 318, each in the form of a PMOS transistor. That is, the conductivity type (N) of the first transistor 310, the second transistor 312, and the third transistor 314 is opposite to the conductivity type (P) of the fourth transistor 316 and the fifth transistor 318. The first (NMOS) transistor 310 has a source 320 connected to the source terminal S302 of the stress-resistant device 300, a gate 322 connected to the gate terminal G 304 of the ST-NMOS device 300, and a drain 324. The second (NMOS) transistor 312 has a source 326 connected to the drain 324 of the first transistor 310, a gate 328 connected to the gate control terminal CG 306 of the ST-NMOS device 300, and a drain 330. The third (NMOS) transistor 314 has a source 332 and a gate 334 connected to the drain 330 of the second transistor 312, and a drain 336 connected to the drain terminal D 308 of the ST-NMOS device 300. The fourth (PMOS) transistor 316 has a drain 338 connected to the gate control terminal CG 306 of the ST-NMOS device 300, a gate 340 connected to the drain terminal D 308 of the ST-NMOS device 300, and a source 342. The fifth transistor 318 has a source 344 connected to the source 342 of the fourth transistor 316, a gate 346 connected to the gate control terminal CG 306 of the ST-NMOS device 300, and a drain 348 connected to the drain terminal D 308 of the ST-NMOS device.

[0052] As Figure 3 The example of the operation of the ST-NMOS device 300 shown herein considers the case where the gate (G) terminal 304 of the ST-NMOS device 300 receives an input signal from the low voltage (VDD) domain and the gate control (CG) terminal 306 is connected to the low voltage supply line VDD.

[0053] If the drain terminal D 308 is connected to a low voltage (i.e., less than or equal to VDD), each of the first through fifth transistors 310, 312, 314, 316, and 318 is safe. The fourth (PMOS) transistor 316 receives the voltage VDD at its gate 340 and is therefore turned on. The second (NMOS) transistors 312 and 314 are also turned on and therefore shorted to the drain (D) terminal 308. In this scenario, the second (NMOS) transistors 312 and 314 act as clamps, and their only effect is to waste 2*Vdsat of the voltage margin (i.e., 2*drain-source voltage at saturation). Therefore, the ST-NMOS device 300 can be used to replace normal NMOS transistors in conventional design circuits to achieve a design that withstands voltage stress, but with a reduction in the 2*Vdsat voltage margin. However, the reduction in the 2*Vdsat margin is negligible compared to the advantage of improved voltage stress.

[0054] Now consider the ST-NMOS device 300 when the drain terminal D 308 is connected to a high voltage (i.e., a voltage higher than VDD). For example, we will consider the drain terminal D 308 connected to voltage 2VDD. The fifth (PMOS) transistor 318 then turns on, with its gate 346 at voltage VDD and its drain 348 at voltage 2VDD. Therefore, the third (NMOS) transistor 314 connects both its gate 334 and drain 336 to voltage 2VDD, effectively forming a diode configuration. The source 332 of the third (NMOS) transistor 314 is thus at 2VDD-|VTH_N|. Meanwhile, the gate 340 of the fourth (PMOS) transistor 316 is at voltage 2VDD and is off. The source 326 of the second (NMOS) transistor 312 is clamped at VDD-|VTH_N|. The result is that the Vds of the second (NMOS) transistor 312 is 2VDD - |VTH_N| - (VDD - |VTH_N|) = VDD, and therefore within the safe range. All other transistors also remain at safe voltages.

[0055] Therefore, in voltage stress design, the ST-NMOS device 300 can be used to replace a normal NMOS transistor without considering stress risks. Figure 3 In the schematic diagram of the ST-NMOS device 300, on the right side, the symbol for the ST-NMOS device 300 described above is shown, where the terminals labeled D, CG, G, and S correspond to the drain (D) terminal 308, gate control (CG) terminal 306, gate (G) terminal 304, and source (S) terminal 302 of the ST-NMOS device 300, respectively. This symbol will be... Figures 5 to 7 The term is used to indicate ST-NMOS device 300.

[0056] For clarity, Figure 3 The body electrode of the transistor is not shown. The body electrode connection can be determined on a case-by-case basis, taking into account process and design goals. For this reason, the body terminal is not included in the ST-NMOS symbol.

[0057] Figure 4 Another stress-resistant semiconductor device 400 in the form of a stress-resistant PMOS semiconductor device 400 according to an exemplary embodiment of the present disclosure is shown. The stress-resistant PMOS semiconductor device 400 (hereinafter referred to as "ST-PMOS device") includes a source terminal S 402, a gate terminal G 404, a gate control terminal CG 406, and a drain terminal D 408. The ST-PMOS device 400 further includes a first transistor 410, a second transistor 412, and a third transistor 414, each in the form of a PMOS transistor. The ST-PMOS device 400 further includes a fourth transistor 416 and a fifth transistor 418, each in the form of an NMOS transistor. That is, the conductivity type (P) of the first transistor 410, the second transistor 412, and the third transistor 414 is opposite to the conductivity type (N) of the fourth transistor 416 and the fifth transistor 418. The first (PMOS) transistor 410 has a source 420 connected to the source terminal S402 of the stress-resistant device 400, a gate 422 connected to the gate terminal G 404 of the ST-PMOS device 400, and a drain 424. The second (PMOS) transistor 412 has a source 426 connected to the drain 424 of the first transistor 410, a gate 428 connected to the gate control terminal CG 406 of the ST-PMOS device 400, and a drain 430. The third (PMOS) transistor 414 has a source 432 and a gate 434 connected to the drain 430 of the second transistor 412, and a drain 436 connected to the drain terminal D 408 of the ST-PMOS device 400. The fourth (NMOS) transistor 416 has a drain 438 connected to the gate control terminal CG 406 of the ST-PMOS device 400, a gate 440 connected to the drain terminal D 408 of the ST-PMOS device 400, and a source 442. The fifth transistor 418 has a source 444 connected to the source 442 of the fourth transistor 416, a gate 446 connected to the gate control terminal CG 406 of the ST-PMOS device 400, and a drain 448 connected to the drain terminal D 408 of the ST-PMOS device.

[0058] As discussed above regarding the corresponding ST-NMOS device 300, the ST-PMOS device 400 can be similarly used to replace a normal PMOS transistor without considering stress risks. Figure 4In the schematic diagram of the ST-PMOS device 400, on the right side, the symbol for the ST-PMOS device 400 described above is shown, where the terminals labeled D, CG, G, and S correspond to the drain (D) terminal 408, gate control (CG) terminal 406, gate (G) terminal 404, and source (S) terminal 402 of the ST-PMOS device 400, respectively. This symbol will be... Figure 5 and 6 The term is used to indicate ST-PMOS device 400.

[0059] For clarity, Figure 4 The body electrode of the transistor is not shown. The body electrode connection can be determined on a case-by-case basis, taking into account process and design goals. For this reason, the body terminal is not included in the ST-PMOS symbol.

[0060] Although the following text will refer to Figure 5 and 6 The use of ST-NMOS device 300 and ST-PMOS device 400 is illustrated in the context of stress-resistant level shifters, but it should be understood that the stress-resistant semiconductor devices 300 and 400 described above can be used in any suitable system or application. Each of the stress-resistant semiconductor devices 300 and 400 can be stacked in series as needed to provide tolerance to even higher voltages.

[0061] Figure 5 A level shifter 500 according to an exemplary embodiment of the present disclosure is schematically shown. The level shifter 500 includes a core circuit LS_CORE 510 for level shifting an input signal IN 530 from a low voltage (VDD) domain to a high voltage (nVDD) domain, and a control circuit CG_CTRL 520 for generating gate control voltages VCG1 525, VCG2 526, and VCG3 527 for the core circuit LS_CORE 510. Figure 5 The embodiment shown is illustrated as a VDD to 2VDD level shifter, i.e., n = 2. However, this is merely an example, and those skilled in the art will understand that the level shifter of this disclosure is applicable to other values ​​of n, such as n = 3, n = 4, etc. For completeness, we should also note that n can take any value and is not limited to integer values.

[0062] The control circuit CG_CTRL 520 includes a VCG generator 522 for generating the desired voltage, and a multiplexer 524 for selecting from the voltages generated by the VCG generator 522 for output to the core circuit LS_CORE 510. For example, the voltage provided by the VCG generator 522 may include one or more of the following: “2VDD” / 2, (“2VDD” / 2±Δ1), VDD, VDD±Δ2, GND, and / or other options, where Δ1 and Δ2 represent tolerance windows for the supply voltage. Depending on design requirements, the control voltages VCG1, VCG2, and VCG3 output by the MUX selector 524 may be the same or different from each other. The difference between the low-voltage supply voltage (VDD) and the high-voltage supply voltage (nVDD) determines the selection of each of the control voltages VCG1, VCG2, and VCG3, which may be the same or different from each other.

[0063] The core circuit LS_CORE 510 includes an input section 530 coupled between a low-voltage supply line (VDD) and ground (GND) and comprising two input nodes 532 and 534, a PMOS transistor 536, and an NMOS transistor 538. The first input node 532 is arranged to receive an input signal IN from the low-voltage (VDD) domain, and the second input node 534 is configured to provide a second input signal INB. The PMOS transistor 536 has a source coupled to the low-voltage supply line VDD, a gate coupled to receive the input signal IN from the first input node 532, and a drain coupled to the second input node 534. The NMOS transistor 538 has a drain coupled to the second input node 534, a source coupled to ground GND, and a gate coupled to receive the input signal IN from the first input node 532.

[0064] The first input signal IN has a first state corresponding to the ground potential GND (e.g., logic level "0") and a second state corresponding to the potential of the low voltage supply line VDD (e.g., logic level "1"). The second input signal INB generated at the second input node 534 correspondingly has a corresponding first state corresponding to the potential of the low voltage supply line VDD and a corresponding second state corresponding to the potential of ground GND.

[0065] The core circuit LS_CORE 510 further includes two first output nodes 540 and 542 for outputting two first output signals OUT1 and OUT1B respectively, and two second output nodes 544 and 546 for outputting two second output signals OUT2 and OUT2B respectively.

[0066] The core circuit LS_CORE 510 further includes a first pair of cross-coupled semiconductor devices 550, 552, each in the form of an ST-PMOS device 400; a second pair of semiconductor devices 560, 562, each in the form of an ST-PMOS device 400; and a third pair of semiconductor devices 570, 572, each in the form of an ST-NMOS device 300.

[0067] Each of the first pair of (ST-PMOS) semiconductor devices 550 and 552 has a source terminal (S) connected to a high-voltage supply line 2VDD. The first 550 of the first pair of (ST-PMOS) semiconductor devices 550 and 552 has a drain terminal (D) connected to the first OUT1 540 of the two first output nodes and a gate terminal (G) connected to the other OUT1B 542 of the two first output nodes. The second 552 of the first pair of (ST-PMOS) semiconductor devices 550 and 552 has a drain terminal (D) connected to the second OUT1B 542 of the two first output nodes and a gate terminal (G) connected to the first OUT1 540 of the two first output nodes. The gate control terminal (CG) of each of the first pair of (ST-PMOS) semiconductor devices 550 and 552 is arranged to receive a first control voltage VCG1 525 output by the control circuit CG_CTRL 520.

[0068] Each of the second pair of (ST-PMOS) semiconductor devices 560 and 562 has a gate terminal (G) connected to the gate terminal (G) of the other of the second pair of (ST-PMOS) semiconductor devices 560 and 562. The source terminal (S) of the first 560 of the second pair of (ST-PMOS) semiconductor devices 560 and 562 is connected to the first OUT1 540 of the two first output nodes 540 and 542. The source terminal (S) of the second 562 of the second pair of (ST-PMOS) semiconductor devices 560 and 562 is connected to the second OUT1B 542 of the two first output nodes 540 and 542. The drain terminal (D) of the first 560 of the second pair of (ST-PMOS) semiconductor devices 560 and 562 is connected to the first OUT2 544 of the two second output nodes 544 and 546. The drain terminal (D) of the second 562 of the second pair of (ST-PMOS) semiconductor devices 560 and 562 is connected to the second OUT2B546 of the two second output nodes 544 and 546. The gate control terminal (CG) of each of the second pair of (ST-PMOS) semiconductor devices 560 and 562 is connected to the gate terminal (G) of the corresponding ST-PMOS device 560 or 562 and is arranged to receive the second control voltage VCG2 526 output by the control circuit CG_CTRL 520.

[0069] Each of the third pair of (ST-NMOS) semiconductor devices 570 and 572 has a source terminal (S) connected to ground (GND). The first 570 of the third pair of (ST-NMOS) semiconductor devices 570 has a drain terminal (D) connected to the first OUT2 544 of the two second output nodes 544 and 546 and a gate terminal (G) arranged to receive the second input signal INB 534 from the input section 530. The second 572 of the third pair of (ST-NMOS) semiconductor devices 570 and 572 has a drain terminal (D) connected to the second OUT2B 546 of the two second output nodes 544 and 546 and a gate terminal (G) arranged to receive the first input signal IN 532. The gate control terminal (CG) of each of the third pair of (ST-NMOS) semiconductor devices 570 and 572 is arranged to receive the third control voltage VCG3527 output by the control circuit CG_CTRL 520.

[0070] The level shifter 500 supports dual-mode output. This is in Figure 5 The lower portion illustrates the behavior of the aspect level shifter 500 for the first input signal IN and the second input signal INB at corresponding input nodes 532 and 534, the first output signals OUT1 and OUT1B at corresponding first output nodes 540 and 542, and the second output signals OUT2 and OUT2B at corresponding second output nodes 544 and 546. To support dual-mode output, control voltage VCG1 can be connected to voltage VDD or 2VDD / 2. Control voltages VCG2 and VCG3 can be connected to VDD, but alternatives are possible.

[0071] Subsequently, in the first state, IN = 0 (GND), making INB = VDD. Therefore, the first 570 of the third pair of (ST-NMOS) semiconductor devices is turned on, and the second 572 of the third pair of (ST-NMOS) semiconductor devices is turned off. From the viewpoint of the first pair of (ST-PMOS) semiconductor devices 550, 552, the second pair of (ST-PMOS) semiconductor devices 560, 562 act as voltage clamps. For this reason, the signals at the two first output nodes 540, 542 are given by OUT1 = VCG2 + |VTH - P| and OUTIB = 2VDD, respectively, where |VTH - P| is the threshold voltage of the PMOS transistor. Because the first 570 of the third pair of (ST-NMOS) semiconductor devices is turned on, the signal at the first 544 of the two second output nodes is given by OUT2 = GND + δ ≈ 0, where δ represents a non-ideal factor and is generally sufficiently small to be negligible. Because the second 552 in the first pair (ST_PMOS) semiconductor device and the second 562 in the second pair (ST_PMOS) semiconductor device are turned on, the signal at the second 546 in the two second output nodes is given by OUT2B = 2VDD - δ ≈ 2VDD.

[0072] Similarly, in the second state, IN = VDD, making INB = 0. Therefore, the first 570 in the third pair of (ST_NMOS) semiconductor devices is off, and the second 572 in the third pair of (ST_NMOS) semiconductor devices is on. With the second pair of (ST-PMOS) semiconductor devices 560 and 562 acting as voltage clamps, the signals at the two first output nodes 540 and 542 are given by OUT1 = 2VDD and OUT1B = VCG2 + |VTH_P|, respectively, where |VTH_P| is the threshold voltage of the PMOS transistor. Because the second 572 in the third pair of (ST_NMOS) semiconductor devices is on, the signal at the second 546 in the two second output nodes is given by OUT2B = GND + δ≈0. Because the first 550 in the first pair of (ST_PMOS) semiconductor devices and the first 560 in the second pair of (ST_PMOS) semiconductor devices are on, the signal at the first 544 in the two second output nodes is given by OUT2 = 2VDD - δ≈2VDD.

[0073] therefore, Figure 5 The level shifter 500 supports the following two modes:

[0074] • Mode 1: Logic "0" transitions from GND to (n-1)VDD, and logic "1" transitions from VDD to nVDD; this mode is provided by output signals OUT1 and OUT1B at the two first output nodes 540 and 542; and

[0075] • Mode 2: Logic “0” transitions from GND to GND and logic “1” transitions from VDD to nVDD; this mode is provided by the output signals OUT2 and OUT2B at the two second output nodes 544 and 546.

[0076] By supporting the two different modes given above, the level shifter 500 is able to support different interfaces with a single design.

[0077] Specifically, because each of the semiconductor devices 550, 552, 560, 562, 570, and 572 is provided in the form of a stress-resistant ST-NMOS device 300 or an ST-PMOS device 400, the level shifter 500 is able to support Mode 2 without any risk of voltage stress.

[0078] In addition to providing the dual-mode output described above, the design of level shifter 500 also offers the flexibility to adapt it to other applications. For example, consider an application where a 2VDD interface is not required, i.e., only a VDD interface is needed. To support a 1VDD interface (n=1), control voltages VCG1 and VCG2 are connected to GND, and control voltage VCG3 is connected to VDD. In this case, all semiconductor devices 550, 552, 560, 562, 570, and 572 act as switches, and the level shifter will operate as in a normal design. Therefore, level shifter 500 can also be used to interface between the VDD and 1VDD domains.

[0079] Figure 6 A level shifter 600 according to another exemplary embodiment of the present disclosure is schematically illustrated. The level shifter 600 is related to... Figure 5The same components as those in level shifter 500 are labeled with the same reference numerals. The core circuit LS_CORE 610 of level shifter 600 differs from that of level shifter 500 in that the first pair of cross-coupled semiconductor devices 650, 652 are provided as standard PMOS transistors 650, 652 rather than stress-resistant PMOS semiconductor devices 550, 552. Each of the cross-coupled PMOS transistors 650, 652 has a source connected to the high-voltage supply line 2VDD. The first 650 of the cross-coupled PMOS transistors 650, 652 has a drain connected to the first OUT1 540 of the two first output nodes and a gate connected to the other OUT1B 542 of the two first output nodes. The second 652 of the cross-coupled PMOS transistors 650, 652 has a drain connected to the second OUT1B 542 of the two first output nodes and a gate connected to the first OUT1 540 of the two first output nodes. Figure 6 As shown in the lower part, the level shifter 600 provides with Figure 5 The level shifter 500 has the same dual-mode outputs OUT1, OUT1B, OUT2, and OUT2B. The advantage of the level shifter 500 is that it requires less area. However, the control voltage VCG2 must be carefully controlled to ensure that there is no voltage stress at the first output nodes OUT1 and OUT1B.

[0080] Figure 7 A level shifter 700 according to yet another exemplary embodiment of the present disclosure is schematically illustrated for level shifting from the VDD to the nVDD domain, where n>2. The level shifter 700 is related to... Figure 5 The same components as those in level shifter 500 are labeled with the same reference numerals. The core circuit LS_CORE 710 of level shifter 700 differs from that of level shifter 500 in that the second pair of semiconductor devices 760, 762 are stacked in series with ST-PMOS devices 400 instead of being... Figure 5The second pair of semiconductor devices 760, 762 are provided in the form of individual stress-resistant PMOS semiconductor devices 550, 552. Specifically, each of these devices comprises n stress-resistant PMOS devices 764...765 and 766...767 connected in series between corresponding first output nodes OUT1 540, OUT1B 542 and corresponding second output nodes OUT2 544, OUT2B 546. The drain terminal of each of the second pair of semiconductor devices 760, 762 is provided by the drain terminal (D) of the first 764, 766 in a corresponding plurality or n stack of stress-resistant devices 764...765, 766...767. The drain terminal (D) of each subsequent (or i-th) 765, 767 in the plurality of stress-resistant devices is coupled to the source terminal (S) of the corresponding preceding (or (i-1)-th) 764, 766 in the plurality of stress-resistant devices. The source terminal of each of the second pair of semiconductor devices 760, 762 is provided by the source terminal (S) of the last (or nth) of the corresponding plurality of stress-resistant devices 764...765, 766...767. The gate (G) and gate control (CG) terminals of each ST_PMOS device 764...765 and 766...767 included in the pair of second semiconductor devices 760, 762 are controlled by control circuitry 720. More specifically, the gate terminal (G) of each stress-resistant PMOS device 764...765, 766...767 in each of the second pair of semiconductor devices 760, 762 is coupled to the gate control terminal of the same stress-resistant device 764...765, 766...767. The gate terminal (G) of each of the plurality of stress-resistant PMOS devices 764...765 of one of the second pair of semiconductor devices 760, 762 is coupled to the gate terminal (G) of the corresponding stress-resistant PMOS device 766...767 of the other of the second pair of semiconductor devices 760, 762, and is configured to receive the corresponding gate control voltage VCG2...VCGn from the control circuit 720. Figure 7 The VCG generator 722 and MUX selector 724 of the level shifter 700 are different. Figure 5The VCG generator 522 and MUX selector 524 of the level shifter 500 are characterized in that the VCG generator 522 generates additional control voltages as needed, and the MUX selector outputs an additional control voltage VCGn 726 to the core circuit LS_CORE 710. The control voltages VCG1 / 2 / 3...n are determined based on the voltage difference between the high-voltage supply line nVDD and the low-voltage supply line VDD, and are selected to keep the end-to-end voltage of each transistor (i.e., Vds, Vgd, Vgs) less than one VDD. For example, voltages VCG1 and VCGn can be set to (n-1)VDD (i.e., the difference between the high-voltage supply nVDD and the low-voltage supply VDD), while voltages VCG2 and VCG3 can be set to VDD, i.e., the voltage of the low-voltage supply. For any ST-PMOS device inserted in stack 760 between ST-PMOS devices 764 and 765, or in stack 762 between ST-PMOS devices 766 and 767, the corresponding control voltage VCGx will take values ​​from 2VDD to (n-2)VDD from bottom to top. Figure 7 The lower portion illustrates the behavior of the aspect level shifter 700 for the first input signal IN and the second input signal INB, the first output signals OUT1 and OUT1B at the corresponding first output nodes 540 and 542, and the second output signals OUT2 and OUT2B at the corresponding second output nodes 544 and 546. For input signals having voltages 0 (logic "0") and VDD (logic "1"), the first output signal OUT1 at the first output node 540 has voltages VCGn+|VTH_P| and nVDD, where VCGn is the voltage applied to the control gate (CG) of the last ST-PMOS device 765, 767 in the corresponding stack of the corresponding second semiconductor devices 760, 762 ST-PMOS devices 764...765, 766...767. For the same input signal having voltages 0 (logic "0") and VDD (logic "1"), the second output signal OUT2 has values ​​of 0 and 2VDD, respectively.

[0081] Figure 8 It is shown in the form of a power switch. Figure 5 , 6 Examples of applications include the output signals OUT2 and OUT2B of the dual-mode level shifters 500, 600, and 700. At the MCU level, power switches will be used more and more frequently, and the loading requirements will become increasingly challenging. A key function of power switches is to drive high currents, while the on-resistance should be as small as possible to avoid large IR drops. Additionally, to reduce power consumption, on / off leakage should be minimized. Figure 8The left side shows an exemplary power switch 800 that can be used to understand this disclosure, wherein a signal from the VDD domain is used to control the gate of a PMOS power transistor. When the gate signal is 0, the PMOS switch 800 is on; when the gate signal is VDD, the PMOS switch 800 is off. Die size and leakage (channel leakage and body leakage) may be undesirably large. Figure 8 The right side shows a power switch 900 according to an exemplary embodiment of the present disclosure, wherein a signal from the nVDD domain is used to control the gate of an NMOS power transistor. The NMOS power transistor is coupled between a low-voltage power supply VDD and a load (“SOC loading”). The gate signal can be generated by... Figure 5 Level shifter 500, Figure 6 Level shifter 600 or Figure 7 One of the two second outputs OUT2, OUT2B of the level shifter 700 is provided, and therefore can have a first state corresponding to ground GND and a second state corresponding to the high voltage supply nVDD. For example, the gate signal for the power switch 900 is shown as having states 0V and 2VDD. When the gate signal is 0, the NMOS switch 900 is off. When the gate signal is 2VDD, the NMOS switch 900 is on, and the gate-source voltage Vgs and gate-drain voltage Vgd are both VDD (no voltage stress). Advantageously, for the same size, the PMOS on-resistance Ron_PMOS can be approximately three times that of the NMOS on-resistance Ron_NMOS for the same size. Using one of the second output signals OUT2 or OUT2B to control the NMOS power transistor can therefore be expected to achieve the same performance while saving approximately 2 / 3 of the die area. For the SOI process, although a "sub-selection solution" is used, the die area savings will be extremely significant. The leakage determined by Vbs = -VDD for the NMOS power switch 900 will be lower than the leakage determined by Vbs = 0V for the PMOS power switch 800. Therefore, the level shifter of this disclosure can be used to drive the gate of the NMOS power switch.

[0082] Based on the foregoing, this disclosure provides a level shifter that uses standard VDD digital technology and provides stress-resistant VDD to nVDD conversion with dual-mode output. The design can be used in all processes and with different power combinations. Individual control of the control voltage of the stress-resistant semiconductor device included in the level shifter means that a single design can flexibly support multiple different applications. Compared to other stress-resistant level shifters, the level shifter disclosed herein offers high compatibility, high flexibility, and small size. Because it does not require any clock or other peripherals, the provided solution is a continuous-time level shift controller. Dual-mode output is particularly important for power switching designs.

[0083] Therefore, the level shifters 500, 600, and 700 have been disclosed above. The level shifters 500, 600, and 700 include: two input nodes 532 and 534; two first output nodes 540 and 542; two second output nodes 544 and 546; a first pair of cross-coupled semiconductor devices 550, 552, 650, and 652, each having a source terminal (S) coupled to a high-voltage supply nVDD, a drain terminal (D) coupled to a corresponding one of the two first output nodes 540 and 542, and a gate terminal (G) coupled to the corresponding other one of the two first output nodes 540 and 542; and a second pair of semiconductor devices 560, 562, 760, and 76 ... a corresponding one of the two first output nodes 540 and 542. Each of the first output nodes 540, 542 has a source terminal (S) coupled to a corresponding one of the two second output nodes 544, 546, and each has a drain terminal (D) coupled to a corresponding one of the two second output nodes 544, 546; and a third pair of semiconductor devices 570, 572, each having a drain terminal (D) coupled to a corresponding one of the two second output nodes 544, 546, each having a source terminal (S) coupled to a reference potential GND, and each having a gate terminal (G) coupled to a corresponding one of the two input nodes 532, 534; wherein each of the second pair of semiconductor devices 560, 562, 760, 762 and each of the third pair of semiconductor devices 570, 572 includes at least one stress-resistant device 300, 400 as disclosed above. Figures 5 to 7 In the exemplary embodiments of the level shifters 500, 600, and 700 shown, each of the third pair of semiconductor devices 570 and 572 is provided by a stress-resistant NMOS device 300. Figures 5 to 6 In the exemplary embodiment of the level shifters 500, 600 shown, each of the second pair of semiconductor devices 560, 562 is provided by a stress-resistant PMOS device 400, while Figure 7 In the exemplary embodiment of the level shifter 700 shown, each of the second pair of semiconductor devices 760, 762 is provided by a series-coupled stack 764...765, 766...767 of a stress-resistant PMOS device 400. Figure 5 and 7 In the exemplary embodiment of the level shifters 500, 700 shown, each of the first pair of semiconductor devices 550, 552 is provided by a stress-resistant PMOS device 400, while... Figure 6 In an exemplary embodiment of the level shifter 600 shown, each of the first pair of semiconductor devices 650, 652 is provided by a PMOS transistor.

[0084] It is readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a wide variety of different configurations. Therefore, the foregoing more detailed description of the various embodiments illustrated in the figures is not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. While various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale.

[0085] The invention may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects merely illustrative and not restrictive. Therefore, the scope of the invention is indicated by the appended claims rather than by the detailed description herein. All variations falling within the equivalent meaning and scope of the claims should be included within their scope.

[0086] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable with this invention should be included in or in any single embodiment of the invention. Rather, language relating to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, discussions of features, advantages, and similar language throughout this specification may (but are not necessarily required to) refer to the same embodiment.

[0087] Furthermore, the features, advantages, and characteristics described in this invention can be combined in any suitable manner in one or more embodiments. Those skilled in the art will recognize that, in view of the description herein, this invention can be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be recognized in certain embodiments.

Claims

1. A stress-resistant semiconductor device, characterized in that, The stress-resistant semiconductor device includes: Source terminal, gate terminal, gate control terminal, and drain terminal; A first transistor has a source terminal connected to the source end of the stress-resistant device, a gate terminal connected to the gate end of the stress-resistant device, and a drain terminal; The second transistor has a source connected to the drain of the first transistor, a gate connected to the gate control terminal of the stress-resistant device, and a drain. The third transistor has a source connected to the drain of the second transistor, a drain connected to the drain terminal of the stress-resistant device, and a gate; A fourth transistor having a drain connected to the gate control terminal of the stress-resistant device, a gate connected to the drain terminal of the stress-resistant device, and a source; and The fifth transistor includes a source connected to the source of the fourth transistor, a gate connected to the gate control terminal of the stress-resistant device, and a drain connected to the drain terminal of the stress-resistant device; The conductivity types of the first transistor, the second transistor, and the third transistor are opposite to those of the fourth transistor and the fifth transistor.

2. A level shifter, characterized in that, The level shifter includes at least one stress-resistant semiconductor device according to claim 1.

3. The level shifter according to claim 2, characterized in that, The level shifter includes: Two input nodes; Two first output nodes; Two second output nodes; The first pair of cross-coupled semiconductor devices each have a source terminal coupled to a high voltage supply, a drain terminal coupled to a corresponding one of the two first output nodes, and a gate terminal coupled to the corresponding other one of the two first output nodes. The second pair of semiconductor devices each has a source terminal coupled to a corresponding one of the two first output nodes, and each has a drain terminal coupled to a corresponding one of the two second output nodes; and The third pair of semiconductor devices each has a drain terminal coupled to a corresponding one of the two second output nodes, a source terminal coupled to a reference potential, and a gate terminal coupled to a corresponding one of the two input nodes. Each of the second pair of semiconductor devices and each of the third pair of semiconductor devices includes at least one stress-resistant device according to claim 1.

4. The level shifter according to claim 3, characterized in that, Each of the second pair of semiconductor devices includes a plurality of stress-resistant devices according to claim 1. The drain terminal of each of the second pair of semiconductor devices is provided by the drain terminal of the first of the respective plurality of stress-resistant devices; The drain end of each of the respective plurality of stress-resistant devices is coupled to the source end of the respective preceding stress-resistant device; The source end of each of the second pair of semiconductor devices is provided by the source end of the last of the respective plurality of stress-resistant devices.

5. The level shifter according to claim 3, characterized in that, The level shifter further includes: An input circuit, coupled between a low-voltage supply and a reference potential, is configured to receive a first input signal having a first state corresponding to the reference potential and a second state corresponding to the potential of the low-voltage supply, and to generate a second input signal having a corresponding first state corresponding to the potential of the low-voltage supply and a corresponding second state corresponding to the reference potential. One of the two input nodes is arranged to receive the first input signal, and the other of the two input nodes is configured to receive the second input signal.

6. The level shifter according to claim 3, characterized in that, The device further includes control circuitry for generating one or more control voltages, wherein a respective gate control terminal of each of the stress-resistant semiconductor devices is arranged to receive one of the one or more control voltages.

7. The level shifter according to claim 6, characterized in that, The device further includes a multiplexer arranged to receive the one or more control voltages and output a corresponding selected one of the one or more control voltages to the corresponding gate control terminal of each of the stress-resistant semiconductor devices.

8. The level shifter according to claim 3, characterized in that, The gate control terminal of each of the first pair of semiconductor devices is arranged to receive a voltage corresponding to half of the voltage supplied by the high voltage, and / or The respective gate control terminal of each of the second pair of semiconductor devices and / or the third pair of semiconductor devices is arranged to receive a voltage corresponding to the low voltage supply.

9. The level shifter according to claim 2, characterized in that, The level shifter includes: Two input nodes; Two first output nodes; Two second output nodes; The first pair of cross-coupled semiconductor devices each have a source terminal coupled to a high-voltage supply line, a drain terminal coupled to a corresponding one of the two first output nodes, and a gate terminal coupled to the corresponding other one of the two first output nodes. The second pair of semiconductor devices each has a source terminal coupled to a corresponding one of the two first output nodes, a gate terminal coupled to the gate terminal of the other of the second pair of semiconductor devices, and a drain terminal coupled to a corresponding one of the two second output nodes; and The third pair of semiconductor devices each has a drain terminal coupled to a corresponding one of the two second output nodes, a source terminal coupled to a reference potential, and a gate terminal coupled to a corresponding one of the two input nodes. Each of the second pair of semiconductor devices and each of the third pair of semiconductor devices includes the stress-resistant device according to claim 1.

10. An electric switch, characterized in that, The power switch includes: NMOS power transistors; and The level shifter according to any one of claims 3 or 9, The gate of the power transistor is coupled to one of the two second output nodes.

Images