Fractional phase-locked loop circuit and working method thereof
By using first and second digital time converters with opposite delays on the reference and feedback paths respectively in a fractional phase-locked loop circuit, the problems of high noise and power consumption of digital time converters are solved, and lower average delay and power consumption are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-15
AI Technical Summary
In existing fractional phase-locked loop circuits, the noise and power consumption of the digital time converter increase significantly, mainly because it can only provide unidirectional delay and requires a fixed bias to cover positive and negative phase errors.
The first and second digital time converters respond to different control signals respectively. The first converter performs a positive delay on the reference path and the second converter performs a negative delay on the feedback path, thereby compensating for positive and negative phase errors respectively, so that the range of each converter is half of the phase error and the average delay offset is 0.
The noise and power consumption of the digital time converters were reduced, and lower average latency and energy consumption were achieved by enabling each converter to operate with a delay only when necessary.
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Figure CN122052780A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuits, and more particularly to a fractional phase-locked loop circuit and its operating method. Background Technology
[0002] Fractional phase-locked loop circuits based on digital time converters are high-precision frequency synthesis schemes. The core of the scheme is to compensate for the quantization phase error introduced by the incremental sum modulator through digital time converters, thereby solving the spurious problem of traditional fractional phase-locked loop circuits. It is widely used in scenarios with strict phase noise requirements, such as radio frequency communication and high-speed interfaces.
[0003] Since digital time converters can only provide unidirectional delay, while the quantization phase error introduced by the incremental summation modulator is usually bidirectional, a fixed bias needs to be set to cover the positive and negative phase errors. However, this results in a larger average delay for the digital time converter, which significantly increases the noise and power consumption of the digital time converter. Summary of the Invention
[0004] This invention provides a fractional phase-locked loop circuit and its operating method to reduce the noise and power consumption of a digital time converter.
[0005] According to a first aspect of the present invention, a fractional phase-locked loop circuit is provided, comprising: A modulation module, wherein the modulation module is used to output a first control signal and a second control signal according to the input frequency control signal; A first digital time converter is configured to, in response to the first control signal, acquire a first delayed signal based on a reference clock signal, comprising: if the enable control bit in the first control signal is in a first state, delaying the reference clock signal to form a first delayed signal; and if the enable control bit in the first control signal is in a second state, determining the reference clock signal as the first delayed signal, wherein the first state is the opposite of the second state. The second digital time converter is configured to respond to the first control signal and obtain a second delayed signal based on a feedback clock signal, including: if the enable control bit in the first control signal is in a second state, delaying the feedback clock signal to form a second delayed signal; if the enable control bit in the first control signal is in a first state, determining the feedback clock signal as the second delayed signal. A phase-locked loop module is used to respond to the second control signal and output a feedback clock signal with the same frequency as the reference clock signal based on the phase difference between the first delay signal and the second delay signal.
[0006] Optionally, the first digital time converter includes: The first AND gate is used to perform an AND operation between the enable control bit and the delay control bit, and output the first delay control signal. The first driving unit is used to drive the input reference clock signal and output the first driving clock signal. The first delay unit is used to delay the first drive clock signal according to the first delay control signal, so as to convert the first drive clock signal into an initial first delay signal. A first buffer is used to convert the input initial first delay signal into the first delay signal for output; The second digital time converter includes: The NOT gate is used to perform a NOT operation on the enable control bit and output a disable control bit. The second AND gate is used to perform an AND operation between the disabled control bit and the delay control bit, and output the first delay control signal. The second driving unit is used to drive the input feedback clock signal and output a second driving clock signal. The second delay unit is used to delay the second drive clock signal according to the second delay control signal, so as to convert the second drive clock signal into an initial second delay signal; The second buffer is used to convert the input initial second delay signal into the second delay signal for output.
[0007] Optionally, the delay control bit is a number of bits preceding the enable control bit.
[0008] Optionally, the first driving unit includes: The first driving PMOS transistor has a source terminal connected to a reference voltage and a gate terminal connected to the reference clock signal. The first driving NMOS transistor has its gate terminal connected to the gate terminal of the first driving PMOS transistor, and its source terminal is grounded. The first driving resistor is connected at both ends to the drain terminal of the first driving PMOS transistor and the drain terminal of the first driving NMOS transistor, respectively, and the drain terminal of the first driving NMOS transistor serves as the output terminal of the first driving unit to output the first driving clock signal. The second drive unit includes: The second driving PMOS transistor has a source terminal connected to a reference voltage and a gate terminal connected to the feedback clock signal. The second driving NMOS transistor has its gate terminal connected to the gate terminal of the second driving PMOS transistor, and its source terminal is grounded. The second driving resistor is connected at both ends to the drain terminals of the second driving PMOS transistor and the second driving NMOS transistor, respectively, and the drain terminal of the second driving NMOS transistor serves as the output terminal of the second driving unit to output the second driving clock signal.
[0009] Optionally, the first delay unit includes a plurality of first coarse delay units and a plurality of first fine delay units. Each first coarse delay unit includes a first coarse delay NMOS transistor and a first coarse delay capacitor. The gate terminal of the first coarse delay NMOS transistor is connected to a first delay control signal, and the source terminal of the first coarse delay NMOS transistor is grounded. The first terminal of the first coarse delay capacitor is connected to the output terminal of the first driving unit, and the second terminal of the first coarse delay capacitor is connected to the drain terminal of the first coarse delay unit. Each first fine delay unit includes a first fine delay NMOS transistor and a first fine delay capacitor. The gate terminal of the first fine delay NMOS transistor is connected to the first delay control signal, and the source terminal of the first fine delay NMOS transistor is grounded. The first terminal of the first fine delay capacitor is connected to the first terminal of the first coarse delay capacitor and the input terminal of the first buffer, and the second terminal of the first fine delay capacitor is connected to the drain terminal of the first fine delay NMOS transistor. The second delay unit includes a plurality of second coarse delay units and a plurality of second fine delay units. Each second coarse delay unit includes a second coarse delay NMOS transistor and a second coarse delay capacitor. The gate terminal of the second coarse delay NMOS transistor is connected to a second delay control signal, and the source terminal of the second coarse delay NMOS transistor is grounded. The first terminal of the second coarse delay capacitor is connected to the output terminal of the second driving unit, and the second terminal of the second coarse delay capacitor is connected to the drain terminal of the second coarse delay unit. Each second fine delay unit includes a second fine delay NMOS transistor and a second fine delay capacitor. The gate terminal of the second fine delay NMOS transistor is connected to a second delay control signal, and the source terminal of the second fine delay NMOS transistor is grounded. The first terminal of the second fine delay capacitor is connected to the first terminal of the second coarse delay capacitor and the input terminal of the second buffer, and the second terminal of the second fine delay capacitor is connected to the drain terminal of the second fine delay NMOS transistor.
[0010] Optionally, the capacitance value of the first coarse delay capacitor is m times the capacitance value of the first fine delay capacitor, the capacitance value of the second coarse delay capacitor is m times the capacitance value of the second fine delay capacitor, the number of the first coarse delay units is twice the number of the first fine delay units, and the number of the second coarse delay units is twice the number of the second fine delay units.
[0011] Optionally, the modulation module includes: An incremental summation modulator is used to output an initial first control signal and a second control signal based on the input frequency control signal; A multiplier is used to apply a gain to the initial first control signal and output the first control signal.
[0012] Optionally, the phase-locked loop module includes: A phase detector is used to output an error signal based on the phase difference between the input first delayed signal and the second delayed signal; A filter is used to filter the error signal and output an oscillation control signal. An oscillator is used to output an initial clock signal according to the oscillation control signal, the frequency of which is controlled by the oscillation control signal; A frequency divider is used to divide the initial clock signal according to the second control signal to output a feedback clock signal. The second control signal is used to adjust the division ratio of the frequency divider.
[0013] Optionally, the filter is a loop filter.
[0014] According to a second aspect of the present invention, a method for operating a fractional phase-locked loop circuit is provided, applied to the aforementioned fractional phase-locked loop circuit, characterized in that it includes: Input a frequency control signal to the modulation module to output a first control signal and a second control signal; In response to the first control signal, a first delay signal is obtained based on a reference clock signal, including: if the enable control bit in the first control signal is in a first state, the reference clock signal is delayed to form a first delay signal; if the enable control bit in the first control signal is in a second state, the reference clock signal is determined as the first delay signal, wherein the first state is the opposite of the second state. In response to the first control signal, a second delayed signal is obtained based on the feedback clock signal, including: if the enable control bit in the first control signal is in a second state, the feedback clock signal is delayed to form a second delayed signal; if the enable control bit in the first control signal is in a first state, the feedback clock signal is determined as the second delayed signal. In response to the second control signal, a feedback clock signal with the same frequency as the reference clock signal is output based on the phase difference between the first delay signal and the second delay signal.
[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the fractional phase-locked loop circuit provided by the present invention, since the first digital time converter can respond to the first control signal and obtain the first delayed signal according to the reference clock signal, and the second digital time converter can respond to the first control signal and obtain the second delayed signal according to the feedback clock signal, the first digital time converter is located in the reference path and the second digital time converter is located in the feedback path, making the delays of the first digital time converter and the second digital time converter opposite. Furthermore, since if the enable control bit in the first control signal is in the first state, the first delayed signal is formed by delaying the reference clock signal; if the enable control bit in the first control signal is in the second state, the feedback clock signal is delayed to form the second delayed signal, and the first state and the second state are opposite, at the same time, based on the different states of the enable control bit of the first control signal, only one of the first and second digital time converters will delay the input signal (reference clock signal or feedback clock signal) to compensate for the phase error generated by the modulation module. In other words, the first digital time converter and the second digital time converter compensate for the positive phase error and the negative phase error generated by the modulation module, respectively. That is, the range of the first digital time converter and the second digital time converter is half of the phase error generated by the modulation module, so that the average delay offset of the first digital time converter and the second digital time converter is 0, thereby making the noise and power consumption of the first digital time converter and the second digital time converter smaller. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a fractional phase-locked loop circuit. Figure 2 yes Figure 1 The relationship between the control signals and the delay of the digital time converter is shown in the diagram. Figure 3 This is a schematic diagram of a fractional phase-locked loop provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the modulation module provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the first digital time converter provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the second digital time converter provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the phase-locked loop module provided in an embodiment of the present invention; Figure 8 yes Figure 3 The diagram shows the relationship between the first control signal and the delay of the digital time converter. Detailed Implementation
[0017] As described in the background section, the average delay of a digital time converter is relatively large, which significantly increases the noise and power consumption of the digital time converter.
[0018] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a fractional phase-locked loop (PLL) circuit. The PLL circuit includes a digital time converter, a modulation module, and a PLL module. The modulation signal outputs a control signal DCW0 based on the input frequency control signal FCW0. The digital time converter, responding to the control signal DCW0, delays the input clock signal REF0 to output a delayed signal D0 to the PLL module. The delay generated by the digital time converter compensates for the phase error generated by the modulation module. Since the phase error generated by the modulation module is bidirectional (positive and negative), while the digital time converter can only generate a positive delay, the digital time converter needs to be set with a fixed bias to cover both positive and negative phase errors. For details, please refer to [reference needed]. Figure 2 , Figure 2 yes Figure 1 The graph shows the relationship between the control signal and the delay of the digital time converter. The horizontal axis represents the delay code in the first control signal, and the vertical axis represents the delay in the digital time converter, normalized to the phase error generated by the modulation module. For example, half of the vertical axis indicates that the delay of the digital time converter is half the range of the phase error generated by the modulation module. The delay code and the delay of the digital time converter have a linear relationship. As the delay code increases, the delay of the digital time converter also increases linearly. Therefore, in order to compensate for the phase error generated by the modulation module, i.e., the sum of the phase error and the delay is a constant value, when the phase error is negative, the delay code is 2N~2N+1, and the corresponding delay is greater than half of the maximum delay that the digital time converter can generate. When the phase error is positive, the delay code is 0~2N, and the corresponding delay is less than half of the maximum delay that the digital time converter can generate, so that its average delay offset is 2N, and the range of the digital time converter is large, where N is a positive integer greater than 1.
[0019] In view of this, the present invention creatively proposes a fractional phase-locked loop circuit, comprising: A modulation module, wherein the modulation module is used to output a first control signal and a second control signal according to the input frequency control signal; A first digital time converter is configured to, in response to the first control signal, acquire a first delayed signal based on a reference clock signal, comprising: if the enable control bit in the first control signal is in a first state, delaying the reference clock signal to form a first delayed signal; and if the enable control bit in the first control signal is in a second state, determining the reference clock signal as the first delayed signal, wherein the first state is the opposite of the second state. The second digital time converter is configured to respond to the first control signal and obtain a second delayed signal based on a feedback clock signal, including: if the enable control bit in the first control signal is in a second state, delaying the feedback clock signal to form a second delayed signal; if the enable control bit in the first control signal is in a first state, determining the feedback clock signal as the second delayed signal. A phase-locked loop module is used to respond to the second control signal and output a feedback clock signal with the same frequency as the reference clock signal based on the phase difference between the first delay signal and the second delay signal.
[0020] The first digital time converter and the second digital time converter compensate for the positive phase error and the negative phase error generated by the modulation module, respectively. That is, the range of the first digital time converter and the second digital time converter is half of the phase error generated by the modulation module, so that the average delay offset of the first digital time converter and the second digital time converter is 0, thereby making the noise and power consumption of the first digital time converter and the second digital time converter relatively small.
[0021] To make the above-mentioned objects, features, and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "second," "first," "second," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] Please refer to Figure 3 This invention provides a fractional phase-locked loop circuit, comprising: a modulation module, a first digital time converter, a second digital time converter, and a phase-locked loop module.
[0023] The modulation module is used to output a first control signal DCW and a second control signal NDIV based on the input frequency control signal FCW.
[0024] In this embodiment, please refer to Figure 4 The modulation module includes an incremental sum modulator (DSM) and a multiplier (Gain).
[0025] The incremental sum modulator (DSM) is used to output an initial first control signal DCW and a second control signal NDIV based on the input frequency control signal FCW. The multiplier Gain is used to apply a gain to the initial first control signal DCW-0 and output the first control signal DCW.
[0026] The first digital time converter is used to respond to the first control signal DCW and obtain the first delayed signal D1 according to the reference clock signal REF, including: if the enable control bit DCW[n] in the first control signal DCW is in a first state, delaying the reference clock signal REF to form the first delayed signal D1; if the enable control bit DCW[n] in the first control signal DCW is in a second state, determining the reference clock signal REF as the first delayed signal D1, the first state and the second state being opposite. Specifically, in the first state and the second state, one is 0 and the other is 1.
[0027] In this embodiment, please refer to Figure 5 The first digital time converter includes a first AND gate AND1, a first drive unit DR1, a first delay unit SB1, and a first buffer BUFFER1.
[0028] The first AND gate AND1 is used to perform an AND operation between the enable control bit DCW[n] and the delay control bit DCW[n-1:0] to output the first delay control signal DCW-RE1. The first drive unit DR1 is used to drive the input reference clock signal REF and output the first drive clock signal CLK11. The first delay unit SB1 is used to delay the first drive clock signal CLK11 according to the first delay control signal DCW-RE1 to convert the first drive clock signal CLK11 into the initial first delay signal CLK12. The first buffer BUFFER1 is used to convert the input initial first delay signal CLK12 into the first delay signal D1 for output.
[0029] Furthermore, the first digital time converter also includes a first inverter NOT1, which allows the reference clock signal REF to be input to the first drive unit DR1 after passing through the first inverter NOT1. The first inverter NOT1 effectively filters out small-amplitude noise superimposed on the reference clock signal REF, while reconstructing the gradually changing edges into steep digital signal edges.
[0030] In this embodiment, the delay control bits DCW[n-1:0] are several bits preceding the enable control bit DCW[n]. Specifically, if the enable control bit DCW[n] is the nth bit of the first control signal DCW, then the delay control bits DCW[n-1:0] are bits 0 to (n-1)th bits of the first control signal DCW, where n is greater than 0.
[0031] In this embodiment, the first driving unit DR1 includes: a first driving PMOS transistor P1, a first driving NMOS transistor N1, and a first driving resistor R1.
[0032] In this configuration, the source terminal of the first driving PMOS transistor P1 is connected to the reference voltage VDD, and the gate terminal of the first driving PMOS transistor P1 is connected to the reference clock signal REF; the gate terminal of the first driving NMOS transistor N1 is connected to the gate terminal of the first driving PMOS transistor P1, and the source terminal of the first driving NMOS transistor N1 is grounded; the two ends of the first driving resistor R1 are connected to the drain terminal of the first driving PMOS transistor P1 and the drain terminal of the first driving NMOS transistor N1, respectively, and the drain terminal of the first driving NMOS transistor N1 serves as the output terminal of the first driving unit DR1 to output the first driving clock signal CLK11.
[0033] In this embodiment, the first delay unit SB1 includes a plurality of first coarse delay units MSB1 and a plurality of first fine delay units LSB1. Each first coarse delay unit MSB1 includes a first coarse delay NMOS transistor NM1 and a first coarse delay capacitor CM1. The gate terminal of the first coarse delay NMOS transistor NM1 is connected to a first delay control signal DCW-RE1, and the source terminal of the first coarse delay NMOS transistor NM1 is grounded. The first terminal of the first coarse delay capacitor CM1 is connected to the output terminal of the first driving unit DR1, and the second terminal of the first coarse delay capacitor CM1 is connected to the first coarse delay unit LSB1. The drain terminal of the timing unit MSB1, each first fine delay unit LSB1 includes a first fine delay NMOS transistor NL1 and a first fine delay capacitor CL1. The gate terminal of the first fine delay NMOS transistor NL1 is connected to the first delay control signal DCW-RE1, the source terminal of the first fine delay NMOS transistor NL1 is grounded, the first terminal of the first fine delay capacitor CL1 is connected to the first terminal of the first coarse delay capacitor CM1 and the input terminal of the first buffer BUFFER1, and the second terminal of the first fine delay capacitor CL1 is connected to the drain terminal of the first coarse delay NMOS transistor NM1.
[0034] It should be noted that, Figure 5 Only one first coarse delay unit MSB1 and one first fine delay unit LSB1 are shown in the figure. Several first coarse delay units MSB1 are connected to endpoint A1, and several first fine delay units LSB1 are connected to endpoint B1.
[0035] The second digital time converter is used to respond to the first control signal DCW and obtain the second delayed signal D2 according to the feedback clock signal F, including: if the enable control bit DCW[n] in the first control signal DCW is in the second state, delaying the feedback clock signal F to form the second delayed signal D2; if the enable control bit DCW[n] in the first control signal DCW is in the first state, determining the feedback clock signal F as the second delayed signal D2.
[0036] In this embodiment, please refer to Figure 6 The second digital time converter includes: NOT gate NOT3, second AND gate AND2, second drive unit DR2, second delay unit SB2, and second buffer BUFFER2.
[0037] Among them, NOT3 is used to NOT the enable control bit DCW[n] and output the disable control bit DCW[n]. The second AND gate AND2 is used to AND the disable control bit DCW[n] with the delay control bit DCW[n-1:0] and output the first delay control signal DCW-RE1. The second drive unit DR2 is used to drive the input feedback clock signal F and output the second drive clock signal CLK21. The second delay unit SB2 is used to delay the second drive clock signal CLK21 according to the second delay control signal DCW-RE2 to convert the second drive clock signal CLK21 into the initial second delay signal CLK22. The second buffer BUFFER2 is used to convert the input initial second delay signal CLK22 into the second delay signal D2 for output.
[0038] Furthermore, the second digital time converter also includes a second inverter NOT2, which allows the feedback clock signal F to be input to the second drive unit DR2 after passing through the second inverter NOT2. The second inverter NOT2 effectively filters out small-amplitude noise superimposed on the feedback clock signal F, while reconstructing the gradually changing edges into steep digital signal edges.
[0039] In this embodiment, the second driving unit DR2 includes: a second driving PMOS transistor P2, a second driving NMOS transistor N2, and a second driving resistor R2.
[0040] In this configuration, the source terminal of the second driving PMOS transistor P2 is connected to the reference voltage VDD, and the gate terminal of the second driving PMOS transistor P2 is connected to the feedback clock signal F; the gate terminal of the second driving NMOS transistor N2 is connected to the gate terminal of the second driving PMOS transistor P2, and the source terminal of the second driving NMOS transistor N2 is grounded; the two ends of the second driving resistor R2 are respectively connected to the drain terminal of the second driving PMOS transistor P2 and the drain terminal of the second driving NMOS transistor N2, and the drain terminal of the second driving NMOS transistor N2 serves as the output terminal of the second driving unit DR2 to output the second driving clock signal CLK21.
[0041] In this embodiment, the second delay unit SB2 includes a plurality of second coarse delay units MSB2 and a plurality of second fine delay units LSB2. Each second coarse delay unit MSB2 includes a second coarse delay NMOS transistor NM2 and a second coarse delay capacitor CM2. The gate terminal of the second coarse delay NMOS transistor NM2 is connected to the second delay control signal DCW-RE2, and the source terminal of the second coarse delay NMOS transistor NM2 is grounded. The first terminal of the second coarse delay capacitor CM2 is connected to the output terminal of the second driving unit DR2, and the second terminal of the second coarse delay capacitor CM2 is connected to... The drain terminal of the second coarse delay unit MSB2. Each second fine delay unit SB2 includes a second fine delay NMOS transistor NL2 and a second fine delay capacitor CL2. The gate terminal of the second fine delay NMOS transistor NL2 is connected to the second delay control signal DCW-RE2. The source terminal of the second fine delay NMOS transistor NL2 is grounded. The first terminal of the second fine delay capacitor CL2 is connected to the first terminal of the second coarse delay capacitor CM2 and the input terminal of the second buffer BUFFER2. The second terminal of the second fine delay capacitor is connected to the drain terminal of the second fine delay NMOS transistor NL2.
[0042] It should be noted that, Figure 6 Only one second coarse delay unit MSB2 and one second fine delay unit LSB2 are shown in the figure. Several second coarse delay units MSB2 are connected to endpoint A2, and several second fine delay units LSB2 are connected to endpoint B2.
[0043] In this embodiment, the capacitance value of the first coarse delay capacitor CM1 is m times the capacitance value of the first fine delay capacitor CL1, the capacitance value of the second coarse delay capacitor CM2 is m times the capacitance value of the second fine delay capacitor CL2, the number of the first coarse delay unit MSB1 is twice the number of the first fine delay unit LSB1, and the number of the second coarse delay unit MSB2 is twice the number of the second fine delay unit LSB2.
[0044] The phase-locked loop module is used to respond to the second control signal NDIV and output a feedback clock signal F with the same frequency as the reference clock signal REF, based on the phase difference between the first delay signal D1 and the second delay signal D2.
[0045] In this embodiment, please refer to Figure 7 The phase-locked loop module includes: a phase detector, a filter, an oscillator, and a frequency divider.
[0046] The phase detector outputs an error signal Cor based on the phase difference between the input first delayed signal D1 and the second delayed signal D2; the filter outputs an oscillation control signal C after filtering the error signal Cor; the oscillator outputs an initial clock signal CLK based on the oscillation control signal C, and the frequency of the initial clock signal CLK is controlled by the oscillation control signal C; the frequency divider divides the initial clock signal based on the second control signal NDIV to output a feedback clock signal F, and the second control signal NDIV is used to adjust the division ratio of the frequency divider.
[0047] In this embodiment, the filter is a loop filter, such as an active RC filter, a passive RC filter, and a charge pump loop filter.
[0048] Please refer to the following: Figure 3 and Figure 7 The first digital time converter is located on the reference path, and its output is connected to the positive input of the phase detector. The second digital time converter is located on the feedback path, and its output is connected to the negative input of the phase detector. Therefore, the first digital time converter performs a positive delay on the input reference clock signal REF, and the second digital time converter performs a negative delay on the input feedback clock signal F. Based on this, when the phase error generated by the modulation module is positive, the enable control bit DCW[n] is in the second state, and the second digital time converter is started to generate negative delay compensation. Correspondingly, when the phase error generated by the modulation module is negative, the enable control bit DCW[n] is in the first state, and the first digital time converter is started to generate positive delay compensation.
[0049] Please refer to Figure 8 , Figure 8The horizontal axis represents the delay code in the first control signal DCW, and the vertical axis represents the delay amount in the first or second digital time converter, normalized to the phase error generated by the control module. For example, half of the vertical axis indicates that the delay amount of the first or second digital time converter is half the range of the phase error generated by the control module. On both sides of the vertical axis, the delay code and the delay amount in the first or second digital time converter exhibit a linear relationship. Therefore, the delay code can be used to control the delay amount in the first or second digital time converter. Specifically, the straight line to the left of the vertical axis represents the delay amount in the second digital time converter when the delay code is -2N to 0, and the straight line to the right of the vertical axis represents the delay amount in the first digital time converter when the delay code is 0 to 2N. That is, the maximum delay amount of both the first and second digital time converters is half the range of the phase error generated by the control module, making the average delay offset 0, where N is a positive integer greater than 1. Based on this, the smaller range of the first and second digital time converters results in lower noise and power consumption for both.
[0050] In summary, in the fractional phase-locked loop circuit provided in this embodiment of the invention, since the first digital time converter can respond to the first control signal DCW and obtain the first delay signal D1 according to the reference clock signal REF, and the second digital time converter can respond to the first control signal DCW and obtain the second delay signal D2 according to the feedback clock signal F, the first digital time converter is located in the reference path and the second digital time converter is located in the feedback path, so that the delays of the first digital time converter and the second digital time converter are opposite. Based on this, if the enable control bit DCW[n] in the first control signal DCW is in the first state, the first delay signal D1 will delay the reference clock signal REF to form the first delay signal D1. If the enable control bit DCW[n] in the first control signal DCW is in the second state, the feedback clock signal F will be delayed to form the second delay signal D2. Since the first state is the opposite of the second state, at the same time, based on the different states of the enable control bit DCW[n] in the first control signal DCW, only one of the first and second digital time converters will delay the input signal (reference clock signal REF or feedback clock signal F) to compensate for the phase error generated by the modulation module. That is, the first and second digital time converters compensate for the positive and negative phase errors generated by the modulation module, respectively. The range of both the first and second digital time converters is half the phase error generated by the modulation module, resulting in an average delay offset of 0 for both the first and second digital time converters. This leads to lower noise and power consumption for both the first and second digital time converters.
[0051] This invention also provides a method for operating a fractional phase-locked loop (PLL) circuit, which is applied to the aforementioned PLL circuit. The specific method includes: Input a frequency control signal FCW to the modulation module to output a first control signal DCW and a second control signal NDIV; In response to the first control signal DCW, the first delayed signal D1 is obtained according to the reference clock signal REF, including: if the enable control bit DCW[n] in the first control signal DCW is in a first state, the reference clock signal REF is delayed to form the first delayed signal D1; if the enable control bit DCW[n] in the first control signal DCW is in a second state, the reference clock signal REF is determined as the first delayed signal D1, and the first state is the opposite of the second state; In response to the first control signal DCW, the second delayed signal D2 is obtained according to the feedback clock signal F, including: if the enable control bit DCW[n] in the first control signal DCW is in the second state, the feedback clock signal F is delayed to form the second delayed signal D2; if the enable control bit DCW[n] in the first control signal DCW is in the first state, the feedback clock signal F is determined as the second delayed signal D2. In response to the second control signal NDIV, a feedback clock signal F with the same frequency as the reference clock signal REF is output based on the phase difference between the first delay signal D1 and the second delay signal D2.
[0052] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A fractional phase-locked loop circuit, characterized in that, include: A modulation module, wherein the modulation module is used to output a first control signal and a second control signal according to the input frequency control signal; A first digital time converter is configured to, in response to the first control signal, acquire a first delayed signal based on a reference clock signal, comprising: if the enable control bit in the first control signal is in a first state, delaying the reference clock signal to form a first delayed signal; and if the enable control bit in the first control signal is in a second state, determining the reference clock signal as the first delayed signal, wherein the first state is the opposite of the second state. The second digital time converter is configured to respond to the first control signal and obtain a second delayed signal based on a feedback clock signal, including: if the enable control bit in the first control signal is in a second state, delaying the feedback clock signal to form a second delayed signal; if the enable control bit in the first control signal is in a first state, determining the feedback clock signal as the second delayed signal. A phase-locked loop module is used to respond to the second control signal and output a feedback clock signal with the same frequency as the reference clock signal based on the phase difference between the first delay signal and the second delay signal.
2. The fractional phase-locked loop circuit according to claim 1, characterized in that, The first digital time converter includes: The first AND gate is used to perform an AND operation between the enable control bit and the delay control bit, and output the first delay control signal. The first driving unit is used to drive the input reference clock signal and output the first driving clock signal. The first delay unit is used to delay the first drive clock signal according to the first delay control signal, so as to convert the first drive clock signal into an initial first delay signal. A first buffer is used to convert the input initial first delay signal into the first delay signal for output; The second digital time converter includes: The NOT gate is used to perform a NOT operation on the enable control bit and output a disable control bit. The second AND gate is used to perform an AND operation between the disabled control bit and the delay control bit, and output the first delay control signal. The second driving unit is used to drive the input feedback clock signal and output a second driving clock signal. The second delay unit is used to delay the second drive clock signal according to the second delay control signal, so as to convert the second drive clock signal into an initial second delay signal; The second buffer is used to convert the input initial second delay signal into the second delay signal for output.
3. The fractional phase-locked loop circuit according to claim 2, characterized in that, The delay control bits are the bits preceding the enable control bits.
4. The fractional phase-locked loop circuit according to claim 2, characterized in that, The first driving unit includes: The first driving PMOS transistor has a source terminal connected to a reference voltage and a gate terminal connected to the reference clock signal. The first driving NMOS transistor has its gate terminal connected to the gate terminal of the first driving PMOS transistor, and its source terminal is grounded. The first driving resistor is connected at both ends to the drain terminal of the first driving PMOS transistor and the drain terminal of the first driving NMOS transistor, respectively, and the drain terminal of the first driving NMOS transistor serves as the output terminal of the first driving unit to output the first driving clock signal. The second drive unit includes: The second driving PMOS transistor has a source terminal connected to a reference voltage and a gate terminal connected to the feedback clock signal. The second driving NMOS transistor has its gate terminal connected to the gate terminal of the second driving PMOS transistor, and its source terminal is grounded. The second driving resistor is connected at both ends to the drain terminals of the second driving PMOS transistor and the second driving NMOS transistor, respectively, and the drain terminal of the second driving NMOS transistor serves as the output terminal of the second driving unit to output the second driving clock signal.
5. The fractional phase-locked loop circuit according to claim 2, characterized in that, The first delay unit includes a plurality of first coarse delay units and a plurality of first fine delay units. Each first coarse delay unit includes a first coarse delay NMOS transistor and a first coarse delay capacitor. The gate terminal of the first coarse delay NMOS transistor is connected to a first delay control signal, and the source terminal of the first coarse delay NMOS transistor is grounded. The first terminal of the first coarse delay capacitor is connected to the output terminal of the first driving unit, and the second terminal of the first coarse delay capacitor is connected to the drain terminal of the first coarse delay unit. Each first fine delay unit includes a first fine delay NMOS transistor and a first fine delay capacitor. The gate terminal of the first fine delay NMOS transistor is connected to a first delay control signal, and the source terminal of the first fine delay NMOS transistor is grounded. The first terminal of the first fine delay capacitor is connected to the first terminal of the first coarse delay capacitor and the input terminal of the first buffer, and the second terminal of the first fine delay capacitor is connected to the drain terminal of the first fine delay NMOS transistor. The second delay unit includes a plurality of second coarse delay units and a plurality of second fine delay units. Each second coarse delay unit includes a second coarse delay NMOS transistor and a second coarse delay capacitor. The gate terminal of the second coarse delay NMOS transistor is connected to a second delay control signal, and the source terminal of the second coarse delay NMOS transistor is grounded. The first terminal of the second coarse delay capacitor is connected to the output terminal of the second driving unit, and the second terminal of the second coarse delay capacitor is connected to the drain terminal of the second coarse delay unit. Each second fine delay unit includes a second fine delay NMOS transistor and a second fine delay capacitor. The gate terminal of the second fine delay NMOS transistor is connected to a second delay control signal, and the source terminal of the second fine delay NMOS transistor is grounded. The first terminal of the second fine delay capacitor is connected to the first terminal of the second coarse delay capacitor and the input terminal of the second buffer, and the second terminal of the second fine delay capacitor is connected to the drain terminal of the second fine delay NMOS transistor.
6. The fractional phase-locked loop circuit according to claim 5, characterized in that, The capacitance value of the first coarse delay capacitor is m times the capacitance value of the first fine delay capacitor, the capacitance value of the second coarse delay capacitor is m times the capacitance value of the second fine delay capacitor, the number of the first coarse delay units is twice the number of the first fine delay units, and the number of the second coarse delay units is twice the number of the second fine delay units.
7. The fractional phase-locked loop circuit according to claim 1, characterized in that, The modulation module includes: An incremental summation modulator is used to output an initial first control signal and a second control signal based on the input frequency control signal; A multiplier is used to apply a gain to the initial first control signal and output the first control signal.
8. The fractional phase-locked loop circuit according to claim 1, characterized in that, The phase-locked loop module includes: A phase detector is used to output an error signal based on the phase difference between the input first delayed signal and the second delayed signal; A filter is used to filter the error signal and output an oscillation control signal. An oscillator is used to output an initial clock signal according to the oscillation control signal, the frequency of which is controlled by the oscillation control signal; A frequency divider is used to divide the initial clock signal according to the second control signal to output a feedback clock signal. The second control signal is used to adjust the division ratio of the frequency divider.
9. The fractional phase-locked loop circuit according to claim 8, characterized in that, The filter is a loop filter.
10. A method for operating a fractional phase-locked loop circuit, applied to the fractional phase-locked loop circuit as described in any one of claims 1 to 9, characterized in that, include: Input a frequency control signal to the modulation module to output a first control signal and a second control signal; In response to the first control signal, a first delay signal is obtained based on a reference clock signal, including: if the enable control bit in the first control signal is in a first state, the reference clock signal is delayed to form a first delay signal; if the enable control bit in the first control signal is in a second state, the reference clock signal is determined as the first delay signal, wherein the first state is the opposite of the second state. In response to the first control signal, a second delayed signal is obtained based on the feedback clock signal, including: if the enable control bit in the first control signal is in a second state, the feedback clock signal is delayed to form a second delayed signal; if the enable control bit in the first control signal is in a first state, the feedback clock signal is determined as the second delayed signal. In response to the second control signal, a feedback clock signal with the same frequency as the reference clock signal is output based on the phase difference between the first delay signal and the second delay signal.