Digital-to-time converter, working method thereof, fractional phase-locked loop and electronic equipment

Abstract

The technical scheme of the invention provides a digital-to-time converter, a working method thereof, a fractional phase-locked loop and electronic equipment. The digital-to-time converter comprises a first bias buffer unit, a second bias buffer unit, a reference selection unit and a digital-to-time conversion module. Since the voltage of the first bias is greater than the voltage of the second bias, two reference clocks with phase deviation are generated with low power consumption and low noise only through the voltage difference between the first bias and the second bias. The delay range of the digital time conversion module is equal to the first phase difference between the second reference clock and the first reference clock, so that the delay range of the digital time conversion module is reduced to the first phase difference from the original twice of the first phase difference; therefore, the dynamic range and noise of the digital time converter are greatly reduced.

Description

Technical Field

[0001] This invention relates to the technical field of electronic circuits, and more particularly to digital time converters and their operating methods, fractional phase-locked loops, and electronic devices. Background Technology

[0002] In a fractional-N PLL, the delay range of the digital-to-time converter (DTC) determines its noise and nonlinearity. Because a traditional RC-type DTC needs to cover the entire quantization error range of the DSM (Delta-Sigma Modulator) output, it has a large delay range. This results in a significant increase in the thermal noise of the DTC and the noise of the buffer, leading to a decrease in delay linearity and a deterioration in system power consumption and reference spurious emissions.

[0003] Existing technologies typically employ the following technical solutions to address the latency range of DTC: (1) Multiphase interpolation: By introducing an additional phase interpolator to interpolate the quantization error of the DSM, the quantization error can be directly compensated, thereby greatly reducing the dynamic range and accuracy requirements of the DTC. However, the problem with this scheme is that the additional phase interpolator will increase the overall power consumption of the phase-locked loop and introduce additional noise; (2) Segmented correction technique: To address the nonlinearity issues that may exist in DTC, segmented correction divides the entire delay range into multiple intervals and uses different correction coefficients in each interval to improve correction accuracy. However, the problem with this approach is that segmented correction techniques typically have a high frequency, which introduces additional power consumption. Summary of the Invention

[0004] To solve the above-mentioned technical problems, this invention provides a digital time converter and its working method, as well as a fractional phase-locked loop and electronic device, so as to halve the delay range of the digital time converter without introducing additional power consumption and noise.

[0005] According to a first aspect of the present invention, a digital time converter is provided, comprising: The first bias buffer unit performs a first bias and a first buffer on the initial reference clock and outputs the first reference clock. The second bias buffer unit performs a second bias and a second buffer on the initial reference clock and outputs a second reference clock. The second reference clock lags behind the first reference clock, and there is a first phase difference between the first reference clock and the second reference clock. A reference selection unit, which selects either the first reference clock or the second reference clock output based on the quantized noise signal; A digital time conversion module, wherein the digital time conversion module adjusts the delay of the first reference clock according to the quantization noise signal and outputs a third reference clock; or adjusts the delay of the second reference clock according to the quantization noise signal and outputs a fourth reference clock, wherein the delay range of the digital time conversion module is equal to the first phase difference.

[0006] Optionally, the first bias buffer unit includes a first isolation capacitor and a first buffer; the first isolation capacitor is used to perform a first AC coupling on the initial reference clock and output a first sine wave signal; the first bias voltage performs a first bias on the first sine wave signal and outputs a first sine bias signal to the first buffer; the first buffer performs a first buffer on the first sine bias signal and outputs the first reference clock.

[0007] Optionally, the second bias buffer unit includes a second isolation capacitor and a second buffer; the second isolation capacitor is used to perform a second AC coupling on the initial reference clock and output a second sine wave signal; the second bias voltage performs a second bias on the second sine wave signal and outputs a second sine bias signal to the second buffer; the second buffer performs a second buffer on the second sine bias signal and outputs the second reference clock, wherein the first phase difference is proportional to the bias voltage difference, and the bias voltage difference is equal to the difference between the first bias voltage and the second bias voltage.

[0008] Optionally, the first bias voltage is equal to half of the supply voltage; The second bias buffer unit further includes an analog-to-digital converter, which performs digital-to-analog conversion on the second bias digital signal and outputs the second bias voltage.

[0009] Optionally, it also includes: a deviation compensation module, used to compare the third reference clock and the second reference clock, and output a delay adjustment signal to the digital time conversion module according to the comparison result; The digital time conversion module is used to correct its own delay range to the first phase difference according to the delay adjustment signal, wherein the delay adjustment signal is proportional to the delay range of the digital time conversion module.

[0010] Optionally, the deviation compensation module includes: A comparator is used to compare the third reference clock and the second reference clock, and output a comparison signal; A successive approximation register is used to output the delay adjustment signal to the digital time conversion module based on the comparison signal.

[0011] According to a second aspect of the present invention, a method for operating a digital time converter is provided, based on the digital time converter described in the first aspect and optional embodiments of the present invention, the method for operating the digital time converter includes: The first bias buffer unit performs a first bias and a first buffer on the initial reference clock to output the first reference clock; The second bias buffer unit performs a second bias and a second buffer on the initial reference clock to output a second reference clock; The reference selection unit selects either the first reference clock or the second reference clock output based on the quantized noise signal; the second reference clock lags behind the first reference clock, and there is a first phase difference between the first reference clock and the second reference clock; The digital time conversion module adjusts the delay of the first reference clock according to the quantization noise signal and outputs a third reference clock; or adjusts the delay of the second reference clock according to the quantization noise signal and outputs a fourth reference clock, wherein the delay range of the digital time conversion module is equal to the first phase difference.

[0012] Optionally, it also includes: when the system is powered on, the quantization noise signal controls the reference selection unit to output only the first reference clock; At this time, the digital time conversion module adjusts the delay of the first reference clock according to the quantized noise signal and outputs the third reference clock; The deviation compensation module compares the third reference clock and the second reference clock, and outputs a delay adjustment signal to the digital time conversion module based on the comparison result; The digital time conversion module corrects its own delay range to the first phase difference according to the delay adjustment signal, and the delay adjustment signal is proportional to the delay range of the digital time conversion module.

[0013] According to a third aspect of the present invention, a fractional phase-locked loop is provided, comprising: The digital time converter described in the first aspect and optional embodiments of the present invention outputs a third reference clock or a fourth reference clock based on a quantized noise signal; A sampling phase detector is used to sample and compare the feedback clock signal with the third reference clock or the fourth reference clock, and output a phase mis-touch signal; A loop filter is used to filter out high-frequency noise in the phase mis-trigger signal and output a control voltage; A voltage-controlled oscillator is used to output a target frequency signal according to the control voltage, the frequency of the target frequency signal being equal to the frequency of the initial reference clock; A multi-mode frequency divider is used to divide and switch the target frequency signal according to the sequence quantization noise signal, and output the feedback clock signal; A differential integral modulator is used to output the sequence quantized noise signal and the quantized noise signal according to a preset fractional allocation of the quantized noise signal.

[0014] According to a fourth aspect of the present invention, an electronic device is provided, comprising the fractional phase-locked loop described in the third aspect of the present invention.

[0015] According to the technical solution of the present invention, a digital time converter includes a first bias buffer unit that performs a first bias and a first buffer on an initial reference clock and outputs a first reference clock; a second bias buffer unit that performs a second bias and a second buffer on the initial reference clock and outputs a second reference clock; a reference selection unit that selects either the first reference clock or the second reference clock for output based on a quantization noise signal; and a digital time conversion module that performs delay adjustment on the first reference clock or the second reference clock based on the quantization noise signal and outputs a corresponding third reference clock or a fourth reference clock, thereby achieving phase compensation for quantization noise.

[0016] Since the voltage of the first bias is greater than the voltage of the second bias, two reference clocks with phase deviation are generated with low power consumption and low noise using only the voltage difference between the first and second biases. Furthermore, since the delay range of the digital time conversion module is equal to the first phase difference between the second and first reference clocks, the delay range of the digital time conversion module is reduced from twice the first phase difference to the first phase difference, thereby greatly reducing the dynamic range and noise of the digital time converter.

[0017] Furthermore, a deviation compensation module is also provided. The deviation compensation module compares the third reference clock and the second reference clock, and outputs a delay adjustment signal to the digital time conversion module according to the comparison result, so as to automatically correct the delay range of the digital time conversion module to the first phase difference, thereby improving the adaptability and consistency of the digital time conversion module, and further improving the accuracy of the digital time conversion module in delay adjustment of the first reference clock or the second reference clock. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic diagram of the circuit structure of the digital time converter provided in the first embodiment of the present invention; Figure 2 This is a waveform diagram of the first reference clock and the second reference clock provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of a digital time converter provided in another embodiment of the present invention; Figure 4 This is a flowchart of the operation method of the digital time converter provided in the first embodiment of the present invention; Figure 5 This is a schematic diagram of the module structure of the fractional phase-locked loop provided in the second embodiment of the present invention.

[0020] 1-Digital time converter; 2-Sampling phase detector; 3-Loop filter; 4-Voltage-controlled oscillator; 5-Multi-mode frequency divider; 6-Differential Integral Modulator; 10 - First bias buffer unit; 11-Second bias buffer unit; 12-Reference Selection Unit; 13-Digital Time Conversion Module; 14- Deviation Compensation Module; 141 - Comparator; 142 - Successive Approximation Register; 143 - Delay Unit; VB1 - First bias voltage; VB2 - Second bias voltage; DCW1 - Quantization noise signal; DCW2 - Delay adjustment signal; v1 - Comparison signal; vdac - Second bias digital signal; C1 - First isolation capacitor; Bufe - First Buffer; C2 - Second isolation capacitor; Bufl - Second buffer; DAC - Analog-to-Digital Converter; REF0 - Initial reference clock; REF1 - First reference clock; REF2 - Second reference clock; REF3 - Third Reference Clock; REF4 - Fourth Reference Clock; φ - First phase difference. Detailed Implementation

[0021] As described in the background section, existing technologies typically employ the following technical solutions to address the latency range of DTC: (1) Multiphase interpolation: By introducing an additional phase interpolator to interpolate the quantization error of the DSM, the quantization error can be directly compensated, thereby greatly reducing the dynamic range and accuracy requirements of the DTC. However, the problem with this scheme is that the additional phase interpolator will increase the overall power consumption of the phase-locked loop and introduce additional noise; (2) Segmented correction technique: To address the nonlinearity issues that may exist in DTC, segmented correction divides the entire delay range into multiple intervals and uses different correction coefficients in each interval to improve correction accuracy. However, the problem with this approach is that segmented correction techniques typically have a high frequency, which introduces additional power consumption.

[0022] In view of this, the present invention provides a new digital time converter, including a first bias buffer unit, a second bias buffer unit, a reference selection unit, and a digital time conversion module.

[0023] Since the voltage of the first bias is greater than the voltage of the second bias, two reference clocks with phase deviation are generated with low power consumption and low noise using only the voltage difference between the first and second biases. Furthermore, since the delay range of the digital time conversion module is equal to the first phase difference between the second and first reference clocks, the delay range of the digital time conversion module is reduced from twice the first phase difference to the first phase difference, thereby greatly reducing the dynamic range and noise of the digital time converter.

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0027] [First Embodiment] Please refer to Figure 1 This embodiment provides a digital time converter 1, including a first bias buffer unit 10, a second bias buffer unit 11, a reference selection unit 12, a digital time conversion module 13, and a bias compensation module 14.

[0028] Please continue to refer to this. Figure 1 In this embodiment, the first bias buffer unit 10 performs a first bias and a first buffer on the initial reference clock REF0 and outputs a first reference clock REF1. The first bias buffer unit 10 includes a first isolation capacitor C1 and a first buffer Buffer.

[0029] One end of the first isolation capacitor C1 is connected to the initial reference clock REF0, and the other end of the first isolation capacitor C1 is connected to the input terminal of the first buffer Buffer. The first isolation capacitor C1 is used to perform the first AC coupling to the initial reference clock REF0 and output the first sine wave signal. It can be understood that the first isolation capacitor C1 isolates the DC signal in the initial reference clock REF0 and outputs the remaining AC signal, namely the first sine wave signal.

[0030] Please refer to Figure 2 The first bias voltage VB1 input from the outside applies a first bias to the first sine wave signal, and then outputs a first sine bias signal to the first buffer Buffer. After the first bias by the first bias voltage VB1, the first sine bias signal has a larger DC component compared to the first sine wave signal.

[0031] The first buffer, Bufe, performs a first buffering on the first sinusoidal bias signal and outputs the first reference clock, REF1. The first reference clock, REF1, is specifically a periodic pulse signal.

[0032] Please continue to refer to this. Figure 1 In this embodiment, the second bias buffer unit 11 performs a second bias and a second buffer on the initial reference clock REF0 and outputs a second reference clock REF2. The second reference clock REF2 lags behind the first reference clock REF1, and there is a first phase difference φ between the first reference clock REF1 and the second reference clock REF2. The second bias buffer unit 11 includes a second isolation capacitor C2, an analog-to-digital converter DAC, and a second buffer Bufl.

[0033] One end of the second isolation capacitor C2 is connected to the initial reference clock REF0, and the other end is connected to the input terminal of the second buffer Bufl. The second isolation capacitor C2 is used to perform a second AC coupling to the initial reference clock REF0 and output a second sine wave signal. This can be understood as the second isolation capacitor C2 isolating the DC signal in the initial reference clock REF0 and outputting the remaining AC signal, i.e., the second sine wave signal. Since the first isolation capacitor C1 and the second isolation capacitor C2 have the same function—isolieving the DC signal in the initial reference clock REF0—the first sine wave signal and the second sine wave signal have the same waveform, frequency, and phase.

[0034] Please continue to refer to this. Figure 2 The analog-to-digital converter (DAC) performs digital-to-analog conversion on the second bias digital signal vdac and outputs the second bias voltage VB2. After the second bias voltage VB2 applies a second bias to the second sine wave signal, a second sine bias signal is output to the second buffer Bufl. After the second bias by the second bias voltage VB2, the second sine bias signal also has a larger DC component compared to the second sine wave signal.

[0035] The second buffer Bufl performs a second buffering on the second sinusoidal bias signal and outputs the second reference clock REF2.

[0036] In this embodiment, the first bias voltage VB1 is equal to half of the power supply voltage, while the magnitude of the second bias voltage VB2 is controlled by the second bias digital signal vdac. Therefore, by controlling the second bias voltage VB2 to be less than the first bias voltage VB1 through the second bias digital signal vdac, a bias voltage difference is formed between the first bias voltage VB1 and the second bias voltage VB2. Since the phases of the first reference clock REF1 and the second reference clock REF2 are each proportional to their corresponding bias voltages, the bias voltage difference between the first bias voltage VB1 and the second bias voltage VB2 causes the first phase difference φ between the first reference clock REF1 and the second reference clock REF2. This can be understood as the second reference clock REF2 lagging behind the first reference clock REF1 by the first phase difference φ.

[0037] Please continue to refer to this. Figure 1 In this embodiment, the first input terminal of the reference selection unit 12 is connected to the output terminal of the first buffer Bufl, and the second input terminal of the reference selection unit 12 is connected to the output terminal of the second buffer Bufl. The reference selection unit 12 selects either the first reference clock REF1 or the second reference clock REF2 for output based on the externally input quantization noise signal DCW1.

[0038] In this embodiment, the reference selection unit 12 can be a multiplexer, which is not limited here.

[0039] Please continue to refer to this. Figure 1 In this embodiment, the input terminal of the digital time conversion module 13 is connected to the output terminal of the reference selection unit 12. The digital time conversion module 13 adjusts the delay of the first reference clock REF1 according to the quantization noise signal DCW1 and outputs a third reference clock REF3; or adjusts the delay of the second reference clock REF2 according to the quantization noise signal DCW1 and outputs a fourth reference clock REF4. This can be understood as follows: when the reference selection unit 12 selects to output the first reference clock REF1, the digital time conversion module 13 adjusts the delay of the first reference clock REF1 to output the third reference clock REF3. When the reference selection unit 12 outputs the second reference clock REF2, the digital time conversion module 13 adjusts the delay of the second reference clock REF2 to output the fourth reference clock REF4.

[0040] Because this embodiment uses two parallel buffer paths with different input biases in the reference clock path to form a first reference clock REF1 and a second reference clock REF2 with a first phase difference φ using the bias voltage difference, no additional RC delay element is needed, thus avoiding the introduction of additional RC noise and power consumption due to the introduction of RC delay element. Furthermore, since the delay range of the digital time conversion module 13 is equal to the first phase difference φ, the earlier phase first reference clock REF1 or the later phase second reference clock REF2 is selected and input to the digital time conversion module 13 according to the delay requirement of the quantized noise signal DCW1 standard. This results in the reference clock output by the digital time conversion module 13 having a delay range equal to twice the first phase difference φ compared to the initial reference clock REF0. It can be understood that without the first bias buffer unit 10, the second bias buffer unit 11, and the reference selection unit 12, the maximum delay of the digital time conversion module 13 relative to the initial reference clock REF0 according to the quantized noise signal DCW1 needs to reach twice the first phase difference φ, that is, the delay range of the digital time conversion module 13 needs to be twice the first phase difference φ. In this embodiment, the delay range of the digital time conversion module 13 only needs to be twice the first phase difference φ, thereby halving the delay range of the digital time conversion module 13 with low power consumption and without increasing noise, so as to greatly reduce the dynamic range and noise of the digital time conversion module 13.

[0041] It should be noted that the first phase difference φ can be adjusted by setting the second bias digital signal vdac. That is, the larger the second bias digital signal vdac, the larger the second bias voltage VB2, and the smaller the voltage difference between the first bias voltage VB1 and the second bias voltage VB2, thus the smaller the first phase difference φ. Conversely, the smaller the second bias digital signal vdac, the smaller the second bias voltage VB2, and the larger the voltage difference between the first bias voltage VB1 and the second bias voltage VB2, thus the larger the first phase difference φ. Therefore, the specific magnitude of the first phase difference φ is related to the original delay range of the digital time conversion module 13; that is, the first phase difference φ is equal to half of the original delay range of the digital time conversion module 13.

[0042] Theoretically, the phase difference between the first reference clock REF1 and the second reference clock REF2 should be equal to the delay range of the digital time conversion module 13. However, in practical applications, the phase difference between the first reference clock REF1 and the second reference clock REF2 and the delay range of the digital time conversion module 13 may have certain errors due to factors such as process technology or ambient temperature. Therefore, it is necessary to correct the delay range of the digital time conversion module 13 through the deviation compensation module 14.

[0043] The calibration usually occurs during the power-on phase of the system. When calibration is performed, the quantization noise signal DCW1 controls the reference selection unit 12 to output only the first reference clock REF1. Therefore, the digital time conversion module 13 adjusts the delay of the first reference clock REF1 according to the quantization noise signal DCW1 and outputs the third reference clock REF3.

[0044] Please continue to refer to this. Figure 1 Therefore, during the calibration phase, the first input terminal of the deviation compensation module 14 is connected to the third reference clock REF3, and the second input terminal of the deviation compensation module 14 is connected to the second reference clock REF2. The deviation compensation module 14 compares the third reference clock REF3 and the second reference clock REF2. At this time, the deviation compensation module 14 outputs a delay adjustment signal DCW2 to the digital time conversion module 13 based on the delay error between the third reference clock REF3 and the second reference clock REF2.

[0045] The digital time conversion module 13 will automatically correct the delay range of the digital time conversion module 13 to the first phase difference φ according to the delay adjustment signal DCW2, thereby improving the adaptability and consistency of the digital time conversion module 13, and further improving the accuracy of the digital time conversion module 13 in delay adjustment of the first reference clock REF1 or the second reference clock REF2.

[0046] Please continue to refer to this. Figure 1 The deviation compensation module 14 includes a comparator 141 and a successive approximation register 142.

[0047] The non-inverting input of comparator 141 serves as the second input of the bias compensation module 14, and the inverting input serves as the first input of the bias compensation module 14. The output of comparator 141 is connected to the input of the successive approximation register 142. Comparator 141 is used to compare the third reference clock REF3 and the second reference clock REF2, and outputs a comparison signal v1.

[0048] The successive approximation register 142 is used to output the delay adjustment signal DCW2 to the digital time conversion module 13 according to the comparison signal v1.

[0049] When the third reference clock REF3 lags behind the second reference clock REF2, the comparison signal v1 is at a high level, and the delay adjustment signal DCW2 continuously decreases to reduce the delay range of the digital time conversion module 13 until the third reference clock REF3 just leads the second reference clock REF2. At this point, the comparison signal v1 flips from a high level to a low level, thereby completing the correction.

[0050] When the third reference clock REF3 leads the second reference clock REF2, the comparison signal v1 is low. The delay adjustment signal DCW2 continuously increases to increase the delay range of the digital time conversion module 13 until the third reference clock REF3 lags the second reference clock REF2. At this point, the comparison signal v1 flips from low to high, thus completing the correction.

[0051] Since the third reference clock REF3 is obtained by delaying the first reference clock REF1 through the digital time conversion module 13, the third reference clock REF3 lags behind the first reference clock REF1 by the delay range of the digital time conversion module 13. Furthermore, because the second reference clock REF2 is set to lag behind the first reference clock REF1 by a first phase difference φ, and the first phase difference φ is equal to the delay range of the digital time conversion module 13, when the third reference clock REF3 and the second reference clock REF2 are in phase, it indicates that the phase difference between the second reference clock REF2 and the first reference clock REF1 is equal to the delay range of the digital time conversion module 13, thus completing the correction.

[0052] Please refer to Figure 3 In another embodiment, the deviation compensation module 14 further includes a delay unit 143, which is used to perform a fixed delay on the second reference clock REF2 and output the second reference clock REF2 after the fixed delay to the non-inverting input of the comparator 141.

[0053] Since the multiplexer in the reference selection unit 12 has a certain delay effect on the first reference clock REF1, the second reference clock REF2 is delayed in the same way by the delay unit 143 to offset this delay, thereby improving the accuracy of the correction. Furthermore, the delay unit 143 may also include a multiplexer.

[0054] Please refer to Figure 1 and Figure 4 This embodiment also provides a method for operating a digital time converter, which specifically includes the following steps: Step S1: The first bias buffer unit 10 performs a first bias and a first buffer on the initial reference clock REF0 to output the first reference clock REF1.

[0055] Step S2: The second bias buffer unit 11 performs a second bias and a second buffer on the initial reference clock REF0 to output the second reference clock REF2.

[0056] Step S3: The reference selection unit 12 selects the first reference clock REF1 or the second reference clock REF2 to output based on the quantized noise signal DCW1.

[0057] Step S4: The digital time conversion module 13 adjusts the delay of the first reference clock REF1 according to the quantization noise signal DCW1 and outputs the third reference clock REF3; or adjusts the delay of the second reference clock REF2 according to the quantization noise signal DCW1 and outputs the fourth reference clock REF4.

[0058] When the system is powered on, the quantization noise signal DCW1 controls the reference selection unit 12 to output only the first reference clock REF1.

[0059] At this time, the digital time conversion module 13 adjusts the delay of the first reference clock REF1 according to the quantization noise signal DCW1, and outputs the third reference clock REF3.

[0060] The deviation compensation module 14 compares the third reference clock REF3 and the second reference clock REF2, and outputs a delay adjustment signal DCW2 to the digital time conversion module 13 based on the comparison result.

[0061] The digital time conversion module 13 corrects its own delay range to the first phase difference φ according to the delay adjustment signal DCW2, and the delay adjustment signal DCW2 is proportional to the delay range of the digital time conversion module 13.

[0062] In summary, the digital time converter 1 provided in this embodiment generates two reference clocks, REF1 and REF2, with phase deviation, while consuming low power and without introducing additional noise. The delay range of the digital time conversion module 13 is set to be equal to the first phase difference φ between the second reference clock REF2 and the first reference clock REF1. Therefore, the delay range of the digital time conversion module 13 is reduced from twice the original first phase difference φ to the first phase difference φ, thereby greatly reducing the dynamic range and noise of the digital time converter 1.

[0063] Furthermore, a deviation compensation module 14 is also provided. The deviation compensation module 14 compares the third reference clock REF3 and the second reference clock REF2, and outputs a delay adjustment signal DCW2 to the digital time conversion module 13 according to the comparison result, so as to automatically correct the delay range of the digital time conversion module 13 to the first phase difference φ, thereby improving the adaptability and consistency of the digital time conversion module 13, and further improving the accuracy of the digital time conversion module 13 in delay adjustment of the first reference clock REF1 or the second reference clock REF2.

[0064] [Second Embodiment] Please refer to Figure 5 This embodiment provides a fractional phase-locked loop, including a digital time converter 1, a sampling phase detector 2, a loop filter 3, a voltage-controlled oscillator 4, a multi-mode frequency divider 5, and a differential integral modulator 6, as provided in the first embodiment.

[0065] The digital time converter 1 outputs a third reference clock REF3 or a fourth reference clock REF4 based on the quantization noise signal DCW1.

[0066] The input terminal of the sampling phase detector 2 is connected to the output terminal of the digital time converter 1. The sampling phase detector 2 is used to sample and compare the feedback clock signal with the third reference clock REF3 or the fourth reference clock REF4, and output a phase mis-touch signal.

[0067] The input terminal of the loop filter 3 is connected to the output terminal of the sampling phase detector 2. The loop filter 3 is used to filter out high-frequency noise in the phase mis-trigger signal and output a control voltage.

[0068] The input terminal of the voltage-controlled oscillator 4 is connected to the output terminal of the loop filter 3. The voltage-controlled oscillator 4 is used to output a target frequency signal according to the control voltage. The frequency of the target frequency signal is equal to the frequency of the initial reference clock REF0.

[0069] The first input terminal of the multi-mode frequency divider 5 is connected to the output terminal of the voltage-controlled oscillator 4, and the output terminal of the multi-mode frequency divider 5 is connected to the input terminal of the sampling phase detector 2. The multi-mode frequency divider 5 is used to divide and switch the target frequency signal according to the sequence quantization noise signal DCW1, and output the feedback clock signal.

[0070] The first output terminal of the differential integral modulator 6 is connected to the input terminal of the digital time converter 1, and the second output terminal of the differential integral modulator 6 is connected to the second input terminal of the multi-mode frequency divider 5. The differential integral modulator 6 is used to allocate the quantization noise signal DCW1 according to the preset fraction of the external input, output the sequence quantization noise signal DCW1 to the multi-mode frequency divider 5, and output the quantization noise signal DCW1 to the digital time converter 1.

[0071] [Third Embodiment] This embodiment provides an electronic device, including the fractional phase-locked loop provided in the second embodiment.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital time converter, characterized in that, include: The first bias buffer unit performs a first bias and a first buffer on the initial reference clock and outputs the first reference clock. The second bias buffer unit performs a second bias and a second buffer on the initial reference clock and outputs a second reference clock. The second reference clock lags behind the first reference clock, and there is a first phase difference between the first reference clock and the second reference clock. A reference selection unit, which selects either the first reference clock or the second reference clock output based on the quantized noise signal; A digital time conversion module, wherein the digital time conversion module adjusts the delay of the first reference clock according to the quantization noise signal and outputs a third reference clock; or adjusts the delay of the second reference clock according to the quantization noise signal and outputs a fourth reference clock, wherein the delay range of the digital time conversion module is equal to the first phase difference.

2. The digital time converter according to claim 1, characterized in that, The first bias buffer unit includes a first isolation capacitor and a first buffer; the first isolation capacitor is used to perform a first AC coupling on the initial reference clock and output a first sine wave signal; the first bias voltage performs a first bias on the first sine wave signal and outputs a first sine bias signal to the first buffer; The first buffer performs a first buffering on the first sinusoidal bias signal and outputs the first reference clock.

3. The digital time converter according to claim 2, characterized in that, The second bias buffer unit includes a second isolation capacitor and a second buffer; the second isolation capacitor is used to perform a second AC coupling on the initial reference clock and output a second sine wave signal. The second bias voltage applies a second bias to the second sine wave signal, and then outputs a second sine bias signal to the second buffer. The second buffer performs a second buffering on the second sinusoidal bias signal and outputs the second reference clock. The first phase difference is proportional to the bias voltage difference, and the bias voltage difference is equal to the difference between the first bias voltage and the second bias voltage.

4. The digital time converter according to claim 3, characterized in that, The first bias voltage is equal to half of the supply voltage; The second bias buffer unit further includes an analog-to-digital converter, which performs digital-to-analog conversion on the second bias digital signal and outputs the second bias voltage.

5. The digital time converter according to claim 1, characterized in that, Also includes: The deviation compensation module is used to compare the third reference clock and the second reference clock, and output a delay adjustment signal to the digital time conversion module according to the comparison result; The digital time conversion module is used to correct its own delay range to the first phase difference according to the delay adjustment signal, wherein the delay adjustment signal is proportional to the delay range of the digital time conversion module.

6. The digital time converter according to claim 5, characterized in that, The deviation compensation module includes: A comparator is used to compare the third reference clock and the second reference clock, and output a comparison signal; A successive approximation register is used to output the delay adjustment signal to the digital time conversion module based on the comparison signal.

7. A method for operating a digital time converter, characterized in that, The digital time converter based on any one of claims 1 to 6, the method of operating the digital time converter includes: The first bias buffer unit performs a first bias and a first buffer on the initial reference clock to output the first reference clock; The second bias buffer unit performs a second bias and a second buffer on the initial reference clock to output a second reference clock; The reference selection unit selects either the first reference clock or the second reference clock output based on the quantized noise signal; the second reference clock lags behind the first reference clock, and there is a first phase difference between the first reference clock and the second reference clock; The digital time conversion module adjusts the delay of the first reference clock according to the quantization noise signal and outputs a third reference clock; or adjusts the delay of the second reference clock according to the quantization noise signal and outputs a fourth reference clock, wherein the delay range of the digital time conversion module is equal to the first phase difference.

8. The operating method of the digital time converter according to claim 7, characterized in that, The feature is that it further includes: when the system is powered on, the quantization noise signal controls the reference selection unit to output only the first reference clock; At this time, the digital time conversion module adjusts the delay of the first reference clock according to the quantized noise signal and outputs the third reference clock; The deviation compensation module compares the third reference clock and the second reference clock, and outputs a delay adjustment signal to the digital time conversion module based on the comparison result; The digital time conversion module corrects its own delay range to the first phase difference according to the delay adjustment signal, and the delay adjustment signal is proportional to the delay range of the digital time conversion module.

9. A fractional phase-locked loop, characterized in that, include: The digital time converter according to any one of claims 1 to 6, wherein the digital time converter outputs a third reference clock or a fourth reference clock based on a quantized noise signal; A sampling phase detector is used to sample and compare the feedback clock signal with the third reference clock or the fourth reference clock, and output a phase mis-touch signal; A loop filter is used to filter out high-frequency noise in the phase mis-trigger signal and output a control voltage; A voltage-controlled oscillator is used to output a target frequency signal according to the control voltage, the frequency of the target frequency signal being equal to the frequency of the initial reference clock; A multi-mode frequency divider is used to divide and switch the target frequency signal according to the sequence quantization noise signal, and output the feedback clock signal; A differential integral modulator is used to output the sequence quantized noise signal and the quantized noise signal according to a preset fractional allocation of the quantized noise signal.

10. An electronic device, characterized in that, Including the fractional phase-locked loop as described in claim 9.

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