Conversion method and device for successive approximation analog-to-digital converter, electronic equipment and storage medium

Abstract

The invention provides a conversion method and device for a successive approximation analog-to-digital converter, electronic equipment and a storage medium, the successive approximation analog-to-digital converter comprises a comparator, a converter and a capacitor array, the resolution of the successive approximation analog-to-digital converter is N, and the number of capacitors of the capacitor array is N; the method comprises the steps that high-order capacitors and low-order capacitors of a capacitor array are determined, the high-order capacitors comprise m capacitors, and the low-order capacitors comprise n capacitors; determining a first comparison result according to the m capacitors and the comparator, and converting the first comparison result into a first code value through the converter according to a first conversion algorithm; determining a second comparison result according to the n capacitors and the comparator, and converting the second comparison result into a second code value through the converter according to a second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm; and determining a target code value according to the first code value and the second code value. By adopting the application, the conversion precision of the successive approximation analog-to-digital converter can be improved.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuits, and more particularly to a conversion method, apparatus, electronic device, and storage medium for a successive approximation analog-to-digital converter. Background Technology

[0002] Currently, analog-to-digital conversion (ADC) is an important part of the field of electronic devices, especially the successive approximation register analog-to-digital converter (SAR ADC), which is a classic architecture in the field of ADC. Its core achieves accurate conversion of continuous analog signals to discrete digital signals through the coordinated work of successive approximation logic and registers.

[0003] Under normal circumstances, successive approximation analog-to-digital converters (such as successive approximation register-type analog-to-digital converters) are widely used in industrial control, medical electronics, portable devices, IoT terminals, and automotive-grade data acquisition scenarios due to their core advantages of medium-to-high accuracy (8~18 bits), moderate conversion speed (100kSps~10MSps), low power consumption, and small chip area. They are especially suitable for latency-sensitive applications such as multiplexed signal acquisition and fast feedback closed-loop control. However, the conversion accuracy of successive approximation analog-to-digital converters is limited in existing technologies. Therefore, the problem of how to improve the conversion accuracy of successive approximation analog-to-digital converters urgently needs to be solved. Summary of the Invention

[0004] This application provides a conversion method, apparatus, electronic device, and storage medium for a successive approximation analog-to-digital converter, which can improve the conversion accuracy of the successive approximation analog-to-digital converter.

[0005] First, this application provides a conversion method for a successive approximation analog-to-digital converter (ADC), applied to an electronic device. The electronic device includes a successive approximation ADC, which comprises a comparator, a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1. The method includes: The high-order capacitors and low-order capacitors of the capacitor array are determined. The high-order capacitors include m capacitors, and the low-order capacitors include n capacitors. The sum of m and n is N, and m and n are both positive integers. A first comparison result is determined based on the m capacitors and the comparator, and the first comparison result is converted into a first code value by the converter according to the first conversion algorithm. A second comparison result is determined based on the n capacitors and the comparator, and the second comparison result is converted into a second code value by the converter according to the second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm. The target code value is determined based on the first code value and the second code value.

[0006] Secondly, this application provides a conversion device for a successive approximation analog-to-digital converter (ADC), applied to an electronic device. The electronic device includes a successive approximation ADC, which includes a comparator, a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1. The device includes: The first determining unit is used to determine the high-order capacitors and low-order capacitors of the capacitor array, wherein the high-order capacitors include m capacitors and the low-order capacitors include n capacitors; the sum of m and n is N, and m and n are both positive integers. The first conversion unit is used to determine a first comparison result based on the m capacitors and the comparator, and convert the first comparison result into a first code value through the converter according to the first conversion algorithm. The second conversion unit is used to determine a second comparison result based on the n capacitors and the comparator, and convert the second comparison result into a second code value through the converter according to a second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm. The second determining unit is used to determine the target code value based on the first code value and the second code value.

[0007] Then, this application provides an electronic device, which includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing the steps in the first aspect of this application.

[0008] Finally, embodiments of this application provide a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform some or all of the steps described in the first aspect of embodiments of this application.

[0009] The embodiments of this application have the following beneficial effects: By implementing the conversion method, apparatus, electronic device, and storage medium for successive approximation analog-to-digital converters (ADCs) in the embodiments of this application, applied to an electronic device, the electronic device includes a successive approximation ADC, the successive approximation ADC includes a comparator and a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1. The high-order capacitors and low-order capacitors of the capacitor array are determined. The high-order capacitors include m capacitors, and the low-order capacitors include n capacitors; the sum of m and n is N, and m and n are both positive integers. A first comparison result is determined based on the m capacitors and the comparator. The first comparison result is converted into a first code value by the converter according to a first conversion algorithm. A second comparison result is determined based on the n capacitors and the comparator. The second comparison result is converted into a second code value by the converter according to a second conversion algorithm. The first conversion algorithm and the second conversion algorithm are different. The target code value is determined based on the first code value and the second code value, which can prevent several high-order (e.g., three to four) capacitors from participating in the transition, thereby greatly reducing the accumulated capacitor mismatch value and improving the accuracy of ADC conversion. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic flowchart of a charge redistribution method for a SAR ADC provided in an embodiment of this application; Figure 2 This is a waveform demonstration diagram provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a temperature code skipping method introduced in the conversion process according to an embodiment of this application; Figure 4 This is a schematic flowchart of a conversion method for a successive approximation analog-to-digital converter provided in an embodiment of this application; Figure 5 This is another waveform demonstration diagram provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application; Figure 8 This is a schematic flowchart of a conversion method for a successive approximation analog-to-digital converter provided in an embodiment of this application; Figure 9This is a schematic diagram of a conversion device for a successive approximation analog-to-digital converter provided in an embodiment of this application. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0013] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0014] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, "multiple" refers to two or more.

[0015] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.

[0016] In this embodiment of the application, MSB conversion can be understood as processing or conversion related to the most significant bit. For example, in an analog-to-digital converter (ADC), the MSB is the first bit sent out, representing the bit with the greatest weight in the digital quantity, and has the greatest impact on the value. In related technologies, the basic working principle of SAR ADCs is as follows: Using a stable reference voltage as a benchmark, a successive approximation register (SAR) generates a series of digital test values ​​according to a binary weighted sequence. These test values ​​are then converted into corresponding analog comparison voltages by an on-chip digital-to-analog converter (DAC, often charge-redistribution type). Subsequently, a high-speed comparator compares this analog comparison voltage bit-by-bit with the original input analog signal, dynamically adjusting the logic state (0 or 1) of each bit of the test value based on the comparison result. Finally, after N comparison iterations (N being the output digital signal bit width), an N-bit digital signal matching the input analog signal is output. Compared to pipelined ADCs, SAR ADCs do not require complex multi-stage parallel processing structures, resulting in a simpler hardware architecture. Compared to flash memory ADCs, they do not require comparator arrays that grow exponentially with resolution, significantly reducing device area and power consumption. Compared to integral-differential (Sigma-Delta) ADCs, SAR ADCs do not require oversampling to reduce conversion speed, nor do they require complex digital filters. In summary, SAR ADCs exhibit significant competitive advantages in balancing accuracy, speed, power consumption, and cost.

[0017] The core digital-to-analog converter (DAC) of SAR ADCs often employs a charge redistribution architecture. This architecture uses a binary weighted capacitor array as its core, converting digital probe values ​​into analog voltages through the charging and discharging of capacitors and the redistribution of charge. Essentially, it compares the charge of the input analog signal with the reference charge stored in the capacitor array. The accuracy and matching degree of the capacitor values ​​directly determine the accuracy of charge distribution. Ideally, the capacitance values ​​of each weighted capacitor must strictly adhere to a binary ratio (e.g., 1C, 2C, 4C, ..., 2ⁿ⁻¹C, where C is the capacitance value and n is the ADC resolution), and the temperature coefficient and voltage coefficient of capacitors from the same batch must be consistent to ensure that the analog comparison voltage output by the DAC accurately corresponds to the digital probe value.

[0018] Among these factors, capacitor mismatch directly leads to the deterioration of several key performance characteristics: First, it causes nonlinear deviations in the DAC output voltage, which in turn introduces integral nonlinearity error (INL) and differential nonlinearity error (DNL), directly reducing the conversion accuracy and linearity of the ADC, and in severe cases, causing missing output digital codes; Second, the dispersion of capacitor values ​​exacerbates charge injection and recoil effects, and the parasitic parameter effects brought about by switching actions lead to a decrease in the comparator's decision accuracy, especially in high-resolution (12-bit and above) scenarios, where even a 0.1% capacitor mismatch may cause the error to exceed the design tolerance; Third, environmental factors such as temperature changes and power supply fluctuations amplify the impact of capacitor mismatch, leading to increased temperature drift and decreased long-term stability of the ADC, making it unable to meet the reliability requirements of demanding scenarios such as industrial control and automotive electronics.

[0019] In relevant SAR ADC methods, capacitance matching is a core component for ensuring conversion accuracy. Mainstream approaches fall into three categories: First, relying on high-precision manufacturing processes, which significantly increases chip manufacturing costs and is limited by process limitations; second, adding additional calibration circuitry to dynamically detect and compensate for capacitance mismatch, improving accuracy but increasing chip area and power consumption; and third, employing special circuit design techniques, such as temperature codes for high-order capacitors or dynamic element matching (DEM) technology. Temperature codes are the most common design technique used in high-precision SAR ADCs to improve capacitance matching. DEM, however, is less commonly used due to its complexity and slow speed.

[0020] This application introduces a novel Thermometer Skip Code (TSK) conversion method based on relevant charge redistribution methods to further improve capacitor matching. Typically, the minimum code value is 0000… (N zeros), the maximum is 1111… (N ones), the median is 01111… (N-1 ones) and 1000… (N-1 zeros), and the highest bit is the sign bit. The maximum linearity error occurs when the input differential signal is near 0 voltage, specifically during the transition between 01111… (N-1 ones) and 1000… (N-1 zeros), as the accumulated capacitor mismatch is greatest in this case. The TSK conversion method, through skip code technology, prevents several high-order capacitors (usually three to four bits) from participating in the transition between 01111… (N-1 ones) and 1000… (N-1 zeros), thereby significantly reducing the accumulated capacitor mismatch and improving the accuracy of the ADC conversion.

[0021] In related technologies, such as Figure 1 The diagram shows a flowchart of the charge redistribution method for a SAR ADC. First, a sampling operation is performed, loading the input analog voltage VIN onto the DAC capacitor array (i.e., VDAC = VIN), and simultaneously initializing the bit index i = N (corresponding to the most significant bit N). Then, a bit-by-bit iteration begins. A comparator compares VDAC with 0. If VDAC > 0, the current bit b_i is set to 1, and VDAC is updated to "VDAC − VS_i" through charge redistribution, where VS_i (i = N~1) represents the absolute value of the voltage step in VDAC caused by the i-th capacitor flipping to VREF or GND. If VDAC < 0, b_i is set to 0, and VDAC is updated to "VDAC + VS_i". After processing the current bit, the bit index i is decremented by 1, and the comparison and conversion process is repeated until i = 0, at which point the ADC operation ends, ultimately outputting a complete N-bit digital code.

[0022] For example, taking a 3-bit SAR ADC, the capacitances of the weighted capacitors from the most significant bit N, the second most significant bit (N-1), to the least significant bit 1 are 4C, 2C, and 1C respectively. An additional sampling capacitor C is added, making the total capacitance 8C. Thus, due to the capacitor switching, the resulting VDAC voltage steps are VREF*(4C / 8C), VREF*(2C / 8C), and VREF*(1C / 8C), satisfying... Figure 1 The formula for the intermediate transformation stage is VREF / 2^(i+1).

[0023] Furthermore, typical waveforms of charge redistribution methods in related technologies are as follows: Figure 2 As shown in (a) and (b). In Figure 2 In (a), the input signal VIN is a negative voltage, and its absolute value is much smaller than VS_N. After sampling, the voltage of VDAC is equal to VIN and less than 0. The comparator determines the first result b_N=1. During the conversion stage, the voltage of VDAC is increased by the voltage of VS_i, VS_i = VREF*(4C / 8C), that is, VIN+VS_i=VIN+VREF*1 / 2. Since the absolute value of VIN is much smaller than VS_i, VIN+VS_i>0, the comparator determines the second result b_N-1=0, and the voltage of VDAC needs to be reduced by the voltage of V(N-1), that is, VIN+VS_i-V(N-1). Since the absolute value of VIN is much smaller than VS_N, and V(N-1)=VREF*(2C / 8C), VIN+VS_i-V(N-1)=VIN+VREF*1 / 2-VREF*1 / 4>0, the comparator determines the third result b_1-1=0. The ADC operation ends, and the result is 100. The final voltage of VDAC is close to, but slightly greater than, 0.

[0024] Furthermore, in Figure 2 In (b), the input signal VIN is a negative voltage with an absolute value slightly greater than VS_N. After sampling, the comparator determines the first result b_N=1, adding the voltage VS_i to the VDAC voltage, resulting in VIN+VS_i. Since the absolute value of VIN is slightly greater than VS_N, VIN+VS_i= VIN+VREF*1 / 2<0. The comparator determines the second result b_N-1=1, adding the voltage V(N-1) to the VDAC voltage, resulting in VIN+VS_i+V(N-1). Since the absolute value of VIN is only slightly greater than VS_N, VIN+VS_i+V(N-1)= VIN+VREF*1 / 2+ VIN+VREF*1 / 4 >0, and the comparator determines the second result b_1=0. The ADC operation ends, and the result is 110. The final voltage of VDAC is still close to but slightly greater than 0.

[0025] Furthermore, such as Figure 3As shown, this application introduces a Thermometer Skip Code (TSK conversion method) in the conversion process. Its sampling and conversion process for the most significant bit N is the same as the charge redistribution method in related technologies. First, a sampling operation is performed, loading the input analog voltage VIN onto the DAC capacitor array (i.e., VDAC = VIN), and simultaneously initializing the bit index i = N (corresponding to the most significant bit N). Then, a comparator compares VDAC with 0. If VDAC > 0, the current bit b_N is set to 1, and VDAC is updated to "VDAC − VS_N" through charge redistribution; if VDAC < 0, b_N is set to 0, and VDAC is simultaneously updated to "VDAC + VS_N". Then, the next stage begins. The bit index i is decremented by 1, and the next round of comparison and conversion begins. It is necessary to determine whether the comparator result b_(N-1) is the same as the first round result b_N: if they are different, the ADC operation ends; if they are the same, the next round of comparison and conversion continues until the bit index i = 0.

[0026] The TSK conversion method is typically sufficient to apply only to the high-order capacitors, as the error sources of high-precision SAR ADCs are primarily located in these capacitors. For example, for a 14-bit SAR ADC, the TSK conversion method is applied only to the three highest capacitors, while the charge redistribution method from related technologies is still used for the lower nine capacitors, thereby simplifying the overall conversion logic of the SAR ADC. Figure 4 Flowcharts are provided for the high 4-bit capacitor using the TSK conversion method and the low 4-bit capacitor using the charge redistribution conversion method from related technologies.

[0027] To illustrate further, continuing with a 3-bit SAR ADC, the capacitances of the weighted capacitors from the most significant bit N, the second most significant bit (N-1) to the least significant bit 1 remain 4C, 2C, and 1C respectively, plus a sampling capacitor C, for a total capacitance of 8C. All capacitances are split into seven 1C capacitors and one sampling 1C capacitor, and the function is achieved through a variable number of conversions (from 2 to 5), instead of the original fixed three conversions.

[0028] Among them, Figure 5In (a), the input signal VIN is a negative voltage, with an absolute value much smaller than VS_N. After sampling, the voltage of VDAC is equal to VIN and less than 0. The comparator determines the first result b_N=1. Since the highest-order 4C capacitor has been split into four 1C capacitors, the VDAC voltage is not increased by the VS_N voltage, but by one-quarter of the VS_N voltage. Since the absolute value of VIN is much smaller than VS_N, VIN+VS_N / 4=VIN+VREF*1 / 8 >0, and the comparator determines the second result b_N-1=0. Since b_N-1 has the opposite sign to b_N, the ADC operation ends, and b_1 is directly set to 0. Only two conversions are performed, and most capacitors do not have a jump action, so they do not contribute to the mismatch error.

[0029] Typically, the minimum code value is 0000… (N zeros), the maximum value is 1111… (N ones), the intermediate values ​​are 01111… (N-1 ones) and 1000… (N-1 zeros), and the highest bit of the code value is the sign bit. The maximum linearity error occurs when the input differential signal is near 0 voltage, i.e., the transition between 01111… (N-1 ones) and 1000… (N-1 zeros). The TSK conversion method reduces the conversion error for code values ​​near 01111… (N-1 ones) and 1000… (N-1 zeros) due to the reduction in the number of participating capacitors.

[0030] Among them, Figure 5 In (b), the input signal VIN is a negative voltage with an absolute value slightly greater than VS_N. The comparator determines the first result b_N=1, and adds one-quarter of the VS_N voltage to the VDAC voltage. Since the absolute value of VIN is slightly greater than VS_N, VIN+VS_N / 4= VIN+VREF*1 / 8<0. The comparator determines the second result b_N-1=1, and VIN+VS_N / 4+VS_N / 4= VIN+VREF*1 / 4<0, continuing to be less than 0. The conversion continues. Until VIN+VS_N / 4+VS_N / 4+VS_N / 4+VS_N / 4+VS_(N-1) / 2= VIN+VREF*5 / 8>0, a total of 5 conversions have been performed. For easier understanding, please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device includes a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a comparator and a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1.

[0031] The electronic device may include a successive approximation analog-to-digital converter.

[0032] The successive approximation analog-to-digital converter (ADC) may include a comparator and a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1. The comparator and converter, and the capacitor array may be electrically connected and / or communicatively connected.

[0033] Furthermore, the following will be combined with Figure 7 The electronic devices in the embodiments of this application will be described. Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device includes one or more processors, a memory, a communication interface, and one or more programs. The processor is connected to the memory and the communication interface through an internal communication bus. The electronic device also includes a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a comparator, a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1.

[0034] It is understood that the electronic device may include more or fewer structural elements than those shown in the above block diagram. For example, the electronic device may also include at least one of the following modules, such as a Bluetooth module, a sensor, a Wi-Fi module, a power module, physical buttons, a speaker, a display module, etc., without limitation.

[0035] The processor can be used for: The high-order capacitors and low-order capacitors of the capacitor array are determined. The high-order capacitors include m capacitors, and the low-order capacitors include n capacitors. The sum of m and n is N, and m and n are both positive integers. A first comparison result is determined based on the m capacitors and the comparator, and the first comparison result is converted into a first code value by the converter according to the first conversion algorithm. A second comparison result is determined based on the n capacitors and the comparator, and the second comparison result is converted into a second code value by the converter according to the second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm. The target code value is determined based on the first code value and the second code value.

[0036] In this embodiment, several high-order capacitors (e.g., three to four) can be excluded from the transition, thereby greatly reducing the accumulated capacitor mismatch value and improving the accuracy of ADC conversion.

[0037] The one or more programs are stored in the aforementioned memory and configured to be executed by the aforementioned processor, and the one or more programs include instructions for performing any step in the above method embodiments.

[0038] The processor can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a general-purpose processor, a digital signal processor (DSP), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0039] Furthermore, the processor can also implement or execute various exemplary logic blocks, units, and circuits described in conjunction with the disclosure of this application. Additionally, the processor can also be a combination of components implementing computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc. Communication units can be communication interfaces, transceivers, transceiver circuits, etc., and storage units can be memory.

[0040] The memory can be volatile or non-volatile, or may include both. The non-volatile memory can be a programmable read-only memory (PROM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or flash memory.

[0041] Furthermore, the volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), static RAM (SRAM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The following is combined Figure 8This application describes a conversion method for a successive approximation analog-to-digital converter (ADC). Figure 8 This is a flowchart illustrating a conversion method for a successive approximation analog-to-digital converter (ADC) according to an embodiment of this application. Applied to an electronic device, the electronic device includes a successive approximation ADC, which comprises a comparator, a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1. The conversion method for the successive approximation ADC specifically includes the following steps: S801: Determine the high-order capacitors and low-order capacitors of the capacitor array, wherein the high-order capacitors include m capacitors and the low-order capacitors include n capacitors; the sum of m and n is N, and m and n are both positive integers; The values ​​of m and n can be preset or set by the system default. m + n = N.

[0042] The allocation of m and n can be related to the attributes of the successive approximation analog-to-digital converter. For example, different models have different allocations of m and n. Alternatively, the allocation of m and n can be related to the application scenario of the successive approximation analog-to-digital converter. Different application scenarios require different levels of precision, so m and n can be allocated accordingly based on different application scenarios.

[0043] S802: Determine a first comparison result based on the m capacitors and the comparator, and convert the first comparison result into a first code value using the converter according to a first conversion algorithm.

[0044] In practice, the higher bits can be compared and transformed first to obtain the corresponding first code value. The first code value can include multiple code values; the number of higher bits corresponds to the number of code values.

[0045] S803: Determine a second comparison result based on the n capacitors and the comparator, and convert the second comparison result into a second code value using the converter according to the second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm.

[0046] The first conversion algorithm is different from the second conversion algorithm.

[0047] In the specific implementation, the lower bits can be compared and transformed to obtain the corresponding second code value. The second code value can include multiple code values; the number of lower bits corresponds to the number of code values.

[0048] S804: Determine the target code value based on the first code value and the second code value.

[0049] Since the first code value corresponds to the high bit and the second code value corresponds to the low bit, the first code value and the second code value can be concatenated to obtain the target code value.

[0050] By implementing the conversion method for a successive approximation analog-to-digital converter (ADC) in the embodiments of this application, applied to an electronic device, the electronic device includes a successive approximation ADC, which includes a comparator, a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N, where N is an integer greater than 1. The high-order capacitors and low-order capacitors of the capacitor array are determined, with m high-order capacitors and n low-order capacitors, where the sum of m and n is N, and both m and n are positive integers. A first comparison result is determined based on the m capacitors and the comparator. The converter converts the first comparison result into a first code value according to a first conversion algorithm. A second comparison result is determined based on the n capacitors and the comparator. The converter converts the second comparison result into a second code value according to a second conversion algorithm. The first conversion algorithm and the second conversion algorithm are different. By determining the target code value based on the first code value and the second code value, several high-order capacitors (e.g., three to four bits) can be excluded from transitions, thereby greatly reducing the accumulated capacitor mismatch value and improving the accuracy of ADC conversion.

[0051] Optionally, the first conversion algorithm includes a temperature code skipping algorithm; the second conversion algorithm includes a charge redistribution algorithm.

[0052] The maximum linearity error occurs when the input differential signal is near 0 voltage, specifically during the transition between 01111… (N-1 ones) and 1000… (N-1 zeros), because the accumulated capacitance mismatch is greatest in this case. The TSK conversion method uses hopping code technology to prevent several high-order capacitors (usually three to four bits) from participating in the transition between 01111… (N-1 ones) and 1000… (N-1 zeros), thereby greatly reducing the accumulated capacitance mismatch and improving the accuracy of ADC conversion.

[0053] Optionally, the above steps for determining the first comparison result based on the m capacitors and the comparator can be implemented in the following manner: For each bit corresponding to the m capacitors, perform the following operations A1-A3 to obtain m first results: A sampling operation is performed to obtain a first analog voltage; the first analog voltage is the analog voltage of any one of the m capacitors; The first analog voltage is applied to the corresponding bit in the capacitor array; The comparator compares whether the first analog voltage is greater than 0. If yes, set the highest bit to 1 and use 1 as the first result corresponding to that bit; if no, set the highest bit to 0 and use 0 as the first result corresponding to that bit. The first comparison result is determined based on the n first results.

[0054] In the specific implementation, firstly, a sampling operation is performed, loading the input analog voltage VIN into the DAC capacitor array (i.e., VDAC = VIN), and simultaneously initializing the bit index i = N (corresponding to the most significant bit N). Then, a bit-by-bit iteration is initiated. A comparator is used to determine the magnitude of VDAC compared to 0; if VDAC > 0, the current bit b_i is set to 1.

[0055] Optionally, the above step, in which the converter transforms the first comparison result into a first code value according to the first conversion algorithm, can be implemented in the following manner: Determine the target first result corresponding to the highest bit in the first comparison result; Obtain the absolute value of the first voltage step of the highest bit; the absolute value of the first voltage step is used to represent the absolute voltage step of VDAC caused by the capacitor of the highest bit flipping to VREF or flipping to GND potential; The first code value corresponding to the highest bit is determined based on the target first result, the first analog voltage corresponding to the highest bit, and the absolute value of the first voltage step. For the first result corresponding to the capacitors among the m capacitors excluding the most significant bit, the following operation is performed: Determine the reference first result corresponding to the a-th bit in the first comparison result; the a-th bit is any bit corresponding to any of the m capacitors except the highest bit; Obtain the first preset voltage value; The first code value corresponding to the a-th bit is determined based on the target first result, the first analog voltage corresponding to the highest bit, and the first preset voltage value.

[0056] The first preset voltage value can be preset or set by system default. For example, the first preset voltage value can be equal to the absolute value of the first voltage step.

[0057] Specifically, for the first code value corresponding to the highest bit, when the target first result is 1, the first code value corresponding to the highest bit is obtained by converting the difference between the absolute value of the first analog voltage and the first voltage step corresponding to the highest bit; conversely, when the target first result is 0, the first code value corresponding to the highest bit is obtained by converting the sum of the absolute value of the first analog voltage and the first voltage step corresponding to the highest bit.

[0058] Specifically, for the first code value corresponding to the non-highest bit, when the target first result is 1, the first code value corresponding to the non-highest bit is obtained by converting the difference between the first analog voltage corresponding to the non-highest bit and the first preset voltage value; conversely, when the target first result is 0, the first code value corresponding to the non-highest bit is obtained by converting the sum of the first analog voltage corresponding to the non-highest bit and the first preset voltage value.

[0059] In specific implementation, combined with Figure 3 This application introduces a temperature code skipping method in the conversion process, and its sampling and conversion process of the most significant bit N is the same as the charge redistribution method in related technologies. First, a sampling operation is performed, loading the input analog voltage VIN onto the DAC capacitor array (i.e., VDAC=VIN), and simultaneously initializing the bit index i=N (corresponding to the most significant bit N). Then, the comparator determines the magnitude of VDAC and 0. If VDAC>0, the current bit b_N is set to 1, and VDAC is updated to "VDAC−VS_N" through charge redistribution; if VDAC<0, b_N is set to 0, and VDAC is updated to "VDAC+VS_N". Then, the next stage begins. The bit index i is decremented by 1, and the next round of comparison and conversion begins. It is necessary to determine whether the comparator result b_(N-1) is the same as the result b_N of the first round: if they are different, the ADC operation ends; if they are the same, the next round of comparison and conversion continues until the bit index i=0.

[0060] The TSK conversion method is typically sufficient to apply only to the high-order capacitors, as the error sources of high-precision SAR ADCs are primarily located in these capacitors. For example, for a 14-bit SAR ADC, the TSK conversion method is applied only to the three highest capacitors, while the charge redistribution method from related technologies is still used for the lower nine capacitors, thereby simplifying the overall conversion logic of the SAR ADC. Figure 4 Flowcharts are provided for the high 4-bit capacitor using the TSK conversion method and the low 4-bit capacitor using the charge redistribution conversion method from related technologies.

[0061] To illustrate further, continuing with a 3-bit SAR ADC, the capacitances of the weighted capacitors from the most significant bit N, the second most significant bit (N-1) to the least significant bit 1 remain 4C, 2C, and 1C respectively, plus a sampling capacitor C, for a total capacitance of 8C. All capacitances are split into seven 1C capacitors and one sampling 1C capacitor, and the function is achieved through a variable number of conversions (from 2 to 5), instead of the original fixed three conversions.

[0062] Among them, Figure 5In (a), the input signal VIN is a negative voltage, with an absolute value much smaller than VS_N. After sampling, the voltage of VDAC is equal to VIN and less than 0. The comparator determines the first result b_N=1. Since the highest-order 4C capacitor has been split into four 1C capacitors, the VDAC voltage is not increased by the VS_N voltage, but by one-quarter of the VS_N voltage. Since the absolute value of VIN is much smaller than VS_N, VIN+VS_N / 4=VIN+VREF*1 / 8 >0, and the comparator determines the second result b_N-1=0. Since b_N-1 has the opposite sign to b_N, the ADC operation ends, and b_1 is directly set to 0. Only two conversions are performed, and most capacitors do not have a jump action, so they do not contribute to the mismatch error.

[0063] Typically, the minimum code value is 0000… (N zeros), the maximum value is 1111… (N ones), the intermediate values ​​are 01111… (N-1 ones) and 1000… (N-1 zeros), and the highest bit of the code value is the sign bit. The maximum linearity error occurs when the input differential signal is near 0 voltage, i.e., the transition between 01111… (N-1 ones) and 1000… (N-1 zeros). The TSK conversion method reduces the conversion error for code values ​​near 01111… (N-1 ones) and 1000… (N-1 zeros) due to the reduction in the number of participating capacitors.

[0064] Among them, Figure 5 In (b), the input signal VIN is a negative voltage with an absolute value slightly greater than VS_N. The comparator determines the first result b_N=1, and adds one-quarter of the VS_N voltage to the VDAC voltage. Since the absolute value of VIN is slightly greater than VS_N, VIN+VS_N / 4= VIN+VREF*1 / 8<0. The comparator determines the second result b_N-1=1, and VIN+VS_N / 4+VS_N / 4= VIN+VREF*1 / 4<0, continuing to be less than 0. The conversion continues. Until VIN+VS_N / 4+VS_N / 4+VS_N / 4+VS_N / 4+VS_(N-1) / 2= VIN+VREF*5 / 8>0, a total of 5 conversions have been performed.

[0065] Optionally, the above step of determining the second comparison result based on the n capacitors and the comparator can be implemented in the following manner: For each bit corresponding to the n capacitors, perform the following operations B1-B3 to obtain n second results: A sampling operation is performed to obtain a second analog voltage; the second analog voltage is the analog voltage of any one of the n capacitors; The second analog voltage is applied to the corresponding bit of the capacitor array; The comparator compares whether the second analog voltage is greater than 0. If yes, set the highest bit to 1 and use 1 as the second result corresponding to that bit; if no, set the highest bit to 0 and use 0 as the second result corresponding to that bit. The second comparison result is determined based on the n second results.

[0066] In the specific implementation, firstly, a sampling operation is performed, loading the input analog voltage VIN into the DAC capacitor array (i.e., VDAC = VIN), and simultaneously initializing the bit index i = X (corresponding to the highest relative bit of the n capacitors). Then, bit-by-bit iteration begins. A comparator compares VDAC with 0; if VDAC > 0, the current bit b_i is set to 1.

[0067] Optionally, the above step of converting the second comparison result into a second code value using the converter according to the second conversion algorithm can be implemented in the following manner: Determine the target second result corresponding to the b-th bit in the second comparison result; the b-th bit is the corresponding bit of any one of the n capacitors; Determine the second preset voltage value of the b-th bit; The second code value corresponding to the b-th bit is determined based on the target second result, the second analog voltage, and the second preset voltage value.

[0068] Specifically, when the target second result is 1, the second code value corresponding to the b-th bit is obtained by converting the difference between the second analog voltage and the second preset voltage value; conversely, when the target second result is 0, the second code value corresponding to the b-th bit is obtained by converting the sum between the second analog voltage and the second preset voltage value.

[0069] In the specific implementation, firstly, a sampling operation is performed, loading the input analog voltage VIN into the DAC capacitor array (i.e., VDAC = VIN), and simultaneously initializing the bit index i = N (corresponding to the most significant bit N). Then, a bit-by-bit iteration begins. A comparator compares VDAC with 0. If VDAC > 0, the current bit b_i is set to 1, and VDAC is updated to "VDAC − VS_i" through charge redistribution, where VS_i (i = N~1) represents the absolute value of the voltage step in VDAC caused by the i-th capacitor flipping to VREF or GND. If VDAC < 0, b_i is set to 0, and VDAC is simultaneously updated to "VDAC + VS_i". After processing the current bit, the bit index i is decremented by 1, and the comparison and conversion process is repeated until i = 0, at which point the ADC operation ends, ultimately outputting a complete N-bit digital code.

[0070] For example, taking a 3-bit SAR ADC, the capacitances of the weighted capacitors from the most significant bit N, the second most significant bit (N-1), to the least significant bit 1 are 4C, 2C, and 1C respectively. An additional sampling capacitor C is added, making the total capacitance 8C. Thus, due to the capacitor switching, the resulting VDAC voltage steps are VREF*(4C / 8C), VREF*(2C / 8C), and VREF*(1C / 8C), satisfying... Figure 1 The formula for the intermediate transformation stage is VREF / 2^(i+1).

[0071] Optionally, the above step of determining the second preset voltage value of the b-th bit can be implemented in the following manner: Determine the reference voltage of the successive approximation analog-to-digital converter; The second preset voltage value of the b-th bit is determined based on the reference voltage.

[0072] Wherein, the second preset voltage value = VREF / 2^(i+1), VREF is the reference voltage of the successive approximation analog-to-digital converter, and i is the i-th bit. Figure 9 This is a schematic diagram of the structure of a conversion device 900 for a successive approximation analog-to-digital converter (ADC) according to an embodiment of this application. The conversion device 900 is applied to an electronic device, which includes a successive approximation ADC. The successive approximation ADC includes a comparator and a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N; N is an integer greater than 1. The conversion device 900 includes: The first determining unit 910 is used to determine the high-order capacitors and low-order capacitors of the capacitor array, wherein the high-order capacitors include m capacitors and the low-order capacitors include n capacitors; the sum of m and n is N, and m and n are both positive integers. The first conversion unit 920 is used to determine a first comparison result based on the m capacitors and the comparator, and convert the first comparison result into a first code value through the converter according to the first conversion algorithm. The second conversion unit 930 is used to determine a second comparison result based on the n capacitors and the comparator, and convert the second comparison result into a second code value through the converter according to a second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm. The second determining unit 940 is used to determine the target code value based on the first code value and the second code value.

[0073] It is understood that the functions of each program module of the conversion device for successive approximation analog-to-digital converter in this embodiment can be specifically implemented according to the methods in the above method embodiments. The specific implementation process can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here. This application also provides a computer-readable storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments, wherein the computer includes an electronic device.

[0074] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer may include an electronic device.

[0075] It should be noted that, for the sake of simplicity, the above embodiments are all described as a series of actions. Those skilled in the art should understand that this application is not limited to the described order of actions, as some steps in the embodiments of this application can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions, steps, modules, or units involved are not necessarily essential to the embodiments of this application.

[0076] In the above embodiments, the descriptions of each embodiment in this application have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0077] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0078] The steps of the methods or algorithms described in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in RAM, flash memory, ROM, EPROM, electrically erasable programmable read-only memory (EEPROM), registers, hard disk, portable hard disk, read-only optical disk (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Furthermore, the ASIC can reside in a terminal device or management device. Alternatively, the processor and storage medium can exist as discrete components in the terminal device or management device.

[0079] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in the embodiments of this application can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0080] The modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both. For example, for devices and products applied to or integrated into a chip, all modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits. For devices and products applied to or integrated into a chip module, all modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The implementation is achieved through a software program that runs on the processor integrated within the chip module. The remaining modules / units (if any) can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into terminal equipment, each of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal equipment. Alternatively, at least some modules / units can be implemented through a software program that runs on the processor integrated within the terminal equipment, while the remaining modules / units (if any) can be implemented using hardware methods such as circuits.

[0081] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above descriptions are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A conversion method for a successive approximation analog-to-digital converter, characterized in that, The method is applied to an electronic device, which includes a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a comparator and a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N. N is an integer greater than 1; the method includes: The high-order capacitors and low-order capacitors of the capacitor array are determined. The high-order capacitors include m capacitors, and the low-order capacitors include n capacitors. The sum of m and n is N, and m and n are both positive integers. A first comparison result is determined based on the m capacitors and the comparator, and the first comparison result is converted into a first code value by the converter according to the first conversion algorithm. A second comparison result is determined based on the n capacitors and the comparator, and the second comparison result is converted into a second code value by the converter according to the second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm. The target code value is determined based on the first code value and the second code value.

2. The method as described in claim 1, characterized in that, The first conversion algorithm includes a temperature code skipping algorithm; the second conversion algorithm includes a charge redistribution algorithm.

3. The method as described in claim 1 or 2, characterized in that, The step of determining the first comparison result based on the m capacitors and the comparator includes: For each bit corresponding to the m capacitors, perform the following operations A1-A3 to obtain m first results: A sampling operation is performed to obtain a first analog voltage; the first analog voltage is the analog voltage of any one of the m capacitors; The first analog voltage is applied to the corresponding bit in the capacitor array; The comparator compares whether the first analog voltage is greater than 0. If yes, set the highest bit to 1 and use 1 as the first result corresponding to that bit; if no, set the highest bit to 0 and use 0 as the first result corresponding to that bit. The first comparison result is determined based on the n first results.

4. The method as described in claim 3, characterized in that, The step of converting the first comparison result into a first code value using the converter according to the first conversion algorithm includes: Determine the target first result corresponding to the highest bit in the first comparison result; Obtain the absolute value of the first voltage step of the highest bit; the absolute value of the first voltage step is used to represent the absolute voltage step of VDAC caused by the capacitor of the highest bit flipping to VREF or flipping to GND potential; The first code value corresponding to the highest bit is determined based on the target first result, the first analog voltage corresponding to the highest bit, and the absolute value of the first voltage step. For the first result corresponding to the capacitors among the m capacitors excluding the most significant bit, the following operation is performed: Determine the reference first result corresponding to the a-th bit in the first comparison result; the a-th bit is any bit corresponding to any of the m capacitors except the highest bit; Obtain the first preset voltage value; The first code value corresponding to the a-th bit is determined based on the target first result, the first analog voltage corresponding to the highest bit, and the first preset voltage value.

5. The method as described in claim 1 or 2, characterized in that, Determining the second comparison result based on the n capacitors and the comparator includes: For each bit corresponding to the n capacitors, perform the following operations B1-B3 to obtain n second results: A sampling operation is performed to obtain a second analog voltage; the second analog voltage is the analog voltage of any one of the n capacitors; The second analog voltage is applied to the corresponding bit of the capacitor array; The comparator compares whether the second analog voltage is greater than 0. If yes, set the highest bit to 1 and use 1 as the second result corresponding to that bit; if no, set the highest bit to 0 and use 0 as the second result corresponding to that bit. The second comparison result is determined based on the n second results.

6. The method as described in claim 5, characterized in that, The step of converting the second comparison result into a second code value using the converter according to the second conversion algorithm includes: Determine the target second result corresponding to the b-th bit in the second comparison result; the b-th bit is the corresponding bit of any one of the n capacitors; Determine the second preset voltage value of the b-th bit; The second code value corresponding to the b-th bit is determined based on the target second result, the second analog voltage, and the second preset voltage value.

7. The method as described in claim 6, characterized in that, Determining the second preset voltage value of the b-th bit includes: Determine the reference voltage of the successive approximation analog-to-digital converter; The second preset voltage value of the b-th bit is determined based on the reference voltage.

8. A conversion device for a successive approximation analog-to-digital converter, characterized in that, The method is applied to an electronic device, which includes a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a comparator and a converter, and a capacitor array. The resolution of the successive approximation ADC is N, and the number of capacitors in the capacitor array is N. N is an integer greater than 1; the device includes: The first determining unit is used to determine the high-order capacitors and low-order capacitors of the capacitor array, wherein the high-order capacitors include m capacitors and the low-order capacitors include n capacitors; the sum of m and n is N, and m and n are both positive integers. The first conversion unit is used to determine a first comparison result based on the m capacitors and the comparator, and convert the first comparison result into a first code value through the converter according to the first conversion algorithm. The second conversion unit is used to determine a second comparison result based on the n capacitors and the comparator, and convert the second comparison result into a second code value through the converter according to a second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm. The second determining unit is used to determine the target code value based on the first code value and the second code value.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory for storing one or more programs and configured to be executed by the processor, the programs including instructions for performing the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer program is stored therein, wherein the computer program causes the computer to execute instructions for the steps described in any one of claims 1-7.

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