Main and standby machine switching circuit and equipment

Abstract

The invention relates to the technical field of wireless networks, and provides a main and standby machine switching circuit and equipment. The circuit is characterized in that an intercommunication end of a host system is connected with an intercommunication end of a standby machine system; the intercommunication end of the host system is used for monitoring the working state of the standby machine system, and the intercommunication end of the standby machine system is used for monitoring the working state of the host system; the control end of the level control circuit is respectively connected with the host system and the standby system, and the input end of the level control circuit is respectively connected with an external low level signal and an external high level signal; the level control circuit is used for outputting a level signal to the antenna switching circuit according to the working state; the input end of the antenna switching circuit is connected with the antenna, and the antenna switching circuit is used for gating a conduction path between the antenna and a host system; or, gating the conduction path between the antenna and the standby machine system. According to the host and standby switching circuit and equipment provided by the invention, automatic identification and automatic switching of the running state of the host and standby system are realized.

Description

Technical Field

[0001] This application relates to the field of wireless network technology, and in particular to a primary / backup switching circuit and device. Background Technology

[0002] In some critical wireless communication devices, a main unit plus a backup unit design is often used to ensure the long-term stability and reliability of the equipment, such as satellite payload communication systems and ground station communication systems. This ensures that if the main unit crashes or malfunctions, the system can switch to the backup unit to continue operating, guaranteeing the continued normal operation of the system. Otherwise, if the satellite payload communication system crashes or malfunctions, the entire satellite will become unusable.

[0003] However, existing traditional main unit and standby switchover schemes require active control of the main unit and standby switchover, and the normal operation of the entire system also requires the normal operation of external power supply control equipment, which increases the probability of equipment failure in case of emergencies and increases costs.

[0004] Therefore, it is of great significance to address the high dependence of traditional switching schemes on external power supply control equipment, ensure that when one system experiences an abnormal failure, it can automatically switch to another system to continue working, realize the automatic identification and automatic switching of the main and backup system operating status, improve the autonomous adaptability of the equipment, and reduce the need for external control. Summary of the Invention

[0005] This application provides a primary / standby switching circuit and device to solve the problem of the high dependence of traditional switching schemes on external power supply control equipment, realize the automatic identification and automatic switching of the operating status of the primary / standby system, and improve the autonomous adaptability of the equipment.

[0006] In a first aspect, this application provides a primary / standby switching circuit, the circuit comprising: a primary system, a standby system, an antenna switching circuit, and a level control circuit; The interconnection terminal of the host system is connected to the interconnection terminal of the standby system; the interconnection terminal of the host system is used to monitor the working status of the standby system, and the interconnection terminal of the standby system is used to monitor the working status of the host system. The control terminal of the level control circuit is connected to the host system and the standby system respectively, and the input terminal of the level control circuit is connected to an external low-level signal and an external high-level signal respectively; the level control circuit is used to output a level signal to the antenna switching circuit according to the working state of the standby system or the working state of the host system. The input terminal of the antenna switching circuit is connected to the antenna, the output terminal of the antenna switching circuit is connected to the host system and the standby system respectively, and the control terminal of the antenna switching circuit is connected to the output terminal of the level control circuit. The antenna switching circuit is used to select the conduction path between the antenna and the host system according to the level signal; or, the antenna switching circuit is used to select the conduction path between the antenna and the standby system according to the level signal.

[0007] Optionally, according to the main / standby switching circuit of this application, the level control circuit includes a first switch and a second switch; The output terminal of the first switch is connected to the control terminal of the antenna switching circuit, the input terminal of the first switch is connected to the output terminal of the second switch, and the control terminal of the first switch is connected to the host system. The input terminal of the second switch is connected to the external low-level signal and the external high-level signal respectively, the output terminal of the second switch is connected to the input terminal of the first switch, and the control terminal of the second switch is connected to the standby system.

[0008] Optionally, according to the master / slave switching circuit of this application, the output terminal of the first switch is connected to the control terminal of the antenna switching circuit, the first input terminal of the first switch is connected to the first output terminal of the second switch, the second input terminal of the first switch is connected to the second output terminal of the second switch, and the control terminal of the first switch is connected to the master system. The first input terminal of the second switch is connected to the external low-level signal, the second input terminal of the second switch is connected to the external high-level signal, the first output terminal of the second switch is connected to the first input terminal of the first switch, the second output terminal of the second switch is connected to the second input terminal of the first switch, and the control terminal of the second switch is connected to the standby system.

[0009] Optionally, according to the master / standby switching circuit of this application, the master system includes a first microcontroller unit (MCU) processing unit, and the standby system includes a second MCU processing unit; The first I / O terminal of the first MCU processing unit is connected to the control terminal of the first switch; The first I / O terminal of the second MCU processing unit is connected to the control terminal of the second switch.

[0010] Optionally, according to the master / standby switching circuit of this application, the master system includes a first MCU processing unit, and the standby system includes a second MCU processing unit; The first I / O terminal of the first MCU processing unit is connected to the first information acquisition terminal of the second MCU processing unit, the second information acquisition terminal of the first MCU processing unit is connected to the control terminal of the antenna switching circuit, and the data transmission terminal of the first MCU processing unit is connected to an external communication device. The first I / O terminal of the second MCU processing unit is connected to the first information acquisition terminal of the first MCU processing unit, the second information acquisition terminal of the second MCU processing unit is connected to the control terminal of the antenna switching circuit, and the data transmission terminal of the second MCU processing unit is connected to an external communication device.

[0011] Optionally, according to the master / slave switching circuit of this application, the circuit further includes a first logic gate circuit and a second logic gate circuit; The first input terminal of the first logic gate circuit is connected to the second I / O terminal of the host system, the second input terminal of the first logic gate circuit is connected to the second I / O terminal of the standby system, and the output terminal of the first logic gate circuit is connected to the level control circuit; the first logic gate circuit is used to generate a low-level signal. The first input terminal of the second logic gate is connected to the third I / O terminal of the host system, the second input terminal of the second logic gate is connected to the third I / O terminal of the standby system, and the output terminal of the second logic gate is connected to the level control circuit; the second logic gate is used to generate a high-level signal.

[0012] Optionally, according to the main / standby switching circuit of this application, the first switch is a single-pole double-throw switch, and the second switch is a double-pole double-throw switch.

[0013] Optionally, according to the master / slave switching circuit of this application, the first logic gate is an AND gate logic chip, and the second logic gate is an OR gate logic chip.

[0014] Secondly, this application provides a chip that implements the master / slave switching circuit as described in the first aspect above.

[0015] Thirdly, this application provides an apparatus that implements the chip as described in the second aspect above.

[0016] The primary / standby switching circuit and device provided in this application monitor the operating status of the primary and standby systems through the interconnection terminal between the primary and standby systems. Based on the operating status, a level control circuit outputs a low-level or high-level signal to the antenna switching circuit. The antenna switching circuit then selects the conduction path between the antenna and the primary system based on the low-level signal, or vice versa, based on the high-level signal. This allows the circuit and device to dynamically and in real-time adjust the antenna conduction path according to the actual operating conditions of the primary and standby systems. This solves the problem of the high dependence of traditional switching schemes on external power supply control equipment, achieving automatic identification and automatic switching of the operating status of the primary and standby systems, thereby improving the device's autonomous adaptability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the structural diagrams of the primary / standby switching circuit.

[0019] Figure 2 This is the second schematic diagram of the main / standby switching circuit. Detailed Implementation

[0020] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, and the number of objects is not limited; for example, the first object can be one or more.

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Figure 1 This is one of the structural schematic diagrams of the primary / standby switching circuit provided in this application, such as... Figure 1As shown, this application provides a master / standby switching circuit, which may include: a master system 110, a standby system 120, an antenna switching circuit 130, and a level control circuit 140; The interconnection terminal of the host system 110 is connected to the interconnection terminal of the standby system 120; the interconnection terminal of the host system 110 is used to monitor the working status of the standby system 120, and the interconnection terminal of the standby system 120 is used to monitor the working status of the host system 110. The control terminal CTL pin of the level control circuit 140 is connected to the main system 110 and the standby system 120 respectively. The input terminal of the level control circuit 140 is connected to the external low-level signal L and the external high-level signal H respectively. The level control circuit 140 is used to output a low-level signal or a high-level signal to the antenna switching circuit 130 according to the working state of the standby system 120 or the working state of the main system. The input terminal of the antenna switching circuit 130 is connected to the antenna A1, and the output terminal of the antenna switching circuit 130 is connected to the host system 110 and the standby system 120 respectively. The control terminal CTL pin of the antenna switching circuit 130 is connected to the output terminal of the level control circuit 140. The antenna switching circuit 130 is used to select the conduction path between the antenna A1 and the host system 110 according to the level signal; or, the antenna switching circuit 130 is used to select the conduction path between the antenna A1 and the standby system 120 according to the level signal.

[0023] Specifically, the interconnection point refers to the establishment of a hardware communication or logical monitoring interface between the host system 110 and the standby system 120.

[0024] The operating status includes normal operation, system crash, abnormal damage, or power failure. This application does not specifically limit this status.

[0025] The host system 110 includes a first MCU (Microcontroller Unit) processing unit and a first radio frequency system.

[0026] The standby system 120 includes a second MCU processing unit and a second radio frequency system.

[0027] Specifically, during the initial startup or normal operation phase, the interconnection terminal of the host system 110 is connected to the interconnection terminal of the standby system 120 to achieve mutual monitoring of their operating status. Based on the operating status of the host system 110 and the standby system 120, the logic switching action inside the control terminal CTL pin of the level control circuit 140 is determined.

[0028] The control terminal CTL pin of the level control circuit 140 is connected to the main system 110 and the standby system 120 respectively. The input terminal of the level control circuit 140 is connected to the external low-level signal L and the external high-level signal H respectively. According to the operating state of the main system 110 and the standby system 120, the level control circuit 140 selects whether to connect its input terminal to the external low-level signal L or the external high-level signal H, and outputs a low-level signal or a high-level signal to the antenna switching circuit 130.

[0029] The antenna switching circuit 130 performs a path switching action based on the received low-level signal or high-level signal.

[0030] It is understandable that the correspondence between low-level or high-level signals and the conduction path can be flexibly set according to the hardware selection of the antenna switching circuit 130 or the actual wiring requirements.

[0031] Optionally, when the antenna switching circuit 130 receives a low-level signal, the antenna switching circuit 130 selects the conduction path between antenna A1 and the host system 110, at which time antenna A1 is connected to the host system 110; when the antenna switching circuit 130 receives a high-level signal, the antenna switching circuit 130 selects the conduction path between antenna A1 and the standby system 120, at which time antenna A1 is connected to the standby system 120.

[0032] Optionally, when the antenna switching circuit 130 receives a low-level signal, the antenna switching circuit 130 selects the conduction path between antenna A1 and the standby system 120, at which time antenna A1 is connected to the standby system 120; when the antenna switching circuit 130 receives a high-level signal, the antenna switching circuit 130 selects the conduction path between antenna A1 and the host system 110, at which time antenna A1 is connected to the host system 110.

[0033] It should be noted that, based on the correspondence between low-level or high-level signals and the conduction path, the control logic corresponding to the host system 110, the standby system 120, and the level control circuit 140 also needs to be adapted to ensure that the hardware logic can accurately trigger the preset switching path. Through this flexible logic configuration, this application can be adapted to different models of RF components.

[0034] The primary / standby switching circuit provided in this application monitors the operating status of the primary and standby systems through the interconnection terminal between the primary and standby systems. Based on the operating status, a level control circuit outputs a low-level or high-level signal to the antenna switching circuit. The antenna switching circuit then selects the conduction path between the antenna and the primary system based on the low-level signal, or vice versa, based on the high-level signal. This allows the circuit to dynamically and in real-time adjust the antenna conduction path according to the actual operating conditions of the primary and standby systems. This solves the problem of the high dependence of traditional switching schemes on external power supply control equipment, achieving automatic identification and automatic switching of the operating status of the primary and standby systems, thereby improving the equipment's autonomous adaptability.

[0035] In one embodiment, the input terminal of the first switch S1 is connected to the output terminal of the second switch S2, and the control terminal CTL pin of the first switch S1 is connected to the host system 110. The input terminal of the second switch S2 is connected to the external low-level signal L and the external high-level signal H respectively. The output terminal of the second switch S2 is connected to the input terminal of the first switch S1. The control terminal CTL pin of the second switch S2 is connected to the standby system 120.

[0036] Specifically, the first switch S1 can be a level switching module composed of a single-pole double-throw analog switch, an integrated logic chip, a field-effect transistor, or an optocoupler. This application does not impose specific limitations on this.

[0037] The second switch S2 can be a level switching module composed of a double-pole double-throw analog switch, an integrated logic chip, a field-effect transistor, or an optocoupler. This application does not specifically limit it in this regard.

[0038] Specifically, the control terminal CTL pin of the second switch S2 is used to receive the level signal from the standby system 120, and the control terminal CTL pin of the first switch S1 is used to receive the level signal from the host system 110.

[0039] The input terminal of the second switch S2 is connected to the external low-level signal L and the external high-level signal H respectively. The second switch S2 performs a gating action according to the level signal of the standby system 120, thereby determining the level signal output from the output terminal of the second switch S2 to the first switch.

[0040] The first switch S1 determines the final output level signal to the antenna switching circuit 130 based on the level state of the host system 110 and the level signal received from the output terminal of the second switch S2.

[0041] The primary / backup switching circuit provided in this application connects the output of the first switch to the control terminal of the antenna switching circuit, and the output of the second switch to the input of the first switch. This allows the circuit to dynamically combine the final transmitted level signal at the physical level, greatly enhancing the determinism of the primary / backup switching action and the overall reliability of the communication system.

[0042] In one embodiment, the host system 110 includes a first microcontroller unit (MCU) processing unit U1, and the standby system 120 includes a second MCU processing unit U2. The first IO terminal of the first MCU processing unit U1 is connected to the control terminal CTL pin of the first switch S1; The first IO terminal of the second MCU processing unit U2 is connected to the control terminal CTL pin of the second switch S2.

[0043] In one embodiment, the first switch S1 is a single-pole double-throw switch, and the second switch S2 is a double-pole double-throw switch.

[0044] Specifically, the second switch S2 includes RF1, RF2, RF3, and RF4. The first switch S1 includes pins 1, 2, and 3. The second switch S2 has its RF1 pin connected to an external low-level signal L and its RF2 pin connected to an external high-level signal H. The first switch S1 has its pin 2 connected to its RF3 pin, its pin 3 connected to its RF4 pin, and its pin 1 connected as an output to the antenna switching circuit 130.

[0045] Specifically, the second switch S2 switches the internal conduction path according to the level signal output by the second MCU processing unit U2.

[0046] Optionally, when the first IO terminal of the second MCU processing unit U2 outputs a low level, the first input terminal RF1 of the second switch S2 is connected to the first output terminal RF3, and the second RF2 terminal is connected to the RF4 terminal. At this time, the external low-level signal L is guided to the RF3 terminal, and the external high-level signal H is guided to the RF4 terminal.

[0047] Optionally, when the first IO terminal of the second MCU processing unit U2 outputs a high level, the RF1 and RF4 pins of the second switch S2 are turned on, and the RF2 and RF3 pins are turned on at the same time; at this time, the external low-level signal L is guided to the RF4 pin, and the external high-level signal H is guided to the RF3 pin.

[0048] The first switch S1 switches the internal conduction path according to the level signal output by the first MCU processing unit U1.

[0049] Optionally, when the first IO terminal of the first MCU processing unit U1 outputs a low level, pins 1 and 2 of the first switch S1 are connected, while pins 1 and 3 are not connected; at this time, the first switch S1 is turned on and outputs a level signal from the RF3 pin of the second switch S2.

[0050] Optionally, when the first IO terminal of the first MCU processing unit U1 outputs a high level, pins 1 and 3 of the first switch S1 are connected, while pins 1 and 2 are not connected; at this time, the first switch S1 is turned on and outputs a level signal from the RF4 pin of the second switch S2.

[0051] The primary / standby switching circuit provided in this application connects the first I / O terminal of the first MCU processing unit to the control terminal of the first switch, and the first I / O terminal of the second MCU processing unit to the control terminal of the second switch. This enables the circuit to dynamically reassemble the level signal output to the antenna switching circuit, significantly improving the robustness and determinism of the primary / standby switching circuit under extreme fault conditions.

[0052] In one embodiment, the level control circuit 140 includes a first switch S1 and a second switch S2; The output terminal of the first switch S1 is connected to the control terminal CTL pin of the antenna switching circuit 130, the first input terminal of the first switch S1 is connected to the first output terminal of the second switch S2, the second input terminal of the first switch S1 is connected to the second output terminal of the second switch S2, and the control terminal CTL pin of the first switch S1 is connected to the host system 110. The first input terminal of the second switch S2 is connected to an external low-level signal L, the second input terminal of the second switch S2 is connected to an external high-level signal H, the first output terminal of the second switch S2 is connected to the first input terminal of the first switch S1, the second output terminal of the second switch S2 is connected to the second input terminal of the first switch S1, and the control terminal CTL pin of the second switch S2 is connected to the standby system 120.

[0053] Understandably, when both the main system 110 and the standby system 120 are operating normally, the conductive path between antenna A1 and the main system 110 is prioritized. In the event of a malfunction in the main system 110, the first MCU processing unit U1 and the second MCU processing unit U2 output opposite level signals, thus establishing a conductive path between antenna A1 and the standby system. Conversely, in the event of a malfunction in the standby system 120, both the first MCU processing unit U1 and the second MCU processing unit U2 output the same level signal, thus establishing a conductive path between antenna A1 and the main system 110.

[0054] Specifically, when the host system 110 and the standby system 120 suddenly experience abnormal crashes or damage during operation, the host system 110 and the standby system 120 confirm each other's working status through the interconnection terminal.

[0055] Table 1 is a logic table showing the relationship between the main and backup system status and control level in the event of a host failure, provided in this application. As shown in Table 1, L represents a low-level signal, H represents a high-level signal, U1-IO1 represents the level state output from the first IO terminal of the first MCU processing unit U1, U2-IO1 represents the level state output from the first IO terminal of the second MCU processing unit U2, and the combined level represents the final signal level output from the level control circuit 140 to the antenna switching circuit 130.

[0056] Table 1. Logic Relationship Between Main and Backup System Status and Control Levels in Case of Main Unit Failure

[0057] When the main system 110 malfunctions and the standby system 120 is working normally, the level control circuit 140 needs to select the external high-level signal H, so that the antenna switching circuit 130 switches to the standby system 120.

[0058] Optionally, if the host system 110 malfunctions and the first IO terminal of the first MCU processing unit U1 outputs a low level, pins 1 and 2 of the first switch S1 are connected, while pins 1 and 3 are disconnected. At this time, if the first IO terminal of the second MCU processing unit U2 outputs a high level, pins RF2 and RF3 of the second switch S2 are connected, and simultaneously pins RF1 and RF4 are connected. Thus, the external high-level signal H is guided to pin RF3 and transmitted from pin 2 of the first switch S1 to pin 1. The first switch S1 outputs the external high-level signal H to the antenna switching circuit S3. At this time, the external low-level signal L is guided to pin RF4. Since pins 1 and 3 of the first switch S1 are disconnected, the external low-level signal L will not interfere with the external high-level signal.

[0059] Correspondingly, pins 1 and 3 of S3 in antenna switching circuit 130 are connected, while pins 1 and 2 are disconnected, thereby selecting the connection path between antenna A1 and the standby system.

[0060] Optionally, if the host system 110 malfunctions and the first IO terminal of the first MCU processing unit U1 outputs a high level, pins 1 and 3 of the first switch S1 are connected, while pins 1 and 2 are disconnected. At this time, if the first IO terminal of the second MCU processing unit U2 outputs a low level, pins RF2 and RF4 of the second switch S2 are connected, and simultaneously pins RF1 and RF3 are connected. Thus, the external high-level signal H is guided to pin RF4 and transmitted from pin 3 of the first switch S1 to pin 1. The first switch S1 outputs the external high-level signal H to the antenna switching circuit S3. At this time, the external low-level signal L is guided to pin RF3. Since pins 1 and 2 of the first switch S1 are disconnected, the external low-level signal L will not interfere with the external high-level signal H.

[0061] Correspondingly, pins 1 and 3 of S3 in antenna switching circuit 130 are connected, while pins 1 and 2 are disconnected, thereby selecting the connection path between antenna A1 and standby system 120.

[0062] Even if the first MCU processing unit U1 fails, the backup system 120 can still ensure that the external high-level signal H is accurately output to the antenna switching circuit 130 by outputting a signal with the opposite level, thus realizing the forced switching of the backup link.

[0063] Table 2 is a logic table showing the relationship between the main and backup system states and control levels in the event of a standby machine malfunction, as provided in this application. As shown in Table 2, L represents a low-level signal, H represents a high-level signal, U1-IO1 represents the level state output by the first IO terminal of the first MCU processing unit U1, U2-IO1 represents the level state output by the first IO terminal of the second MCU processing unit U2, and the combined level represents the final signal level output by the level control circuit 140 to the antenna switching circuit 130.

[0064] Table 2. Logic Relationship Between Main and Standby System Status and Control Levels in Case of Standby Unit Malfunction

[0065] When the standby system 120 malfunctions and the host system 110 is operating normally, the level control circuit 140 needs to select the external low-level signal H, thereby switching the antenna switching circuit 130 to the host system 110.

[0066] Optionally, if the standby system 120 malfunctions and the first I / O pin of the second MCU processing unit U2 outputs a low level, pins RF2 and RF4 of the second switch S2 are connected, while pins RF1 and RF3 are also connected. At this time, if the first I / O pin of the first MCU processing unit U1 outputs a low level, pins 1 and 2 of the first switch S1 are connected, while pins 1 and 3 are disconnected. Thus, the external low-level signal L is guided to pin RF3 and transmitted from pin 2 of the first switch S1 to pin 1. The first switch S1 then outputs the external low-level signal L to the antenna switching circuit 130. At this time, the external high-level signal H is guided to pin RF4. Since pins 1 and 3 of the first switch S1 are disconnected, the external high-level signal H will not interfere with the external low-level signal L.

[0067] Correspondingly, pins 1 and 2 of S3 in antenna switching circuit 130 are connected, while pins 1 and 3 are not connected, thus establishing a connection path between the selected antenna A1 and the host system 110.

[0068] Optionally, if the standby system 120 malfunctions and the first I / O pin of the second MCU processing unit U2 outputs a high level, pins RF1 and RF4 of the second switch S2 are connected, while pins RF2 and RF3 are also connected. At this time, if the first I / O pin of the first MCU processing unit U1 outputs a high level, pins 1 and 3 of the first switch S1 are connected, while pins 1 and 2 are disconnected. Thus, the external low-level signal L is guided to pin RF4 and transmitted from pin 3 of the first switch S1 to pin 1. The first switch S1 then outputs the external low-level signal L to the antenna switching circuit 130. At this time, the external high-level signal H is guided to pin RF3. Since pins 1 and 2 of the first switch S1 are disconnected, the external high-level signal H will not interfere with the external low-level signal L.

[0069] Accordingly, pins 1 and 2 of the antenna switching circuit 130 are connected, while pins 1 and 3 are disconnected, thereby selecting the connection path between antenna A1 and host system 110.

[0070] The primary / standby switching circuit provided in this application connects the output terminal of the first switch to the control terminal CTL pin of the antenna switching circuit, the first output terminal of the second switch to the first input terminal of the first switch, and the second output terminal of the second switch to the second input terminal of the first switch. This circuit avoids logic lockout caused by system failure and can dynamically combine the final transmitted level signal at the physical level, greatly enhancing the determinism and reliability of primary / standby switching under extreme conditions.

[0071] In one embodiment, the host system 110 includes a first MCU processing unit U1, and the standby system 120 includes a second MCU processing unit U2; The first I / O terminal of the first MCU processing unit U1 is connected to the first information acquisition terminal of the second MCU processing unit U2, the second information acquisition terminal of the first MCU processing unit U1 is connected to the control terminal CTL pin of the antenna switching circuit 130, and the data transmission terminal of the first MCU processing unit U1 is connected to an external communication device. The first I / O terminal of the second MCU processing unit U2 is connected to the first information acquisition terminal of the first MCU processing unit U1, the second information acquisition terminal of the second MCU processing unit U2 is connected to the control terminal CTL pin of the antenna switching circuit 130, and the data transmission terminal of the second MCU processing unit U2 is connected to an external communication device.

[0072] Specifically, the first information acquisition terminal and the second information acquisition terminal are used as input pins for detecting level signals or acquiring status data, such as GPIO input terminals, ADC sampling terminals, etc.

[0073] Data transmission endpoints refer to communication interfaces used for remote information exchange, such as UART serial ports and network ports.

[0074] External communication equipment is used to receive and record real-time operating data from the host system 110 or the standby system 120. For example, it can enable mutual monitoring of the operating status of the host system 110 or the standby system 120 and closed-loop verification of antenna switching results.

[0075] Optionally, the first MCU processing unit U1 sends a level signal representing its own operating status to the first information acquisition terminal of the second MCU processing unit U2 through its first I / O terminal; correspondingly, the second MCU processing unit U2 sends a feedback signal to the first information acquisition terminal of the first MCU processing unit U1 through its first I / O terminal. Through this connection, the host system 110 and the standby system 120 can mutually determine whether the other party and its connected radio frequency system are in normal working condition.

[0076] Optionally, both the first MCU processing unit U1 and the second MCU processing unit U2 sample the real-time level of the CTL pin of the antenna switching circuit 130 control terminal through their respective second information acquisition terminals. By monitoring the voltage state of the CTL pin of the antenna switching circuit 130 control terminal, the main and backup systems can dynamically confirm whether the actual conduction path executed by the antenna switching circuit 130 is consistent with the software-preset logic.

[0077] Optionally, the first MCU processing unit U1 and the second MCU processing unit U2 respectively transmit the monitored operating status level of the other party, their own transmitted data, and the real-time status information of the antenna switching circuit 130 to an external communication device through their data transmission terminals. The external communication device summarizes and analyzes the above data, thereby realizing remote real-time monitoring of the operating status of the entire main / standby switching circuit.

[0078] The primary / standby switching circuit provided in this application establishes a working status monitoring between the first MCU processing unit and the second MCU processing unit, and feeds back the CTL pin level of the antenna switching circuit control terminal through the second information acquisition terminal, and then reports the system information to the external communication device through the data transmission terminal. This enables the circuit to realize real-time closed-loop monitoring of the operating status of the primary and standby systems, avoids switching misjudgments caused by switch abnormalities, and greatly enhances the certainty and reliability of the primary / standby switching action under extreme operating conditions.

[0079] Figure 2 This is the second schematic diagram of the main / standby switching circuit provided in this application, as shown below. Figure 2 As shown, the circuit also includes a first logic gate circuit U3 and a second logic gate circuit U4; The first input terminal A of the first logic gate circuit U3 is connected to the second IO terminal of the host system 210, the second input terminal B of the first logic gate circuit U3 is connected to the second IO terminal of the standby system 220, and the output terminal Y of the first logic gate circuit U3 is connected to the level control circuit 230; the first logic gate circuit U3 is used to generate a low-level signal L. The first input terminal A of the second logic gate circuit U4 is connected to the third IO terminal of the host system 210, the second input terminal B of the second logic gate circuit U4 is connected to the third IO terminal of the standby system 220, and the output terminal Y of the second logic gate circuit U4 is connected to the level control circuit 230; the second logic gate circuit U4 is used to generate a high-level signal H.

[0080] In one embodiment, the first logic gate U3 is an AND gate logic chip, and the second logic gate U4 is an OR gate logic chip.

[0081] Table 3 is the truth table of logic gate circuits provided in this application. According to the AND gate logic of the first logic gate circuit U3, when any input terminal inputs a low level (0), the output terminal Y outputs a low level (0); according to the OR gate logic of the second logic gate circuit U4, when any input terminal inputs a high level (1), the output terminal Y outputs a high level (1).

[0082] Table 3 Truth Table of Logic Gates

[0083] In this application embodiment, either a digitally controlled switch or a GPIO-controlled analog switch can be selected. In the application scenario of a digitally controlled switch, the first logic gate circuit U3 and the second logic gate circuit U4 can use hardware logic operations to replace the traditional external level signal in digital control mode, thereby achieving redundant backup of the reference level source.

[0084] As shown in Table 3, regardless of whether any processing unit in the host system 210 or the standby system 220 malfunctions, as long as the other normally functioning system outputs a low level 0 at its corresponding second IO terminal, the signal output to the level control circuit 230 can be maintained at a low level 0.

[0085] Optionally, when the second IO terminal of the host system 210 outputs logic 0 and the second IO terminal of the standby system 220 outputs logic 0, the first input terminal A of the first logic gate circuit U3 is 0 and the second input terminal B of the first logic gate circuit U3 is 0. At this time, the output terminal Y of the first logic gate circuit U3 outputs logic 0, thereby achieving stable maintenance of the low-level signal L.

[0086] Optionally, when the second IO terminal of the host system 210 outputs logic 0 and the second IO terminal of the standby system 220 outputs logic 1, the first input terminal A of the first logic gate circuit U3 is 0 and the second input terminal B of the first logic gate circuit U3 is 1. At this time, the output terminal Y of the first logic gate circuit U3 outputs logic 0, thereby achieving stable maintenance of the low-level signal L.

[0087] Optionally, when the second IO terminal of the host system 210 outputs logic 1 and the second IO terminal of the standby system 220 outputs logic 0, the first input terminal A of the first logic gate circuit U3 is 1 and the second input terminal B of the first logic gate circuit U3 is 0. At this time, the output terminal Y of the first logic gate circuit U3 outputs logic 0, thereby achieving stable maintenance of the low-level signal L at 0.

[0088] Optionally, when both the second I / O terminal of the host system 210 and the second I / O terminal of the standby system 220 output logic 1, the first input terminal A of the first logic gate circuit U3 is 1 and the second input terminal B of the first logic gate circuit U3 is 1. At this time, the output terminal Y of the first logic gate circuit U3 outputs logic 1. It should be noted that at this time, the output terminal Y outputs a high-level signal and is not used as a low-level signal L.

[0089] As shown in Table 3, regardless of whether either the host system 210 or the standby system 220 crashes or malfunctions, as long as the other normally functioning system outputs a high level 1 at its corresponding third IO terminal, the signal output to the level control circuit 230 can always be maintained at a stable high level 1.

[0090] Optionally, when both the third I / O terminal of the host system 210 and the third I / O terminal of the standby system 220 output logic 0, the first input terminal A of the second logic gate circuit U4 is 0 and the second input terminal B of the second logic gate circuit U4 is 0. In this case, the output terminal Y of the second logic gate circuit U4 outputs logic 0. It should be noted that the output at this time is a low-level signal and is not used as a high-level signal H.

[0091] Optionally, when the third IO terminal of the host system 210 outputs logic 0 and the third IO terminal of the standby system 220 outputs logic 1, the first input terminal A of the second logic gate circuit U4 is 0 and the second input terminal B of the second logic gate circuit U4 is 1. At this time, the output terminal Y of the second logic gate circuit U4 outputs logic 1, thereby achieving stable maintenance of the high-level signal H.

[0092] Optionally, when the third IO terminal of the host system 210 outputs logic 1 and the third IO terminal of the standby system 220 outputs logic 0, the first input terminal A of the second logic gate circuit U4 is 1 and the second input terminal B of the second logic gate circuit U4 is 0. At this time, the output terminal Y of the second logic gate circuit U4 outputs logic 1, thereby achieving stable maintenance of the high-level signal H.

[0093] Optionally, when the third IO terminal of the host system 210 outputs logic 1 and the third IO terminal of the standby system 220 outputs logic 1, the first input terminal A of the second logic gate circuit U4 is 1 and the second input terminal B of the second logic gate circuit U4 is 1. At this time, the output terminal Y of the second logic gate circuit U4 still outputs logic 1, thus achieving stable maintenance of the high-level signal H.

[0094] This application also provides a chip, including the master / slave switching circuit of the above embodiments.

[0095] This application also provides an electronic device, including the chip described in the above embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0097] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Although this application has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications, or equivalent substitutions of the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application and should be covered within the scope of the claims of this application.

Claims

1. A primary / standby switching circuit, characterized in that, include: Main unit system, backup unit system, antenna switching circuit, and level control circuit; The interconnection terminal of the host system is connected to the interconnection terminal of the standby system; The interconnection terminal of the host system is used to monitor the working status of the standby system, and the interconnection terminal of the standby system is used to monitor the working status of the host system. The control terminal of the level control circuit is connected to the host system and the standby system respectively, and the input terminal of the level control circuit is connected to an external low-level signal and an external high-level signal respectively. The level control circuit is used to output a level signal to the antenna switching circuit according to the working state of the standby system or the working state of the host system; The input terminal of the antenna switching circuit is connected to the antenna, the output terminal of the antenna switching circuit is connected to the host system and the standby system respectively, and the control terminal of the antenna switching circuit is connected to the output terminal of the level control circuit; the antenna switching circuit is used to select the conduction path between the antenna and the host system according to the level signal. Alternatively, the antenna switching circuit is used to select the conduction path between the antenna and the standby system based on the level signal.

2. The primary / standby switching circuit according to claim 1, characterized in that, The level control circuit includes a first switch and a second switch; The output terminal of the first switch is connected to the control terminal of the antenna switching circuit, the input terminal of the first switch is connected to the output terminal of the second switch, and the control terminal of the first switch is connected to the host system. The input terminal of the second switch is connected to the external low-level signal and the external high-level signal respectively, the output terminal of the second switch is connected to the input terminal of the first switch, and the control terminal of the second switch is connected to the standby system.

3. The primary / standby switching circuit according to claim 2, characterized in that, The output terminal of the first switch is connected to the control terminal of the antenna switching circuit, the first input terminal of the first switch is connected to the first output terminal of the second switch, the second input terminal of the first switch is connected to the second output terminal of the second switch, and the control terminal of the first switch is connected to the host system. The first input terminal of the second switch is connected to the external low-level signal, the second input terminal of the second switch is connected to the external high-level signal, the first output terminal of the second switch is connected to the first input terminal of the first switch, the second output terminal of the second switch is connected to the second input terminal of the first switch, and the control terminal of the second switch is connected to the standby system.

4. The primary / standby switching circuit according to claim 2, characterized in that, The host system includes a first microcontroller unit (MCU) processing unit, and the standby system includes a second MCU processing unit. The first I / O terminal of the first MCU processing unit is connected to the control terminal of the first switch; The first I / O terminal of the second MCU processing unit is connected to the control terminal of the second switch.

5. The primary / standby switching circuit according to claim 1, characterized in that, The host system includes a first MCU processing unit, and the standby system includes a second MCU processing unit. The first I / O terminal of the first MCU processing unit is connected to the first information acquisition terminal of the second MCU processing unit, the second information acquisition terminal of the first MCU processing unit is connected to the control terminal of the antenna switching circuit, and the data transmission terminal of the first MCU processing unit is connected to an external communication device. The first I / O terminal of the second MCU processing unit is connected to the first information acquisition terminal of the first MCU processing unit, the second information acquisition terminal of the second MCU processing unit is connected to the control terminal of the antenna switching circuit, and the data transmission terminal of the second MCU processing unit is connected to an external communication device.

6. The primary / standby switching circuit according to claim 1, characterized in that, It also includes a first logic gate circuit and a second logic gate circuit; The first input terminal of the first logic gate circuit is connected to the second I / O terminal of the host system, the second input terminal of the first logic gate circuit is connected to the second I / O terminal of the standby system, and the output terminal of the first logic gate circuit is connected to the level control circuit; the first logic gate circuit is used to generate a low-level signal. The first input terminal of the second logic gate is connected to the third I / O terminal of the host system, the second input terminal of the second logic gate is connected to the third I / O terminal of the standby system, and the output terminal of the second logic gate is connected to the level control circuit; the second logic gate is used to generate a high-level signal.

7. The primary / standby switching circuit according to any one of claims 2 to 4, characterized in that, The first switch is a single-pole double-throw switch, and the second switch is a double-pole double-throw switch.

8. The primary / standby switching circuit according to claim 6, characterized in that, The first logic gate is an AND gate logic chip, and the second logic gate is an OR gate logic chip.

9. A chip, characterized in that, Includes the main / standby switching circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the chip described in claim 9 above.

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