Multi-VRF routing processing method and device, switching chip and network equipment

Abstract

The embodiment of the invention provides a multi-VRF routing processing method and device, a switching chip and network equipment, and relates to the technical field of communication. The method comprises the following steps: splicing a virtual routing forwarding instance identifier of a data packet to be looked up with a destination IP address to form a section of combined data, and executing longest mask matching operation on the combined data so as to look up a matched target routing entry in a multi-stage hardware lookup table structure for storing routing information. Therefore, a unified lookup mechanism based on joint coding of the VRF identifier and the destination IP address is realized, the utilization rate of hardware resources is improved, and the routing table storage overhead in a multi-VRF scene is reduced.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to a multi-VRF routing processing method, apparatus, switching chip, and network device. Background Technology

[0002] Virtual Routing and Forwarding (VRF) technology plays a crucial role in modern network architectures. By deploying multiple independent routing instances on the same physical network device, it can provide logically isolated network environments for different customers or services. With the rapid development of cloud computing and data center networks, multi-VRF architecture has become the mainstream technical solution for achieving multi-tenant network isolation and business logic segmentation.

[0003] Currently, mainstream technical solutions employ a combination of two types of memory: Ternary Content Addressable Memory (TCAM) and Static Random-Access Memory (SRAM) to collaboratively store routing tables. SRAM storage units use complete routing addresses as basic entries (e.g., 192.168.1.0 / 24), while TCAM storage units simultaneously contain VRF instance identification information and the common prefix information of the routing addresses in the corresponding SRAM entries (e.g., 192.168.0.0 / 16).

[0004] However, when different VRF instances contain routes with the same IP address, each VRF instance requires independent TCAM entry resources. Especially in large-scale multi-VRF application scenarios (such as 8K VRF instances), this design puts significant pressure on the hardware storage resources of the routing table. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide a multi-VRF routing processing method, apparatus, switching chip and network device to at least partially improve the above-mentioned problems.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a multi-VRF routing processing method, the method comprising: The virtual route forwarding instance identifier of the data packet to be found is concatenated with the destination IP address to form a combined data segment; A longest mask matching operation is performed on the combined data to find a matching target route entry in a multi-level hardware lookup table structure used to store routing information; wherein each level of the multi-level hardware lookup table structure is built based on the combined data.

[0007] Optionally, the step of concatenating the virtual route forwarding instance identifier of the data packet to be searched with the destination IP address to form a combined data segment includes: Convert the virtual route forwarding instance identifier and the destination IP address of the data packet to be searched into the first binary representation and the second binary representation, respectively; The first binary representation and the second binary representation are concatenated to form an extended bit string as combined data.

[0008] Optionally, the multi-level hardware lookup table structure includes a tri-state content-addressable memory and a static random access memory; the step of performing a longest mask matching operation on the combined data to find a matching target route entry in the multi-level hardware lookup table structure used to store routing information includes: The combined data is used to perform longest prefix matching with each routing entry in the tri-state content addressing memory to obtain a target pointer pointing to the static random access memory. Based on the target pointer, locate the corresponding target memory block in the static random access memory; The combined data is used to perform longest prefix matching with each routing entry in the target storage block to obtain the target routing entry.

[0009] Optionally, the method further includes: Receive a route addition message; the route addition message includes the identifier of the virtual route forwarding instance to be stored and the IP address to be stored. The virtual route forwarding instance identifier to be stored is concatenated with the IP address to be stored to form the combined data to be stored; The combined data to be stored is matched with the longest prefix of each routing entry in the tri-state content addressing memory to obtain a target pointer to the static random access memory. Based on the target pointer, locate the corresponding target memory block in the static random access memory; When the remaining capacity of the target storage block is sufficient, the complete routing information of the combined data to be stored is stored in the target storage block; When the remaining capacity of the target storage block is insufficient, all routing entries in the target storage block and the combined data to be stored are reassembled and stored.

[0010] Optionally, the reorganization and storage of all routing entries and the combined data to be stored in the target storage block includes: Extract the existing combined data corresponding to all existing routing entries in the target storage block; The existing combined data and the combined data to be stored are re-clustered based on binary prefix similarity. Based on the re-clustering results, create new static random access memory blocks and reallocate the storage contents; Update the pointer relationships in the tri-state content-addressable memory and the static random access memory.

[0011] Optionally, the multi-level hardware lookup table structure includes a tri-state content-addressable memory, a first static random access memory, and a second static random access memory; the step of performing a longest mask matching operation on the combined data to find a matching target route entry in the multi-level hardware lookup table structure used to store routing information includes: The combined data is used to perform longest prefix matching with each routing entry in the tri-state content addressing memory to obtain a first target pointer pointing to the first static random access memory. Based on the first target pointer, locate the corresponding first target memory block in the first static random access memory; The combined data is used to perform longest prefix matching with each routing entry in the first target storage block to obtain a second target pointer pointing to the second static random access memory. Based on the second target pointer, locate the corresponding second target memory block in the second static random access memory; The combined data is used to perform longest prefix matching with each routing entry in the second target storage block to obtain the target routing entry.

[0012] Optionally, the method further includes: When no matching target route entry is found in the multi-level hardware lookup table structure, the default route entry is used for packet forwarding.

[0013] Secondly, embodiments of the present invention provide a multi-VRF routing processing apparatus, comprising: The data splicing unit is used to splice the virtual route forwarding instance identifier of the data packet to be searched with the destination IP address to form a combined data segment; A route lookup unit is used to perform a longest mask matching operation on the combined data to find a matching target route entry in a multi-level hardware lookup table structure used to store routing information; wherein each level entry in the multi-level hardware lookup table structure is established based on the combined data.

[0014] Thirdly, embodiments of the present invention provide a switching chip for performing the method as described in any of the first aspects.

[0015] Fourthly, embodiments of the present invention provide a network device, including a switching chip as described in the third aspect and a multi-level hardware lookup table structure for storing routing entries.

[0016] This invention provides a multi-VRF routing processing method, apparatus, switching chip, and network device. By concatenating VRF identifiers and IP addresses into unified combined data and constructing a multi-level hardware lookup table structure based on this combined data, it achieves prefix sharing capability across VRF instances, effectively reduces the occupation of high-cost TCAM resources, improves the storage efficiency and lookup performance of routing table entries, and is suitable for high-speed forwarding requirements in large-scale multi-tenant network environments.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart for route matching is provided as an embodiment of the present invention; Figure 2 A flowchart illustrating a multi-VRF routing processing method provided in an embodiment of the present invention; Figure 3 This is another flowchart illustrating a multi-VRF routing processing method provided in an embodiment of the present invention; Figure 4 This is another flowchart illustrating a multi-VRF routing processing method provided in an embodiment of the present invention; Figure 5 This is a storage diagram of a multi-level hardware lookup table structure provided in an embodiment of the present invention; Figure 6 This is another flowchart illustrating a multi-VRF routing processing method provided in an embodiment of the present invention; Figure 7 This is another storage diagram illustrating a multi-level hardware lookup table structure provided in an embodiment of the present invention; Figure 8 This is another flowchart illustrating a multi-VRF routing processing method provided in an embodiment of the present invention; Figure 9 This is another storage diagram illustrating a multi-level hardware lookup table structure provided in an embodiment of the present invention; Figure 10 This is a schematic structural block diagram of a multi-VRF routing processing device provided in an embodiment of the present invention.

[0020] Icons: 300 - Multi-VRF routing processing device; 310 - Data splicing unit; 320 - Route lookup unit. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0025] As described in the background section, current mainstream solutions use both TCAM and SRAM memory to store routing tables. (See reference...) Figure 1When a data packet arrives at the switch device, the switch chip first searches for an entry in the TCAM that has the same VRF instance and matches the longest mask of the data packet's destination IP address. Then, it continues to find the longest mask matching routing address in the corresponding SRAM entry according to the longest mask matching principle, and determines the next hop behavior of the data packet.

[0026] However, this scheme requires each VRF instance to occupy at least one TCAM entry resource. This puts pressure on the hardware resources of the routing table in multi-VRF instance scenarios (such as 8K VRF instances).

[0027] Based on the above, embodiments of the present invention provide a multi-VRF routing processing method, apparatus, switching chip, and network device, aiming to solve the problem of wasted hardware resources caused by VRF instances independently occupying TCAM entries in traditional multi-VRF architectures. By introducing a joint encoding mechanism of VRF-ID and destination IP address, the utilization efficiency of key hardware resources such as TCAM is significantly improved while ensuring the accuracy of route lookup.

[0028] The following is an exemplary description of the multi-VRF routing processing method provided by the present invention. See [link to documentation]. Figure 2 The method includes, for example Figure 2 The following steps are described: S11: Concatenate the virtual route forwarding instance identifier of the data packet to be searched with the destination IP address to form a combined data segment.

[0029] S12: Perform a longest mask matching operation on the combined data to find a matching target route entry in the multi-level hardware lookup table structure used to store routing information. Each level of the multi-level hardware lookup table structure is built based on the combined data.

[0030] After a data packet enters the switching device, its Virtual Router Forwarding Instance ID (VRF ID) is first determined based on its ingress port or tag information. This VRF ID is used to distinguish logically isolated routing spaces between different users or services.

[0031] At the same time, the destination IP address of the data packet is extracted and used as a key field for subsequent route lookup.

[0032] The core of this invention lies in the fact that instead of treating the VRF ID and the destination IP address as two independent dimensions, they are concatenated into a unified combined data. This combined data participates as a whole in the subsequent longest mask matching process.

[0033] For example, assuming a data packet has a VRF ID of 8190 and a destination IP address of 1.1.1.5, the system will combine these two fields into a single logical "lookup key," denoted as `[VRF=8190, IP=1.1.1.5]`. This combined data will be treated as a single operation object throughout the entire lookup process.

[0034] The combined data can be in the form of a continuous bit string or a structured lookup key, as long as it remains consistent during subsequent lookups. The specific encoding method can be flexibly set according to hardware implementation requirements.

[0035] A multi-level hardware lookup table structure is used to store routing entries, and the Longest Prefix Match (LPM) operation is performed based on the combined data generated above to locate the matching target routing entry.

[0036] This multi-level hardware lookup table structure includes at least two levels of storage units, such as a combination of Tri-State Content Addressable Memory (TCAM) and Static Random Access Memory (SRAM), or other architectures suitable for high-speed lookups. Crucially, the entries stored at each level of this multi-level structure are built upon composite data. For example, higher-level storage units (such as TCAM) store prefix information for the composite data, such as the generic pattern corresponding to "VRF=81xx, IP=1.1.1.0 / 24"; lower-level storage units (such as SRAM) store more precise composite data entries, or even complete routing configuration information, such as next-hop address, outgoing port, QoS policy, etc.

[0037] When a lookup request is initiated using the combined data corresponding to the current data packet, the lookup engine performs the longest mask matching operation layer by layer in the entire multi-level structure, prioritizing the entry with the longest matching prefix, and finally obtaining the uniquely matching target route entry.

[0038] Since multiple different VRF instances with the same IP address prefix can be considered as having "similar combined data prefixes" in this invention, they may share the same high-level prefix entry. For example, 1.1.1.0 / 24 under VRF 8190 and 1.1.1.0 / 24 under VRF8189 form different complete data after being combined, but their high-level prefixes may overlap, thus allowing them to share the same TCAM entry.

[0039] This mechanism significantly reduces the use of high-cost hardware resources (especially TCAM), improves the overall utilization of routing table entries, and thus supports larger-scale VRF deployments and denser routing table capacity.

[0040] This method encodes the VRF ID and the destination IP address into a combined data segment, and performs longest mask matching based on this combined data throughout the multi-level hardware lookup structure. This enables prefix sharing across VRF instances and effectively solves the technical problem of rapid consumption of routing resources due to the increase in the number of VRFs in traditional solutions.

[0041] To further improve search efficiency and ensure that the hardware circuit can efficiently perform the longest mask matching operation, this embodiment of the invention uses a binary encoding-based concatenation method for generating the combined data in step S11. See also Figure 3 Step S11 may include the following sub-steps: S111: Convert the virtual route forwarding instance identifier and destination IP address of the data packet to be searched into the first binary representation and the second binary representation, respectively.

[0042] The VRF ID of the packet to be searched is converted into a first binary representation, and the destination IP address is converted into a second binary representation.

[0043] The first binary representation refers to encoding the integer value of the VRF ID as a binary bit string of fixed or variable length. For example, if the system supports a maximum of 8192 VRF instances, the VRF ID can be represented by a 13-bit binary number (because 2^13 = 8192). For example, if the VRF ID is 8190, its binary representation is `11111111111110b`.

[0044] The second binary representation refers to the 32-bit binary form of a standard IPv4 address. For example, the destination IP address `1.1.1.5` corresponds to the binary representation `00000001 00000001 00000001 00000101`.

[0045] The conversion process is completed by the message parsing module inside the switching chip, which can be achieved at the beginning of the data packet entering the lookup pipeline with extremely low latency.

[0046] S112: Concatenate the first binary representation and the second binary representation to form an extended bit string as combined data.

[0047] The first binary representation and the second binary representation are concatenated in a preset order to form an extended bit string as the final combined data.

[0048] For example, the 3-bit binary representation of VRF ID 8190 is 1111111111110, and the 32-bit binary representation of IP address 1.1.1.5 is 00000001000000010000000100000101. Combining these two bits results in 1111111111110 0000000100000001000000100000101.

[0049] This extended bit string serves as a complete lookup key, participating in the longest prefix matching operation throughout the multi-level hardware lookup table structure.

[0050] To achieve an efficient, scalable, and resource-saving routing lookup mechanism, in one optional implementation, the multi-level hardware lookup table structure of this invention includes a tri-state content-addressable memory and a static random access memory, see [link to relevant documentation]. Figure 4 Step S12 may include the following sub-steps: S121: Use the combined data to perform the longest prefix match with each routing entry in the tri-state content addressing memory to obtain the target pointer to the static random access memory.

[0051] The combined data generated in step S11 is input into TCAM and matched with the longest prefix of each route entry stored therein.

[0052] Each entry stored in TCAM is a high-level prefix information constructed based on the combined data, representing a group of VRF-IP combinations with similar high-bit patterns.

[0053] Each TCAM entry is also associated with a target pointer to an SRAM region, indicating the location for the next level of lookup.

[0054] The matching process follows the longest prefix priority principle: when multiple entries match at the same time, the entry with the longest mask length (i.e. the most matching bits) is selected as the output result.

[0055] Finally, an optimal matching entry and its corresponding target pointer are obtained.

[0056] S122: Locate the corresponding target memory block in the static random access memory based on the target pointer.

[0057] Using the target pointer obtained in S121, the corresponding target storage block is located in SRAM. This storage block is typically a contiguous or pre-allocated memory space used to store a set of semantically related or prefix-similar complete routing entries.

[0058] S123: Use the combined data to perform the longest prefix match with each routing entry in the target storage block to obtain the target routing entry.

[0059] The original combined data is matched one by one with the longest prefix of all routing entries in the target storage block. The entry with the most exact match is then used as the final target routing entry.

[0060] For example, see Figure 5 Currently, there is an entry in TCAM named `11 1111 1111b`. The SRAM block pointed to by this entry contains two routing entries, `8190+1.1.1.0 / 24` and `8189+1.1.1.0 / 24`, which correspond to the combined data `1 1111 1111 1110 0000 0001 0000 0001 0000 0001 0000 0000` and `1 11111111 1101 0000 0001 0000 0001 0000 0001 0000 0000`.

[0061] The combined data to be searched is `1 1111 1111 1110 0000 0001 0000 0001 0000 00010000 0000`. First, the `11 1111 1111b` entry is matched in TCAM using the longest prefix matching algorithm. Then, it is matched in SRAM with the combined data of `8190+1.1.1.0 / 24` and `8189+1.1.1.0 / 24` respectively, resulting in the routing entry of `8190+1.1.1.0 / 24`.

[0062] Building upon the aforementioned routing lookup architecture based on longest mask matching using combined data, this invention further provides a dynamic routing update mechanism. In one possible implementation, see [link to relevant documentation]. Figure 6 The method may also include: S21: Receive a new route message; the new route message includes the identifier of the virtual route forwarding instance to be stored and the IP address to be stored.

[0063] S22: Concatenate the virtual route forwarding instance identifier to be stored with the IP address to be stored to form the combined data to be stored.

[0064] S23: Use the combined data to be stored to perform the longest prefix match with each routing entry in the tri-state content addressing memory to obtain the target pointer to the static random access memory.

[0065] S24: Locate the corresponding target memory block in the static random access memory based on the target pointer.

[0066] S25: When the remaining capacity of the target storage block is sufficient, store the complete routing information of the combined data to be stored into the target storage block.

[0067] S26: When the remaining capacity of the target storage block is insufficient, reassemble and store all routing entries and combined data to be stored in the target storage block.

[0068] When a new route message is received, the message includes at least: the Virtual Router Forwarding Instance ID (VRF ID) to be stored; the destination IP address and its subnet mask (i.e., IP prefix) to be stored; and optional forwarding attributes such as next-hop information, outgoing port, and label.

[0069] For example: Add a new route `1.1.1.0 / 24` belonging to VRF ID 8188. Concatenate the received VRF ID and the destination IP address in the same way as in the lookup phase to form a combined data to be stored: `1 1111 11111100 0000 0001 0000 0001 0000 0001 0000 0001 0000 0000`.

[0070] See also Figure 5 Using the combined data to be stored, find the existing entry in TCAM that has the longest common prefix with it, and get the entry `11 1111 1111b`. Obtain a target pointer to SRAM and find the corresponding storage block in SRAM, which now contains two routing entries. This storage block can also store one more routing entry. Simply store the newly added routing entry into this storage block.

[0071] If a new route `1.1.1.0 / 24` belonging to VRF ID 8187 is added at this time, and the storage block capacity is insufficient, the storage reorganization mechanism will be activated to reorganize all existing route entries in the target storage block as well as the new entry to be inserted.

[0072] In one possible implementation, step S26 may include the following sub-steps: S261: Extract existing combined data corresponding to all existing routing entries in the target storage block.

[0073] Read all existing routing entries and their existing combination data stored in the target storage block that is currently full or about to overflow.

[0074] S262: Re-cluster existing combined data and combined data to be stored based on binary prefix similarity.

[0075] All existing combined data and the combined data to be inserted and stored are included in the analysis set, and cluster analysis is performed based on their prefix similarity in binary representation.

[0076] "Prefix similarity" refers to the number of consecutive identical bits in the high-order bits of two combined data. The higher the number, the more likely the two data pairs are to share a higher-order prefix during the longest prefix matching search.

[0077] Clustering algorithms can employ: hierarchical clustering: constructing a binary prefix tree to identify the longest shared path, or the optimal partitioning strategy under the constraint of preset maximum block capacity.

[0078] This process identifies several subsets of routes with high prefix consistency, each of which is suitable for allocation to the same SRAM storage block.

[0079] S263: Based on the re-clustering results, create new static random access memory blocks and reallocate the storage contents.

[0080] Based on the clustering results, create one or more new SRAM storage blocks, redistribute the routing entries in the original storage blocks according to their cluster affiliation to different new blocks, and assign the new routing entries to be inserted this time to the best matching cluster group and write them to the corresponding new storage blocks.

[0081] S264: Update the pointer relationships in the tri-state content-addressable memory and static random access memory.

[0082] Then, each new storage block is associated with the corresponding entry in TCAM.

[0083] For example, a new route `1.1.1.0 / 24` for VRF ID 8187 is added. The existing combined data in the storage block is retrieved to obtain the combined data as shown in the image. Table 1

[0084] Extracting the common prefix from these four data combinations yields `1 1111 1111 1`, but the storage block can only hold 3 routes. Since there are 4 routes, we further extract one bit of the common prefix, resulting in a 12-bit common prefix. This gives us `11111 1111 11` and `1 1111 1111 10`. Therefore, we now store two entries, `1 1111 1111 11` and `1 111111111 10`, in the TCAM, pointing to two storage blocks in SRAM, storing VRF8188-8190 and 8187 respectively. Figure 7 As shown.

[0085] To adapt to application scenarios with larger-scale routing tables and higher aggregation levels (such as carrier backbone networks and data center interconnections), one possible implementation could include a multi-level hardware lookup table structure comprising a tri-state content-addressable memory, a first static random access memory (SRAM1), and a second static random access memory (SRAM2). This structure, by adding a prefix convergence layer, achieves a more refined hierarchical matching mechanism, further reducing dependence on TCAM while ensuring lookup performance. See also Figure 8 Step S12 may include the following sub-steps: S121: Use the combined data to perform the longest prefix match with each routing entry in the tri-state content addressing memory to obtain the first target pointer pointing to the first static random access memory.

[0086] S122`: Locate the corresponding first target memory block in the first static random access memory according to the first target pointer.

[0087] S123`: Use the combined data to perform the longest prefix match with each routing entry in the first target storage block to obtain a second target pointer pointing to the second static random access memory.

[0088] S124`: Locate the corresponding second target memory block in the second static random access memory according to the second target pointer.

[0089] S125`: Use the combined data to perform longest prefix matching with each routing entry in the second target storage block to obtain the target routing entry.

[0090] The combined data generated from the data packet to be searched is input into TCAM and matched with the longest prefix of each route entry stored therein. The first target pointer points to a storage block in SRAM1. Based on the first target pointer, the corresponding first target storage block is found in SRAM1. This storage block is used to store a set of intermediate route indices with common higher-layer prefix characteristics. The role of SRAM1 is to achieve second-level prefix convergence, that is, to further refine the classification after the initial screening in TCAM. Each storage block contains several entries, each recording a more precise combined data prefix and its corresponding second target pointer, pointing to the specific location in SRAM2.

[0091] The original combined data is then used to perform a longest prefix match against all entries in the first target memory block to find the match with the longest mask, thus obtaining a second target pointer to SRAM2. Based on the second target pointer, the final second target memory block is located in SRAM2.

[0092] The combined data is used to perform a final longest prefix match with all routing entries in the second target storage block. The entry with the most matching bits is selected as the final target routing entry, and the corresponding forwarding decision is output.

[0093] For example, such as Figure 7 The storage diagram of the two-tier storage architecture in the three-tier storage is as follows: Figure 9 As shown, `11 1111 1111b` is stored in the TCAM, and the memory block pointed to by `11 1111 1111b` stores `111 1111 1111b` and `111 1111 1110b`. `111 1111 1111b` and `111 1111 1110b` then point to corresponding memory blocks in SRAM2. This method can further save space in the TCAM.

[0094] The method may also include: When no matching target route entry is found in the multi-level hardware lookup table structure, the default route entry is used for packet forwarding.

[0095] When no match is detected, the forwarding engine automatically activates the default route entry and performs packet encapsulation and forwarding based on the specified next-hop address and outgoing interface. This process requires no software intervention and can achieve low-latency response at the pure hardware level, thereby ensuring the continuity and reliability of network communication.

[0096] Furthermore, embodiments of the present invention also provide a multi-VRF routing processing device, see [link to related document]. Figure 10 The multi-VRF routing processing device 300 includes: The data splicing unit 310 is used to splice the virtual routing forwarding instance identifier of the data packet to be searched with the destination IP address to form a combined data segment.

[0097] The route lookup unit 320 is used to perform a longest mask matching operation on the combined data in order to find a matching target route entry in the multi-level hardware lookup table structure used to store routing information; wherein each level entry in the multi-level hardware lookup table structure is established based on the combined data.

[0098] Furthermore, embodiments of the present invention also provide a switching chip for performing the multi-VRF routing processing method described above.

[0099] Furthermore, embodiments of the present invention also provide a network device, including the switching chip described above and a multi-level hardware lookup table structure for storing routing entries.

[0100] In summary, the multi-VRF routing processing method, apparatus, switching chip, and network device provided by this invention effectively overcomes the resource bottleneck of each VRF instance independently occupying TCAM entries in traditional schemes by jointly encoding the VRF ID and destination IP address into an extended bit string as a unified lookup key, and performing the longest prefix matching operation based on this combined data in the entire multi-level hardware lookup table structure (such as TCAM+SRAM or multi-level SRAM). Since routing entries with the same or similar IP address prefixes under different VRF instances may still share the high-order prefix pattern after combination, the same prefix entry can be shared in higher-level storage units (such as TCAM), significantly reducing TCAM resource consumption and improving the space utilization of the hardware routing table. Furthermore, by combining the storage block capacity judgment during dynamic route insertion with the reorganization clustering mechanism based on binary prefix similarity, efficient organization and load balancing of routing entries can be achieved on the SRAM side, avoiding local overflow and improving system scalability. In addition, the design supporting two or more hierarchical lookup structures enhances architectural flexibility and is suitable for high-density multi-VRF application scenarios such as large-scale data centers, cloud networks, and carrier backbone networks.

[0101] In the embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0102] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0103] If the functionality is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0104] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0105] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A multi-VRF routing processing method, characterized in that, The method includes: The virtual route forwarding instance identifier of the data packet to be found is concatenated with the destination IP address to form a combined data segment; A longest mask matching operation is performed on the combined data to find a matching target route entry in a multi-level hardware lookup table structure used to store routing information; wherein each level of the multi-level hardware lookup table structure is built based on the combined data.

2. The method as described in claim 1, characterized in that, The step of concatenating the virtual route forwarding instance identifier of the data packet to be searched with the destination IP address to form a combined data segment includes: Convert the virtual route forwarding instance identifier and the destination IP address of the data packet to be searched into the first binary representation and the second binary representation, respectively; The first binary representation and the second binary representation are concatenated to form an extended bit string as combined data.

3. The method as described in claim 1, characterized in that, The multi-level hardware lookup table structure includes a tri-state content-addressable memory and a static random access memory; the longest mask matching operation performed on the combined data to find a matching target route entry in the multi-level hardware lookup table structure used to store routing information includes: The combined data is used to perform longest prefix matching with each routing entry in the tri-state content addressing memory to obtain a target pointer pointing to the static random access memory. Based on the target pointer, locate the corresponding target memory block in the static random access memory; The combined data is used to perform longest prefix matching with each routing entry in the target storage block to obtain the target routing entry.

4. The method as described in claim 3, characterized in that, The method further includes: Receive a route addition message; the route addition message includes the identifier of the virtual route forwarding instance to be stored and the IP address to be stored. The virtual route forwarding instance identifier to be stored is concatenated with the IP address to be stored to form the combined data to be stored; The combined data to be stored is matched with the longest prefix of each routing entry in the tri-state content addressing memory to obtain a target pointer to the static random access memory. Based on the target pointer, locate the corresponding target memory block in the static random access memory; When the remaining capacity of the target storage block is sufficient, the complete routing information of the combined data to be stored is stored in the target storage block; When the remaining capacity of the target storage block is insufficient, all routing entries in the target storage block and the combined data to be stored are reassembled and stored.

5. The method as described in claim 4, characterized in that, The reorganization and storage of all routing entries and the combined data to be stored in the target storage block includes: Extract the existing combined data corresponding to all existing routing entries in the target storage block; The existing combined data and the combined data to be stored are re-clustered based on binary prefix similarity. Based on the re-clustering results, create new static random access memory blocks and reallocate the storage contents; Update the pointer relationships in the tri-state content-addressable memory and the static random access memory.

6. The method as described in claim 1, characterized in that, The multi-level hardware lookup table structure includes a tri-state content-addressable memory, a first static random access memory, and a second static random access memory; the longest mask matching operation performed on the combined data to find a matching target route entry in the multi-level hardware lookup table structure used to store routing information includes: The combined data is used to perform longest prefix matching with each routing entry in the tri-state content addressing memory to obtain a first target pointer pointing to the first static random access memory. Based on the first target pointer, locate the corresponding first target memory block in the first static random access memory; The combined data is used to perform longest prefix matching with each routing entry in the first target storage block to obtain a second target pointer pointing to the second static random access memory. Based on the second target pointer, locate the corresponding second target memory block in the second static random access memory; The combined data is used to perform longest prefix matching with each routing entry in the second target storage block to obtain the target routing entry.

7. The method as described in claim 1, characterized in that, The method further includes: When no matching target route entry is found in the multi-level hardware lookup table structure, the default route entry is used for packet forwarding.

8. A multi-VRF routing processing device, characterized in that, include: The data splicing unit is used to splice the virtual route forwarding instance identifier of the data packet to be searched with the destination IP address to form a combined data segment; A route lookup unit is used to perform a longest mask matching operation on the combined data to find a matching target route entry in a multi-level hardware lookup table structure used to store routing information; wherein each level entry in the multi-level hardware lookup table structure is established based on the combined data.

9. A switching chip, characterized in that, Used to perform the method as described in any one of claims 1 to 7.

10. A network device, characterized in that, It includes the switching chip as described in claim 9 and a multi-level hardware lookup table structure for storing routing entries.

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