Monolithic wordlines, methods of manufacturing monolithic wordlines, and systems including monolithic wordlines

Abstract

Monolithic wordlines (WLs), methods of fabricating monolithic wordlines, and systems including monolithic wordlines are disclosed. The monolithic word line includes a conductive element and a first dielectric. A conductive element connects the array WL at the first edge in the array region to the pad WL at the second edge in the pad region. A conductive element is disposed in the interconnect region between the first edge and the second edge. A first dielectric is disposed on the array WL, the conductive elements, and the pad WL. The first dielectric has a dielectric surface extending from the interconnect region to the pad region. The conductive elements and the first dielectric form a monolithic WL from the array WL and the pad WL through the second edge.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 720,163, filed November 13, 2024, and U.S. Patent Application No. 19 / 334,796, filed September 19, 2025, the disclosures of which are fully set forth herein and are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosure generally relates to memory devices. More specifically, the subject matter disclosed herein relates to the formation of monolithic word lines in memory circuitry. Background Technology

[0003] This background section is intended to provide context only, and the disclosure of any concept in this section does not constitute an admission that the concept is prior art.

[0004] Three-dimensional (3D) memory fabrication is gaining popularity. 3D memory devices, such as vertically stacked dynamic random access memory (VSDRAM) and vertical NAND (V-NAND) flash memory, consist of memory cells stacked vertically to increase storage density. A characteristic of 3D memory circuitry is the arrangement of bit lines (BL) and word lines (WL). As memory density increases, the arrangement of BL and WL can lead to problems such as short circuits, which represent defective electrical connections between two points.

[0005] However, existing technologies for preventing short circuits and other device failures face several challenges, especially for high-density and high aspect ratio memory circuits. Techniques such as stitch (or splicing) WL, precise device profile fabrication, optimized patterning and photolithography, precise deposition of insulating materials, and analysis of device profiles are expensive, difficult to implement, and may still carry the risk of short circuits and defects.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background information disclosed, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] To overcome these problems, a system and method for forming an integrated array and pad lines (WL) in a three-dimensional (3D) memory device are described herein. In some embodiments, the 3D memory device includes a structure connecting WLs from WL pad regions to an array region. The structure includes a conductive element and a first dielectric. The conductive element connects an array WL at a first edge in the WL array region to a pad WL at a second edge in the WL pad region. The conductive element is disposed in an interconnect region between the first and second edges. The first dielectric is disposed on the array WL, the conductive element, and the pad WL. The first dielectric has a dielectric surface extending from the interconnect region to the WL pad region. The conductive element and the first dielectric form a monolithic WL from the array WL and the pad WL through the second edge.

[0008] In some embodiments, the structure further includes a second dielectric disposed on a first dielectric in the interconnect region and a third dielectric disposed on a first dielectric in the WL pad region. In some embodiments, the predetermined thickness is equal to the gate oxide thickness. In some embodiments, the first dielectric is different from the second dielectric, the third dielectric, or both the second dielectric and the third dielectric. Attached Figure Description

[0009] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a system utilizing a 3D memory circuit according to an embodiment.

[0011] Figure 2 This is a diagram illustrating a 3D memory circuit utilizing a monolithic WL structure according to an embodiment.

[0012] Figure 3 This is a diagram showing three views illustrating the cover manufacturing process of a monolithic WL according to an embodiment.

[0013] Figure 4 This is a diagram showing the first half of the manufacturing process of a single WL sheet according to an embodiment, in a 3D view.

[0014] Figure 5 This is a diagram showing the latter half of the cover manufacturing process of a single WL in a 3D view according to an embodiment.

[0015] Figure 6 This is a diagram illustrating the first half of the cover manufacturing process for a monolithic WL in an array view according to an embodiment.

[0016] Figure 7 This is a diagram showing the latter half of the cover manufacturing process for a monolithic WL in an array view according to an embodiment.

[0017] Figure 8 This is a diagram illustrating the first half of the cover manufacturing process for a monolithic WL in an array view according to an embodiment.

[0018] Figure 9 This is a diagram showing the latter half of the cover manufacturing process for a monolithic WL in an array view according to an embodiment.

[0019] Figure 10 This is a diagram illustrating the process flow for forming interconnect regions according to an embodiment.

[0020] Figure 11 This is a diagram showing three views illustrating the mask process flow for manufacturing a monolithic WL according to an embodiment.

[0021] Figure 12 This is a diagram illustrating the first half of the mask process flow for manufacturing a monolithic WL in an array view according to an embodiment.

[0022] Figure 13 This is a diagram showing the latter half of the mask process flow for manufacturing a monolithic WL in an array view according to an embodiment.

[0023] Figure 14 This is a diagram illustrating the first half of the mask process flow for manufacturing a monolithic WL in an array view according to an embodiment.

[0024] Figure 15 This is a diagram showing the latter half of the mask process flow for manufacturing a monolithic WL in an array view according to an embodiment.

[0025] Figure 16 This is a diagram illustrating the first half of the mask process flow for manufacturing a monolithic WL in an interconnect view according to an embodiment.

[0026] Figure 17 This is a diagram showing the latter half of the mask process flow for manufacturing a monolithic WL in an interconnect view according to an embodiment.

[0027] Figure 18 This is a flowchart illustrating the process of manufacturing a monolithic WL structure of a memory circuit according to an embodiment.

[0028] Figure 19 This is a flowchart illustrating process 1820 for preparing one or more monolithic WL channels using a cap according to an embodiment.

[0029] Figure 20 This is a flowchart illustrating process 1820 for fabricating one or more monolithic WL pathways using a mask according to an embodiment. Detailed Implementation

[0030] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, those skilled in the art will understand that aspects of the disclosure may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0031] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily preferred or advantageous over other embodiments. Additionally, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two-dimensional", "pre-determined", "pixel specific", etc.), and uppercase entries (e.g., "counter clock", "row select", "pixout", etc.) may be used interchangeably with their corresponding non-uppercase versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeability should not be considered inconsistent with each other.

[0032] Furthermore, depending on the context of this discussion, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures shown and discussed herein (including component diagrams) are for illustrative purposes only and are not drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to others. Additionally, reference numerals have been repeated in the figures where appropriate to indicate corresponding and / or similar elements. In the following, the figures depicting various components, structures, interconnections, construction, and manufacturing steps are primarily for illustrative purposes. They are not intended to accurately describe these elements. Cross-sectional representations may be used to represent 3D blocks in 3D structures. In some cases, related components in the figures are shown clearly, while other components are shown with lower sharpness or clarity to avoid confusion and improve contrast and clarity. These components may be referenced in the preceding figures and therefore do not need to be described again. These components may also have little to do with the components being described. Furthermore, the shading of components in the figures may not have a consistent design and may be altered to maintain sharpness and contrast in the figures. For example, component A in… Figure X The figures may have light shading in the center, but dark shading in Figure Y. Furthermore, as mentioned above, components in the figures may not be drawn to scale.

[0033] The terminology used herein is for the purpose of describing some exemplary embodiments only and is not intended to limit the claimed subject matter. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification specify the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0034] It will be understood that when an element or layer is referred to as being on, "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers present. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers present. The same reference numerals always denote the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] As used herein, the terms “first,” “second,” etc., serve as labels for nouns that follow them and do not imply any kind of order (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to denote parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is merely for simplicity of description and ease of discussion; it does not imply that the construction or architectural details of such components or units are identical across all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0036] As used herein, the term "monolithic" means "formed from a single element." A single or monolithic element may comprise a uniformly distributed material. "Monolithic formation" refers to the simultaneous formation of elements to create a monolithic, single, or monolithic element. This contrasts with the formation of an element by stitching together two or more individual elements, or by integrating two or more individual elements together, through joining or connecting them. Stitching two or more individual elements together can create an uneven surface at the stitching point, causing the surface to become skewed, bent, or warped, which can lead to interlayer short circuits, fractures, and other defects.

[0037] As used herein, the term "path" refers to a patterned channel or trench filled with material, prepared according to a specified function. When the patterned channel or trench is filled with metal, it becomes a conductive line used as a WL or BL in a memory circuit or any other conductive line carrying a signal in the circuit. The term "path" is sometimes used to mean channel, hollow space, trench, pattern, patterned line, or wire.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and not as having an idealized or overly formalized meaning.

[0039] Many applications, especially in artificial intelligence (AI) and signal processing, require massive storage capacity and high-throughput computing. To meet these needs, high-density memory circuitry in 3D has been developed. A typical 3D dynamic random access memory (DRAM) device vertically stacks multiple layers of memory cells. Bit lines (BLs) and word lines (WLs) are arranged vertically to access cells in different layers. BLs and WLs are conductive elements used to select memory cells that can be arranged in row and column arrays. WL pads are structures that allow the WL to be connected to other components of the memory circuitry and external circuitry. Thus, the WL can extend from the pad region to the array region. When this WL extending from the pad region to the array region is formed in a single process step, the resulting WL can be referred to as a monolithic WL.

[0040] Hereinafter, systems and methods for monolithic formation of WLs from array WLs and pad WLs are described. In some embodiments, a 3D memory device includes a structure connecting WLs from WL pad regions to array regions. The WL pad regions have one or more WLs, referred to as pad WLs for ease of reference. Similarly, the WL array regions have one or more WLs, referred to as array WLs. Typically, the array WL is shorter than the pad WL. The structure includes conductive elements and a first dielectric. The conductive elements connect the array WL in the WL array region at a first edge to the pad WL in the WL pad region at a second edge. The conductive elements are disposed in an interconnect region between the first and second edges. The first dielectric is disposed on the array WL, the conductive elements, and the pad WLs. The first dielectric has a dielectric surface extending from the interconnect region to the WL pad region. The conductive elements and the first dielectric form a monolithic WL from the array WL and pad WLs through the second edge. The structure also includes a second dielectric disposed on the first dielectric in the interconnect region and a third dielectric disposed on the first dielectric in the WL pad region. In some embodiments, a predetermined thickness is equal to the gate oxide thickness. In some embodiments, the first dielectric is different from the second dielectric, the third dielectric, or both the second and third dielectrics. In some embodiments, all three dielectrics are different from each other. The first edge is the boundary between the array region and the interconnect region. The second edge is the boundary between the interconnect region and the pad region, and is referred to as the cell block edge. A cell block edge is a well-defined edge of a semiconductor block that serves as a unit for some physical property or quality measurement (e.g., flatness, purity, geometric regularity). The conductive element is at least one of a metal and titanium nitride. In some embodiments, the metal can be any of the following: tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), and rhodium (Rh). The conductive element can also be a combination of two or more of the above materials.

[0041] The monolithic fabrication process for weld lines (WLs) in 3D memory circuits results in flat surfaces for conductive elements between the array WL and the pad WL, avoiding the risk of short circuits or breakages in the WL region. This is achieved by simultaneously forming the WL in the array region and the WL in the pad region as one or more monolithic WLs. This contrasts with techniques that form the array WL and pad WL separately or one after another and then stitch them together. Stitching WLs from two separate regions or areas can lead to layer-to-layer short circuits or line breaks. These techniques, which form the two types of WLs separately, result in uneven or sloping surfaces at the boundary between the connecting region and the pad region.

[0042] This technology is effective in manufacturing processes. It is particularly advantageous for high aspect ratio vertically stacked memory circuits. The inherently flat surface is achieved by simultaneously depositing metal along the entire WL, including both the array region and the pad region.

[0043] Figure 1 This is a block diagram illustrating a system utilizing 3D memory circuitry according to an embodiment. System 100 includes digital baseband circuitry 105, radio frequency (RF) transceiver circuitry 150, and analog baseband circuitry 170. System 100 may represent a digital system or a mobile system. When system 100 is used as a digital system without mobile circuitry, RF transceiver circuitry 160 and analog baseband circuitry 190 are not used. Additionally, when system 100 is used as a mobile device, many digital features are scaled down, and some features may be unavailable.

[0044] The digital baseband circuit 105 includes a central processing unit (CPU) 110, a memory controller 120, and an I / O controller 130. System 100 may include more or fewer components than those listed above. Additionally, components may be integrated into another component. Integration may be partial and / or overlapping. For example, memory controller 120 and I / O controller 130 may be integrated into a single controller.

[0045] CPU 110 is a programmable device that can execute programs or sets of instructions to perform tasks. CPU 110 can be a host that controls or manages other processors or devices. Specifically, CPU 110 may include an application programming interface (API), application, or driver executed by CPU 110 to perform a specified task. CPU 110 may be a general-purpose processor, a digital signal processor, a microcontroller, or a specially designed processor. CPU 110 may include a single core or multiple cores. Each core may have multiple threads. CPU 110 may have simultaneous multithreading features to further utilize the parallelism caused by multithreading across multiple cores. In addition, CPU 110 may have multi-level internal caches. CPU 110 communicates with other devices in the system via bus 115. Bus 115 can be any suitable bus that connects CPU 110 to other devices. For example, bus 115 may be a direct media interface (DMI). Bus 115 may also include other custom buses (such as a bus for interfacing to the analog portion when system 100 is used as a mobile device).

[0046] Memory controller 120 controls memory devices such as main memory 122, cache memory 124, and flash memory 126. Main memory 122 includes RAM comprising static random access memory (SRAM) and dynamic RAM (DRAM), and / or read-only memory (ROM) and other types of memory. DRAM may include synchronous DRAM (SDRAM), DDR SDRAM with variants such as second-generation double data rate (DDR2), DDR3, DDR4, DDR5, and DDR6. Main memory 122 may store instructions or programs loaded from a mass storage device that, when executed by CPU 110, cause CPU 110 to perform operations for a specified task. Main memory 122 may also store data used in operation. ROM may be a solid-state drive (SSD) and includes instructions, programs, constants, or data that are maintained regardless of whether it is powered on. Instructions or programs may correspond to functions described below. In one embodiment, the main memory 122 includes a 3D memory device or circuitry 128 (such as VSDRAM and V-NAND flash memory), or any other memory device having memory cells that are vertically stacked to increase storage density.

[0047] I / O controller 130 controls input device 132, output device 134, and mass storage device 136. Input device 132 may include a keyboard, mouse, image sensor or camera, game console, and microphone. Other input devices, such as styluses, joysticks, scanners, and light pens, may also be available. Input devices may also have a user interface that interfaces with a computer or laptop computer 142 and / or user 144. Output device 134 may include a printer, monitor or screen, headphones, and multi-monitor sets. When used as a computing device without mobile features, a monitor is a high-resolution display. For gaming and other multi-monitor modes, multi-monitor sets provide high resolution with multiple monitors (e.g., three monitors). When used for mobile communications, a screen provides the user with a main interface for navigation, accessing various applications, and performing tasks. The screen may use an organic light-emitting diode (OLED) (Super Retina) display with multi-touch or haptic touch features. Mass storage device 136 may include CD-ROM, hard disk, and solid-state drive (SSD). I / O controller 130 also has a network interface card (NIC) 146 that provides an interface to a network and wireless medium (or network) 148.

[0048] Additional devices or bus interfaces can be used for interconnection and / or expansion. Some examples may include the Peripheral Component Interconnect Fast (PCIe) bus, Universal Serial Bus (USB), etc.

[0049] The RF transceiver circuit 150 includes a transmitter 152, an antenna array 158, a voltage-controlled oscillator (VCO) 156, and a receiver 154. The RF circuit 150 operates in the high GHz band to accommodate modern cellular devices, such as wireless fifth generation (5G).

[0050] Transmitter 152 transmits digital baseband data to antenna array 158. Transmitter 152 may include a digital-to-analog converter (DAC), an automatic gain controller (AGC), intermediate frequency (IF) circuitry, a mixer, RF circuitry, and a power amplifier (PA). Other components may include filters, amplifiers, multiplexers, coaxial cables, phase shifters, etc. The DAC converts digital data f1 (not shown) into an analog signal f2 (not shown). The AGC automatically adjusts the signal amplitude of f2 to generate a signal f3 (not shown) to maintain a consistent strength level in dynamic and changing environments. The IF circuitry performs intermediate frequency processing (such as filtering) to generate a signal f4 (not shown). The mixer converts the frequency of signal f4 to another frequency. This is done by mixing signal f4 with a signal v from VCO 156. t(Not shown) Mixing is used to accomplish this. Mixing here refers to frequency modulation that transforms signal f4 into a signal f5 (not shown) of a different frequency. For the transmitter, the transformed frequency is higher than the frequency of f4. This conversion is called upconversion. For 5G communication, the frequency range can include low-frequency bands (below 1 GHz), mid-frequency bands (1 GHz to 6 GHz), and high-frequency bands (24 GHz to 53 GHz or higher). The resulting signal f5 then undergoes various radio frequency processing (such as high-pass filtering) performed by RF circuitry to produce signal f6 (not shown). Signal f6 is boosted and amplified by a PA to produce signal f7 (not shown). Signal f7 then enters antenna array 158 to be transmitted to the appropriate destination and medium (e.g., a base station). Antenna array 158 uses beamforming to focus the radio waves from f7 in the desired direction. Antenna array 158 can be used for both transmitting and receiving. In reception, antenna array 158 receives RF signals and transmits them to receiver 154. The number of antennas in antenna array 158 depends on the desired coverage area. Antenna array 158 may include antennas 161, 162, 163, and 164 configured to operate in conjunction with 5G communication, Gigabit LTE, Wi-Fi (e.g., 2.4 GHz, 5 GHz, and 6 GHz), and Bluetooth, respectively. The number of antennas may be more or less than the above.

[0051] The VCO 156 couples multiple in-phase oscillators together to provide low phase noise oscillation. The VCO 156 directs the signal v at a specific frequency. t and v r (Not shown) Generated to the mixer. The VCO 156 may include multiple oscillator core circuits (or VCO cores) to provide high-frequency periodic signals.

[0052] Receiver 154 processes the received signal r7 (not shown) in the reverse manner of transmitter 152. Receiver 154 may include a low-noise amplifier (LNA), RF circuitry, a mixer, IF circuitry, AGC, and an analog-to-digital converter (ADC). Receiver 154 may include more or fewer components than those listed above. The LNA amplifies the weak signal r7 while maintaining a good signal-to-noise ratio (SNR) to produce a signal r6 (not shown) for further processing. Signal r6 is then processed by RF circuitry (e.g., bandpass filtering) to provide signal r5 (not shown). Additional filtering may be performed in the next stage. Signal r5 is then compared with signal v from VCO 156. rA mixer is used to downconvert signal r5 to a signal r4 (not shown) at a suitable low frequency. Similar to the mixer in transmitter 152, but with the opposite operation, the mixer in receiver performs frequency modulation to convert the high-frequency signal r5 into the low-frequency signal r4. Signal r4 is processed by an IF circuit (e.g., additional filtering) to produce signal r3 (not shown). An AGC amplifies and enhances the signal and generates signal r2 (not shown). An ADC converts analog signal r2 into digital data r1 (not shown) that will be processed by CPU 110.

[0053] Analog baseband circuit 170 provides analog processing for various components. Analog baseband circuit 170 controls the processing of signals and data between digital baseband circuit 105 and RF transceiver circuit 150. Analog baseband circuit 170 may include analog and digital components for performing various tasks, including modulation / demodulation and controlling RF transceiver circuit 150, and specialized circuitry for 3G, 4G / LTE, Bluetooth, and 5G communications. Analog baseband circuit 170 may also interface with baseband unit 172, audio device circuitry 174, sensor circuitry 176, Subscriber Identity Module (SIM) card 178, and other components. Audio device circuitry 174 may include operation blocks for processing audio signals and performing audio-related functions such as filtering, correlation, and speech recognition. Audio device circuitry 174 may include digital circuitry for performing Fast Fourier Transform (FFT) to perform signal processing in the frequency domain. Sensor circuitry 176 may include various sensors, such as proximity sensors, ambient light sensors, motion sensors (accelerometers and gyroscopes), compasses, barometers, fingerprint sensors for touch recognition (ID), image sensors for facial ID, light detection and ranging (LiDAR) scanners, etc. SIM card 178 is a small, portable chip that stores the user's phone number and carrier information, allowing the device to connect to a cellular network.

[0054] The power and battery circuitry (or power / battery) 180 provides backup power and battery supply to the entire system. The power and battery circuitry 180 may include a charger to charge the battery. The battery may be a rechargeable lithium-ion battery. Power management may be performed by application software and circuitry to provide low-power modes and performance management.

[0055] System 100 is an example illustrating the role of 3-D memory devices in laptop, desktop, or mobile environments. In many cases, the environment of the application adds additional requirements, including low power consumption, reliable signal integrity, fault tolerance, and reliable operation under extreme conditions, including heat and confined spaces. Examples of other applications that would benefit from 3-D memory devices or circuits include mobile communications (e.g., smartphones, base stations, user equipment), cameras, vehicles, entertainment (e.g., games, multimedia, music, movies), technical design (e.g., animation, graphics), medical (e.g., visualization, medical imaging), robotics, drones, automated test equipment, audio processing, speech synthesizers, video and image analytics, vision, automated facial recognition, artificial intelligence (AI) applications, and data centers.

[0056] Figure 2 This is a diagram illustrating a 3D memory circuit 128 utilizing a monolithic WL structure according to an embodiment. The 3D memory circuit 128 includes a structure 201 and other circuit elements (not shown). The structure 201 includes regions or areas 210, 220, and 225.

[0057] Region 210 is a region having an array of memory cells, which may consist of capacitors for storage elements and transistors for switching control to select, enable, or disable storage elements during memory access operations. The memory cell array may include one or more bit lines (BLs) and word lines (WLs) that provide conductive paths to storage elements for memory addressing. For ease of reference, region 210 may be referred to as an array region, and the WL within the array region may be referred to as an array WL.

[0058] Region 220 is a region having pads for connecting WLs to other circuitry, such as line decoders. Region 220 may be referred to as a WL pad region or pad region. WL pad region 220 includes one or more WLs extending into array region 210 to form one or more monolithic WLs. For ease of reference, region 220 may be referred to as a WL pad region, or simply a pad region, and WLs within the pad region may be referred to as pad WLs. In some embodiments, the array WL is shorter than the pad WL. WLs in memory circuitry are single-line and monolithic. The names array WL and pad WL do not indicate two different WLs. Rather, these terms refer to the same WL existing in two different regions. The portion of a WL located in array region 210 will be referred to as the array WL, and the portion of a WL located in WL pad region 220 will be referred to as the pad WL. Similarly, when a WL passes through an interconnect region connecting the array region and the pad region, the portion of the WL in the interconnect region may be referred to as an interconnect WL. The names “array WL,” “interconnect WL,” and “pad WL” are primarily for ease of reference. For each WL, these three names refer to the same single and monolithic WL extending from inside the pad region 220 through the interconnect region 250 into the array region 230.

[0059] Region 225 is a region where one or more array WLs and one or more pad WLs are joined or connected to form one or more monolithic WLs. A cross-section of region 225 is shown to illustrate the arrangement of various components. This cross-section shows that the array region and pad region of the 3D structure 201 can be considered as internal structures located on the same plane. Region 225 is divided or subdivided into three parts or regions: array region 230, pad region 240, and interconnect region 250. Array region 230 and interconnect region 250 are separated by a boundary or edge 235 referred to as a first edge 235. Pad region 240 and interconnect region 250 are separated by a boundary or edge 245 referred to as a second edge 245. As mentioned above, the second edge 245 can also be referred to as a cell block edge. In memory circuitry, region 225 includes a structure 222 corresponding to the WL.

[0060] Structure 222 includes an array WL 232 in array region 230, a pad WL 270 in pad region 240, and a conductive element 260 in interconnect region 250. The conductive element 260 is an interconnect WL. As mentioned above, although they are referred to by three different names, the array WL, interconnect WL, and pad WL are single monolithic WLs formed simultaneously from the same material. Array WL 232, interconnect WL 260, and pad WL 270 are made of or include at least one of a metal and titanium nitride (TiN). In one embodiment, the metal is at least one of tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), and rhodium (Rh). The metal may also be a combination of the above elements. A conductive element or interconnect WL 260 connects array WL 232 at a first edge 235 in array region 230 to pad WL 270 at a second edge 245 in pad region 240. The conductive element or interconnect WL 260 is disposed in interconnect region 250 between the first edge 235 and the second edge 245.

[0061] Structure 222 also includes a first dielectric 281, a second dielectric 282, and a third dielectric 283. The arrangement of these dielectrics is represented by arrangement 267 in the interconnect region and arrangement 269 in the pad region. In some embodiments, at least one of the first dielectric 281, the second dielectric 282, and the third dielectric 283 includes silicon dioxide (SiO2), silicon nitride (SiN), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), or other high-k dielectrics. In one embodiment, the first dielectric 281, the second dielectric 282, and the third dielectric 283 include different dielectrics. In another embodiment, at least the first dielectric 281 includes a dielectric different from both the second dielectric 282 and the third dielectric 283.

[0062] A first dielectric 281 is disposed on array WL 232, conductive element 260, and pad WL 270. The first dielectric 281 has a dielectric surface 285 extending from interconnect region 250 to WL pad region 240. As discussed above, conductive element 260 and first dielectric 281 form a monolithic WL. In some embodiments, dielectric surface 285 is flat, having a roughness smaller than a predetermined thickness, at least in the region 265 surrounding the second edge 245. The roughness is defined as the difference between the minimum and maximum thickness of the surface. In some embodiments, the predetermined thickness is equal to one of the gate oxide thicknesses (e.g., between sub-nm and 2nm or between 2nm and 3nm).

[0063] As shown in arrangement 267, a second dielectric 282 is disposed on the first dielectric 281 in interconnect region 250, extending from a first edge 235 to a second edge 245. In some embodiments, the second dielectric 282 extends from one conductive element 260 to an adjacent conductive element 260 in interconnect region 250.

[0064] As shown in arrangement 269, a third dielectric 283 is disposed on a first dielectric 281 in a pad region 240, extending from one pad WL 270 to an adjacent pad WL 270 in the pad region 240. In some embodiments, the third dielectric 283 extends from an array region 230 between two adjacent first dielectrics 281 within the second dielectric 282 to near a second edge 245.

[0065] Because metal deposition occurs simultaneously in array WL 232, pad WL 270, and interconnect WL 260, a dielectric surface 285 is obtained. This allows the metal to fill the conductive pathways reserved for the WL within the recessed channels, thus achieving a flat surface at the periphery of the channels in the vertical direction. This is formed through a manufacturing process.

[0066] There are two implementations for the manufacturing process. One is called the cover process, and the other is the mask process. The two processes differ in how the array and pad sides are masked.

[0067] Figure 3 This is a diagram illustrating three views of the cover manufacturing process 300 for a monolithic WL according to an embodiment. Process 300 has three views: 3D view 310, array view 330, and pad view 350. Process 300 includes seven stages. Each stage can be seen in one of the three views above. To maintain clarity and efficiency when presenting the diagram, each view is divided into two parts. The first part includes stages 1 to 4, and the second part includes stages 5 to 7.

[0068] Stage 1: Partially form the array WL on the 3D structure. Stage 2: Deposit a cap mask on top of the 3D structure. Stage 3: Etch and open the WL pad regions. Stage 4: Strip the silicon paths. Stage 5: Remove the cap mask. Stage 6: Remove the substrate oxide. Stage 7: Deposit metal into the WL paths.

[0069] 3D view 310 includes a first part 311 and a second part 312. The first part 311 includes structures 321, 322, 323, and 324, corresponding to stages 1, 2, 3, and 4, respectively. The second part 312 includes structures 325, 326, and 327, corresponding to stages 5, 6, and 7, respectively. Elements in array view 330 and pad view 350 may not be visible in 3D view 310.

[0070] Array view 330 includes a first portion 331 and a second portion 332. The first portion 331 includes structures 341, 342, 343, and 344, corresponding to stages 1, 2, 3, and 4, respectively. The second portion 332 includes structures 345, 346, and 347, corresponding to stages 5, 6, and 7, respectively. Elements in 3D view 310 and pad view 350 may not be visible in array view 330.

[0071] Pad view 350 includes a first portion 351 and a second portion 352. The first portion 351 includes structures 361, 362, 363, and 364, corresponding to stages 1, 2, 3, and 4, respectively. The second portion 352 includes structures 365, 366, and 367, corresponding to stages 5, 6, and 7, respectively. Elements in 3D view 310 and array view 330 may not be visible in pad view 350.

[0072] Figure 4 This is a diagram illustrating the first part 311 of the manufacturing process of a single WL sheet according to an embodiment, shown in a 3D view. The first part 311 includes components respectively related to… Figure 3 The structures 321, 322, 323 and 324 corresponding to stages 1, 2, 3 and 4 are shown in the figure.

[0073] Phase 1 forms structure 321 by partially creating patterns of WL pathways 410 (not shown) and 420 (not shown). The patterns and pathways are formed as follows: Figure 2 Region 220 is shown in the diagram. Passage 410 represents an array WL passage, and passage 420 represents a pad WL passage. The cutouts show the internal structure of the pattern. This structure includes dielectrics 432 and 434 and a semiconductor material (e.g., silicon (Si), polysilicon, silicon germanium (SiGe)) 436. These patterns will be further etched and deposited together with other materials in subsequent stages.

[0074] Phase 2 forms structure 322 by depositing a cap (or cap mask) 430 on top of structure 321 in Phase 1. The cap 430 can be a suitable material to allow selective etching using a hard mask. In some embodiments, the cap 430 comprises amorphous carbon (abbreviated as aC or aC). The purpose is to mask the array side while opening another trench on the pad side. The cap 430 protects the underlying components from contamination. The cap 430 can be deposited using any suitable deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or spin-on glass (SOG).

[0075] Phase 3 forms structure 323 by etching and opening the WL pad region 440. A cap 430 serves as a hard mask for the pad-side openings. This is accomplished by planarizing the cap 430 using a planarization process, such as chemical mechanical polishing (CMP). The height of the cap 430 is reduced to become a planarized cap 435.

[0076] Phase 4 forms structure 324 by stripping semiconductor material (e.g., Si / polysilicon / SiGe) on the pathway 452 in the pad region.

[0077] Figure 5 This is a diagram illustrating the second part 312 of the cover manufacturing process of a single-piece WL according to an embodiment, shown in a 3D view. The second part 312 includes components respectively related to... Figure 3 The structures 325, 326, and 327 corresponding to stages 5, 6, and 7 are shown in the figure.

[0078] Stage 5 forms structure 325 by removing the planarized cap 435. In some embodiments, removal can be performed using oxygen plasma. This can be done by generating an oxygen plasma containing reactive substances such as oxygen radicals. The oxygen radicals react with the cap material (e.g., aC) to generate volatile byproducts (e.g., carbon monoxide CO, carbon dioxide CO2) that can be removed using a vacuum pump.

[0079] Stage 6 forms structure 326 by removing the substrate dielectric (e.g., oxide). This creates hollow spaces at the silicon pathways in the array region and pad region. These hollow spaces correspond to the WL extending from the array region (array WL) to the pad region (pad WL). A cleaning process cleans the dielectric to connect the array hollow spaces to the pad hollow spaces. Enlarged view 510 shows the internal structure of array hollow space 520 and pad hollow space 530. Enlarged view 510 has slightly different shading in some sections to improve clarity. These hollow spaces will allow metallization to be performed simultaneously in both the array region and the pad region, thus... Figure 2 The diagram shows a consistent and flat surface at the boundary between the array region, interconnect region, and pad region.

[0080] Stage 7 forms structure 327 by metallization after depositing oxide material onto the semiconductor material (e.g., Si, polysilicon, SeGe) in the array region, while simultaneously repairing any seams or voids through the dielectric in the pad region. Metallization is accomplished by depositing metal (e.g., TiN, W, Mo) in both the array and pad voids to form a consistent and monolithic WL extending from the pad region to the array region. Because the metal is deposited simultaneously in both the array and pad regions through the cleaned and prepared voids, the resulting WL always has a flat and smooth surface. Therefore, short circuits or defects on the WL are eliminated. The array region 230, interconnect region 250, and pad region 240 are as follows: Figure 2 As shown in the diagram. Similarly, the obtained WL is as follows: Figure 2 232, 260, and 270 are shown in the diagram. The first edge 235 and the second edge 245 are as follows: Figure 2 As shown in the image.

[0081] Figure 6 This is a diagram illustrating the first portion 331 of the cover manufacturing process for a monolithic WL in an array view according to an embodiment. The first portion 331 includes components respectively related to… Figure 3 The structures 341, 342, 343 and 344 corresponding to stages 1, 2, 3 and 4 are shown in the figure.

[0082] Structures 341, 342, 343, and 344 correspond to, respectively, as follows: Figure 3 Phases 1, 2, 3, and 4 are shown. Structures 341, 342, 343, and 344 are seen from the array region in a 2-D view. Except for the elements in structures 341, 342, 343, and 344, which are viewed as 2D views in the array region, the elements in structures 341, 342, 343, and 344 are respectively... Figure 4 The elements in structures 321, 322, 323, and 324 shown are identical. Therefore, except for some observations, the descriptions of the elements in structures 341, 342, 343, and 344 will not be repeated here. Figure 4 The cover 430 in the middle becomes the cover 630 as seen from the array view. Figure 4 The flattened cover 435 in the image becomes cover 635 as seen from the array view.

[0083] Figure 7 This is a diagram illustrating the second part 332 of the cover manufacturing process for a monolithic WL in an array view according to an embodiment. The second part 332 includes components respectively related to... Figure 3 The structures 345, 346, and 347 corresponding to stages 5, 6, and 7 are shown in the figure.

[0084] Structures 345, 346, and 347 correspond to, respectively, as follows: Figure 3 Stages 5, 6, and 7 are shown. Structures 345, 346, and 347 are viewed from the array region in a 2-D view. Except for the elements in structures 345, 346, and 347, which are viewed in the 2D region, the elements in structures 345, 346, and 347 are respectively... Figure 5 The elements in structures 325, 326, and 327 shown are identical. Therefore, except for some observations, the descriptions of the elements in structures 345, 346, and 347 will not be repeated here. Figure 5 The hollow space 520 in the diagram becomes the hollow space 720 in structure 346. Array WL 232 is shown in structure 347. Since these diagrams are considered as array regions, the elements in the pad regions are not visible.

[0085] Figure 8 This is a diagram illustrating the first portion 351 of the cap manufacturing process for a single-piece WL according to an embodiment. The first portion 351 includes components respectively related to… Figure 3 The structures 361, 362, 363, and 364 corresponding to stages 1, 2, 3, and 4 are shown in the figure.

[0086] Structures 361, 362, 363, and 364 correspond to, respectively, as follows: Figure 3 Phases 1, 2, 3, and 4 are shown. Structures 361, 362, 363, and 364 are seen from the pad region in a 2-D view. Except for the elements in structures 361, 362, 363, and 364, which are viewed as 2D views in the pad region, the elements in structures 361, 362, 363, and 364 are respectively... Figure 4 The elements in structures 321, 322, 323, and 324 shown are identical. Therefore, except for some observations, the descriptions of the elements in structures 361, 362, 363, and 364 will not be repeated here. Figure 4 The cover 430 in the middle becomes the cover 830 as seen from the pad view. Figure 4 The flattened cover 435 becomes the cover 835 as seen from the pad view.

[0087] Figure 9 This is a diagram illustrating the second part 352 of the cap manufacturing process for a single-piece WL according to an embodiment. The second part 352 includes components respectively related to… Figure 3 The structures 365, 366, and 367 corresponding to stages 5, 6, and 7 are shown in the figure.

[0088] Structures 365, 366, and 367 correspond to, respectively, as follows: Figure 3 Stages 5, 6, and 7 are shown. Structures 365, 366, and 367 are viewed from the pad region in a 2-D view. Except for the elements in structures 365, 366, and 367, which are viewed as 2D views in the pad region, the elements in structures 365, 366, and 367 are respectively... Figure 5 The elements in structures 325, 326, and 327 shown are identical. Therefore, except for some observations, the descriptions of the elements in structures 365, 366, and 367 will not be repeated here. Figure 5 The hollow space 530 in the pad becomes the hollow space 930 in structure 366. Pad WL 270 is shown in structure 367. Since these figures are considered as pad regions, the elements in the array regions are not visible.

[0089] Figure 10 This is a diagram illustrating a process flow 1000 for forming interconnect regions according to an embodiment. Process flow 1000 illustrates the formation of interconnect elements connecting an array WL and a pad WL in a single metallization, which occurs simultaneously in both the array region and the pad region to form a consistent and monolithic WL. Process flow 1000 corresponds to... Figure 3 The process flow 300 focuses on the interconnection region. Process flow 1000 includes structures 1010, 1020, 1030, 1040, 1050, and 1060. Each structure is the result of a process stage that operates on a previous structure. For structure 1010, the previous structure is a 3D substrate. The order of the processing stages is... Figure 3 The order is the same.

[0090] Stage 1 forms a structure 1010 having dielectrics 1012 and 1014 and a semiconductor channel 1016. An edge 1015 is formed across dielectrics 1012, 1014 and the semiconductor channel 1016. As indicated by arrow 1023, Stage 3 forms a structure 1020 having a silicon nitride (SiN) recess. The recess stops at edge 1025. As indicated by arrow 1035, Stage 4 forms a structure 1030 by performing Si stripping. As indicated by arrow 1045, Stage 6 forms a structure 1040 by oxide cleaning. The first part of Stage 7 forms a structure 1050 by depositing gate oxide (Gox) at layers 1052, 1054, and 1055. In one embodiment, the oxide is of the low-temperature chemical bath deposition (CBD) type for ease of cleaning. The thickness of layer 1052 in the array region around the silicon pathway is thicker than that of layer 1054 in the pad region to provide better chemical reaction with silicon. The second part of stage 7 forms structure 1060 by depositing at least one of a metal and TiN. Structure 1060 shows array region 230, interconnect region 250, and pad region 240. First edge 235 corresponds to edge 1025 at structure 1020. Second edge 245 corresponds to edge 1015 at structure 1010. Dielectrics 281, 282, and 283 are formed by dielectrics 1012 and 1014. Parts of structures 1050 and 1060 are shown in enlarged view 1065. Enlarged view 1065 shows that the thickness d1 of layer 1052 is greater than the thickness d2 of layer 1054.

[0091] A second embodiment of the process for forming a monolithic WL is called a mask process. This process involves the last two stages ( Figure 3 Phases 6 and 7 shown in the diagram are similar to Figure 3 The process of making the lid.

[0092] Figure 11 This is a diagram showing three views of a mask process flow 1100 for manufacturing a monolithic WL according to an embodiment. The process 1100 has three views: an array view 1110, a pad view 1130, and an interconnect view 1150. The process 1100 includes six stages. Each stage can be seen in one of the three views above. To maintain clarity and efficiency in presenting the figures, each view is divided into two parts. The first part includes stages 1 through 3, and the second part includes stages 4 through 6.

[0093] Stage 1 uses high aspect ratio (HAR) oxide etching to etch the array region and pad region. Stage 2 forms the channel silicon nitride substrate recess. Stage 3 removes the semiconductor material (e.g., silicon). Stage 4 cleans the substrate oxide. Stage 5 deposits the gate oxide. Stage 6 deposits metal into the WL path.

[0094] Array view 1110 includes a first portion 1111 and a second portion 1112. The first portion 1111 includes structures 1121, 1122, and 1123, corresponding to stages 1, 2, and 3, respectively. The second portion 1112 includes structures 1124, 1125, and 1126, corresponding to stages 4, 5, and 6, respectively. Elements in pad view 1130 and interconnect view 1150 may not be visible in array view 1110.

[0095] Pad view 1130 includes a first portion 1131 and a second portion 1132. The first portion 1131 includes structures 1141, 1142, and 1143, corresponding to stages 1, 2, and 3, respectively. The second portion 1132 includes structures 1144, 1145, and 1146, corresponding to stages 4, 5, and 6, respectively. Elements in array view 1110 and interconnect view 1150 may not be visible in pad view 1130.

[0096] Interconnection view 1150 includes a first portion 1151 and a second portion 1152. The first portion 1151 includes structures 1161, 1162, and 1163, corresponding to stages 1, 2, and 3, respectively. The second portion 1152 includes structures 1164, 1165, and 1166, corresponding to stages 4, 5, and 6, respectively. Components in array view 1110 and pad view 1130 may not be visible in interconnection view 1150.

[0097] Figure 12 This illustrates the fabrication of a single WL wafer in an array view according to an embodiment. Figure 11 The diagram shows the first part 1111 of the mask process flow 1100. The first part 1111 includes components respectively related to... Figure 11 The structures 1121, 1122, and 1123 corresponding to stages 1, 2, and 3 are shown in the figure.

[0098] Stage 1 forms a hard mask 1210 for structure 1121 on top of the 3D structure. The patterning includes patterns for semiconductor material (e.g., silicon) 1220 and dielectrics 1232 and 1234. Stage 2 forms structure 1122 by opening the hard mask 1210 to make it a mask 1240. An oxide substrate recess 1250 is formed. Stage 3 forms structure 1123 by peeling off the semiconductor material (e.g., silicon).

[0099] Figure 13 This illustrates the fabrication of a single WL wafer in an array view according to an embodiment. Figure 11 The diagram shows the second part 1112 of the mask process flow 1110. The second part 1112 includes components respectively related to... Figure 11The structures 1124, 1125, and 1126 corresponding to stages 4, 5, and 6 are shown in the figure.

[0100] Stage 4 forms structure 1124 by cleaning the substrate oxide, thereby obtaining the cleaned semiconductor and dielectric channel 1310. Stage 5 forms structure 1125 by depositing gate oxide 1320 on the semiconductor and dielectric channel. This stage is similar to... Figure 3 The first part of stage 7 in the capping process is shown in the figure. Stage 6 forms structure 1126 by depositing metal (e.g., Ti, W) into the hollow spaces in the array region and pad region to form WL 1330. Enlarged view 1340 shows WL 1330. This stage is similar to Figure 3 The second part of stage 7 in the cover process is shown in the figure.

[0101] Figure 14 This is a view illustrating the manufacture of a single WL sheet according to an embodiment. Figure 11 The diagram shows the first part 1131 of the mask process flow 1110. The first part 1131 includes components respectively related to... Figure 11 The structures 1141, 1142, and 1143 corresponding to stages 1, 2, and 3 are shown in the figure.

[0102] Phase 1 uses mask 1140 to form structure 1141. Virtual lines or reference lines 1 and 2 are used in conjunction with... Figure 12 The corresponding lines of structure 1121 are the same. Stage 2 forms structure 1142. Mask 1410 in structure 1141 becomes mask 1420. Stage 3 forms structure 1143.

[0103] Figure 15 This is a view illustrating the manufacture of a single WL sheet according to an embodiment. Figure 11 The diagram shows the second part 1132 of the mask process flow 1110. The second part 1132 includes components respectively related to... Figure 11 The structures 1144, 1145, and 1146 corresponding to stages 4, 5, and 6 are shown in the figure.

[0104] Stage 4 forms structure 1144 by cleaning the substrate oxide, thereby obtaining a cleaned semiconductor and dielectric channel 1510. Stage 5 forms structure 1145 by depositing gate oxide 1520 on the semiconductor and dielectric channel. Enlarged view 1546 shows gate oxide 1520. This stage is similar to... Figure 3 The diagram shows the first part of stage 7 in the capping process. Stage 6 forms structure 1146 by depositing metal (e.g., Ti, W) into the hollow spaces in the array region and pad region to form WL 1530. This stage is similar to... Figure 3The second part of stage 7 in the cover process is shown in the figure.

[0105] Figure 16 This is an interconnect view illustrating the fabrication of a monolithic WL according to an embodiment. Figure 11 The diagram shows the first part 1151 of the mask process flow 1110. The first part 1151 includes components respectively related to... Figure 11 The structures 1161, 1162, and 1163 corresponding to stages 1, 2, and 3 are shown in the figure.

[0106] Phase 1 use Figure 12 Structure 1121 and Figure 14 The virtual lines 1 and 2 shown in structure 1141 form structure 1161. Structure 1161 has a semiconductor 1610 and dielectrics 1612 and 1614. Stage 2 forms structure 1162 with a recessed portion 1620. Stage 3 forms structure 1163.

[0107] Figure 17 This is an interconnect view illustrating the fabrication of a monolithic WL according to an embodiment. Figure 11 The diagram shows the second part 1152 of the mask process flow 1100. The second part 1152 includes components respectively related to... Figure 11 The structures 1164, 1165, and 1166 corresponding to stages 4, 5, and 6 are shown in the figure.

[0108] Stage 4 forms structure 1164 with the cleaned substrate oxide 1710. Stage 5 forms structure 1165 by depositing gate oxide 1720 at the semiconductor and dielectric channels. This stage is similar to... Figure 3 The diagram shows the first part of stage 7 in the capping process. Stage 6 forms structure 1166 by depositing metal (e.g., Ti, W) into the hollow spaces in the array region and pad region to form conductive pathways 1730. This stage is similar to... Figure 3 The second part of stage 7 in the cover process is shown in the diagram. Conductive path 1730 includes... Figure 2 The array WL 232, interconnect WL 260, and pad WL 270 are shown in the diagram. Structure 1166 also includes... Figure 2 The first edge 235 and the second edge 245 are shown in the figure.

[0109] Figure 18 This is a flowchart illustrating process 1800 for manufacturing a monolithic WL structure for memory circuitry according to an embodiment. Process 1800 corresponds to... Figure 3 The cover embodiment shown in the figure and Figure 11 The mask embodiment shown is illustrated. For the sake of brevity, it is not described in detail. Figure 3 and Figure 11 The structure and Figure 18 All the correspondences between the processes in the document.

[0110] Process 1800 forms an array word line (WL) region with one or more array WL paths and a pad WL region with one or more pad WL paths in a three-dimensional (3D) structure (Process 1810). Next, Process 1800 fabricates one or more monolithic WL paths including one or more array WL paths, one or more pad WL paths, and one or more interconnect WL paths (Process 1820). Process 1820 implements... Figure 19 The cover process described in the text and Figure 20 The mask process described in the text.

[0111] Then, process 1800 deposits gate oxide in one or more pad WL channels, one or more interconnect WL channels, and one or more array WL channels (process 1830). Next, process 1800 simultaneously deposits at least one of a metal and titanium nitride (TiN) in one or more pad WL channels, one or more interconnect WL channels, and one or more array WL channels to form one or more monolithic WLs from one or more monolithic WL channels (process 1840). The metal can be at least one of tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), and rhodium (Rh), or any combination of these materials. Process 1800 then performs various cleaning tasks and then terminates. Process 1840 produces... Figure 5 Structure 327 in Figure 7 Structure 347 and Figure 9 Structure 367 (for the cover embodiment) and Figure 13 Structure 1126 in Figure 15 Structure 1146 and Figure 7 Structure 1166 (for mask embodiment).

[0112] Figure 19 This illustrates the preparation of the cover according to an embodiment. Figure 18 The flowchart of process 1820 for one or more monolithic WL paths is shown. Process 1820 represents... Figure 3 The portions of stages 1 to 7 are shown in three views (3D view 310, array view 330 and pad view 350).

[0113] Process 1820 creates dielectric recesses in the array WL region and the pad WL region (Process 1910). Process 1910 produces... Figure 4 Structure 321 in Figure 6 Structure 341 and Figure 8Structure 361 in the middle. Next, process 1820 forms a cap on top of the 3D structure (process 1920). Process 1920 produces Figure 4 Structure 322 in Figure 6 Structure 342 and Figure 8 Structure 362 in the diagram. Then, process 1820 etches the pad WL region (process 1930). Next, process 1820 strips the silicon in the pad WL region into one or more interconnect WL pathways in the interconnect region between the array WL region and the pad WL region (process 1940). Then, process 1820 removes the cap (process 1950). This is accomplished by ashing the cap using oxygen plasma. If amorphous carbon is used to form the cap, ashing the cap involves removing the amorphous carbon using a low-temperature process with an excitation gas or plasma. Process 1950 produces... Figure 5 Structure 325 in Figure 7 Structure 345 and Figure 9 The structure is 365. Next, process 1820 cleans the oxide in the WL region of the array (process 1960), and then terminates.

[0114] Figure 20 This illustrates the use of a mask to prepare according to an embodiment. Figure 18 The flowchart of process 1820 for one or more monolithic WL paths is shown. Process 1820 represents... Figure 11 The portions of phases 1 to 6 are shown in three views (array view 1110, pad view 1130, and interconnection view 1150).

[0115] Process 1820 forms a mask on top of the 3D structure (Process 2010). Process 2010 produces... Figure 12 Structure 1121 in Figure 14 Structure 1141 and Figure 16 Structure 1161 in the diagram. Next, process 1820 creates openings in the mask above the array WL regions on the array side and the pad WL regions on the pad side (process 2020). Then, process 1820 etches one or more array WL channels and one or more pad WL channels (process 2030). Next, process 1820 etches one or more array WL channels and one or more pad WL channels with different depths by adjusting the mask thickness on the pad side. Next, process 1820 creates dielectric recesses at the array regions and semiconductor recesses at the pad regions (process 2040). The dielectric at the interconnect regions is cleaned to connect one or more array WL channels to one or more pad WL channels (process 2050). Then process 1820 terminates.

[0116] While this specification may contain numerous specific details of implementation, these details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of specific features of particular embodiments. Specific features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination and even initially claimed in this way, one or more features from a claimed combination may be removed from the combination in some cases, and a claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0117] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential order, or to perform all of the shown operations, in order to achieve the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0118] Therefore, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing can be advantageous.

[0119] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied across a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but is defined by the appended claims.

Claims

1. A single-chip word line, comprising: A conductive element connects the array word line at the first edge of the array region to the pad word line at the second edge of the pad region. The conductive element is disposed in the interconnection region between the first edge and the second edge. as well as A first dielectric is disposed on the array word lines, conductive elements, and pad word lines, and the first dielectric has a dielectric surface extending from the interconnect region to the pad region. In this process, the conductive element and the first dielectric form a monolithic word line from the array word line and the pad word line through the second edge.

2. The single-chip word line according to claim 1, wherein the single-chip word line further comprises: The second dielectric is disposed on the first dielectric in the interconnect region.

3. The single-chip word line according to claim 2, wherein the single-chip word line further comprises: The third dielectric is disposed on the first dielectric in the pad region.

4. The single-chip word line according to claim 1, wherein, The dielectric surface is flat and has a thickness equal to or less than that of the gate oxide.

5. The single-chip word line according to claim 3, wherein, The first dielectric is different from at least one of the second and third dielectrics.

6. The single-chip word line according to claim 1, wherein, The second edge is the cell block edge.

7. The single-piece character line according to claim 1, wherein, The conductive element includes at least one of a metal and titanium nitride (TiN).

8. The single-chip word line according to claim 7, wherein, The metals include at least one of tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), and rhodium (Rh).

9. The single-chip word line according to any one of claims 1 to 8, wherein, The line spacing of the array letter is shorter than that of the pad letter.

10. The single-chip word line according to any one of claims 1 to 8, wherein, Array word lines and pad word lines are word lines in a three-dimensional memory circuit.

11. A method for manufacturing a single-chip word line, comprising: In a three-dimensional structure, an array word line region with array word line paths and a pad word line region with pad word line paths are formed; Fabricate a monolithic word line path including array word line paths, pad word line paths, and interconnect word line paths; Deposit gate oxide in pad word line paths, interconnect word line paths, and array word line paths; as well as At least one of a metal and titanium nitride (TiN) is deposited in the pad word line path, the interconnect word line path, and the array word line path to form a monolithic word line from the monolithic word line path.

12. The method according to claim 11, wherein, The steps for preparing a single-chip word line path include: Dielectric recesses are created in the array word line region and the pad word line region; A cover is formed on top of the three-dimensional structure; Etching of the padding area; and The silicon in the pad word line region is stripped into the interconnect word line path in the interconnect region between the array word line region and the pad word line region.

13. The method according to claim 12, wherein, The steps for preparing a single-chip word line path also include: Remove the cap; and Clean the oxides in the array word line region.

14. The method according to claim 11, wherein, The steps for preparing a single-chip word line path include: A mask is formed on top of the three-dimensional structure; An opening is made in the mask above the array word line area on the array side and the pad word line area on the pad side; Etch the array word line path and the pad word line path; This causes the dielectric in the array region and the semiconductor in the pad region to be recessed; and Clean the dielectric in the interconnect area to connect the array word line path to the pad word line path.

15. The method according to claim 14, wherein, The steps for etching the array word line paths and pad word line paths include: By adjusting the mask thickness on the pad side, array word line paths and pad word line paths with different depths are etched.

16. The method according to claim 12, wherein, The steps for forming the cap include: Amorphous carbon is used to form the cap.

17. The method according to claim 13, wherein, The steps to remove the cap include: Oxygen plasma is used to ashing the cover.

18. The method according to claim 11, wherein, The metal is at least one of tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), and rhodium (Rh).

19. The method according to claim 11, wherein, The step of depositing at least one of the metal and titanium nitride (TiN) includes: Simultaneously, at least one of the metal and titanium nitride (TiN) is deposited in the pad word line path, interconnect word line path, and array word line path.

20. A system including a single-chip word line, comprising: Memory circuitry, including: The array area has array word lines; The pad area has pad lines; and Interconnection structure, including: Conductive elements connect the array word lines at the first edge to the pad word lines at the second edge, and the conductive elements are disposed in the interconnection region between the first edge and the second edge; and A first dielectric is disposed on the array word lines, conductive elements, and pad word lines, and the first dielectric has a dielectric surface extending from the interconnect region to the pad region. In this process, the conductive element and the first dielectric form a monolithic word line from the array word line and the pad word line through the second edge.

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