Selective epitaxy method for SiGe:C based regions of high speed SiGe HBTs

Abstract

This invention discloses a method for selective epitaxy of the SiGe:C base region in high-speed silicon-germanium (HBT), comprising: providing a patterned substrate having a base region growth window; performing RCA cleaning on the patterned substrate; forming a low-pressure environment in the epitaxial chamber; and forming the SiGe:C base region in the base region growth window of the patterned substrate through selective epitaxy. In this invention, optimized pretreatment of the patterned substrate surface effectively suppresses the etching damage caused by highly reactive carbon atoms and their uncontrollable migration on the dielectric surface; thereby significantly widening the process window for selective SiGe:C epitaxy and improving process stability and repeatability; conducting the reaction under low pressure increases the mean free path of gas molecules and facilitates surface reaction control, strengthening the dependence of growth / etching on surface chemical properties and enhancing selectivity.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit chip manufacturing, and in particular relates to a SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBTs. Background Technology

[0002] The core of SiGe HBTs lies in introducing materials with narrower bandgap widths into the base region to achieve bandgap engineering, thereby significantly improving performance. To obtain high current gain and high-frequency characteristics, the SiGe base region requires a high concentration of boron (B) doping. However, subsequent high-temperature processing steps (such as emitter polysilicon annealing) can cause B atoms to diffuse outwards, sometimes even reaching the emitter, leading to a decrease in current gain. Alternatively, they can diffuse to the collector, widening the base region and causing a sharp drop in the cutoff frequency (fT) and maximum oscillation frequency (fmax). Introducing a small amount (10⁻⁶) of boron into the SiGe layer... 19 ~10 20 cm -3 Carbon atoms occupy substitution sites in the silicon lattice and combine with silicon vacancies, thus significantly suppressing the diffusion of boron atoms. The incorporation of C offers several benefits: maintaining a steep doping profile, relaxing thermal budget requirements, improving device uniformity and reliability, and compensating for lattice mismatch introduced by Ge. However, due to the extremely high chemical and surface migration activity of carbon (C), this can cause etching damage to SiO2 or SiN dielectrics and uncontrollable migration behavior on the dielectric surface. Both of these factors significantly reduce the process window for SiGe:C selective epitaxy, leading to decreased process reliability and consistency, and in severe cases, device failure. Summary of the Invention

[0003] To address the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBTs.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A method for selective epitaxy of SiGe:C base region in high-speed silicon-germanium (HBT) includes the following steps: S100. A patterned substrate is provided, the patterned substrate having a base region growth window; S300, RCA cleaning is performed on the patterned substrate; S500: A low-pressure environment is formed in the epitaxial chamber, and a SiGe:C base region is formed in the base region growth window of the patterned substrate through selective epitaxy.

[0005] Furthermore, the patterned substrate is fabricated using the following steps: S110. A silicon substrate is provided, and an oxide layer is deposited on the silicon substrate; S120, A dielectric layer is deposited on the oxide layer to form a dielectric layer; S130, the oxide layer and dielectric layer are etched sequentially to form a base region growth window exposed on the surface of the silicon substrate.

[0006] Furthermore, the oxide layer is composed of SiO2, and the dielectric layer is composed of SiO2 or SiN.

[0007] Furthermore, after obtaining the patterned substrate, the following steps are performed: S200, Planarize the surface of the patterned substrate.

[0008] Furthermore, the method for planarizing the surface of the patterned substrate is as follows: The SiO2 and / or SiN on the surface of a patterned substrate are etched using vapor-phase HF acid etching technology.

[0009] Furthermore, the RCA cleaning of the patterned substrate includes the following sub-steps: S310. The patterned substrate is cleaned sequentially using SPM, DHF, SC-1 solution and SC-2 solution. S320. The cleaned patterned substrate is dried using isopropanol vapor.

[0010] Furthermore, in step S500, during selective epitaxy, SiH2Cl2 is introduced into the epitaxial chamber as the main silicon source, GeH4 is introduced as the main germanium source, and CH3SiHCl2 is introduced as the carbon source and auxiliary silicon source.

[0011] Furthermore, in step S500, during selective epitaxy, H2 is introduced into the epitaxial chamber as the main carrier gas, and Cl2 is introduced as the etching gas.

[0012] Furthermore, in step S500, selective epitaxy is performed under a low-pressure environment of 5 to 10 torr.

[0013] Furthermore, in step S500, the typical reaction temperature in the epitaxial chamber during selective epitaxy is 600℃~725℃.

[0014] In this invention, by optimizing the pretreatment of the patterned substrate surface and adjusting the process gas, the etching damage of highly reactive carbon atoms to the SiO2 / SiN dielectric and their uncontrollable migration on the dielectric surface are effectively suppressed. This significantly broadens the process window for SiGe:C selective epitaxy, improving process stability and repeatability. Furthermore, carbon doping effectively suppresses boron diffusion in the base region, optimizing the device doping distribution and thus improving the frequency characteristics of the SiGe HBT. Ultimately, this method achieves a synergistic enhancement of epitaxial selectivity, device performance, and manufacturing reliability and consistency. Conducting the reaction under low pressure increases the mean free path of gas molecules, allowing etching gases such as Cl2 to diffuse more effectively to all corners of the patterned structure (e.g., trenches with high aspect ratios), uniformly performing the etching function. The low-pressure environment also facilitates surface reaction control, further strengthening the dependence of growth / etching on surface chemical properties, thereby enhancing selectivity. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of an embodiment of the SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT of the present invention.

[0016] Figure 2 This is a schematic diagram of the patterned substrate structure.

[0017] Figure 3 This is a schematic diagram of the structure after a germanium-silicon base region is formed in the base region growth window of a patterned substrate.

[0018] The diagrams in the instruction manual are labeled as follows: 1. Silicon substrate; 2. Oxide layer; 3. Dielectric layer; 4. Base region growth window; 5. SiGe:C base region. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0020] Please see Figure 1 , Figure 1 This is a flowchart of an embodiment of the selective epitaxy method for the SiGe:C base region of a high-speed silicon-germanium (HBT) according to the present invention. The selective epitaxy method for the SiGe:C base region of a high-speed silicon-germanium (HBT) in this embodiment includes the following steps: S100, please refer to Figure 2A patterned substrate is provided, the patterned substrate having a base region growth window 4. The patterned substrate in this step can be fabricated using the following steps: S110. A silicon substrate 1 is provided, and an oxide layer 2 is deposited on the silicon substrate 1. The oxide layer 2 is composed of SiO2, that is, the oxide layer 2 can be formed by depositing silicon oxide (SiO2).

[0021] S120. A dielectric layer 3 is deposited on the oxide layer 2. The dielectric layer 3 is generally composed of SiO2 or SiN. That is, the dielectric layer 3 can be formed by depositing silicon oxide (SiO2) or silicon nitride (SiN). In this embodiment, the dielectric layer 3 is preferably silicon nitride.

[0022] S130: The oxide layer 2 and the dielectric layer 3 are etched sequentially to form a base region growth window 4 exposed on the surface of the silicon substrate 1, thereby obtaining a patterned substrate. In this step, the region where the base region growth window 4 is located can be defined by photolithography, and then silicon oxide and silicon nitride can be etched by dry etching and wet etching processes to form the base region growth window 4. The specific process is existing technology and will not be described in detail here.

[0023] After obtaining the patterned substrate, the following steps can be performed: S200. Planarize the surface of the patterned substrate. The method for planarizing the surface of the patterned substrate can be as follows: The SiO2 and / or SiN on the surface of a patterned substrate are etched using vapor-phase HF acid etching technology, thereby planarizing the dielectric on the surface of the patterned substrate. Vapor-phase HF acid etching technology is beneficial for dielectric planarization and rounding of sharp corners. This method has advantages such as high selectivity, high uniformity, and no plasma damage.

[0024] The principle of vapor phase HF etching of SiO2 is as follows: SiO2(s) + 4HF(g) →SiF4(g) + 2H2O(g) The principle of vapor phase HF etching of SiN is as follows: Si3N4(s) + 16HF(g) →3SiF(g) + 4NH4F(s) Carbon precursors such as (SiH3CH3) decompose to produce energy-rich hydrocarbon radicals (e.g., -CH3). These highly reactive radicals steal oxygen atoms from SiO2, initiating a reduction reaction. This reaction is a vapor-phase etching process, which can damage the dielectric. The smooth SiO2 surface becomes rough due to corrosion, generating numerous dangling bonds and defect sites. These rough defects and exposed silicon become nucleation centers for subsequent Si and Ge atoms, completely destroying selectivity. After the patterned substrate is formed, using vapor-phase HF acid etching to etch the SiN or SiO2 surface can planarize the dielectric, preventing nucleation caused by surface roughness during SiGe:C growth and thus preventing the destruction of selectivity.

[0025] S300. Perform RCA cleaning on the patterned substrate. The purpose of RCA cleaning before epitaxy is to create a perfect silicon surface through the synergistic effect of the chemical solution, laying the foundation for subsequent high-quality single-crystal epitaxial growth. This step may include the following sub-steps: S310 involves sequentially cleaning the patterned substrate using SPM, DHF, SC-1 solution, and SC-2 solution. The SPM cleaning solution can be formulated as concentrated sulfuric acid (H2SO4) + hydrogen peroxide (H2O2), typically in a 3:1 or 4:1 volume ratio. SPM powerfully removes organic residues. This is the first step in the cleaning sequence, designed to utilize the strong oxidizing properties and high heat of reaction of SPM to thoroughly decompose and remove most of the photoresist, polymers, and other organic contaminants remaining after the patterning process. It provides a roughly cleaned substrate for subsequent steps.

[0026] The formulation of DHF (dilute hydrofluoric acid) is: hydrofluoric acid (HF) + deionized water (H2O), with a concentration typically between 0.5% and 5%. The purpose of DHF cleaning is to strip away the natural oxide layer and passivate the surface. After SPM (Surface Purification Processing), a chemical oxide layer forms on the silicon surface. DHF can quickly and selectively remove this chemical oxide layer, while hydrogen termination on the silicon surface makes it inert for a short period, preventing immediate re-oxidation. This step is crucial for obtaining a clean, oxide-free starting surface for subsequent epitaxial growth.

[0027] SC-1 and SC-2 are two standard steps in RCA cleaning. SC-1 (Standard Clean-1, i.e., RCA-1) is formulated with ammonia (NH4OH) + hydrogen peroxide (H2O2) + deionized water (H2O), typically in a volume ratio of 1:1:5 or 1:2:7. SC-1 is primarily used to remove particulate matter and trace organic matter. It strips away organic residues through oxidation and complexation, and detaches particles through continuous oxidation and slight etching of the silicon surface. After the natural oxide layer is removed by DHF, SC-1 uses its weak, isotropic silicon etching action (rolling wood effect) to detach particles adhering to the surface, while further removing any remaining trace organic contaminants.

[0028] The formulation of SC-2 (Standard Clean-2, or RCA-2) is: hydrochloric acid (HCl) + hydrogen peroxide (H2O2) + deionized water (H2O), typically in a volume ratio of 1:1:6. SC-2 is primarily used to remove metal ion contamination. This is the final step, designed to complex and dissolve any metal ions (such as Fe, Cu, Zn, Ni, etc.) that may have been introduced in previous steps, ensuring the surface reaches a state of extremely low metal contamination before entering the epitaxial reaction chamber. This is crucial for the electrical properties of high-performance thin films like SiGe:C. Hydrochloric acid can form soluble chloride complexes with many metal ions, while hydrogen peroxide keeps the metals in an easily removable ionic state and prevents hydrochloric acid from corroding the silicon.

[0029] S320. The cleaned patterned substrate is dried using IPA (isopropyl alcohol) vapor to avoid water droplet residue causing contamination or defects. The surface tension gradient generated by the IPA vapor pulls away the water, achieving contactless and particulate-free drying.

[0030] S500: A low-pressure environment is formed in the epitaxial chamber, and a SiGe:C base region 5 is formed in the base region growth window 4 of the patterned substrate by selective epitaxy. In this embodiment, selective epitaxy is preferably performed in a low-pressure environment of 5 to 10 torr. The typical reaction temperature in the epitaxial chamber during selective epitaxy is preferably 600°C to 725°C.

[0031] In this embodiment, during selective epitaxy, H2 is introduced into the epitaxial chamber as the main carrier gas, SiH2Cl2 as the main silicon source, GeH4 as the main germanium source, CH3SiHCl2 as the carbon source and auxiliary silicon source, and Cl2 as the etching gas. CH3SiHCl2 is chosen as the C source because chlorine (Cl) atoms can effectively etch nuclei onto the dielectric (SiO2 / SiN) during growth. Compared to other chlorine-containing precursors, it has higher activity, enabling high-quality epitaxy at relatively lower temperatures while retaining the high doping efficiency of methylsilane carbon (C). Cl2 is used as the selective etching gas because it has higher selective etching capability, resulting in a higher selectivity ratio during SiGe:C epitaxy, inhibiting SiGe:C nucleation on the dielectric surface, and improving the reliability of selective epitaxy.

[0032] Please refer to Figure 3 , Figure 3 The figure shows a schematic diagram of the structure after selective epitaxy of SiGe:C. As shown, SiGe:C grows only within the Si window and has good contact between the inner and outer base regions. No nucleation occurs on the SiO2 / SiN medium.

[0033] In the epitaxial chamber, the typical reaction temperature for SiGe:C is preferably 600℃~725℃. During SiGe:C growth, the precursors H2, SiH2Cl2, GeH4, CH3SiHCl2, and Cl2 introduced into the epitaxial chamber decompose in the gas phase. The active substances produced by decomposition (such as Si atoms, Ge atoms, CH3 radicals, etc.) are adsorbed on the substrate surface, find suitable lattice positions through surface migration, and desorb from the substrate (Si) surface, incorporating into the grown thin film to form a covalent SiGe:C alloy. In this process, since the probability of nucleation on the dielectric surface is much lower than that on the Si surface, even if a small number of nuclei form on the dielectric surface, they will disappear due to the etching effect of HCl formed by the decomposition of Cl2, thus achieving selective epitaxy.

[0034] To achieve good SiGe:C selective epitaxy, the low-pressure environment for the epitaxial growth reaction is preferably 5 to 10 torr. At low pressure, the mean free path of gas molecules increases, and the diffusion coefficient increases. This allows reactants to diffuse more rapidly from the main gas flow to the substrate surface. Under low pressure, the surface reaction rate within the Si growth window can compete with and become dominant over the mass transport rate. In single-crystal Si windows, the presence of a dangling bond and suitable lattice positions allows for efficient precursor decomposition and epitaxial growth. The surface reaction rate is fast in single-crystal Si windows. In dielectrics (SiO2 / SiN), the lack of active sites results in extremely slow surface reactions, thus achieving good selectivity.

[0035] The method proposed in this embodiment has the following beneficial effects: (1) Significantly improved process window and reliability of selective epitaxy. By optimizing the pretreatment of the patterned substrate surface and adjusting the process gas, the etching damage of highly active carbon atoms to SiO2 / SiN dielectric and their uncontrollable migration on the dielectric surface were effectively suppressed. This fundamentally solved the problem of narrow process window and poor consistency caused by the negative behavior of carbon, and greatly improved the stability and repeatability of SiGe:C selective epitaxy process.

[0036] (2) Ensured and optimized device performance: Based on achieving high-selectivity epitaxy, the inherent advantages of carbon doping were fully utilized, and the diffusion of boron (B) in the base region was effectively suppressed. This enabled the fabricated device to obtain a steeper doping distribution, thereby significantly improving the frequency characteristics of SiGe HBT.

[0037] (3) Improved device reliability and consistency. A wider and more stable process window directly translates into controllability of the manufacturing process, reducing the risk of device performance dispersion and failure due to process fluctuations. This ensures that the final SiGe HBT devices have higher reliability and batch-to-batch consistency, meeting the stringent requirements of high-speed applications.

[0038] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for selective epitaxy of the SiGe:C base region in high-speed silicon-germanium (HBT), characterized in that, Includes the following steps: S100. A patterned substrate is provided, the patterned substrate having a base region growth window; S300, RCA cleaning is performed on the patterned substrate; S500: A low-pressure environment is formed in the epitaxial chamber, and a SiGe:C base region is formed in the base region growth window of the patterned substrate through selective epitaxy.

2. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 1, characterized in that, The patterned substrate is prepared using the following steps: S110. A silicon substrate is provided, and an oxide layer is deposited on the silicon substrate; S120, A dielectric layer is deposited on the oxide layer to form a dielectric layer; S130, the oxide layer and dielectric layer are etched sequentially to form a base region growth window exposed on the surface of the silicon substrate.

3. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 2, characterized in that: The oxide layer is composed of SiO2, and the dielectric layer is composed of SiO2 or SiN.

4. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 3, characterized in that, After obtaining the patterned substrate, the following steps are performed: S200, Planarize the surface of the patterned substrate.

5. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 4, characterized in that, The method for planarizing the surface of a patterned substrate is as follows: The SiO2 and / or SiN on the surface of a patterned substrate are etched using vapor phase HF acid etching technology.

6. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 1, characterized in that, RCA cleaning of patterned substrates includes the following sub-steps: S310. The patterned substrate is cleaned sequentially using SPM, DHF, SC-1 solution and SC-2 solution. S320. The cleaned patterned substrate is dried using isopropanol vapor.

7. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBTs as described in any one of claims 1 to 6, characterized in that: In step S500, during selective epitaxy, SiH2Cl2 is introduced into the epitaxial chamber as the main silicon source, GeH4 is introduced as the main germanium source, and CH3SiHCl2 is introduced as the carbon source and auxiliary silicon source.

8. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 7, characterized in that: In step S500, during selective epitaxy, H2 is introduced into the epitaxy chamber as the main carrier gas, and Cl2 is introduced as the etching gas.

9. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 8, characterized in that: In step S500, selective epitaxy is performed under a low-pressure environment of 5 to 10 torr.

10. The SiGe:C base region selective epitaxy method for high-speed silicon-germanium HBT as described in claim 9, characterized in that: In step S500, the typical reaction temperature in the epitaxial chamber during selective epitaxy is 600℃~725℃.

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