Preparation and application of ferroelectric-antiferroelectric coexisting multi-state memory

Abstract

The invention relates to the technical field of microelectronic devices, in particular to preparation and application of a ferroelectric-antiferroelectric coexisting multi-state memory. The invention provides a ferroelectric-anti-ferroelectric coexisting multi-state memory. The ferroelectric-anti-ferroelectric coexisting multi-state memory comprises a substrate layer; the bottom electrode layer is arranged on the substrate layer; the functional layer is arranged on the surface, away from the substrate layer, of the bottom electrode layer, and the functional layer is a film with a ferroelectric phase and an anti-ferroelectric phase coexisting; and the top electrode layer is arranged on the surface, deviating from the bottom electrode layer, of the functional layer. The functional layer of the multi-state memory is a film with coexistence of a ferroelectric phase and an anti-ferroelectric phase, and the coexistence microcosmic pattern enables the material to have multiple ferroelectric hysteresis loops and a multi-order polarization switch macroscopically, so that a brand new material platform and a device scheme are provided for realizing high-density and high-reliability multi-bit nonvolatile memory.

Description

Technical Field

[0001] This application belongs to the field of microelectronic device technology, and in particular relates to the fabrication and application of a multi-state memory with ferroelectric and antiferroelectric coexistence. Background Technology

[0002] With the rapid development of information technologies such as artificial intelligence, the total amount of global data is exploding, placing unprecedented demands on the storage density, read / write speed, power consumption, and reliability of storage devices. Traditional non-volatile memories, such as flash memory, are based on the principle of charge storage, with each cell typically storing only 1 bit of information. Limited by physical miniaturization limits and manufacturing costs, simply reducing device size to increase storage density is becoming increasingly difficult. To overcome this bottleneck, polymorphic memory technology has emerged. Its core lies in enabling a single storage cell to stably store multiple discrete logic states, thereby multiplying storage density without significantly increasing chip area, becoming an important development direction for next-generation high-density storage technology.

[0003] Among numerous emerging memory technologies, ferroelectric random access memory (FeRAM) has attracted considerable attention due to its non-volatility, high-speed read / write, low power consumption, and excellent fatigue resistance. Traditional FeRAM achieves binary storage based on the bistable polarization properties of ferroelectric materials. To achieve multi-state storage, researchers have explored various technical approaches, such as generating intermediate polarization states by precisely controlling the flipping of some ferroelectric domains, or introducing different coercive fields using thickness or composition gradients in ferroelectric thin films. However, these methods generally suffer from poor intermediate-state stability, narrow operating voltage windows, and uneven state distribution. These shortcomings severely restrict the practical application and large-scale production of multi-state memories based on traditional ferroelectric materials.

[0004] Antiferroelectric materials, as important dielectrics, have been extensively studied in the field of high-energy-density capacitors due to their ability to undergo antiferroelectric-ferroelectric phase transitions under an electric field, accompanied by significant nonlinear polarization responses. Typical materials, such as lead zirconate (PbZrO3), can exhibit double hysteresis loops under specific conditions. Recent studies have found that by precisely controlling the deposition process and structural parameters of PbZrO3 thin films, intrinsic coexistence of ferroelectric and antiferroelectric phases can be achieved within the film. This microscopic phase coexistence structure can induce richer macroscopic electrical properties than a single phase, such as multipolarization and current-switching characteristics. However, current research on PbZrO3-based materials mainly focuses on optimizing their energy storage performance through doping and interface engineering. Systematic research and reports on how to utilize the multi-order polarization switching characteristics unique to ferroelectric-antiferroelectric coexistence systems, derived from phase transition dynamics, to develop novel non-volatile multi-state memories are still lacking.

[0005] Therefore, there is an urgent need to develop a completely new memory solution that utilizes the intrinsic and stable polymorphic properties of materials to provide a new technical path for achieving high-density and high-reliability information storage. Summary of the Invention

[0006] The purpose of this application is to provide a fabrication and application of a multi-state memory with ferroelectric and antiferroelectric coexistence, aiming to solve the problems of unstable intermediate states, uneven distribution, and narrow operating window in traditional multi-state memories.

[0007] To achieve the above-mentioned objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides a multi-state memory where ferroelectricity and antiferroelectricity coexist, comprising: Substrate layer; The bottom electrode layer is disposed on the substrate layer; The functional layer is disposed on the surface of the bottom electrode layer away from the substrate layer, and the functional layer is a thin film with ferroelectric and antiferroelectric phases coexisting. The top electrode layer is disposed on the surface of the functional layer opposite to the bottom electrode layer.

[0008] In some embodiments, the substrate layer includes any one of SrTiO3, silicon wafer, and flexible mica.

[0009] In some embodiments, the bottom electrode layer includes SrRuO3, La 0.7 Sr 0.3 Any one of MnO3, LaCoO3, and LaNiO3.

[0010] In some embodiments, the functional layer includes PbZrO3, PbHfO3, and Hf 0.5 Zr 0.5 Any one of O2, Hf0.8Zr0.2O2, or NaNbO3.

[0011] In some embodiments, the top electrode comprises any one of Au, Pt, TiN, and TaN.

[0012] In some embodiments, the substrate is SrTiO3.

[0013] In some embodiments, the bottom electrode layer is SrRuO3.

[0014] In some embodiments, the functional layer is PbZrO3.

[0015] In some embodiments, the top electrode is Au.

[0016] In some embodiments, epitaxial growth occurs between the substrate layer and the bottom electrode layer.

[0017] In some embodiments, the thickness of the functional layer is 100 nm-300 nm.

[0018] In some embodiments, the thickness of the bottom electrode layer is 30 nm-40 nm.

[0019] In some embodiments, the particle size of the top electrode is 50-200 μm.

[0020] Secondly, the method for fabricating a polymorphic memory provided in this application includes the following steps: Provide a substrate layer; A bottom electrode layer is prepared on the surface of a substrate layer using an epitaxial deposition process; A functional layer is deposited on the surface of the bottom electrode layer opposite to the substrate layer; A top electrode layer is prepared by depositing a top electrode on the surface of the functional layer that is opposite to the bottom electrode layer.

[0021] Thirdly, this application provides an application of polymorphic memory as a storage unit in an integrated circuit chip.

[0022] The first aspect of this application provides a multi-state memory with coexisting ferroelectric and antiferroelectric phases, comprising a stacked structure of "substrate layer - bottom electrode layer - functional layer - top electrode layer". The functional layer is a thin film with both ferroelectric and antiferroelectric phases coexisting. This coexisting microstructure causes the material to exhibit a unique electrical response on a macroscopic scale: its polarization-electric field loop exhibits multiple transitions and multiple hysteresis loops. Under the control of an applied electric field, the ferroelectric and antiferroelectric regions can be selectively and stepwise switched, thereby realizing multi-stage polarization switching. This provides a novel material platform and device solution for achieving high-density, high-reliability multi-bit non-volatile memory.

[0023] The second aspect of this application provides a method for fabricating a multi-state memory. This method involves fabricating a bottom electrode layer through an epitaxial deposition process and depositing a functional layer on the bottom electrode layer to achieve the same "ferroelectric-antiferroelectric coexistence" functional layer. The fabrication process determines the deposition process conditions according to the specific materials. This fabrication method is simple and conducive to industrial application.

[0024] The third aspect of this application describes the application of polymorphic memory as a storage unit in integrated circuit chips. A single polymorphic memory unit with a capacity of ~2.58 bits is used as a basic unit and integrated into the integrated circuit chip in an array. Within the chip, these units are addressed via word lines / bit lines and controlled by peripheral read / write circuitry, collectively forming a high-density non-volatile memory module. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a multi-state memory structure with ferroelectric-antiferroelectric coexistence in an embodiment of this application; Figure 2 It is the polarization-voltage (PV) hysteresis of the PbZrO3 thin film with ferroelectric-antiferroelectric coexistence in Example 1; Figure 3 These are the accompanying current-voltage (IV) curves of the PbZrO3 thin film with ferroelectric-antiferroelectric coexistence in Example 1; Figure 4 This describes the distribution of six polarization states in a multi-state memory where ferroelectric and antiferroelectric coexistence is shown in the embodiments of this application. Figure 5 These are the polarization-voltage (PV) hysteresis and accompanying current-voltage (IV) curves of the PbZrO3 thin film in Example 2; Figure 6 These are the polarization-voltage (PV) hysteresis and accompanying current-voltage (IV) curves of the PbZrO3 thin film in Example 3. Detailed Implementation

[0027] To make the technical problems, technical solutions, and beneficial effects of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can both mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple.

[0030] It should be understood that in the various embodiments of this application, the order of the above processes does not imply the order of execution. Some or all steps may be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0031] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms "a" and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0032] The weights of the relevant components mentioned in the embodiments of this application can refer not only to the specific content of each component, but also to the proportional relationship between the weights of the components. Therefore, any scaling up or down of the content of the relevant components according to the embodiments of this application is within the scope disclosed in the embodiments of this application. Specifically, the mass in the embodiments of this application can be a well-known unit of mass in the chemical industry, such as µg, mg, g, or kg.

[0033] The terms "first" and "second" are used for descriptive purposes only, to distinguish objects, such as substances, from one another, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. For example, without departing from the scope of the embodiments of this application, "first XX" may also be referred to as "second XX," and similarly, "second XX" may also be referred to as "first XX." Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature.

[0034] Terminology Explanation: Ferroelectric phase (FE): refers to adjacent dipoles arranged in the same direction, with macroscopic net polarization, and the polarization-electric field (PE) relationship is a double loop.

[0035] Antiferroelectric phase (AFE): refers to adjacent dipoles arranged in opposite directions, with a macroscopic net polarization of zero, and the PE relationship is a double hysteresis loop (i.e., two adjacent but opposite ferroelectric loops superimposed).

[0036] The first aspect of this application provides a multi-state memory where ferroelectricity and antiferroelectricity coexist, such as... Figure 1 As shown, it includes: Substrate layer; The bottom electrode layer is disposed on the substrate layer; The functional layer is disposed on the surface of the bottom electrode layer away from the substrate layer, and the functional layer is a thin film with ferroelectric and antiferroelectric phases coexisting. The top electrode layer is disposed on the surface of the functional layer opposite to the bottom electrode layer.

[0037] The first aspect of this application provides a multi-state memory with ferroelectric and antiferroelectric coexistence, comprising a stacked structure of "substrate layer - bottom electrode layer - functional layer - top electrode layer," wherein the functional layer is a thin film with both ferroelectric and antiferroelectric phases coexisting. This coexisting microstructure causes the material to exhibit a unique electrical response on a macroscopic scale: its polarization-electric field loop exhibits multiple transitions and multiple hysteresis loops. Under the control of an applied electric field, the ferroelectric and antiferroelectric regions can be selectively and stepwise switched, thereby realizing multi-stage polarization switching, providing a novel material platform and device solution for achieving high-density, high-reliability multi-bit non-volatile memory.

[0038] A polymorphic memory includes a substrate layer. The substrate layer provides mechanical support for the entire multilayer thin-film device, ensuring the structural integrity of the device.

[0039] In some embodiments, the substrate layer includes any one of SrTiO3, silicon wafer, and flexible mica. In some specific embodiments, the substrate layer is selected from SrTiO3; a single-crystal oxide substrate is chosen because its highly ordered atomic arrangement provides a template for subsequent epitaxial growth of high-quality, oriented bottom electrode layers and functional layers.

[0040] Furthermore, the polymorphic memory includes a bottom electrode layer disposed on the substrate layer. The bottom electrode layer is typically located between the substrate layer and the functional layer, serving as a bridging layer; it also acts as one of the electrodes for applying an external electric field, responsible for transmitting voltage signals to the functional layer. In some embodiments, the bottom electrode layer includes SrRuO3, La... 0.7 Sr 0.3 The substrate is any one of MnO3, LaCoO3, and LaNiO3. In some specific embodiments, the substrate layer is SrTiO3. SrTiO3 is a conductive oxide, which can achieve high-quality epitaxial growth with the oxide substrate and form good crystallographic matching and chemical compatibility with the functional layer.

[0041] In some embodiments, the thickness of the bottom electrode layer is 30 nm-40 nm. If the bottom electrode layer is too thin, it will result in excessive leakage current and weaken conductivity; if the bottom electrode layer is too thick, it will affect the stress between the functional layer and the substrate layer. In some specific embodiments, the thickness of the bottom electrode layer includes, but is not limited to, typical but not limiting values ​​such as 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, and 40 nm.

[0042] In some embodiments, epitaxial growth occurs between the substrate layer and the bottom electrode layer. Epitaxial growth means that the atomic arrangement of the bottom electrode layer strictly follows the lattice period of the single-crystal substrate layer by layer, forming a sharp, abruptly chemically abrupt heterogeneous interface at the atomic level. This helps to eliminate random grain boundaries and rough interfaces caused by amorphous or polycrystalline structures, thus forming a perfect interface; it ensures that the applied electric field can act uniformly and without distortion perpendicularly on the upper functional layer, avoiding local electric field concentration caused by interface unevenness, thereby guaranteeing the uniformity and reliability of multi-state switching behavior.

[0043] Furthermore, the polymorphic memory also includes a functional layer disposed on the surface of the bottom electrode layer opposite to the substrate layer. The functional layer is a thin film with both ferroelectric and antiferroelectric phases coexisting. The functional layer is the core dielectric layer for information storage and processing, and is the physical carrier of all functions. The functional layer provided in this application is a thin film with both ferroelectric and antiferroelectric phases coexisting; this is beneficial for exhibiting multiple hysteresis loops and multi-order polarization switching characteristics.

[0044] In some embodiments, the functional layer includes PbZrO3, PbHfO3, and Hf 0.5 Zr 0.5 Any one of O2, Hf0.8Zr0.2O2, and NaNbO3. In some specific embodiments, the functional layer is PbZrO3.

[0045] In the polymorphic memory provided in this application embodiment, the SrTiO3 substrate and the PbZrO3 functional layer interact critically through their epitaxial growth relationship, jointly achieving the stable coexistence of the ferroelectric (FE) and antiferroelectric (AFE) phases at the nanoscale. Specifically, the SrTiO3 substrate acts as a cubic perovskite single-crystal template, forcing the epitaxially grown PbZrO3 functional layer to undergo in-plane biaxial compressive strain on its surface. Thermodynamically, this suppresses the stability of the intrinsic orthorhombic antiferroelectric phase of the PbZrO3 functional layer, while significantly reducing the energy of the tetragonal or rhombohedral metastable ferroelectric phase, thus creating conditions for the emergence of ferroelectric order. However, the strain distribution in the three-dimensional space of the thin film is not uniform: in the high-strain region near the interface of the SrTiO3 substrate, the PbZrO3 functional layer is locked in the strain-stable ferroelectric phase; as the film grows, the strain gradually relaxes through dislocation formation or domain structure evolution, while in regions far from the interface, the PbZrO3 functional layer tends to revert to its intrinsic antiferroelectric phase. This leads to the spontaneous formation of a nanocomposite structure within the thin film, where ferroelectric and antiferroelectric phases coexist and intertwine, thereby achieving characteristics such as multiple hysteresis loops and multi-stage polarization switching.

[0046] In some embodiments, the thickness of the functional layer is 100 nm to 300 nm. If the functional layer is too thin, it will lead to excessive leakage current and weaken the antiferroic electrode; if the functional layer is too thick, it will hinder the miniaturization and integration of the device. In some specific embodiments, the thickness of the functional layer includes, but is not limited to, typical but non-limiting values ​​such as 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, and 300 nm.

[0047] The polymorphic memory also includes a top electrode layer disposed on the surface of the functional layer opposite to the bottom electrode layer. The top electrode serves as the other pole for circuit connections, applying an electric field, and encapsulating the functional layer. Together with the bottom electrode layer, it forms two parallel plates for applying the electric field, allowing the vertical electric field to penetrate uniformly throughout the entire functional layer, driving polarization changes or phase transitions. Simultaneously, it isolates the functional layer from the external environment to a certain extent, preventing contamination or degradation, and serves as a bonding pad for external interconnect metal lines. In some embodiments, the top electrode includes any one of Au, Pt, TiN, and TaN. In some specific embodiments, the top electrode is Au.

[0048] In some embodiments, the particle size of the top electrode is 50-200 μm. If the particle size is too small, it will be difficult to connect the electrode and the electrical properties cannot be tested; if the particle size is too large, it will result in excessive leakage current.

[0049] The method for fabricating a polymorphic memory provided in the second aspect of this application includes the following steps: S01. Provide a substrate layer; S02. A bottom electrode layer is prepared on the surface of the substrate layer by epitaxial deposition; S03. Deposit a functional layer on the surface of the bottom electrode layer opposite to the substrate layer; S04. Deposit a top electrode on the surface of the functional layer opposite to the bottom electrode layer to prepare the top electrode layer.

[0050] The second aspect of this application provides a method for fabricating a multi-state memory. This method involves fabricating a bottom electrode layer through an epitaxial deposition process and depositing a functional layer on the bottom electrode layer to achieve the same "ferroelectric-antiferroelectric coexistence" functional layer. The fabrication process determines the deposition process conditions according to the specific materials. This fabrication method is simple and conducive to industrial application.

[0051] In step S01, a substrate layer is provided. The substrate layer is a (111) oriented substrate layer.

[0052] In step S02, a bottom electrode layer is prepared on the surface of the substrate layer by an epitaxial deposition process.

[0053] In some embodiments, a pulsed laser deposition method is employed.

[0054] In some embodiments, the deposition temperature of the bottom electrode layer is 670–690 °C, the oxygen partial pressure is 80–120 mTorr, the laser energy is 340–360 mJ, the pulsed laser frequency is 8–10 Hz, the deposition rate is 10–20 °C / min, and the laser focal length is [missing information]. 10~-20 mm, deposition rate 2~5 nm / min.

[0055] In step S03, a functional layer is deposited on the surface of the bottom electrode layer away from the substrate layer.

[0056] In some embodiments, a pulsed laser deposition method is employed.

[0057] In some embodiments, the deposition temperature of the functional layer is 580~620 °C, the oxygen partial pressure is 80~120 mTorr, the laser energy is 340~360 mJ, the pulsed laser frequency is 8~10 Hz, the deposition temperature rate is 10~20 °C / min, the laser focal length is 5~15 mm, and the deposition rate is 2~5 nm / min.

[0058] By controlling the deposition parameters of the bottom electrode layer and the functional layer, the prepared film not only has a good epitaxial structure, but also exhibits a hysteresis loop with coexistence of ferroelectric and antiferroelectric properties.

[0059] In step S04, a top electrode is deposited on the surface of the functional layer opposite to the bottom electrode layer to prepare the top electrode layer.

[0060] Furthermore, it also includes: performing a cooling post-treatment on the obtained ferroelectric-antiferroelectric coexisting thin film, keeping the oxygen partial pressure constant, and slowly cooling the ferroelectric-antiferroelectric coexisting PbZrO3 thin film to room temperature at a cooling rate of 10~20 ℃ / min.

[0061] By controlling the cooling rate under the original oxygen partial pressure atmosphere, the internal defects of the prepared material can be reduced, and the density and crystallinity can be improved, which is beneficial to improving performance.

[0062] The third aspect of this application provides an application of polymorphic memory as a storage unit in an integrated circuit chip.

[0063] The third aspect of this application describes the application of polymorphic memory as a storage unit in an integrated circuit chip. A single polymorphic memory unit with a capacity of ~2.58 bits is used as a basic unit and integrated into the integrated circuit chip in an array. Within the chip, these units are addressed via word lines / bit lines and controlled by peripheral read / write circuitry, collectively forming a high-density non-volatile memory module.

[0064] The following description is based on specific embodiments.

[0065] Example 1 A multi-state memory with ferroelectric and antiferroelectric coexistence includes: a substrate layer, a bottom electrode SrRuO3 layer, a PbZrO3 thin film layer, and a top electrode layer.

[0066] The fabrication method of the aforementioned ferroelectric-antiferroelectric coexisting multi-state memory includes the following steps: (1) SrTiO3 (111) was selected as the substrate layer.

[0067] (2) Using a pulsed laser deposition system, a SrRuO3 layer was deposited on a SrTiO3 substrate as a bottom electrode layer, with a thickness of 36 nm; the deposition temperature was 680 ℃, the oxygen partial pressure was 100 mTorr, the laser energy was 350 mJ, the pulsed laser frequency was 10 Hz, the deposition rate was 15 ℃ / min, and the laser focal length was [missing information]. 15 mm, deposition rate 2.5 nm / min.

[0068] (3) Using a pulsed laser deposition system, a PbZrO3 thin film was deposited on the SrRuO3 bottom electrode layer. The thickness of the deposited PZO thin film was 320 nm. The deposition temperature was 500 ℃, the oxygen partial pressure was 100 mTorr, the laser energy was 350 mJ, the pulsed laser frequency was 10 Hz, the deposition rate was 15 ℃ / min, the laser focal length was 10 mm, and the deposition rate was 5 nm / min.

[0069] (4) The prepared PbZrO3 thin film material was cooled and treated to room temperature at a cooling rate of 10 °C / min while keeping the oxygen partial pressure constant.

[0070] (5) Au point electrodes were deposited on PbZrO3 thin films using a small ion sputtering instrument.

[0071] like Figure 2 The figure shows the polarization-voltage (PV) curves of a PbZrO3 thin film with ferroelectric and antiferroelectric coexistence. It can be seen from the figure that in addition to the double hysteresis loop of the antiferroelectric, there is also a hysteresis loop near the zero electric field, and the whole film presents a unique triple hysteresis loop.

[0072] like Figure 3 The accompanying current-voltage (IV) curves of a ferroelectric-antiferroelectric coexisting PbZrO3 thin film are shown. Two current peaks appear at approximately ±50.3 kV / cm, superimposed on the four typical current peaks associated with the antiferroelectric-to-ferroelectric and ferroelectric-to-antiferroelectric phase transitions in typical antiferroelectric materials. This phenomenon confirms the triple hysteresis observed in the hysteresis loop, indicating that six polarization reversals occurred within the thin film under the applied electric field.

[0073] like Figure 4 The figure shows the distribution of six polarization states in a multi-state memory where ferroelectric and antiferroelectric coexistence occurs. The results show that all six polarization states exhibit a normal distribution with a standard deviation of less than 0.5 μC / cm. 2 This narrow distribution demonstrates excellent repeatability between devices, meeting the key requirements for polymorphic memory applications.

[0074] Example 2 A multi-state memory with ferroelectric and antiferroelectric coexistence includes: a substrate layer, a bottom electrode SrRuO3 layer, a PbZrO3 thin film layer, and a top electrode layer.

[0075] Antiferroelectric thin films were prepared using the method of Example 1. Antiferroelectric PbZrO3 thin films with the same thickness of 320 nm were deposited on the SrRuO3 bottom electrode layer, except that the deposition temperature was 550 °C.

[0076] The electrical properties of the antiferroelectric thin film prepared in this embodiment were tested, and the results are shown in the figure. Figure 5 . Figure 5 The polarization-voltage (PV) hysteresis and associated current-voltage (IV) curves of the PbZrO3 thin film are shown, and the results show the characteristics of double hysteresis lines and corresponding four current peaks.

[0077] Example 3 A multi-state memory with ferroelectric and antiferroelectric coexistence includes: a substrate layer, a bottom electrode SrRuO3 layer, a PbZrO3 thin film layer, and a top electrode layer.

[0078] Antiferroelectric thin films were prepared using the method in Example 1. Antiferroelectric PbZrO3 thin films with the same thickness of 320 nm were deposited on the SrRuO3 bottom electrode layer, except that the deposition temperature was 600 °C.

[0079] The electrical properties of the antiferroelectric thin film prepared in this embodiment were tested, and the results are shown in the figure. Figure 6 . Figure 6 The polarization-voltage (PV) hysteresis and associated current-voltage (IV) curves of the PbZrO3 thin film are shown, and the results show the characteristics of double hysteresis lines and corresponding four current peaks.

[0080] Comparing Examples 1, 2, and 3, the following conclusions can be drawn: By optimizing the thin film preparation process and structural parameters, a PbZrO3 thin film exhibiting ferroelectric-antiferroelectric coexistence can be obtained. This film displays triple hysteresis characteristics, and its six-fold polarization states possess stable repeatability and reversible tunability. Crucially, this ferroelectric-antiferroelectric coexistence multi-state memory achieves 2.58-bit operation per cell with minimal inter-device variability, and its six-fold polarization states exhibit excellent data retention and cycle durability. These findings collectively establish a structural design paradigm for realizing ferroelectric-antiferroelectric coexistence materials with intrinsically multiple polarization states, and pave the way for the development of next-generation high-density non-volatile multi-state memory devices.

[0081] In summary, the embodiments of this application have the following beneficial technical effects: 1. Stable and controllable intrinsic ferroelectric-antiferroelectric coexistence was achieved in PbZrO3 thin films.

[0082] In existing technologies, inducing ferroelectric phases in antiferroelectric PbZrO3 often relies on external strong strain or complex heterostructures, making it difficult to control and resulting in poor stability. This invention, by adjusting process parameters such as deposition temperature, obtains an IV characteristic curve with a unique triple hysteresis loop and six peaks, providing a solid material foundation for multi-state memory.

[0083] 2. Stable polymorphic (6 states) and multi-bit (approximately 2.58-bit) storage has been achieved.

[0084] Based on the unique electrical response described above, the memory provided by this invention has six non-volatile polarization states. The existence and distribution of the six polarization states were verified by designing specific write / read pulse sequences (with different amplitudes and pulse widths). Therefore, a single memory cell can store six states, with an information capacity of log2(6) ≈ 2.58 bits, which theoretically increases the storage density by 2.58 times compared to traditional binary ferroelectric memories.

[0085] 3. The six polarization states exhibit an excellent normal distribution across devices, indicating stable and repeatable performance among devices.

[0086] Since the polymorphic memory characteristics originate from the intrinsic microscopic dipole arrangement of the PbZrO3 thin film, rather than a random domain structure, our statistical analysis of one hundred devices revealed that the distribution of the six polarization states across the devices all conforms to a normal distribution, with a relative standard deviation of less than 0.5. This narrow distribution confirms the good consistency among the devices, meeting the key requirements for polymorphic memory applications.

[0087] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multi-state memory with ferroelectric and antiferroelectric coexistence, characterized in that, include: Substrate layer; A bottom electrode layer is disposed on the substrate layer; A functional layer is disposed on the surface of the bottom electrode layer opposite to the substrate layer, and the functional layer is a thin film having a ferroelectric phase and an antiferroelectric phase coexisting. A top electrode layer is disposed on the surface of the functional layer opposite to the bottom electrode layer.

2. The multi-state memory with ferroelectric-antiferroelectric coexistence according to claim 1, characterized in that, The substrate layer includes any one of SrTiO3, silicon wafer, and flexible mica.

3. The multi-state memory with ferroelectric-antiferroelectric coexistence according to claim 1, characterized in that, The bottom electrode layer includes SrRuO3 and La. 0.7 Sr 0.3 Any one of MnO3, LaCoO3, and LaNiO3.

4. The multi-state memory with ferroelectric-antiferroelectric coexistence according to claim 1, characterized in that, The functional layer includes PbZrO3, PbHfO3, and Hf 0.5 Zr 0.5 Any one of O2, Hf0.8Zr0.2O2, or NaNbO3.

5. The multi-state memory with ferroelectric-antiferroelectric coexistence according to claim 1, characterized in that, The top electrode includes any one of Au, Pt, TiN, and TaN.

6. The multi-state memory with ferroelectric-antiferroelectric coexistence according to any one of claims 1-5, characterized in that, The substrate layer is SrTiO3; and / or, The bottom electrode layer is SrRuO3; and / or, The functional layer is PbZrO3; and / or, The top electrode is Au.

7. The multi-state memory with ferroelectric-antiferroelectric coexistence according to any one of claims 1-5, characterized in that, The substrate layer and the bottom electrode layer are grown epitaxially.

8. A multi-state memory with ferroelectric-antiferroelectric coexistence according to any one of claims 1-5, characterized in that, The thickness of the functional layer is 100 nm-300 nm; and / or, The thickness of the bottom electrode layer is 30 nm-40 nm; and / or, The particle size of the top electrode is 50-200 μm.

9. A method for fabricating a multi-state memory with ferroelectric-antiferroelectric coexistence as described in any one of claims 1-8, characterized in that, Includes the following steps: Provide a substrate layer; A bottom electrode layer is prepared on the surface of the substrate layer by an epitaxial deposition process; A functional layer is deposited on the surface of the bottom electrode layer opposite to the substrate layer; A top electrode is deposited on the surface of the functional layer opposite to the bottom electrode layer to prepare the top electrode layer.

10. The application of a multi-state memory with ferroelectric and antiferroelectric coexistence as a storage unit in an integrated circuit chip, as described in any one of claims 1-8.

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