Semiconductor device
By introducing defects on the surface of the second protective layer of the phase-change memory (PCM), the interfacial thermal resistance is enhanced, which solves the write error problem caused by thermal disturbance during the write operation of PCM, improves data reliability, and reduces the power consumption of the operating current.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 新存科技(武汉)有限责任公司
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-15
AI Technical Summary
Phase-change memory is prone to write errors caused by thermal disturbances during write operations, which reduces data reliability.
By introducing defects on the surface of the second protective layer, the interfacial thermal resistance between the second protective layer and the insulation layer is increased, limiting heat diffusion and reducing heat crosstalk.
It improves data reliability and reduces power consumption of operating current.
Smart Images
Figure CN122054600A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology
[0002] As a candidate for the next generation of non-volatile semiconductor memory, phase change memory (PCRAM) has attracted widespread attention due to its advantages such as high-speed read, high erasure and write cycles, non-volatility, small device size, low power consumption, and resistance to strong shocks and radiation.
[0003] Phase-change memory (PCM) is a semiconductor memory based on phase-change materials, which are materials that can electrically switch between amorphous and polycrystalline states. The basic principle of PCM is to use electrical pulse signals applied to the device cells to cause a reversible phase transition of the phase-change material between an amorphous and polycrystalline state. By distinguishing between the high resistance in the amorphous state and the low resistance in the polycrystalline state, the operations of writing, erasing, and reading information are achieved.
[0004] Phase-change memory (PCM) relies on the Joule heating of current to manipulate the phase-change material, causing it to transition between a crystalline (low resistance) and an amorphous (high resistance) state, thereby achieving SET-RESET switching and completing data storage. For the manipulated memory cell, the Joule heating of its current generates thermal disturbances to surrounding memory cells, causing a crystalline-to-amorphous state reversal in the phase-change storage layer of those cells, resulting in write disturb (WD) errors and reducing the data reliability of the PCM. Summary of the Invention
[0005] This application provides a semiconductor device that enhances the interfacial thermal resistance between the second protective layer and the thermal insulation layer by increasing the defect density at the second surface of the second protective layer. This reduces thermal crosstalk, thereby reducing write errors and improving data reliability.
[0006] This application provides a semiconductor device, including: a substrate; a plurality of memory cells arranged in an array on the substrate; a first protective layer and a second protective layer located on the sidewalls of the memory cells, the first protective layer being located between the memory cells and the second protective layer, the first protective layer including a first surface facing away from the memory cells, the second protective layer including a second surface facing away from the memory cells, and both the material of the second protective layer and the material of the first protective layer including silicon oxide; a heat insulation layer located between adjacent memory cells and located on the second surface of the second protective layer; wherein the defect density at the second surface is greater than the defect density at the first surface.
[0007] In some embodiments, the roughness of the second surface is greater than the roughness of the first surface.
[0008] In some embodiments, the roughness of the second surface is greater than or equal to twice the roughness of the first surface.
[0009] In some embodiments, the second protective layer further includes a third surface facing away from the heat insulation layer, wherein the roughness of the second surface is greater than that of the third surface.
[0010] In some embodiments, the second protective layer further includes a third surface facing away from the heat insulation layer, and the first protective layer further includes a fourth surface facing away from the second protective layer, wherein the roughness of the third surface is greater than that of the fourth surface.
[0011] In some embodiments, the material of the heat insulation layer includes siloxane, and the ratio of the difference between the lattice constant of the second protective layer and the lattice constant of the heat insulation layer is 1% to 10%.
[0012] In some embodiments, the lattice constant of the second protective layer is greater than that of the heat insulation layer, and the material of the second protective layer further includes doping elements, wherein the atomic radius of the doping elements is greater than that of silicon atoms.
[0013] In some embodiments, the doping element includes at least one of Ge, Ti, Zr, Ga, Al, Y, and Cr.
[0014] In some embodiments, the lattice constant of the second protective layer is smaller than that of the heat insulation layer, and the material of the second protective layer further includes doping elements, wherein the atomic radius of the doping elements is smaller than that of silicon atoms.
[0015] In some embodiments, the material of the heat insulation layer further includes doping elements, wherein the ratio of the difference between the atomic radius of the doping element and the atomic radius of silicon atoms is 1% to 10%.
[0016] In the semiconductor device of this application embodiment, a heat insulation layer is located on the second surface of the second protective layer. By introducing defects on the second surface of the second protective layer, the defect density is increased compared to the first protective layer, thus increasing the interfacial thermal resistance between the second protective layer and the heat insulation layer. Since the second protective layer is located on the sidewall of the memory cell, increasing this interfacial thermal resistance can enhance the thermal self-limitation of the memory cell, concentrating heat within the memory cell and reducing its diffusion to the surroundings, thereby reducing thermal crosstalk. This not only reduces the risk of write errors and improves data reliability but also reduces operating current, achieving low power consumption.
[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0019] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in some embodiments of this application; Figure 2 This is a schematic cross-sectional view of a semiconductor device along the YZ direction provided in some embodiments of this application; Figure 3 This is a schematic cross-sectional view of a semiconductor device along the XZ direction provided in some embodiments of this application; Figure 4 This is a temperature distribution diagram of the second surface under different roughnesses provided in some embodiments of this application; Figures 5 to 7 This is a temperature distribution map near the sidewall of the memory cell near the second surface of the operated memory cell under different roughnesses, provided in some embodiments of this application; Figure 8 This application provides some embodiments of the second surface with different roughness at various locations outside the memory cell; Figure 9 These are the AFM three-dimensional topography and height distribution diagrams under baseline RF power; Figure 10 A3D topographic map and height distribution map of AFM with doubled RF power. Detailed Implementation
[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0021] Please see Figure 1 , Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in some embodiments of this application.
[0022] The semiconductor device includes a substrate, a plurality of memory cells 10, a first conductive line 20, and a second conductive line 30. The plurality of memory cells 10 are arranged in an array on the substrate along a first direction X and a second direction Y. The first conductive line 20 extends along the first direction X, and the second conductive line 30 extends along the second direction Y. The memory cell 10 is located between the first conductive line 20 and the second conductive line 30, and is located at the intersection of the first conductive line 20 and the second conductive line 30. One of the first conductive line 20 and the second conductive line 30 is a bit line, and the other is a word line.
[0023] In this embodiment, both the first direction X and the second direction Y are parallel to the surface of the substrate, and the first direction X and the second direction Y intersect in opposite directions. For example, the first direction X and the second direction Y are perpendicular to each other, but this application is not limited to this. In this embodiment, the third direction Z is used to represent the direction perpendicular to the substrate surface.
[0024] The storage unit 10 includes a phase change unit 11 and a gating unit 12, wherein the gating unit 12 is located between the substrate and the phase change unit 11.
[0025] Because the memory cell 10 has a certain critical distance (CD) deviation during manufacturing, a large RESET current is required during the operation of the memory cell 10 to ensure that memory cells 10 with different CDs can be fully RESETd to achieve a significant distinction in resistance between the SET and RESET states. The Joule heating of the current will generate thermal disturbances to the surrounding phase change memory layer, causing a crystalline-amorphous state reversal in the surrounding phase change memory layer, resulting in write disturb (WD) errors and reducing the data reliability of the phase change memory.
[0026] Analysis of the heat generation process and heat conduction path reveals that for the operated memory cell 10, the heat is primarily generated by the phase change unit 11. The heat conduction paths, according to direction, can be categorized as follows: 1. Conducted vertically to the lower first conductive line 20 (e.g., bit line BL); 2. Conducted vertically to the upper second conductive line 30 (e.g., word line WL); 3. Conducted along the direction of the first conductive line 20 to the adjacent memory cell 10; 4. Conducted along the direction of the second conductive line 30 to the adjacent memory cell 10. The heat conducted along the BL / WL directions will cause thermal crosstalk (WD) in the BL / WL directions, resulting in reduced data reliability.
[0027] In one embodiment, the memory further includes a sidewall (i.e., a protective layer) located on the sidewall of the storage cell 10 and a heat insulation layer located on the surface of the sidewall. Methods to improve the thermal resistance in the heat conduction path include using sidewall materials (liners) and heat insulation layer materials (SOD) with low thermal conductivity, increasing the number of sidewall layers, etc., but there are risks such as material compatibility and structural changes.
[0028] Based on this, this application provides a semiconductor device, including: a substrate; a plurality of memory cells arranged in an array on the substrate; a first protective layer and a second protective layer located on the sidewalls of the memory cells, the first protective layer being located between the memory cells and the second protective layer, the first protective layer including a first surface facing away from the memory cells, the second protective layer including a second surface facing away from the memory cells, and both the material of the second protective layer and the material of the first protective layer including silicon oxide; a heat insulation layer located between adjacent memory cells and located on the second surface of the second protective layer; wherein the defect density at the second surface is greater than the defect density at the first surface.
[0029] In the semiconductor device of this application embodiment, a heat insulation layer is located on the second surface of the second protective layer. By introducing defects on the second surface of the second protective layer, the defect density is increased compared to the first protective layer, thus increasing the interfacial thermal resistance between the second protective layer and the heat insulation layer. Since the second protective layer is located on the sidewall of the memory cell, increasing this interfacial thermal resistance can enhance the thermal self-limitation of the memory cell, concentrating heat within the memory cell and reducing its diffusion to the surroundings, thereby reducing thermal crosstalk. This not only reduces the risk of write errors and improves data reliability but also reduces operating current, achieving low power consumption.
[0030] The semiconductor devices provided in the embodiments of this application will be described below with reference to the accompanying drawings.
[0031] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic cross-sectional view of a semiconductor device along the YZ direction provided in some embodiments of this application. Figure 3 This is a schematic cross-sectional view of a semiconductor device along the XZ direction provided in some embodiments of this application. The three-dimensional structure of this semiconductor device can be referred to... Figure 1 .
[0032] The semiconductor device 100 includes a substrate 40, a plurality of memory cells 10, a first protective layer 51, a second protective layer 52, and a heat insulation layer 60. The plurality of memory cells 10 are arrayed on the substrate 40. The first protective layer 51 and the second protective layer 52 are located on the sidewalls of the memory cells 10. The first protective layer 51 is located between the memory cells 10 and the second protective layer 52. The first protective layer 51 includes a first surface 511 facing away from the memory cells 10, and the second protective layer 52 includes a second surface 521 facing away from the memory cells 10. The material of the second protective layer 52 and the first protective layer 51 both include silicon oxide. The heat insulation layer 60 is located between adjacent memory cells 10 and is located on the second surface 521 of the second protective layer 52. The defect density at the second surface 521 is greater than the defect density at the first surface 511.
[0033] In some embodiments, the storage unit 10 includes a phase change unit 11 and a gating unit 12, wherein the gating unit 12 is located between the substrate 40 and the phase change unit 11.
[0034] It should be noted that the membrane layer of the storage unit 10 can also be other configurations, and is not limited to the one shown in the figure.
[0035] In some embodiments, a first protective layer 51 is located on the sidewall of the phase change unit 11, and a second protective layer 52 is located on the sidewall of the phase change unit 11 and the gating unit 12.
[0036] It should be noted that the specific locations of the first protective layer 51 and the second protective layer 52 on the side wall of the storage unit 10 can also be other arrangements, and are not limited to one shown in the figure.
[0037] In some embodiments, the gating unit 12 may include a first electrode 121, a second electrode 122, and a gating layer 123, wherein the gating layer 123 is located between the first electrode 121 and the second electrode 122. The first electrode 121 may be located between the gating layer 123 and the substrate 40.
[0038] Exemplary materials for the first electrode 121 and the second electrode 122 include amorphous carbon, and the material of the gate layer 123 may include a first chalcogenide compound, which may include at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S.
[0039] The phase change unit 11 may include a phase change storage layer 111 and a third electrode 112, wherein the phase change storage layer 111 is located between the gating unit 12 and the third electrode 112.
[0040] An exemplary material for the third electrode 112 may include amorphous carbon, and the material for the phase change storage layer 111 may include a second chalcogenide compound, the material of which differs from that of the first chalcogenide compound. The second chalcogenide compound may include at least one of the following: germanium-tellurium (Ge-Te) compound, antimony-tellurium (Sb-Te) compound, germanium-antimony-tellurium (Ge-Sb-Te) compound, silicon-antimony-tellurium (Si-Sb-Te) compound, titanium-antimony-tellurium (Ti-Sb-Te) compound, aluminum-antimony-tellurium (Al-Sb-Te) compound, germanium-antimony-selenium (Ge-Sb-Se), germanium-gallium-selenium (Ge-Sb-Ga), and germanium-bismuth-selenium (Ge-Sb-Bi).
[0041] An exemplary material for the first protective layer 51 is silicon oxide. The first protective layer 51 is located on the sidewall of the phase change unit 11 and is used to protect the phase change unit 11. It can reduce the damage to the phase change unit 11 caused by subsequent processes after the formation of the phase change unit 11.
[0042] In some embodiments, the semiconductor device 100 may further include a third protective layer 71, which is located between the first protective layer 51 and the phase change unit 11, and the material of the third protective layer 71 includes silicon nitride, so as to prevent oxygen in the first protective layer 51 from directly contacting the phase change unit 11 and reduce the oxidation of the phase change storage layer 111.
[0043] An exemplary material for the second protective layer 52 is silicon oxide. The second protective layer 52 is located on the sidewalls of the phase change unit 11 and the gate unit 12, and extends continuously between the sidewalls of the phase change unit 11 and the gate unit 12. The second protective layer 52 is used to protect the sidewalls of the storage unit 10.
[0044] In some embodiments, the semiconductor device 100 may further include a fourth protective layer 72, which is located between the first protective layer 51 and the second protective layer 52, and between the gate unit 12 and the second protective layer 52. The material of the fourth protective layer 72 includes silicon nitride, which can prevent oxygen in the second protective layer 52 from contacting the gate unit 12 and reduce oxidation of the gate layer 123.
[0045] The heat insulation layer 60 is located on the second sidewall of the second protective layer 52. The material of the heat insulation layer 60 may include siloxane, which has low thermal conductivity and mainly provides heat insulation for adjacent storage cells 10.
[0046] It should be noted that since the first protective layer 51 and the second protective layer 52 are made of the same material, and the forming processes of the first protective layer 51 and the second protective layer 52 are usually the same, the defect density on the outer surface of the first protective layer 51 and the outer surface of the second protective layer 52 is usually the same. Therefore, this embodiment of the application takes the first protective layer 51 as a reference, and by setting the defect density at the second surface 521 of the second protective layer 52 to be greater than the defect density at the first surface 511 of the first protective layer 51, this embodiment of the application increases the defect density of the second surface 521 of the second protective layer 52 in contact with the heat insulation layer 60, thereby increasing the interfacial thermal resistance between the second protective layer 52 and the heat insulation layer 60.
[0047] The term "defect density" as used in this application refers to the number of defects per unit area on the surface of the film. "Defects" can include both physical and microscopic defects. Physical defects are those observable in the macroscopic structure of the material, including surface roughness, cracks, pores, delamination, and particle boundaries. Microscopic defects are those existing at the atomic or molecular scale, including point defects (such as vacancies and interstitial atoms), dislocations, grain boundaries, and phase interfaces. Both physical and microscopic defects increase interfacial thermal resistance.
[0048] In some embodiments, the roughness of the second surface 521 is greater than the roughness of the first surface 511.
[0049] This embodiment increases the defect density at the second surface 521 by increasing the roughness of the outer surface of the second protective layer 52. On the one hand, this reduces the actual contact area between the second protective layer 52 and the heat insulation layer 60, thereby increasing the interfacial thermal resistance. On the other hand, the uneven interface leads to localized changes in heat flux density, increases interfacial gaps (air has lower thermal conductivity), and makes the heat flow path more tortuous, thus increasing the interfacial thermal resistance. Increasing this interfacial thermal resistance enhances the thermal self-limitation of the phase change unit 11, concentrating heat within the phase change unit 11 and reducing its diffusion to the surroundings, thereby reducing thermal crosstalk. This not only reduces the risk of write errors and improves data reliability but also reduces operating current, achieving low power consumption.
[0050] In some embodiments, the roughness of the second surface 521 is greater than or equal to twice the roughness of the first surface 511, for example, twice, three times, or four times. This increases the roughness difference between the second surface 521 and the first surface 511, further increasing the roughness of the second surface 521, and thereby further improving the interfacial thermal resistance between the second protective layer 52 and the heat insulation layer 60.
[0051] Please see Figure 4 , Figure 4 This is a temperature distribution diagram of the second surface under different roughnesses provided in some embodiments of this application.
[0052] It should be noted that the second surface 521 of the second protective layer 52 includes two surfaces opposite each other along the direction of the first conductive line 20 (i.e. Figure 3 The second surface 521 shown, and the two surfaces opposite each other along the direction of the second conductive line 30 (i.e. Figure 2 The black bar on the left of the second surface 521 (shown as a second surface 521) represents the temperature at the location opposite to the second conductive line 30 (WL), and the gray bar on the right represents the temperature at the location opposite to the first conductive line 20. The temperature here refers to the highest temperature.
[0053] Baseline refers to the case where the roughness of the second surface 521 of the second protective layer 52 is the same as the roughness of the first surface 511 of the first protective layer 51. Roughness×2 refers to the case where the roughness of the second surface 521 is twice that of the first surface 511. Roughness×3 refers to the case where the roughness of the second surface 521 is three times that of the first surface 511.
[0054] Comparing the temperatures at different roughnesses on the second surface 521 opposite the word line WL direction, it can be seen that as the roughness of the second surface 521 opposite the word line WL direction increases, the maximum temperature of this surface gradually decreases. Comparing the temperatures at different roughnesses on the second surface 521 opposite the bit line BL direction, it can be seen that as the roughness of the second surface 521 opposite the bit line BL direction increases, the maximum temperature of this surface gradually decreases. This indicates that the temperature of all second surfaces 521 (including the four surfaces) decreases with increasing roughness.
[0055] The aggressive cell line refers to the highest temperature at the sidewall of memory cell 10. As the roughness at the second surface 521 increases, the temperature of the sidewall of memory cell 10 gradually increases. This indicates that more of the heat generated by memory cell 10 is confined to the sidewall of memory cell 10, reducing heat diffusion to the second protective layer 52. This results in an increase in the temperature at the sidewall of memory cell 10, while the temperature at the second surface 521 of the second protective layer 52 decreases. Thermal simulation calculations show that, under the same reset current conditions, the highest temperature of the sidewall of the operated memory cell 10 increases from 1123K to 1153K.
[0056] In general, the increased roughness of the second surface 521 leads to an increased defect density of physical defects on the second surface 521, which in turn increases the interfacial thermal resistance between the second protective layer 52 and the heat insulation layer 60.
[0057] Please see Figures 5 to 7 , Figures 5 to 7This is a temperature distribution map of the second surface of the operated memory cell at the adjacent memory cell sidewall under different roughnesses according to some embodiments of this application. The adjacent memory cell 10 can refer to the memory cell 10 adjacent to the operated memory cell 10 in the word line direction.
[0058] Figure 5 The roughness of the second surface 521 of the second protective layer 52 in the operated storage cell 10 is the same as the roughness of the first surface 511 of the first protective layer 51. Figure 6 The roughness of the second surface 521 of the second protective layer 52 in the operated storage cell 10 is twice the roughness of the first surface 511 of the first protective layer 51. Figure 7 The roughness of the second surface 521 of the second protective layer 52 in the operating storage cell 10 is three times the roughness of the first surface 511 of the first protective layer 51.
[0059] Figure 5 , Figure 6 and Figure 7 In the middle, the darker temperature region is the high-temperature region T. By comparison, it can be seen that as the roughness of the second surface 521 of the second protective layer 52 in the operated storage cell 10 increases, the range of the high-temperature region T of the adjacent storage cell 10 gradually decreases. This indicates that the thermal disturbance of the adjacent storage cell 10 is smaller.
[0060] Please see Figure 8 , Figure 8 This describes the temperature distribution at various locations outside the storage cell on the second surface under different roughness conditions provided in some embodiments of this application. The curves represented by hollow circles indicate the case where the roughness of the second surface 521 is the same as that of the first surface 511; the curves represented by square black dots indicate the case where the roughness of the second surface 521 is twice that of the first surface 511; and the curves represented by circular black dots indicate the case where the roughness of the second surface 521 is three times that of the first surface 511.
[0061] Figure 8 The temperatures at different locations of the fourth protective layer 72, the second protective layer 52, and the insulation layer 60 are shown from left to right, and the interfaces between the fourth protective layer 72 and the second protective layer 52, as well as the interfaces between the second protective layer 52 and the insulation layer 60, are indicated by dashed lines.
[0062] Depend on Figure 8It can be seen that the temperature gradually decreases at different locations from the fourth protective layer 72 along the second protective layer 52 to the heat insulation layer 60. Focusing on the interface between the second protective layer 52 and the heat insulation layer 60, comparing different roughness conditions, it can be seen that as the roughness of the second surface 521 increases, the temperature drop near the interface between the second protective layer 52 and the heat insulation layer 60 gradually increases. In particular, when the roughness of the second surface 521 increases to three times that of the first surface 511, the temperature drop near the interface between the second protective layer 52 and the heat insulation layer 60 increases significantly. After experimental testing and obtaining material data, simulation was performed. Thermal simulation calculations show that, under the same reset current conditions, the temperature drop provided by the interface between the second protective layer 52 and the heat insulation layer 60 with three times the roughness increases from 16K to 65K, an increase of approximately three times. This indicates that increasing the roughness of the second surface 521 increases the defect density, thereby increasing the interfacial thermal resistance between the second protective layer 52 and the heat insulation layer 60.
[0063] In some embodiments, to increase the roughness of the second surface 521, a second protective layer 52 (silicon oxide) can be grown using atomic layer deposition (ALD). By reducing the single cycle time of the precursor circulation during the early stage of ALD and increasing the number of cycles, the island-like growth pattern in the early stage of film formation can be enhanced, thereby improving the film roughness. Surface roughness can also be improved by lowering the ALD growth temperature.
[0064] For example, when growing SiO2 using the ALD method, to obtain SiO2 with a rough surface, the growth conditions can be set as follows: single-pass gas time 10ms~150ms, number of cycles 10~300, and reaction temperature 30℃~250℃. This low-temperature, short-time, and multi-cycle mode promotes island-like growth. It is understandable that the first protective layer 51 can also be grown using the ALD method, but the reaction temperature of the first protective layer 51 is relatively higher, the single-pass gas time is longer, and the number of cycles is fewer, resulting in a lower roughness on the first surface 511 of the first protective layer 51.
[0065] In some embodiments, the surface roughness is improved by changing the precursor. For example, the precursor used in the first protective layer 51 is SiH4, while the precursor used in the second protective layer 52 is changed to SiCl4 and H2O. SiO2 grown by H2O has a greater surface roughness.
[0066] In some embodiments, to increase only the roughness of the second surface 521, conventional ALD growth (with SiH4 as the precursor) can be used initially. In the final cycle, SiCl4 and H2O are used as the reaction precursors, NH3 as the catalyst gas, and N2 as the carrier gas to grow SiO2 in the reaction chamber. SiO2 grown using H2O has a greater surface roughness. In this embodiment, using conventional ALD growth in the early stages does not change the roughness of the inner surface of the second protective layer 52. Changing the precursor in the final cycle increases only the roughness of the outer surface (i.e., the second surface 521) of the second protective layer 52.
[0067] Therefore, the second protective layer 52 also includes a third surface 522 facing away from the heat insulation layer 60, and the roughness of the second surface 521 is greater than the roughness of the third surface 522. In this way, by only increasing the roughness of the second surface 521 to improve the interfacial thermal resistance between the second protective layer 52 and the heat insulation layer 60, the influence of the change in the roughness of the third surface 522 on the adhesion between the fourth protective layer 72 and the second protective layer 52 can be avoided, as well as other effects caused by the change in the roughness of the third surface 522.
[0068] In some embodiments, the roughness of the second surface 521 can be improved by changing the deposition method of the second protective layer 52 from ALD growth to chemical vapor deposition (CVD) growth.
[0069] For example, SiO2 can be grown using CVD methods, including but not limited to LPCVD and PECVD. Silicon sources can include TEOS and SiH4. Taking PECVD as an example, SiH4 is used as the Si source, reacting with introduced O2 in an Ar environment to generate a SiO2 thin film. During deposition, the wafer back-side cooling temperature is maintained between 50℃ and 200℃, and the gas pressure inside the deposition chamber is between 1 mTorr and 20 mTorr. The plasma is driven by an inductively coupled coil, with the power supply of the inductively coupled plasma (ICP) controlled between 100W and 1000W. Simultaneously, an RF bias can be applied to the substrate, with an RF bias power supply power of 0W to 300W and a bias voltage of 0 to 100V. By controlling parameters such as deposition gas pressure and RF power (i.e., RF bias power supply power), the surface roughness of the thin film can be significantly adjusted.
[0070] Please see Figure 9 and Figure 10 , Figure 9 These are the AFM 3D topography and height distribution diagrams at baseline RF power. Figure 10 Three-dimensional topographic map and height distribution map of AFM under doubled RF power. Figure 10 The corresponding RF power is Figure 9 Twice the corresponding RF power, AFM stands for Atomic Force Microscope.
[0071] Depend on Figure 9 and Figure 10 The test results show that when the RF power is doubled, the root mean square roughness Rq measured by AFM increases from 0.68nm to 0.93nm, an improvement of about 37%.
[0072] In other embodiments, the second protective layer 52 further includes a third surface 522 facing away from the heat insulation layer 60, and the first protective layer 51 further includes a fourth surface 512 facing away from the second protective layer 52, wherein the roughness of the third surface 522 is greater than the roughness of the fourth surface 512.
[0073] In other words, the inner surface roughness of the second protective layer 52 is also improved compared to the inner surface roughness of the first protective layer 51. Theoretically, this can increase the defect density of the inner surface of the second protective layer 52, thereby increasing the interfacial thermal resistance between the fourth protective layer 72 and the second protective layer 52, further reducing heat crosstalk, and thus reducing write errors and improving data reliability.
[0074] In some embodiments, the material of the heat insulation layer 60 includes siloxane, and the ratio of the difference between the lattice constant of the second protective layer 52 and the lattice constant of the heat insulation layer 60 is 1% to 10%.
[0075] Since the material composition of the heat insulation layer 60 also contains a relatively large amount of Si and O, the chemical composition difference between the second protective layer 52 and the heat insulation layer 60 is limited, and their interface is unclear, making it difficult to generate a significant interfacial thermal resistance effect. Therefore, this embodiment increases the difference between the lattice constant of the second protective layer 52 and the lattice constant of the heat insulation layer 60 to increase the interfacial mismatch between the second protective layer 52 and the heat insulation layer 60, thereby increasing the defect density of the micro-defects on the second surface 521. This can create a more significant structural or compositional difference in the interfacial region between the second protective layer 52 and the heat insulation layer 60. These defects are good phonon scattering sources, which can enhance the phonon scattering efficiency at the interface and thus increase the interfacial thermal resistance.
[0076] The ratio of the difference between the lattice constant of the second protective layer 52 and the lattice constant of the heat insulation layer 60 is greater than or equal to 1%, resulting in a certain lattice difference between the two; the ratio of the difference between the lattice constant of the second protective layer 52 and the lattice constant of the heat insulation layer 60 is less than or equal to 10%, which can reduce the stress generated at the interface, thereby reducing the warping, cracking or peeling of the film or coating caused by such stress.
[0077] In some embodiments, the lattice constant of the second protective layer 52 is greater than that of the heat insulation layer 60, and the material of the second protective layer 52 further includes doping elements, wherein the atomic radius of the doping elements is greater than that of silicon atoms. That is, by doping the second protective layer 52 with elements having an atomic radius greater than that of Si, the lattice constant of the second protective layer 52 is increased, causing silicon oxide to undergo a certain lattice expansion.
[0078] For example, the doping element includes at least one of Ge, Ti, Zr, Ga, Al, Y, and Cr. The atomic radii of these doping elements are larger than those of Si and have a significant difference from those of Si, such that the difference between the lattice constant of the second protective layer 52 and the lattice constant of the heat insulation layer 60 is greater than 1%.
[0079] The radius of a Si atom is 117 pm, the radius of a Ge atom is 122 pm, the radius of a Ti atom is 132 pm, the radius of a Zr atom is 132 pm, the radius of a Ga atom is 128 pm, the radius of an Al atom is 121 pm, the radius of a Y atom is 180 pm, and the radius of a Cr atom is 128 pm.
[0080] In some embodiments, the doping element is Ti, and the process of the second protective layer 52 can be as follows: using titanium butoxide as Ti source and SiH4 as Si source, controlling the mass ratio of titanium butoxide to SiH4 to be greater than 0 and less than or equal to 0.5, first volatilizing titanium butoxide into gas at 210°C, and using Ar and O2 as carrier gases together with SiH4 to be introduced into the deposition chamber for deposition to form SiO2 and TiO2 thin films.
[0081] In other embodiments, the lattice constant of the second protective layer 52 is smaller than that of the heat insulation layer 60. The material of the second protective layer 52 also includes doping elements, and the atomic radius of the doping elements (e.g., nitrogen) is smaller than that of silicon atoms. That is, by doping the second protective layer 52 with elements whose atomic radius is smaller than that of Si, the lattice constant of the second protective layer 52 is reduced, which also increases the lattice mismatch between the second protective layer 52 and the heat insulation layer 60, thereby increasing the interface mismatch and thus increasing the defect density at the interface.
[0082] It should be noted that, compared to doping elements with smaller atomic radii in the second protective layer 52, doping elements with larger atomic radii in the second protective layer 52 results in a more stable structure, because elements with smaller radii are more prone to diffusion and instability.
[0083] In some embodiments, the material of the heat insulation layer 60 further includes doping elements, wherein the ratio of the difference between the atomic radius of the doping element and the atomic radius of silicon atoms is 1% to 10%. That is, by doping the heat insulation layer 60 with elements having an atomic radius greater than Si, the lattice constant of the heat insulation layer 60 is increased to create a certain difference from the lattice constant of the second protective layer 52.
[0084] It should be noted that, since the second protective layer 52 is thinner than the heat insulation layer 60 is thicker, compared with the embodiment in which elements are doped in the heat insulation layer 60, the lattice constant of the second protective layer 52 can be significantly changed with a smaller doping amount; and other effects (such as changes in thermal conductivity) caused by doping elements in the heat insulation layer 60 can be avoided.
[0085] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0087] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0088] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A semiconductor device, characterized in that, include: Substrate; Multiple storage cells are arranged in an array on the substrate; A first protective layer and a second protective layer are located on the sidewall of the storage cell. The first protective layer is located between the storage cell and the second protective layer. The first protective layer includes a first surface facing away from the storage cell, and the second protective layer includes a second surface facing away from the storage cell. The materials of the second protective layer and the first protective layer both include silicon oxide. A heat insulation layer is located between adjacent storage cells and on the second surface of the second protective layer; The defect density at the second surface is greater than the defect density at the first surface.
2. The semiconductor device according to claim 1, characterized in that, The roughness of the second surface is greater than that of the first surface.
3. The semiconductor device according to claim 2, characterized in that, The roughness of the second surface is greater than or equal to twice the roughness of the first surface.
4. The semiconductor device according to claim 2, characterized in that, The second protective layer also includes a third surface facing away from the heat insulation layer, the roughness of the second surface being greater than that of the third surface.
5. The semiconductor device according to claim 2, characterized in that, The second protective layer further includes a third surface facing away from the heat insulation layer, and the first protective layer further includes a fourth surface facing away from the second protective layer, wherein the roughness of the third surface is greater than that of the fourth surface.
6. The semiconductor device according to claim 1, characterized in that, The material of the heat insulation layer includes siloxane, and the ratio of the difference between the lattice constant of the second protective layer and the lattice constant of the heat insulation layer is 1% to 10%.
7. The semiconductor device according to claim 6, characterized in that, The lattice constant of the second protective layer is greater than that of the heat insulation layer. The material of the second protective layer also includes doping elements, and the atomic radius of the doping elements is greater than that of silicon atoms.
8. The semiconductor device according to claim 7, characterized in that, The doping element includes at least one of Ge, Ti, Zr, Ga, Al, Y, and Cr.
9. The semiconductor device according to claim 6, characterized in that, The lattice constant of the second protective layer is smaller than that of the heat insulation layer. The material of the second protective layer also includes doping elements, and the atomic radius of the doping elements is smaller than that of silicon atoms.
10. The semiconductor device according to claim 6, characterized in that, The material of the heat insulation layer also includes doping elements, and the ratio of the difference between the atomic radius of the doping element and the atomic radius of silicon atoms is 1% to 10%.