Method for improving reliability of laterally diffused metal oxide semiconductor

Abstract

The invention provides a method for improving the reliability of a laterally diffused metal oxide semiconductor. The method comprises the following steps: providing a semiconductor substrate and defining a drift region and a well region on the semiconductor substrate; performing ion implantation in the substrate to form a body region, and introducing a damage layer on the surface of the body region in the implantation process; carrying out a surface treatment process on the surface of the body region, and stripping a damaged layer; and performing source and drain injection. Preferably, silicon surface damage caused by ion implantation (such as arsenic ions) is removed by using hot phosphoric acid wet etching. According to the method, the surface damage layer is removed, the interface state density is effectively reduced, the surface electric field distribution is optimized, and on the premise that the direct-current electrical performance of the device is kept unchanged, the heat carrier injection aging resistance of the device is remarkably improved, and the long-term service life of the device is remarkably prolonged.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the reliability of laterally diffused metal-oxide semiconductors. Background Technology

[0002] LDMOS (Laterally Diffused Metal-Oxide Semiconductor) devices offer advantages such as high breakdown voltage (BV), fast switching speed, and ease of integration, making them widely used in wireless communication, industrial, and medical fields. In the design and manufacturing of LDMOS devices, breakdown voltage (BV), on-resistance (Rsp), and safe operating area (SOA) are three crucial performance indicators, often requiring designers to make trade-offs. Improving device lifespan and reliability while meeting DC performance requirements has been a key research focus in this field.

[0003] In traditional P-body LDMOS processes, arsenic (As) ions are typically implanted to form the P-body region. This implantation process not only serves as a lightly doped drain (LDD) but also helps adjust the device's threshold voltage. However, due to the large atomic radius of arsenic ions, high-dose or high-energy implantation can easily damage the silicon surface lattice near the LDMOS channel region, forming a surface damage layer.

[0004] Such surface damage increases the interface state density. During device operation, a higher interface state density can lead to device parameter drift due to the hot carrier injection (HCI) effect, resulting in poor device reliability. While some existing processes can meet basic electrical performance requirements, they often struggle to balance the needs of surface lattice quality repair and device morphology control when facing stringent reliability requirements.

[0005] Therefore, there is a need for a manufacturing method that can effectively improve the surface quality of P-body LDMOS, enhance device reliability, and not affect the DC characteristics of the device. Summary of the Invention

[0006] The technical problem this invention aims to solve is that in existing laterally diffused metal-oxide-semiconductor (LDMOS) manufacturing processes, especially for P-type body LDMOS, high-mass ion implantation (such as arsenic ions) is typically used to form the body region, which leads to severe lattice damage and amorphization of the silicon surface. This surface damage significantly increases the interface state density, causing severe parameter drift under hot carrier injection (HCI) stress, thereby reducing device reliability and lifespan.

[0007] To address the aforementioned technical problems, this invention provides a method for improving the reliability of laterally diffused metal-oxide semiconductors, the method comprising the following steps:

[0008] Step 1: Provide a semiconductor substrate, and define a drift region and a well region on the semiconductor substrate;

[0009] Step 2: An ion implantation process is performed in the semiconductor substrate to form a bulk region. The ion implantation process introduces a damage layer on the surface of the bulk region.

[0010] Step 3: Perform a surface treatment process on the surface of the body region to remove the damaged layer;

[0011] Step 4: Perform source implantation in the body region and drain implantation in the drift region.

[0012] Preferably, the laterally diffused metal-oxide semiconductor is a P-type body region laterally diffused metal-oxide semiconductor; in step one, the semiconductor substrate is a P-type semiconductor substrate and the drift region is an N-type drift region; in step two, the body region is a P-type body region; in step four, the source implantation process forms an N-type source and the drain implantation process forms an N-type drain.

[0013] Preferably, the method further includes the step of forming a gate structure on the surface of the semiconductor substrate after step one and before step two.

[0014] Preferably, in step two, the ion implantation process is performed using the gate structure as a mask to form the self-aligned body region.

[0015] Preferably, the step of forming the gate structure includes defining a stepped oxide layer located above the drift region.

[0016] Preferably, the step of forming the gate structure further includes defining a gate oxide layer located on the surface of the active region of the device.

[0017] Preferably, the step of forming the gate structure specifically includes: after forming the stepped oxide layer and the gate oxide layer, depositing polysilicon material, and defining the polysilicon gate through photolithography and etching processes.

[0018] Preferably, in step one, providing the semiconductor substrate specifically includes: selecting a semiconductor substrate silicon; defining a buried layer on the surface of the semiconductor substrate silicon, the buried layer serving as a bottom isolation layer for the device; and growing an epitaxial layer on the semiconductor substrate silicon.

[0019] Preferably, in step one, the definition of the drift region and the well region specifically includes: defining a deep well, a well, and a drift region on the surface of the semiconductor substrate through photolithography and ion implantation processes.

[0020] Preferably, in step two, the ions implanted by the ion implantation process include arsenic ions.

[0021] Preferably, in step three, the surface treatment process employs a wet etching process.

[0022] Preferably, in step three, the etching solution used in the wet etching process includes hot phosphoric acid.

[0023] Preferably, in step four, the source implantation process includes heavy doping implantation, and the drain implantation process includes heavy doping implantation.

[0024] Preferably, the method further includes step five: defining a silicide barrier layer, contact holes, metal interconnects, and field plates to form the electrode leads of the device.

[0025] As described above, the method for improving the reliability of laterally diffused metal-oxide semiconductors of the present invention has the following beneficial effects:

[0026] This invention effectively removes the silicon surface damage layer caused by heavy ion (e.g., arsenic ion) implantation, resulting in amorphization or lattice breakage, by introducing a specialized surface treatment process (such as hot phosphoric acid wet etching) after ion implantation in the bulk region and before source / drain implantation. This significantly reduces the interface state density on the bulk surface. This improved interface quality greatly suppresses device parameter degradation caused by the hot carrier injection (HCI) effect, increasing device reliability lifetime by more than an order of magnitude (e.g., from 0.014 years to 0.165 years). Simultaneously, this surface treatment process allows for fine-tuning of the surface morphology at the source edge (e.g., forming a smooth transition below the gate edge), helping to optimize the surface electric field distribution and reduce the peak electric field. Furthermore, this method significantly improves the safe operating area (SOA) and long-term reliability without negatively impacting key DC electrical parameters such as breakdown voltage (BV), on-resistance (Rsp), and threshold voltage, achieving a balance between high performance and high reliability. Attached Figure Description

[0027] Figure 1 The diagram shown is a schematic representation of the process flow of the method of the present invention.

[0028] Figure 2 The diagram shows a cross-sectional view of the device structure during the semiconductor substrate preparation stage in the method of the present invention.

[0029] Figure 3 The diagram shows a cross-sectional view of the device structure during the epitaxial layer formation stage in the method of the present invention.

[0030] Figure 4 The diagram shows a cross-sectional view of the device structure during the definition phase of the drift region and the well region in the method of the present invention.

[0031] Figure 5 The diagram shows a cross-sectional view of the device structure during the gate structure definition stage in the method of the present invention.

[0032] Figure 6 The diagram shows a cross-sectional view of the device structure during the body region ion implantation stage in the method of the present invention.

[0033] Figure 7 The diagram shows a cross-sectional view of the device structure during the body region surface treatment stage in the method of the present invention.

[0034] Figure 8 The diagram shown is a cross-sectional view of the device structure finally formed in the method of the present invention.

[0035] Figure 9 The diagram shows a comparison of HCI reliability data between the device prepared according to the present invention and the prior art device.

[0036] Figure 10 The diagram shows a comparison of the linear current (Idlin) characteristics of the device prepared according to the present invention and the prior art device.

[0037] Figure 11 This diagram shows a comparison of the Off-state breakdown voltage (OFFBV) characteristics of the device prepared according to the present invention and the prior art device.

[0038] Figure 12 This diagram shows a comparison of the On-state breakdown voltage (ONBV) characteristics of the device prepared according to the present invention and the prior art device. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] This application provides a method for improving the reliability of laterally diffused metal-oxide semiconductors. Figure 1 This is a schematic diagram of the process flow of the method provided in the embodiments of this application. Figures 2 to 8 This is a schematic cross-sectional view of the device structure in each step of the method provided in the embodiments of this application. Figures 9 to 12 This is a performance comparison chart between the device prepared according to the embodiments of this application and the prior art device.

[0041] Please refer to Figure 1 The method includes the following steps:

[0042] Step 1: Provide a semiconductor substrate and define drift regions and well regions on the substrate. This step provides the basic working environment for subsequent device fabrication.

[0043] In some embodiments, step one, providing a semiconductor substrate specifically includes: selecting a silicon semiconductor substrate; defining a buried layer on the surface of the silicon semiconductor substrate, the buried layer serving as a bottom isolation layer for the device; and growing an epitaxial layer on the silicon semiconductor substrate. Figure 2 As shown, a P-type semiconductor substrate 101 (PSUB) is provided, on which an N-type buried layer 102 (NBL) is defined by ion implantation. As Figure 3 As shown, a P-type epitaxial layer 103 (PEPI) is grown on a P-type semiconductor substrate 101. Subsequent steps will be performed on this P-type epitaxial layer 103. The semiconductor substrate may comprise elemental semiconductors, such as silicon (Si) or germanium (Ge); compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); or alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium arsenide phosphide indium (GaInAsP). Furthermore, the semiconductor substrate may also be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate with a strained layer. Depending on design requirements, the substrate may have P-type or N-type doping, or contain multiple regions with different doping concentrations. Epitaxial layers are typically semiconductor layers with a specific lattice orientation formed on a single-crystal substrate through epitaxial growth processes, such as p-type doped single-crystal silicon epitaxial layers. Epitaxial layer growth can be achieved through chemical vapor deposition (CVD) processes, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). The doping concentration and thickness of the epitaxial layer are adjusted according to the device's breakdown voltage requirements. Buried layers are typically formed through high-energy ion implantation to provide isolation in the vertical direction of the device and prevent latch-up effects.

[0044] In some embodiments, step one, specifically defining the drift region and the well region, includes defining a deep well, a well, and a drift region on the surface of a semiconductor substrate using photolithography and ion implantation processes. For example... Figure 4As shown, the P-type epitaxial layer 103 defines structures such as an N-type drift region 104, a P-type well 105 in the core region, an N-type well 106 in the core region, a P-type layer 108 at the bottom, a P-type buried layer 109 at the edge, and a P-type well 110 at the edge. Figure 4 The diagram also shows shallow trench isolation (STI) 107, which is typically filled with a dielectric such as silicon oxide to isolate different active regions and prevent leakage current. Additionally, the diagram schematically marks the locations 111 and 112 where the P-type heavily doped region and N-type heavily doped region will subsequently form. The photolithography process includes coating, exposure, development, and baking. In the ion implantation process, ions implanted into the N-type region can be selected from Group V elements such as phosphorus (P), arsenic (As), and antimony (Sb); ions implanted into the P-type region can be selected from Group III elements such as boron (B), boron difluoride (BF2), and indium (In). By adjusting the implantation energy and dose, the junction depth and impurity concentration distribution in each region can be precisely controlled, thereby optimizing the device's on-resistance and breakdown voltage.

[0045] In some embodiments, the method further includes forming a gate structure on the surface of a semiconductor substrate after step one and before step two. The gate structure, as a terminal controlling the on / off state of the LDMOS channel, directly affects device performance.

[0046] In some embodiments, the step of forming the gate structure includes defining a stepped oxide layer located above the drift region. For example... Figure 5 As shown, a stepped oxide layer 113 is located above the N-type drift region 104. The stepped oxide layer 113 can be formed using thermal oxidation, localized silicon oxide (LOCOS) technology, or shallow trench isolation (STI) technology. Its material can be silicon dioxide, silicon oxynitride, or other insulating dielectrics. The presence of the stepped oxide layer 113 increases the oxide layer thickness above the drift region 104, effectively reducing the electric field strength at the gate edge and improving the device's breakdown voltage through the RESURF (reduced surface electric field) effect.

[0047] In some embodiments, the step of forming the gate structure further includes defining a gate oxide layer located on the surface of the active region of the device. For example... Figure 5As shown, the gate oxide layer 114 is located on the surface of the active region and its thickness is typically smaller than that of the stepped oxide layer 113. The gate oxide layer 114 can be grown using dry oxide or wet oxide. Alternatively, the gate oxide layer 114 can also be made of a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or a combination thereof, prepared by atomic layer deposition (ALD) to reduce gate leakage current while maintaining a small equivalent oxide thickness (EOT).

[0048] In some embodiments, the step of forming the gate structure specifically includes: after forming a stepped oxide layer and a gate oxide layer, depositing polysilicon material, and defining the polysilicon gate through photolithography and etching processes. For example... Figure 5 As shown, a polysilicon gate 115 is formed on a gate oxide layer 114 and a portion of a stepped oxide layer 113. The polysilicon material can be formed by low-pressure chemical vapor deposition (LPCVD), and subsequently N-type or P-type doping can be performed by in-situ doping or subsequent ion implantation to reduce resistivity. Alternatively, the polysilicon gate 115 can be replaced by a metal gate material, including but not limited to tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), cobalt (Co), nickel (Ni), or alloys thereof, to further reduce gate resistance and eliminate the polysilicon depletion effect.

[0049] Step 2: An ion implantation process is performed in the semiconductor substrate to form a bulk region. The ion implantation process introduces a damage layer on the surface of the bulk region.

[0050] In some embodiments, in step two, the ion implantation process is performed using a gate structure as a mask to form a self-aligned bulk region. For example... Figure 6 As shown, using the polysilicon gate 115 as a hard mask, a P-body region 116 is implanted in the window in the middle of the PCD (Poly Critical Dimension) region to form a self-aligned structure. In this step, the implanted ions damage the silicon surface within the window. Using the gate and its underlying oxide layer as a hard mask ensures precise alignment between the lateral diffusion start point of the body region 116 and the gate edge, eliminating channel length fluctuations caused by photolithographic alignment errors, thereby achieving high consistency in the device's threshold voltage (Vth) and conduction characteristics.

[0051] In some embodiments, the body region can also be formed using a non-self-aligned process. Specifically, prior to ion implantation, a photoresist mask is formed on the surface of the semiconductor substrate using a photolithography process. This photoresist mask defines the implantation range of the body region 116 through its openings. In this case, the boundary of the body region 116 is defined by the sidewalls of the photoresist mask, rather than strictly by the edge of the polysilicon gate 115. While this non-self-aligned process requires consideration of photolithographic alignment errors, it allows designers to flexibly set the overlap between the body region 116 and the polysilicon gate 115 by adjusting the photolithographic pattern, thereby providing additional degrees of freedom to adjust the effective channel length and threshold voltage in addition to adjusting the ion implantation energy and angle.

[0052] In some embodiments, the laterally diffused metal-oxide semiconductor is a P-type body region laterally diffused metal-oxide semiconductor; in step one, the semiconductor substrate is a P-type semiconductor substrate, and the drift region is an N-type drift region; in step two, the body region is a P-type body region. In this configuration, the device operates in electronic conduction mode. The P-type semiconductor substrate 101 and the P-type body region 116 are typically doped with boron ions or boron difluoride ions. The N-type drift region 104 provides a drift path for electrons.

[0053] In some embodiments, the ions implanted in step two include arsenic ions. In some process integration schemes, to obtain a steeper junction profile or to accommodate other functions, heavier atomically mass arsenic ions are selected for implantation or auxiliary implantation of the P-type body region 116. Because arsenic ions have a large atomic radius, they collide violently with the silicon lattice during implantation, leading to lattice breakage, amorphization, or dislocation formation on the silicon surface, thereby forming a thick damage layer on the surface of the P-type body region 116. If this physical damage is not repaired, it will become a high-density interface state trap center, affecting carrier mobility.

[0054] Step 3: Perform a surface treatment process on the body region to remove the damaged layer. This step aims to repair the lattice damage introduced in Step 2 and restore surface quality.

[0055] In some embodiments, in step three, the surface treatment process employs a wet etching process. Wet etching utilizes a chemical solution to react with the damaged silicon surface, exhibiting high selectivity and isotropic etching characteristics, enabling uniform removal of the damaged layer without causing secondary damage to the underlying lattice.

[0056] In some embodiments, the etching solution used in step three of the wet etching process includes hot phosphoric acid. For example... Figure 7 As shown, hot phosphoric acid was used to wet-peel the surface of the exposed P-type region 116 through a window (the curved arrow in the figure indicates the chemical reaction process) to remove the surface damage layer caused by the injection. Combined with... Figure 8The device morphology comparison shown shows that in the optimized device (i.e., after hot phosphoric acid cleaning), not only are the damaged silicon layers on the surface removed and the interface states reduced, but the rinsing process also slightly changes the morphology of the device source end. For example, a smooth undercut or transition is formed below the edge of the polysilicon gate 115. This morphology change helps to change the surface electric field distribution, reduce the electric field peak, and further improve reliability.

[0057] In one specific implementation, the wafer can be rinsed using a phosphoric acid solution heated to a certain temperature. Alternatively, other chemical reagents capable of controlled removal of the silicon surface can be used as the etching solution, such as a mixture of ammonium hydroxide / hydrogen peroxide / water (SC-1), or a diluted solution of a mixture of hydrofluoric acid and nitric acid (HNA). By controlling the concentration, temperature, and processing time of the etching solution, damaged amorphous silicon layers or defect layers can be precisely stripped (e.g., removing thicknesses of several nanometers to tens of nanometers), while having minimal impact on non-P-type bulk regions (such as areas already covered by photoresist or oxide layers).

[0058] Step 4: Perform source implantation in the body region and drain implantation in the drift region.

[0059] In some embodiments, in step four, the source implantation process includes heavily doped implantation, and the drain implantation process includes heavily doped implantation. For example... Figure 8 As shown, a source region (typically containing heavily N+ and P+ doped implants) is formed within the P-type body region 116, and a drain region (containing the heavily N+ doped implanted region 120) is formed within the N-type drift region 104. Figure 8 The image also shows an N-type lightly doped drain 119 (NLDD) formed in the drift region. Heavy doping implantation typically uses large doses of arsenic or phosphorus ions (for N-type) or boron ions (for P-type) to achieve the desired degeneracy doping level. After implantation, an activation annealing process, such as rapid thermal annealing (RTA), laser annealing (LSA), or furnace tube annealing, is usually required to activate the impurities and repair the lattice.

[0060] In some embodiments, in step four, the source implantation process forms an N-type source, and the drain implantation process forms an N-type drain. As the main current ports, the high concentration of N-type doping at the source and drain ensures good ohmic contact with the subsequent metal layer, reducing contact resistance.

[0061] In some embodiments, the method further includes step five: defining a silicide barrier layer, contact holes, metal interconnects, and a field plate to form electrode leads for the device. For example... Figure 8 As shown, a silicide barrier layer 117 (SAB) and a field plate 118 (CFP) are formed on the surface of the device, and the electrode leads are realized through the contact structure.

[0062] Specifically, step five may include the following detailed process:

[0063] First, a dielectric layer is deposited on a semiconductor substrate 101. This dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, spin-coated glass (SOG), silicon fluoride glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, parylene, polyimide, and / or other suitable insulating materials. This dielectric layer can be formed by chemical vapor deposition (CVD), spin coating, sputtering, or other suitable processes. Next, a silicide barrier layer 117 (SAB) pattern is defined on the dielectric layer using photolithography and etching processes, and a selective metallization process is performed to form metal silicide layers on the exposed surfaces of the source, drain, and gate. The metal silicide layers may include titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), platinum silicide (PtSi), tungsten silicide (WSi), or other refractory metal silicides.

[0064] Subsequently, an interlayer dielectric (ILD) is deposited, which may include silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorine-doped silicon glass (FSG), carbon-doped silicon oxide (SiCOH), spin-on glass (SOG), or low-k dielectric materials (e.g., dielectric constant less than 3.9), such as porous silica, hydrosilsesquioxane (HSQ), methylsilsesquioxane (MSQ), organosilicon glass (OSG), and combinations thereof. The interlayer dielectric can be formed using suitable techniques such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), subatmospheric pressure chemical vapor deposition (SACVD), and spin-on coating.

[0065] Contact holes leading to the source, drain, and gate are formed in the interlayer dielectric layer using photolithography and anisotropic etching (such as reactive ion etching, RIE). A barrier metal layer (or adhesion layer) is deposited within the contact holes; the material is selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium-tungsten alloy (TiW), or combinations thereof. Next, a conductive metal is deposited to fill the contact holes; the conductive metal is selected from tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), cobalt (Co), or alloys thereof (such as aluminum-copper alloy AlCu, aluminum-silicon-copper alloy AlSiCu). Excess metal on the dielectric layer surface is removed using chemical mechanical planarization (CMP) or etch-back processes to form conductive plugs (e.g., tungsten plugs, W-plugs).

[0066] Next, a metal layer is deposited on top of the ILD, and the interconnect metal lines and field plate 118 structure are defined by photolithography and etching. The material for the metal interconnects can be selected from conductive materials such as aluminum (Al), copper (Cu), aluminum-copper alloy (AlCu), tungsten (W), and gold (Au). The metal layer can be formed using physical vapor deposition (PVD, such as sputtering), CVD, or electroplating processes. For copper interconnect processes, damascene or dual-damascene processes are typically used, including etching trenches in the dielectric layer, depositing a barrier layer (such as Ta / TaN) and a seed layer (such as Cu), electroplating filler copper, and CMP planarization. Figure 8 The field plate 118 (CFP) in the text is a field plate structure that can be composed of a first metal layer (Metal 1) or a polysilicon layer and extend to the surface of the dielectric layer (such as the stepped oxide layer 113 or the field oxide layer) above the drift region 104 to adjust the surface electric field distribution.

[0067] Finally, multilayer interconnect structures and passivation layers can be formed as needed to complete the electrode lead-out and protection of the device. The multilayer interconnect structure includes alternating stacked inter-metal dielectric (IMD) layers and metal interconnect layers, with vertical connections between the metal layers achieved through vias. The passivation layer protects the device from external moisture, ions, and mechanical damage. Its materials typically include silicon oxide, silicon nitride (Si3N4), silicon oxynitride, silicon phosphosilicate glass (PSG), polyimide, benzocyclobutene (BCB), or combinations thereof. The passivation layer can consist of a single material layer or a multilayer stacked structure (such as a silicon oxide / silicon nitride composite layer) and is formed using CVD or spin-coating processes. Pad windows are created on the passivation layer to expose the top layer metal for wire bonding or flip-chip packaging.

[0068] Please refer to Figure 9This figure illustrates comparative data on the hot carrier injection (HCI) reliability of the P-type body region SNLDMOS device fabricated according to embodiments of this application and a control device without hot phosphoric acid rinsing. The horizontal axis represents the stress test time (Time), in hours (H); the vertical axis represents the percentage of linear leakage current shift (% Idlin shift). As shown in the figure, the control device without hot phosphoric acid rinsing (the curve corresponds to the blue circular data points in the figure) exhibits a faster linear current decay trend, and the fitting formula for its degradation curve is: goodness of fit The value is 0.9974. In contrast, the device using the hot phosphoric acid rinsing process provided in the embodiments of this application (the curve corresponds to the orange square data point in the figure) exhibits a significantly slower linear current decay trend, and the fitting formula for its degradation curve is: goodness of fit The value is 0.9913. By comparing the intercepts and slopes of the two curves, it can be seen that under the same stress time, the current drift of the device after removing the surface damage layer through hot phosphoric acid treatment is significantly reduced, indicating that the device's resistance to hot carrier aging is enhanced. Based on industry-standard lifetime calculation criteria (e.g., using 10% Idlin degradation as the failure criterion), and combined with the data in the figure, the lifetime of the device without hot phosphoric acid rinsing is approximately 0.014 years, while the lifetime of the device with hot phosphoric acid rinsing is significantly increased to 0.165 years. This confirms that the method of the embodiments of this application effectively reduces interface states by repairing surface damage in the repair area, thereby improving the reliability lifetime of the device by more than an order of magnitude.

[0069] Please refer to Figures 10 to 12 The embodiments of this application improve reliability without negatively affecting the DC electrical properties of the device. Figure 10 The Idlin comparison curves are shown, with the horizontal axis representing the gate voltage VG (V) and the vertical axis representing the leakage current ID (A). As shown in the figure, the Idlin-VG curves with and without phosphoric acid rinsing (blue curve) basically overlap across the entire voltage range, indicating that parameters such as threshold voltage and transconductance have not drifted. Figure 11 The figure shows a comparison curve of the Off-state breakdown voltage (OFFBV), with the horizontal axis representing the leakage voltage VD (V) and the vertical axis representing the leakage current ID (A). As shown in the figure, the leakage current level and breakdown voltage value of the two curves are highly consistent before the breakdown point (around 42V). Figure 12 The on-state breakdown voltage (ONBV) comparison curves are shown, which also demonstrate that the breakdown voltage characteristics (breakdown occurs around 37V) of the devices with and without phosphoric acid rinsing are basically the same in the on-state. In summary, Figures 10 to 12The data confirms that the method of this application has successfully improved the SOA and long-term reliability of the device without sacrificing DC performance indicators such as BV and Rsp.

[0070] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the reliability of laterally diffused metal-oxide-semiconductor, characterized in that, At least including: Step 1: Provide a semiconductor substrate, and define a drift region and a well region on the semiconductor substrate; Step 2: An ion implantation process is performed in the semiconductor substrate to form a bulk region. The ion implantation process introduces a damage layer on the surface of the bulk region. Step 3: Perform a surface treatment process on the surface of the body region to remove the damaged layer; Step 4: Perform source implantation in the body region and drain implantation in the drift region.

2. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: The laterally diffused metal-oxide semiconductor is a P-type bulk region laterally diffused metal-oxide semiconductor; in step one, the semiconductor substrate is a P-type semiconductor substrate, and the drift region is an N-type drift region; In step two, the body region is a P-type body region; in step four, the source implantation process forms an N-type source, and the drain implantation process forms an N-type drain.

3. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: The method further includes the step of forming a gate structure on the surface of the semiconductor substrate after step one and before step two.

4. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 3, characterized in that: In step two, the ion implantation process is performed using the gate structure as a mask to form the self-aligned body region.

5. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 3, characterized in that: The step of forming the gate structure includes defining a stepped oxide layer located above the drift region.

6. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 5, characterized in that: The step of forming the gate structure further includes defining a gate oxide layer located on the surface of the active region of the device.

7. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 6, characterized in that: The steps for forming the gate structure specifically include: after forming the stepped oxide layer and the gate oxide layer, depositing polysilicon material, and defining the polysilicon gate through photolithography and etching processes.

8. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: In step one, providing a semiconductor substrate specifically includes: selecting a silicon semiconductor substrate; defining a buried layer on the surface of the silicon semiconductor substrate, the buried layer serving as a bottom isolation layer for the device; and growing an epitaxial layer on the silicon semiconductor substrate.

9. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: In step one, the definition of the drift region and the well region specifically includes: defining deep wells, wells, and drift regions on the surface of the semiconductor substrate through photolithography and ion implantation processes.

10. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 2, characterized in that: In step two, the ions implanted by the ion implantation process include arsenic ions.

11. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: In step three, the surface treatment process employs a wet etching process.

12. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 11, characterized in that: In step three, the etching solution used in the wet etching process includes hot phosphoric acid.

13. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: In step four, the source implantation process includes heavy doping implantation, and the drain implantation process includes heavy doping implantation.

14. The method for improving the reliability of laterally diffused metal-oxide-semiconductor according to claim 1, characterized in that: The method also includes step five, defining a silicide barrier layer, contact holes, metal interconnects, and field plates to form the electrode leads of the device.

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