Gallium nitride epitaxial structure formation method and semiconductor device

Abstract

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for forming gallium nitride epitaxial structures and semiconductor devices. Background Technology

[0002] Against the backdrop of rapid advancements in semiconductor technology, enhancement-mode gallium nitride (GNU) devices have become a research hotspot in the field of power electronics due to their electrical performance and application prospects. Currently, most mainstream GNU devices on the market employ a P-type gate structure, with the P-type doping concentration in the epitaxial layer typically maintained within a certain range to form a Schottky contact gate electrode structure. However, this structure suffers from a low gate breakdown voltage when facing high gate voltage applications. The nominal maximum gate operating voltage of most devices is only 7V, and the actual operating voltage is often lower than 6V, making it difficult to meet the higher operating voltage requirements of devices with large gate threshold voltage drift, thus limiting the stability and anti-interference capability of the driving circuit.

[0003] To address these challenges, the research and industry communities have made numerous efforts. One technical solution involves stacking an n-type GaN layer on p-type gallium nitride (PGaN), using a PN junction to replace the traditional Schottky junction to improve gate breakdown voltage. However, in actual MOCVD epitaxial growth, this method is affected by the Mg memory effect, requiring extremely high concentrations of Si or Ge doping to form n-type GaN, which in turn leads to threshold voltage drift due to excessive impurities. Another approach is to deposit p-type SnO and n-type SnO2 layers on the barrier layer to enhance gate breakdown voltage. However, SnO is not a standard CMOS process material and is incompatible with the CMOS-compatible processes widely used in current GaN on Si devices, limiting its application in large-scale production.

[0004] Furthermore, some researchers have attempted to maintain a high concentration of PGaN doping above the AlGaN layer during MOCVD epitaxial growth, and then reduce the Mg doping concentration when the surface PGaN layer is grown, in order to balance the threshold voltage and gate breakdown voltage. However, the memory effect of Mg makes this method difficult to implement, because even if the Mg source supply is stopped or reduced, the Mg remaining in the reaction chamber and pipeline will still diffuse to subsequent epitaxial layers at high temperatures, affecting material properties. On the other hand, using Si for n-type doping compensation requires extremely high concentrations due to the Mg memory effect, increasing process complexity and cost. Therefore, developing a novel gallium nitride epitaxial structure and growth method that can effectively improve the gate breakdown voltage, maintain the stability of the device threshold voltage, and is compatible with existing CMOS processes is an urgent problem to be solved in the current semiconductor device field. Summary of the Invention

[0005] The purpose of this application is to provide a novel gallium nitride epitaxial structure, its growth method, and a semiconductor device, which effectively improves the gate breakdown voltage while maintaining the stability of the device threshold voltage and on-resistance, and the process is compatible with standard CMOS processes. This objective is achieved through the following technical solution: the method for forming the gallium nitride epitaxial structure of this application includes:

[0006] A substrate is provided, on which a buffer layer, an intrinsic GaN layer, and an AlGaN layer are grown;

[0007] A GaN epitaxial layer comprising p-type doped atoms is grown on the AlGaN layer, with the doping concentration controlled at 1.5E. 19 cm -3 -3E 19 cm -3 Within the specified range, the thickness is controlled within the range of 70nm-110nm;

[0008] N-type ion implantation was performed on the GaN epitaxial layer including P-type doped atoms, with the implantation depth controlled within the range of 20nm-30nm;

[0009] After ion implantation is completed, annealing is performed;

[0010] In the ion implantation step, the amount of implanted N-type ions is controlled so that the implanted portion remains P-type doped after annealing, with the doping concentration controlled at 5E. 17 cm -3 -1E 19 cm -3 Within the range.

[0011] In one embodiment, the P-type dopant atom is Mg, and the concentration of Mg precursor gas is gradually reduced during the formation of the GaN epitaxial layer including the P-type dopant atom.

[0012] In one embodiment, ion implantation is performed using three or more different implantation energies and implantation doses, with the implantation energy and implantation dose gradient decreasing.

[0013] This application further provides another method for forming gallium nitride epitaxial structures, including:

[0014] A substrate is provided, on which a buffer layer, an intrinsic GaN layer, and an AlGaN layer are grown;

[0015] P-type ion implantation is performed on the AlGaN layer to form an asymmetric P-type doped region in the AlGaN layer;

[0016] A GaN epitaxial layer including P-type doped atoms is grown on the AlGaN layer in which an asymmetric P-type doped region is formed, and N-type ion implantation is performed on the GaN epitaxial layer including P-type doped atoms.

[0017] After N-type ion implantation is completed, annealing is performed;

[0018] In the N-type ion implantation step, the amount of implanted N-type ions is controlled so that the implanted part remains P-type doped after annealing.

[0019] In one embodiment, the P-type doped region is in the shape of an inverted triangle.

[0020] In one embodiment, the width of the P-type doped region first increases and then decreases in the horizontal direction.

[0021] This application further provides a semiconductor device formed on the aforementioned gallium nitride epitaxial structure, comprising:

[0022] Substrate;

[0023] Buffer layer;

[0024] A channel layer is formed on the buffer layer;

[0025] A barrier layer is formed on the channel layer;

[0026] A contact layer is formed on the barrier layer; a source electrode, a drain electrode, and a gate electrode are formed on the contact layer, and the source electrode and the drain electrode extend into the channel layer or the buffer layer;

[0027] The contact layer is obtained by patterning the P-type GaN layer in the gallium nitride epitaxial structure.

[0028] In one embodiment, a passivation layer is also included, which is formed on the sidewalls of the contact layer and the exposed barrier layer surface.

[0029] This application further provides a semiconductor device formed on the aforementioned gallium nitride epitaxial structure, comprising:

[0030] Substrate;

[0031] Buffer layer;

[0032] A channel layer is formed on the buffer layer;

[0033] A barrier layer is formed on the channel layer;

[0034] A contact layer is formed on the barrier layer; a source electrode, a drain electrode, and a gate electrode are formed on the contact layer, and the source electrode and the drain electrode extend into the channel layer or the buffer layer;

[0035] The contact layer is obtained by patterning the P-type GaN layer in the gallium nitride epitaxial structure, and the barrier layer has a P-type doped region with the highest doping concentration or the largest doped area at the position corresponding to the contact layer.

[0036] In one embodiment, the barrier layer further includes etched trenches surrounding the contact layer, the width of which is in the range of 5-200 nm.

[0037] Compared with the prior art, this application has the following beneficial effects:

[0038] This application achieves this by growing AlGaN layers of specific thickness (70nm-110nm) and doping concentration (1.5E). 19 cm -3 -3E 19 cm -3 A p-type GaN epitaxial layer is constructed, followed by controlled N-type ion implantation, which enables it to withstand higher reverse bias voltages. By controlling the dose of implanted N-type ions, the implanted region retains p-type conductivity after annealing (doping concentration 5E). 17 cm -3 - 1E 19 cm -3 This method increases the gate breakdown voltage. Precisely controlled N-type ion implantation into the P-type GaN epitaxial layer, combined with annealing, can repair some lattice defects, helping to stabilize the device's threshold voltage. Simultaneously, this method avoids excessive damage to the two-dimensional electron gas (2DEG) channel, which helps maintain low on-resistance, high electron mobility, and results in low resistance and high efficiency.

[0039] The ion implantation technology employed in this application is a mature technology in standard CMOS processes, making the entire fabrication process compatible with the CMOS-compatible processes widely used in existing silicon-based GaN devices, thus avoiding integration barriers caused by the introduction of non-standard CMOS materials such as SnO. Gradually reducing the Mg precursor gas concentration during the growth of the p-type GaN epitaxial layer helps alleviate the memory effect of Mg and improve interface quality. In addition, gradient ion implantation using various implantation energies and doses can form a more gradual doping concentration distribution and optimize carrier transport characteristics.

[0040] In another implementation, an asymmetric P-type doped region (e.g., an inverted triangular shape or a region whose width initially increases and then decreases) is formed by P-type ion implantation into the AlGaN layer. A P-type doped region with the highest doping concentration or largest doped area is then formed at the corresponding position in the barrier layer corresponding to the contact layer. This modulates the electric field distribution at the gate edge, alleviates electric field concentration, and further improves the long-term reliability of the device. The etching trenches surrounding the contact layer in the barrier layer, combined with the passivation layer formed on the sidewalls of the contact layer and the surface of the barrier layer, effectively suppress charge movement from the barrier layer and sidewall defects generated during etching, reducing leakage current and charge transfer to the gate, thereby improving the stability and reliability of the threshold voltage. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of GaN-based semiconductor devices in the prior art;

[0042] Figure 2 This is a flowchart illustrating a method for forming a gallium nitride epitaxial structure in one embodiment of this application;

[0043] Figure 3 This is a flowchart illustrating a method for forming a gallium nitride epitaxial structure in another embodiment of this application;

[0044] Figure 4 This is a schematic diagram of the gallium nitride epitaxial structure obtained by the method for forming a gallium nitride epitaxial structure in one embodiment of this application;

[0045] Figure 5 This is a schematic diagram of the gallium nitride epitaxial structure obtained by the method for forming a gallium nitride epitaxial structure in another embodiment of this application;

[0046] Figure 6 This is a schematic diagram of the structure of a semiconductor device in one embodiment of this application;

[0047] Figure 7 This is a schematic diagram of the structure of a semiconductor device in another embodiment of this application;

[0048] Figure 8 This is a top view schematic diagram of a gallium nitride epitaxial structure obtained by a gallium nitride epitaxial structure formation method in another embodiment of this application.

[0049] Explanation of reference numerals in the attached figures: 100, substrate; 200, buffer layer; 300, channel layer; 310, intrinsic GaN layer; 400, barrier layer; 410, AlGaN layer; 420, P-type doped region; 500, contact layer; 510, P-type GaN layer; 511, first P-type GaN sublayer; 512, second P-type GaN sublayer; 610, source electrode; 620, drain electrode; 630, gate electrode. Detailed Implementation

[0050] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0051] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0052] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0053] Gallium nitride (GaN), a wide-bandgap semiconductor material, exhibits promising applications in power electronics, high-frequency communications, and radio frequency devices due to its high electron mobility, high breakdown electric field, and excellent thermal stability. Especially in enhancement-mode gallium nitride devices, please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the structure of a GaN-based semiconductor device in the prior art, including a substrate 100, a buffer layer 200, a channel layer 300, a barrier layer 400, a contact layer 500, a source electrode 610, a drain electrode 620, and a gate electrode 630. The P-type gate structure, as a key component, directly affects the reliability and efficiency of the device. However, traditional P-type gallium nitride epitaxial layers often face the challenge of Mg doping memory effect during fabrication. Typically, the contact layer is a single-layer structure formed epitaxially, making it difficult to precisely control the surface doping concentration, thus limiting the improvement of the gate breakdown voltage. To solve this problem, this application proposes a novel gallium nitride epitaxial structure and its growth method. Through layered doping design, especially reducing the doping concentration of the surface P-type GaN, the gate breakdown voltage is effectively improved while maintaining the stability of the device's threshold voltage and on-resistance. The following will describe in detail the growth method, structure, and application of this gallium nitride epitaxial structure in semiconductor devices. Please refer to... Figure 2 This application provides a method for forming a gallium nitride epitaxial structure, characterized by comprising: providing a substrate 100; growing a buffer layer 200, an intrinsic GaN layer 310, and an AlGaN layer 410 on the substrate 100; and growing a GaN epitaxial layer including p-type doped atoms on the AlGaN layer 410, wherein the doping concentration is controlled at 1.5E. 19 cm -3 -3E 19 cm -3 Within a specified range, with the thickness controlled between 70nm and 110nm, N-type ion implantation is performed on the GaN epitaxial layer including P-type doped atoms. The implantation depth is controlled between 20nm and 30nm. After ion implantation, annealing is performed. During the ion implantation step, the amount of implanted N-type ions is controlled so that the ion-implanted portion remains P-type doped after annealing, and the doping concentration is controlled at 5E. 17 cm -3 -1E 19 cm -3 Within the range.

[0054] In the specific implementation method, a suitable substrate 100 material, such as silicon, is first provided. A buffer layer 200, an intrinsic GaN layer 310 (uGaN layer), and an AlGaN layer 410 are sequentially grown on the substrate 100 using metal-organic chemical vapor deposition (MOCVD) technology. The buffer layer 200 is used to alleviate the lattice mismatch between the substrate 100 and the epitaxial layer. The intrinsic GaN layer 310 can serve as the channel layer 300 of the HEMT device, and the AlGaN layer 410 serves as the barrier layer 400 of the device.

[0055] A GaN epitaxial layer containing p-type doped atoms (such as Mg) was grown on an AlGaN layer 410 using MOCVD technology. The doping concentration of this layer was controlled at 1.5E. 19 cm -3 -3E 19 cm -3 Within the specified range, the thickness is controlled within the range of 70nm-110nm.

[0056] N-type ions (such as Si ions) are implanted into the grown GaN epitaxial layer containing P-type doped atoms. By precisely controlling the parameters of the ion implantation equipment, the implantation depth is controlled within the range of 20nm-30nm, thereby adjusting the concentration of P-type doping on the surface layer.

[0057] After ion implantation, the sample is annealed in a high-temperature environment. Annealing activates the implanted ions, allowing them to occupy suitable positions in the crystal lattice and exert their intended doping effect. It also repairs lattice damage caused by ion implantation, restoring the integrity of the material's crystal structure. During the ion implantation step, the amount of implanted N-type ions is carefully controlled. After annealing, the ion-implanted portion retains its P-type doping characteristics, with the doping concentration controlled at 5E. 17 cm -3 -1E 19 cm -3 Within the range.

[0058] In traditional methods for growing Mg-containing P-type GaN layers (510) via MOCVD, Mg exhibits a memory effect. Even after the Mg-containing P-nitride layer is grown, and the flow rate of the Mg-containing organometallic source gas is reduced or shut off, a significant amount of Mg remains in the reaction chamber and reaction pipes. This residual Mg diffuses into the next epitaxial layer due to high temperatures during subsequent epitaxial layer growth, affecting material properties. Our proposed method, however, first grows a complete P-type doped GaN layer via MOCVD, then uses ion implantation to implant Si ions for compensatory doping. This effectively avoids the adverse effects of the Mg memory effect on material properties, ensuring the stability and consistency of the epitaxial layer quality.

[0059] Ion implantation technology offers high precision, allowing for easy control of implantation energy and dosage. By precisely adjusting these parameters, the thickness of the first layer (the ion-implanted portion) and the compensated doping concentration can be accurately controlled. This enables customized design of the doping distribution of the p-type GaN layer 510 according to the specific performance requirements of the device, thereby optimizing the device's electrical performance, such as improving gate withstand voltage and reducing on-resistance. Ion implantation is a standard process in CMOS. This application utilizes ion implantation technology for doping adjustment, which is perfectly compatible with the current mainstream GaN on Si process. This means that gallium nitride epitaxial structure growth and device fabrication can be achieved on existing semiconductor manufacturing lines without large-scale equipment modifications, significantly improving device performance while reducing production costs.

[0060] Unlike some existing technologies, this method strictly controls the concentration of Si ions during ion implantation, so that the ion-implanted part still retains the P-type doping characteristics after annealing. This characteristic is crucial for maintaining the normal operation of the device, ensuring that the device has a high gate withstand voltage and that its basic electrical functions, such as threshold voltage and conduction characteristics, are not affected by changes in doping type.

[0061] After MOCVD growth, Mg activation is required, typically achieved through high-temperature annealing. In this application, the annealing process used for Mg activation in the original process not only activates the implanted Si ions but also simultaneously repairs the lattice damage caused by Si ion implantation. Repairing lattice damage helps restore the electrical and mechanical properties of the material, improves device reliability and stability, and extends device lifespan.

[0062] In the gallium nitride epitaxial structure growth method of this application, metal-organic chemical vapor deposition (MOCVD) thin film growth technology is employed. Specifically, firstly, using an MOCVD device, a high-quality buffer layer 200 is grown on the surface of a substrate 100 by controlling parameters such as the flow rate, temperature, and pressure of the metal-organic source, nitrogen source, and carrier gas. This buffer layer 200 effectively alleviates lattice mismatch and thermal mismatch between the substrate 100 and subsequent epitaxial layers. Next, using MOCVD technology, an intrinsic GaN layer 310 (u-GaN layer) is grown on the buffer layer 200. By optimizing the growth parameters, the intrinsic GaN layer 310 is ensured to have high crystal integrity and low defect density, providing a pure GaN material basis for the device. Subsequently, in the same MOCVD system, an AlGaN layer 410 is grown on the intrinsic GaN layer 310. By controlling the ratio of Al source to Ga source, the Al composition in the AlGaN layer 410 is controlled, thereby obtaining a barrier layer 400 with a specific band structure. Finally, a GaN epitaxial layer containing P-type doped atoms (such as Mg) is grown on the AlGaN layer 410. During the growth process, the flow rate of the Mg source and the growth temperature are controlled to keep the P-type doping concentration within the required range.

[0063] MOCVD technology offers high precision in material growth control, enabling atomic-level control over the thickness, composition, and doping concentration of epitaxial layers. Buffer layers 200, intrinsic GaN layers 310, AlGaN layers 410, and p-type doped GaN epitaxial layers grown using this technology exhibit high crystal integrity and uniformity, low defect density, and effectively reduce leakage current and scattering effects in devices, thereby improving carrier mobility and conductivity. Accurate p-type doping concentration is crucial for forming a good p-type conductive region, directly affecting device performance such as threshold voltage and gate breakdown voltage. MOCVD technology can control the p-type doping concentration to within 1.5E. 19 cm -3 -3E 19 cm -3 Within the range (during the initial growth stage), it avoids the device performance degradation caused by uneven doping concentration or deviation from the design value.

[0064] The high-quality surface smoothness and crystal structure of the epitaxial layers grown by MOCVD provide a solid foundation for subsequent processes such as ion implantation, photolithography, and etching. For example, during N-type ion implantation, the high-quality epitaxial layer surface reduces scattering and damage during the ion implantation process, improving the accuracy and uniformity of ion implantation. In photolithography and etching processes, the smooth surface and clear crystal structure help to obtain high-precision pattern transfer and etching contours.

[0065] In the gallium nitride epitaxial structure growth method of this application, magnesium (Mg) is selected as the p-type dopant atom. When forming a GaN epitaxial layer containing p-type dopant atoms using metal-organic chemical vapor deposition (MOCVD) technology, the concentration of Mg precursor gas is gradually reduced throughout the GaN epitaxial layer growth process.

[0066] In the gallium nitride epitaxial structure growth and doping control process of this application, the ion implantation stage has been further optimized. Specifically, three or more different combinations of implantation energy and implantation dose are used to perform ion implantation operations on the target region, and the implantation energy and implantation dose exhibit a gradient decrease. That is, the first ion implantation uses a relatively high implantation energy and implantation dose, and the energy and dose of subsequent ion implantations decrease sequentially. Through this gradual decrease, multi-level control of the doping concentration of the 510 surface layer of the p-type GaN layer is achieved.

[0067] Traditional single-energy and single-dose ion implantation methods can only create a relatively singular doped region in the material, making it difficult to achieve complex doping concentration distributions. However, by using three or more different implantation energies and doses with decreasing gradients, multiple regions with varying depths and doping concentrations can be formed on the surface of the p-type GaN 510 layer. High-energy ion implantation allows ions to penetrate deeper regions, while high-dose implantation creates a high doping concentration in those regions. As the implantation energy and dose gradually decrease, subsequent implanted ions can only remain in shallower regions, and the doping concentration decreases accordingly. The doping concentration distribution can be designed at the microscale. In regions requiring high electric field strength, shallow layers with high doping concentrations can be formed to enhance carrier injection and transport; while in regions requiring a more uniform electric field distribution, a smooth transition of the electric field can be achieved by adjusting the doped regions with different depths and concentrations.

[0068] In ion implantation, the uniformity of implantation energy and dose is crucial for consistent device performance. Employing multiple combinations of implantation energies and doses with decreasing gradients allows for the comprehensive consideration of factors such as ion beam scattering and implantation depth inhomogeneity. Through multiple implantations and the cumulative effect, the uniformity of the entire implanted region is improved. The diffusion and distribution of ion beams with different energies and doses within the material complement each other, resulting in a more uniform doped region in terms of depth and concentration. This is particularly important for mass-produced gallium nitride (GaN) devices, ensuring similar performance parameters across different batches, improving yield and reliability, and reducing production costs.

[0069] Ion implantation is performed on the entire surface of a GaN epitaxial layer containing P-type doped atoms. The GaN epitaxial layer containing P-type doped atoms is placed in the vacuum chamber of an ion implantation device. The required N-type ions (such as silicon (Si) ions) are generated by precisely controlling the ion source. An ion beam focusing and scanning system is used to uniformly cover the entire surface of the GaN epitaxial layer, ensuring that ion implantation is performed in every micro-region of the surface according to predetermined parameters. Ion implantation of the entire surface guarantees a high degree of uniformity in the distribution of doped atoms on the GaN epitaxial layer surface. This process eliminates the need for a mask and facilitates uniform ion activation and lattice repair during annealing, reducing stress concentration and defect formation caused by localized inhomogeneities. For P-type doped GaN epitaxial layers, implanting N-type ions (such as Si ions) can perform compensatory doping, reducing the surface P-type doping concentration. Precise control can meet the specific surface electrical performance requirements of different types of gallium nitride devices. In enhancement-mode gallium nitride high electron mobility transistors (HEMTs), the threshold voltage of the device can be optimized by controlling the surface P-type doping concentration.

[0070] Please refer to further information. Figure 3 , Figure 3 This is a flowchart illustrating a method for forming a gallium nitride epitaxial structure in another embodiment of this application. The method for forming a gallium nitride epitaxial structure in this embodiment includes: providing a substrate 100; growing a buffer layer 200, an intrinsic GaN layer 310, and an AlGaN layer 410 on the substrate 100; performing P-type ion implantation on the AlGaN layer 410; forming an asymmetric P-type doped region 420 in the AlGaN layer 410; growing a GaN epitaxial layer including P-type doped atoms on the AlGaN layer 410 with the asymmetric P-type doped region 420; performing N-type ion implantation on the GaN epitaxial layer including P-type doped atoms; and annealing after completing the N-type ion implantation. In the N-type ion implantation step, the amount of implanted N-type ions is controlled so that the ion-implanted portion remains P-type doped after annealing.

[0071] In this embodiment, the method for forming a gallium nitride epitaxial structure achieves synergistic optimization of the device's electrical performance, particularly gate breakdown voltage and threshold voltage stability, by introducing an asymmetric P-type doped region 420 and combining it with subsequent N-type ion implantation compensation. Asymmetry refers to differences in location or implantation shape; specifically, it could mean different distribution positions or different doping widths on both sides of the gate.

[0072] First, after the growth of the buffer layer 200, intrinsic GaN layer 310, and AlGaN barrier layer 400 on the substrate 100, P-type ion implantation is performed on the AlGaN layer 410 to form an asymmetric P-type doped region 420. The shape of this asymmetric doped region can be designed as an inverted triangle or a pattern where the width first increases and then decreases in the horizontal direction. The asymmetric geometric distribution can modulate the lateral electric field distribution in the AlGaN barrier layer 400, allowing the high electric field region at the gate edge to flatten out, thereby mitigating the electric field concentration effect. In one specific embodiment, different concentrations of doping are applied at different heights, and lateral diffusion during annealing forms a shape similar to an inverted triangle. Optimization of the electric field distribution helps improve the breakdown voltage of the device, enabling it to withstand higher operating voltages. Magnesium (Mg) can be selected as the P-type dopant, a commonly used P-type dopant in GaN materials, which generates acceptor levels at group III element sites.

[0073] Secondly, on the AlGaN layer 410 where the asymmetric P-type doped region 420 has been formed, a GaN epitaxial layer containing P-type doped atoms is grown, followed by N-type ion implantation into this P-type GaN epitaxial layer. In the N-type ion implantation step, the dosage of implanted ions needs to be precisely controlled so that the net doping concentration of the implanted region retains its P-type characteristics after subsequent annealing. For example, silicon (Si) ions can be implanted as the N-type dopant. The diffusion behavior of Si in GaN is closely related to the material's microstructure, and its diffusion coefficient is relatively low in the temperature range of 600-900℃, which is beneficial for controlling the doping concentration in the implanted region. Compensatory doping of the P-type GaN can form a P-type region with a lower net doping concentration in the surface region near the gate metal contact, helping to reduce the maximum electric field strength at the gate metal-P-type GaN interface, thereby delaying impact ionization and avalanche breakdown caused by high electric fields and further improving the gate's breakdown voltage. Meanwhile, the uncompensated P-type GaN at the bottom layer and the P-type doped region 420 in the AlGaN layer 410 together ensure that the device has a sufficiently high threshold voltage.

[0074] After N-type ion implantation, annealing is performed. Annealing is crucial for activating the implanted ions and repairing lattice damage caused by the ion implantation process. For example, annealing at 700°C effectively reduces defects in GaN materials and improves their electrical properties. Through annealing, the implanted N-type impurities (such as Si) are activated, occupying lattice sites and acting as donors; simultaneously, the Mg acceptors originally present in P-type GaN are further activated. More importantly, the annealing process helps repair lattice disorder caused by ion implantation and reduces trap centers.

[0075] By first constructing an asymmetric P-type doped region 420 in the AlGaN barrier layer 400 to optimize the lateral electric field distribution, then using controlled N-type ion implantation in the P-type GaN epitaxial layer for precise compensation doping to reduce the surface electric field and maintain P-type conductivity, and finally achieving ion activation and lattice repair through an annealing process.

[0076] In a further embodiment, the P-type doped region 420 is shaped like an inverted triangle. In this embodiment, the inverted triangle shape of the P-type doped region 420 implies a gradual lateral extension of the doped region in the vertical direction, typically showing a gradual narrowing of its horizontal width from the surface of the AlGaN layer 410 downwards. This geometry can modulate the electric field distribution within the device. Specifically, in high-voltage applications, semiconductor device breakdown is often caused by electric field concentration at the gate edge. By introducing the inverted triangle P-type doped region 420, the gradient change in its doping concentration and geometric profile can guide the redistribution of electric field lines throughout the bulk, preventing excessive electric field concentration at specific points, thereby helping to improve the device's breakdown voltage. This region can be achieved by implanting magnesium (Mg) ions as P-type dopant atoms.

[0077] Furthermore, the width of the P-type doped region 420 is configured to first increase and then decrease in the horizontal direction. This width modulation results in the P-type doped region 420 exhibiting an asymmetric spindle-shaped or elliptical lateral profile within the AlGaN layer 410, increasing the lateral coverage of the P-type doped region 420 at a specific depth. This allows for more effective modulation of the two-dimensional electron gas distribution in the underlying channel and simultaneously smooths both the longitudinal and lateral components of the electric field. The horizontally increasing-then-decreasing width design, combined with the inverted triangular longitudinal shape, forms a smoother doping transition region in three-dimensional space, which helps to further suppress peak electric fields and improve the long-term reliability of the device. In a further embodiment, the depth of the P-type doped region 420 gradually increases towards the gate.

[0078] Furthermore, the spacing width of the P-type doped regions 420 is designed to decrease first and then increase. When multiple such P-type doped regions 420 are arranged periodically or in an array within the active region of the device, the spacing between adjacent doped regions (i.e., the spacing width) is not constant. The arrangement of the spacing width decreasing first and then increasing means that the P-type doped regions 420 exhibit a periodic structure with alternating dense and sparse areas in the horizontal direction. This arrangement can introduce an additional dimension of electric field modulation, providing a more continuous electric field buffer in regions requiring strong electric field suppression through smaller spacing (denser arrangement), while maintaining a lower specific on-resistance in other regions through larger spacing (sparser arrangement), providing a means of regulation to achieve a balance between increasing breakdown voltage and maintaining good conduction characteristics.

[0079] Furthermore, grooves may be included between the P-type doped regions 420, with the groove depth initially increasing and then decreasing relative to the AlGaN layer 410 thickness. This groove structure is typically formed in the barrier layer 400 between the P-type doped regions 420 via an etching process. The initial increase followed by a decrease in groove depth, combined with the specific distribution of the P-type doped regions 420, allows them to form a composite termination structure in three-dimensional space. The introduction of grooves can locally modulate the two-dimensional electron gas in the channel below, and the change in depth makes this modulation gradual in the horizontal direction, optimizing the electric field distribution of the device in the off-state, particularly effective in mitigating electric field concentration at the drain edge. The groove width design, for example, controlling it within the range of 5nm-200nm, combined with the depth variation, allows for precise control of the electric field distribution profile.

[0080] Please refer to further information. Figure 4 , Figure 4 The image below is a schematic diagram of a gallium nitride epitaxial structure obtained by a method for forming a gallium nitride epitaxial structure in one embodiment of this application. The gallium nitride epitaxial structure includes a substrate 100, a buffer layer 200, an intrinsic GaN layer 310, an AlGaN layer 410, and a p-type GaN layer 510.

[0081] The P-type GaN layer 510 includes a first P-type GaN sublayer 511 and a second P-type GaN sublayer 512, wherein the first P-type GaN sublayer 511 is formed on the AlGaN layer 410.

[0082] The first P-type GaN sublayer 511 includes P-type doped atoms, and the second P-type GaN sublayer 512 includes both P-type and N-type doped atoms;

[0083] The doping concentration of the first P-type GaN sublayer 511 is 1.5E. 19 cm -3 -3E 19 cm -3Within the range, the doping concentration of the second P-type GaN sublayer 512 is 5E. 17 cm -3 -1E 19 cm -3 Within the specified range, the thickness of the first P-type GaN sublayer 511 is in the range of 50nm-80nm, and the thickness of the second P-type GaN sublayer 512 is in the range of 20nm-30nm.

[0084] The gallium nitride epitaxial structure is a multilayer structure, comprising, from bottom to top: a substrate 100, a buffer layer 200, an intrinsic GaN layer 310, an AlGaN layer 410, and a p-type GaN layer 510. The p-type GaN layer 510 is further subdivided into a first p-type GaN sublayer 511 and a second p-type GaN sublayer 512, with differences in doping characteristics and thickness. The first p-type GaN sublayer 511 is in direct contact with the AlGaN layer 410. As part of the p-type GaN layer 510, it is doped with a high concentration of p-type dopant atoms (such as Mg), with the doping concentration controlled at 1.5E. 19 cm -3 To 3E 19 cm -3 Within the range, ensure good electrical contact and carrier transport performance with AlGaN layer 410.

[0085] The second p-type GaN sublayer 512 is located above the first p-type GaN sublayer 511. This layer contains not only p-type doped atoms but also n-type doped atoms (such as Si). By adjusting the ratio of the two, the doping concentration can be reduced, ranging from 5E. 17 cm -3 To 1E 19 cm -3 In this process, device performance is optimized by reducing the doping concentration of the surface P-type GaN sublayer. Simultaneously, the thickness is controlled within the range of 20nm to 30nm.

[0086] In traditional MOCVD growth, the memory effect of Mg doping often leads to unstable control over the surface doping concentration. This application addresses this issue through a layered doping design, specifically by first completing the MOCVD growth of the entire P-type GaN layer (510) and then performing N-type ion implantation compensation doping on the surface. This reduces the doping concentration of the surface P-type GaN sublayer, enhancing the maximum breakdown electric field at the interface and thus raising the gate breakdown voltage of the P-type gate to a higher level. While the doping concentration of the surface P-type GaN sublayer is reduced, the underlying P-type GaN sublayer maintains a high doping concentration, ensuring excellent threshold voltage characteristics and low on-resistance. This allows the device to improve its breakdown voltage without sacrificing its fundamental electrical performance. Furthermore, the ion implantation Si technology used in this application is compatible with standard CMOS processes, simplifying the manufacturing process and reducing production costs.

[0087] The p-type dopant atom is Mg, and the n-type dopant atom is Si. Mg doping technology in gallium nitride MOCVD growth is relatively mature; therefore, using Mg as the p-type dopant atom ensures the stability and repeatability of the p-type doped GaN layer growth process before ion implantation. Introducing Si as the n-type dopant atom into the second p-type GaN sublayer 512 allows for precise reduction of the p-type doping concentration through competitive doping with Mg. This layered doping method avoids the problem of precisely controlling the surface doping concentration in the p-type GaN layer 510 due to the Mg memory effect during traditional MOCVD growth by directly controlling the Mg element concentration.

[0088] In the gallium nitride epitaxial structure design of this application, a more refined doping concentration control strategy is implemented for the second P-type GaN sublayer 512. Specifically, the second P-type GaN sublayer 512 is designed to contain regions with three or more different doping concentrations in a stepped manner. These doping concentrations gradually decrease from the interface with the first P-type GaN sublayer 511 outwards (i.e., away from the first P-type GaN sublayer 511). By setting a stepped doping concentration in the second P-type GaN sublayer 512, more refined control of the interface electric field distribution can be achieved. As the doping concentration gradually decreases, the electric field strength at the interface also decreases accordingly, thereby more effectively avoiding electric field concentration and improving the breakdown voltage and reliability of the device. In gallium nitride devices, threshold voltage drift is a common problem, which can be caused by various factors, including changes in doping concentration and stress effects. By implementing a stepped doping concentration design, threshold voltage drift caused by abrupt changes in doping concentration can be reduced, thereby improving the stability and consistency of the device.

[0089] The gallium nitride epitaxial structure in this embodiment further optimizes the electrical performance of gallium nitride-based semiconductor devices by combining an asymmetric p-type doped region 420 with a layered doped GaN epitaxial layer, particularly providing a synergistic enhancement effect in improving gate breakdown voltage and stabilizing threshold voltage. Please refer to [link to relevant documentation]. Figure 5 , Figure 5The image above is a schematic diagram of a gallium nitride epitaxial structure obtained by a method for forming a gallium nitride epitaxial structure in another embodiment of this application. The gallium nitride epitaxial structure obtained in this embodiment includes a substrate 100, and a buffer layer 200, an intrinsic GaN layer 310, and an AlGaN layer 410 sequentially formed on the substrate 100. The AlGaN layer 410 contains an asymmetric P-type doped region 420 formed by P-type ion implantation. The shape of this asymmetric P-type doped region 420 can be designed, for example, as an inverted triangle, or its width can exhibit a trend of first increasing and then decreasing in the horizontal direction. This specific geometric distribution can modulate the lateral electric field within the AlGaN barrier layer 400, alleviating electric field concentration at the gate edge, thereby positively impacting the device's breakdown voltage.

[0090] A GaN epitaxial layer containing P-type doped atoms is grown on the AlGaN layer 410 and its asymmetric P-type doped region 420. This GaN epitaxial layer further includes a first P-type GaN sublayer 511 and a second P-type GaN sublayer 512 formed by N-type ion implantation. The first P-type GaN sublayer 511 serves as an interface layer with the AlGaN layer 410, maintaining a relatively high P-type doping concentration (e.g., the doping concentration is controlled at 1.5E). 19 cm -3 To 3E 19 cm -3 Within this range, this helps ensure good electrical contact with the underlying AlGaN layer 410 and provides sufficient carrier concentration to maintain the threshold voltage. The second P-type GaN sublayer 512 then has its net doping concentration reduced by controlled N-type ion implantation (e.g., implantation of silicon (Si) ions) (e.g., doping concentration controlled at 5E after annealing). 17 cm -3 To 1E 19 cm -3 Within a certain range, while maintaining P-type conductivity. This compensating doping on the surface of the P-type GaN epitaxial layer helps reduce the electric field strength at the interface between the gate metal and the P-type GaN, thereby delaying impact ionization and further improving the gate's breakdown voltage. Annealing after ion implantation is crucial for activating the implanted ions and repairing lattice damage caused by the ion implantation process, helping to reduce the interface state density and thus stabilizing the device's threshold voltage and on-resistance.

[0091] In this embodiment, the asymmetric P-type doped region 420 in the AlGaN layer 410 and the layered doping structure in the GaN epitaxial layer together constitute a combined vertical and horizontal electric field modulation system. The asymmetric P-type doped region 420 in the AlGaN layer 410 mainly optimizes the lateral electric field distribution and suppresses the electric field peak at the gate edge; while the concentration gradient design in the GaN epitaxial layer (from the first P-type GaN sublayer 511 to the second P-type GaN sublayer 512, the net doping concentration gradually decreases) mainly optimizes the vertical electric field distribution and reduces the electric field intensity at the gate interface. The synergistic effect of the two mechanisms makes the electric field distribution in the device more uniform when subjected to high gate voltage, thereby maintaining the stability of the threshold voltage while improving the gate breakdown voltage.

[0092] In a further embodiment of this application, the method for forming the gallium nitride epitaxial structure involves P-type ion implantation into the AlGaN layer 410 to form a P-type doped region 420 with a specific geometric distribution therein. The P-type doped region 420 is configured as an inverted triangle, with its width increasing and then decreasing horizontally. In this embodiment, the P-type doped region 420 is configured as an inverted triangle, with the doped region having a gradually decreasing lateral extension in the vertical direction, typically starting from the interface between the AlGaN layer 410 and the GaN epitaxial layer and gradually narrowing its horizontal width downwards (i.e., towards the substrate 100). This geometry can modulate the electric field distribution within the device. Specifically, in high-voltage applications, semiconductor device breakdown is often caused by electric field concentration at the gate edge. By introducing the inverted-triangular P-type doped region 420, the gradient change in its doping concentration and geometric profile can guide the redistribution of electric field lines within the bulk, preventing excessive electric field concentration at specific points, thereby helping to improve the device's breakdown voltage. This region can be achieved by implanting magnesium (Mg) ions as P-type dopant atoms. Furthermore, this inverted triangle shape design is related to the kinetics of the material growth process. For example, when epitaxially growing nitride materials on a beveled substrate 100, the bevel angle of the substrate 100 will affect the crystal growth mode and the continuation of defects. A similar principle can be applied to understand the contour of the doped region formed after P-type ion implantation. Its specific shape helps to guide the lattice arrangement in the subsequent epitaxial layer growth and reduce defects caused by lattice mismatch.

[0093] Furthermore, the width of the P-type doped region 420 is configured to first increase and then decrease in the horizontal direction. This width modulation results in the P-type doped region 420 exhibiting an asymmetric spindle-shaped or elliptical lateral profile within the AlGaN layer 410. This design increases the lateral coverage of the P-type doped region 420 at a specific depth, thereby more effectively modulating the distribution of the two-dimensional electron gas (2DEG) in the underlying channel and simultaneously smoothing both the longitudinal and lateral components of the electric field. The horizontally increasing-then-decreasing width design, combined with the inverted triangular longitudinal shape, creates a smoother doping transition region in three-dimensional space. This gradually changing doping profile helps mitigate potential electric field abrupt changes at the edges of the doped region, further suppressing peak electric fields and improving the long-term reliability of the device. Simultaneously, this width variation, which first increases and then decreases, is also related to the growth rate of the crystal or the distribution characteristics of ion implantation in different crystal orientations. By adapting to the intrinsic properties of the material, it can promote the improvement of epitaxial layer quality.

[0094] Please see Figure 6 This application further provides a semiconductor device formed on a gallium nitride epitaxial structure obtained in one of the aforementioned embodiments, comprising:

[0095] Substrate 100;

[0096] Buffer layer 200;

[0097] A channel layer 300 is formed on the buffer layer 200;

[0098] A barrier layer 400 is formed on the channel layer 300;

[0099] A contact layer 500 is formed on the barrier layer 400; a source electrode 610, a drain electrode 620, and a gate electrode 630 are formed on the contact layer 500, and the source electrode 610 and the drain electrode 620 extend into the channel layer 300 or the buffer layer 200.

[0100] The contact layer 500 is obtained by patterning the P-type GaN layer 510 in the gallium nitride epitaxial structure.

[0101] The specific structure of the semiconductor device includes, from bottom to top, a substrate 100, a channel layer 300, a barrier layer 400, and a contact layer 500. The barrier layer 400 serves as the supporting structure for the entire semiconductor device, and common materials include sapphire substrate 100, silicon substrate 100, and silicon carbide substrate 100; silicon is preferred in this application. A buffer layer 200 is grown on the substrate 100, and its main function is to alleviate the stress caused by the difference in lattice constant and thermal expansion coefficient between the substrate 100 and the upper epitaxial layer, thereby reducing lattice defects. The channel layer 300 is formed on the buffer layer 200 and is the main channel for the transport of charge carriers (such as electrons), and is typically made of intrinsic GaN material. The barrier layer 400 is located on the channel layer 300 and is generally made of AlGaN material. Because its band structure differs from that of the channel layer 300, it can form a two-dimensional electron gas (2DEG) in the channel layer 300. By precisely controlling the composition and thickness of Al in the AlGaN layer 410, the concentration and mobility of the two-dimensional electron gas can be adjusted. The contact layer 500 is formed on top of the barrier layer 400 and is obtained by patterning the P-type GaN layer 510 in the aforementioned gallium nitride epitaxial structure. The patterning process can fabricate the P-type GaN layer 510 into a structure of specific shape and size according to the device design requirements to achieve good contact with the electrode and optimize electrical performance.

[0102] The gate electrode 630 is formed on the contact layer 500, while the source electrode 610 and drain electrode 620 extend into the channel layer 300 or the buffer layer 200. Electrode materials are typically metals with good conductivity and chemical stability, such as titanium, aluminum, nickel, and gold, and are fabricated using processes such as photolithography, evaporation, and lift-off. For the aforementioned device, the main cause of gate failure is collisional ionization at the Schottky junction formed between the metal and the P-type GaN layer 510 under high voltage. When the electric field strength reaches a certain value, charge carriers gain sufficient energy to collide with lattice atoms, causing lattice atoms to ionize and generating new electron-hole pairs. An effective way to reduce the electric field strength at the interface is to reduce the doping concentration of the P-type GaN layer 510. However, the threshold voltage of GaN devices is closely related to the doping concentration of the P-type GaN layer 510. Typically, in order to ensure that the device has a threshold voltage greater than 1V to meet the switching characteristics requirements of the device during normal operation, the doping concentration of the P-type GaN layer 510 needs to be kept at a high level. A balance needs to be found between reducing the doping concentration to reduce the interface electric field strength and increasing the threshold voltage in order to optimize the device performance.

[0103] By patterning the contact layer 500 from a specially designed and processed p-type GaN layer 510, and by controlling the doping concentration of the p-type GaN layer 510, the electric field strength at the metal-pGaN interface is effectively reduced. This allows the device to delay impact ionization when subjected to high voltages, avoiding avalanche breakdown, thereby increasing the maximum operating voltage of the device, broadening its application range, and enabling it to operate stably in higher voltage scenarios.

[0104] The doping concentration of the P-type GaN layer 510 was reduced to decrease the interfacial electric field strength. However, through the gallium nitride epitaxial structure and the layered doping method of the P-type GaN layer 510, a threshold voltage greater than 1V can still be guaranteed for the device. A stepped doping concentration design is employed in the P-type GaN layer 510, maintaining a relatively high doping concentration near the barrier layer 400 to ensure a sufficient threshold voltage; while reducing the doping concentration in the surface region near the metal electrode to decrease the interfacial electric field strength. This allows the device to achieve accurate switching control while maintaining high breakdown voltage, thereby improving the device's reliability and stability.

[0105] Please see Figure 7 , Figure 8 This application further provides a semiconductor device with another structure, formed on a gallium nitride epitaxial structure obtained in the aforementioned other embodiment, comprising:

[0106] Substrate 100;

[0107] Buffer layer 200;

[0108] A channel layer 300 is formed on the buffer layer 200;

[0109] A barrier layer 400 is formed on the channel layer 300;

[0110] A contact layer 500 is formed on the barrier layer 400; a source electrode 610, a drain electrode 620, and a gate electrode 630 are formed on the contact layer 500, and the source electrode 610 and the drain electrode 620 extend into the channel layer 300 or the buffer layer 200.

[0111] The contact layer 500 is obtained by patterning the P-type GaN layer 510 in the gallium nitride epitaxial structure, and the barrier layer 400 has a P-type doped region 420 with the highest doping concentration or the largest doped area at the position corresponding to the contact layer 500. This technical solution includes forming an asymmetric P-type doped region in the AlGaN layer.

[0112] In the barrier layer 400 of this semiconductor device, a P-type doped region 420 with the highest doping concentration or the largest doped area is formed at the position corresponding to the contact layer 500. In semiconductor device design, heavy doping or increasing the doped area in specific regions is a common technique for optimizing the electrical performance of devices. For example, prior art indicates that several P-type GaN regions with high doping concentrations are distributed on the P-type GaN layer 510. The heavily doped P-type GaN regions increase the contact area between the ohmic contact region of the P-type region and the P-type GaN, which can reduce the on-resistance of the device. In this application, the P-type doped region 420 below the contact layer 500 in the barrier layer 400 is enhanced by locally increasing the P-type doping concentration (e.g., using magnesium (Mg) as the P-type doping atom) or increasing its lateral doping area, aiming to enhance the carrier concentration and injection efficiency in this region. A higher P-type doping concentration helps to form a more effective hole accumulation layer under the gate, which has a positive effect on maintaining the threshold voltage of the enhancement-mode device. Meanwhile, local heavy doping or large-area P-type regions can improve the contact characteristics between the gate metal and the semiconductor material, which helps to reduce contact resistance and thus reduce the conduction loss of the device.

[0113] The P-type doped region 420 is precisely positioned within the barrier layer 400 corresponding to the contact layer 500. This positioning allows the P-type doped region 420 to form a superimposed P-type semiconductor region with the upper P-type GaN contact layer 500 in the vertical direction. This structural design, on the one hand, enhances the P-type carrier distribution in the region below the gate, helping to better deplete the two-dimensional electron gas (2DEG) in the channel, thus providing conditions for enhancement-mode (normally off) operation. On the other hand, the P-type doped region 420 in the barrier layer 400, combined with the upper P-type GaN contact layer 500, constitutes a region with optimized doping concentration in the vertical dimension. This combined structure can modulate the electric field distribution below the gate, especially under high gate voltage or high drain voltage operating conditions, helping to alleviate electric field concentration at the gate edge, thereby improving the device's gate withstand voltage and reliability.

[0114] The contact layer 500 is obtained by patterning a P-type GaN layer 510, which is spatially aligned with the P-type doped region 420 in the barrier layer 400. This alignment design allows the two to work together to optimize device performance. The P-type GaN contact layer 500, as the direct contact layer 500 of the gate metal, has a direct impact on the Schottky or Ohmic contact characteristics due to its doping concentration and crystal quality. The P-type doped region 420 in the barrier layer 400 provides additional carrier support and modulates the electric field from below. This top-bottom synergistic P-type region design constitutes a vertical carrier enhancement and electric field modulation structure, which can more effectively control the concentration and distribution of the two-dimensional electron gas in the channel, thereby potentially improving its transconductance and switching characteristics while maintaining the stability of the device threshold voltage.

[0115] In a preferred embodiment, an etching trench is provided within the barrier layer 400 of the semiconductor device, surrounding the contact layer 500, and the width of the etching trench is limited to the range of 5nm to 200nm. In a preferred embodiment, it is limited to the range of 5nm-10nm. In a further embodiment, the etching trench is formed only in the region between the source and the gate. The etching trench structure optimizes the electrical performance and reliability of the device by defining specific dimensions and its spatial layout in the device.

[0116] The etching trench is formed in the barrier layer 400 and surrounds the contact layer 500. The depth control of the etching trench allows it to penetrate the barrier layer 400 and partially enter the channel layer 300, or precisely terminate inside the barrier layer 400, thereby achieving precise interruption or modulation of the two-dimensional electron gas (2DEG) channel.

[0117] When forming the etched trench, low-damage etching techniques can be employed to ensure the interface quality of the trench sidewalls and bottom. For example, neutral beam etching (NBE) or wet etching can be used instead of traditional plasma etching. This helps to mitigate lattice damage and surface state generation caused by high-energy ion bombardment. Wet etching using hot KOH solution can also effectively reduce the roughness of the etched surface, which is crucial for improving interface properties and reducing leakage current. Furthermore, by combining multi-step etching processes such as inductively coupled plasma (ICP) etching and reactive ion etching (RIE), the sidewall angle and bottom morphology of the etched trench can be further controlled, for example, forming sidewalls with specific angles or stepped structures, thereby optimizing the step coverage during subsequent dielectric layer filling and mitigating electric field concentration.

[0118] The etched trenches alter the electric field distribution within the device through their physical structure. Under reverse bias or off-state conditions, this structure alleviates electric field concentration at the gate edge or contact layer 500 edge, resulting in a more uniform electric field distribution throughout the device and thus contributing to improved breakdown voltage. Because the etched trenches effectively interrupt conductive paths in the barrier layer 400 and reduce trap-assisted tunneling effects due to their high-quality etched surfaces and interfaces, they help reduce reverse leakage current. The etched trenches surrounding the contact layer 500 also physically provide an effective isolation region, helping to suppress electrical crosstalk between adjacent devices.

[0119] The semiconductor device structure and fabrication method provided in this application exhibit good process compatibility and repeatability. Through precise control of the gallium nitride epitaxial structure and optimization of the patterning process, high-precision fabrication of the 500-layer contact layer can be achieved, reducing errors and uncertainties in the process. This semiconductor device combines advantages such as high breakdown voltage, optimized threshold voltage, high reliability, and stability, and can meet the diverse needs of various fields for semiconductor devices.

[0120] The semiconductor device provided in this application further introduces a passivation layer on top of the original structure. The passivation layer is uniformly and densely formed on the sidewalls of the contact layer 500 and the exposed surface of the barrier layer 400. During the fabrication process, by controlling deposition parameters such as temperature, pressure, and gas flow rate, it is ensured that the passivation layer completely covers the surface of the sidewalls of the contact layer 500 and the area exposed on the barrier layer 400 due to device fabrication, forming a continuous, defect-free protective film. The sidewalls of the contact layer 500 and the exposed surface of the barrier layer 400 contain numerous dangling bonds and lattice defects. These unsaturated chemical bonds form surface states and interface states. These surface states and interface states trap charge carriers, leading to increased scattering and recombination probabilities, thereby reducing the carrier mobility and lifetime in the device and affecting its conductivity and switching characteristics.

[0121] As described above, this application provides a gallium nitride epitaxial structure and its growth method. The gallium nitride epitaxial structure is a multilayer structure, consisting of a substrate, a buffer layer, an intrinsic GaN layer, an AlGaN layer, and a P-type GaN layer from bottom to top. The P-type GaN layer is further divided into a first P-type GaN sublayer and a second P-type GaN sublayer, which differ in doping characteristics and thickness. The first P-type GaN sublayer is in direct contact with the AlGaN layer and is doped with a high concentration of P-type doped atoms (Mg) to ensure good electrical contact and carrier transport with the AlGaN layer. The second P-type GaN sublayer is located above the first P-type GaN sublayer and contains both P-type and N-type (Si) doped atoms. By adjusting the ratio of these two doped atoms, the doping concentration is reduced, thereby controlling the interface electric field distribution, improving breakdown voltage and reliability, and reducing threshold voltage drift.

[0122] In terms of growth method, a substrate (such as silicon) is first provided, and a buffer layer, an intrinsic GaN layer (uGaN layer), and an AlGaN layer are sequentially grown using MOCVD technology. The buffer layer alleviates lattice and thermal mismatch, the intrinsic GaN layer serves as the channel layer, and the AlGaN layer serves as the barrier layer. Next, a Mg-containing GaN epitaxial layer is grown on the AlGaN layer, and the doping concentration is controlled by controlling the Mg source flux and growth temperature. Then, N-type (Si) ion implantation is performed on the GaN epitaxial layer containing P-type doped atoms, and the implantation depth is adjusted by controlling the parameters. Finally, annealing is performed to activate ions and repair lattice damage, and the amount of implanted N-type ions is controlled so that the ion-implanted part is still P-type doped after annealing. This method first grows a complete P-type GaN layer and then performs ion implantation to compensate for doping, avoiding the Mg memory effect and ensuring the stability of the epitaxial layer quality. The ion implantation precision is high, the doping distribution can be customized, the electrical performance can be optimized, and it is compatible with GaN on Si process, reducing costs. The annealing process simultaneously activates Mg and repairs the lattice damage caused by Si ion implantation.

[0123] The semiconductor device formed based on the above-described gallium nitride epitaxial structure includes a substrate (preferably silicon), a buffer layer, a channel layer (intrinsic GaN), a barrier layer (AlGaN), a contact layer (obtained by patterning a P-type GaN layer), a source electrode, a drain electrode, and a gate electrode. The gate electrode is located on the contact layer, while the source and drain electrodes extend into the channel layer or the buffer layer. This device reduces the electric field strength at the metal-interface by optimizing the doping of the contact layer and the P-type GaN layer, thus delaying impact ionization and increasing the maximum operating voltage.

[0124] The above is only one specific implementation of this application, and any other improvements made based on the concept of this application shall be considered within the scope of protection of this application.

Claims

1. A method for forming a gallium nitride epitaxial structure, characterized in that, include: A substrate is provided, on which a buffer layer, an intrinsic GaN layer, and an AlGaN layer are grown; P-type ion implantation is performed on the AlGaN layer to form multiple asymmetric, separate P-type doped regions in the AlGaN layer. The P-type doped regions are inverted triangular in shape. A GaN epitaxial layer including P-type doped atoms is grown on the AlGaN layer in which an asymmetric P-type doped region is formed, and N-type ion implantation is performed on the GaN epitaxial layer including P-type doped atoms. After N-type ion implantation is completed, annealing is performed; In the N-type ion implantation step, the amount of implanted N-type ions is controlled so that the implanted part remains P-type doped after annealing.

2. The method for forming a gallium nitride epitaxial structure according to claim 1, characterized in that, The spacing width of the P-type doped regions first decreases and then increases.

3. A semiconductor device, characterized in that, Formed on the gallium nitride epitaxial structure according to any one of claims 1-2, comprising: Substrate; Buffer layer; A channel layer is formed on the buffer layer; A barrier layer is formed on the channel layer; A contact layer is formed on the barrier layer; The device includes a source electrode, a drain electrode, and a gate electrode, wherein the gate electrode is formed on the contact layer, and the source electrode and the drain electrode extend into the channel layer or the buffer layer. The contact layer is obtained by patterning the P-type GaN layer in the gallium nitride epitaxial structure, and the barrier layer has a P-type doped region with the highest doping concentration or the largest doped area at the position corresponding to the contact layer.

4. The semiconductor device according to claim 3, characterized in that, The barrier layer also includes etched grooves surrounding the contact layer, the width of which is in the range of 5-200 nm.

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