Chip module cutting method

Abstract

The invention discloses a chip module cutting method, and relates to the technical field of semiconductor manufacturing. The chip module cutting method comprises the steps that a wafer to be cut is cut, independent chip modules are obtained, the wafer to be cut comprises a plurality of chip modules, each chip module comprises an intermediary layer and crystal grains, and the crystal grains are arranged on the surface of the intermediary layer; and chamfering the chip module to obtain the chamfered chip module. By implementing the chip module cutting method provided by the embodiment of the invention, chamfering processing is performed on the four corners of the interposer of the chip module, stress concentration points are eliminated, the mechanical stress problem of the large-size expensive interposer is improved, and the product manufacturing yield is improved; furthermore, a silicon interposer with a larger size can be manufactured to carry a high-performance processor and more high-bandwidth memories, so that the computing power is further improved; and a secondary cutting process is adopted in the cutting process, so that damage to the silicon interposer caused by non-uniform stress at a medium junction can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for cutting chip modules. Background Technology

[0002] With the development of high-performance computing (HPC) and artificial intelligence (AI) technologies, the demand for chip computing power, energy efficiency, and data bandwidth is growing exponentially. Traditional monolithic integrated manufacturing processes are limited by factors such as photolithography area, manufacturing yield, and power density, making it difficult to meet the requirements of memory bandwidth and high chip integration for scenarios such as large model training and scientific computing.

[0003] Driven by the continuous growth of computing power, COWOS (Chip-on-Wafer-on-Substrate) packaging technology has emerged. COWOS integrates processors (such as GPUs and AI accelerators) and multiple high-bandwidth memory (HBM) chips side-by-side on a silicon interposer, utilizing through-silicon vias (TSVs) on the interposer to achieve ultra-high-density interconnects, significantly shortening data transmission paths, increasing bandwidth, and reducing latency and power consumption. To accommodate more powerful processors and more high-bandwidth memory, further improving computing power, the area of ​​the silicon interposer is increased to accommodate larger processors and more high-bandwidth memory. However, excessively large silicon interposers can lead to problems such as warping and stress concentration. The larger the silicon interposer, the worse its mechanical reliability, making it prone to cracking and resulting in product failure. Therefore, a chip module cutting method is urgently needed to solve the mechanical reliability problem of large-size silicon interposers. Summary of the Invention

[0004] To address the mechanical reliability issues of large-size silicon interposers, this application provides the following technical solution: A method for cutting a chip module is provided, comprising: The wafer to be cut is used to obtain independent chip modules. The wafer to be cut includes several chip modules. Each chip module includes an interposer layer and a die. The die is disposed on the surface of the interposer layer. The chip module is chamfered to obtain the chamfered chip module.

[0005] Furthermore, the chip module is chamfered to obtain a chamfered chip module, including: The chip module is positioned at a first horizontal position, and the chip module is chamfered along the chamfering trajectory in a direction perpendicular to the first horizontal position. Rotate the chip module horizontally by a preset angle so that the chip module is positioned in the second horizontal position; The chip module is chamfered along the chamfering trajectory in a direction perpendicular to the second horizontal position to obtain the chamfered chip module.

[0006] Furthermore, the chip module is chamfered along the chamfering trajectory, including: Focus the pulsed laser at a predetermined depth in the interlayer; Set the pulsed laser energy to the preset energy; The intermediate layer is irradiated with a pulsed laser of preset energy along the chamfered trajectory.

[0007] Furthermore, the chamfer trajectory is set as follows: perpendicular to the angle bisector of the corner, and at a distance from the vertex of the corresponding corner: S C = S – S S Among them, S C S represents the distance from the chamfer trajectory to the vertex of the corresponding corner, and S represents the closest distance from the grain to the vertex of the corresponding corner. S This indicates the minimum safe distance between the chamfer trajectory and the corresponding grain.

[0008] Further, the wafer to be cut is diced to obtain individual chip modules, including: Material is removed from the surface of the dicing groove to a first depth with a first width along the dicing groove provided on the surface of the wafer to be diced; Following the trace left after material removal, the material is removed from the first depth to the second depth with a second width to obtain an independent chip module, wherein the first width is greater than the second width.

[0009] Furthermore, before obtaining the chamfered chip module, the following steps are also included: The obtained individual chip modules are transferred to the cutting tape.

[0010] Further, the obtained individual chip modules are transferred to dicing tape, including: Set the chip modules sequentially on the cutting tape.

[0011] Furthermore, transferring the obtained individual chip modules to the cutting tape also includes: The chip modules are spaced apart on the cutting tape.

[0012] Furthermore, the method of removing material includes at least one of the following: removing material by mechanical cutting, removing material by laser stealth cutting, or removing material by plasma etching.

[0013] Furthermore, the maximum radius of the grinding wheel used for mechanical material removal is: Where, l = min [a, b], indicating that the smaller of a and b is used as the value of l, a represents the spacing between adjacent chip modules in the same row on the surface of the cutting tape, b represents the spacing between chip modules in adjacent rows on the surface of the cutting tape, r represents the maximum radius of the grinding wheel, and S C This indicates the distance from the chamfer trajectory to the vertex of the corresponding corner.

[0014] By implementing the chip module cutting method provided in this application embodiment, the four corners of the chip module interposer are chamfered to eliminate stress concentration points, improve the mechanical stress problem of large-size expensive interposers, and improve product manufacturing yield; thereby, it is possible to manufacture larger-size silicon interposers to accommodate high-performance processors and more high-bandwidth memory, further improving computing power; the use of a secondary cutting process during the cutting process can avoid damage to the silicon interposer caused by uneven stress at the dielectric interface. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a chip module cutting method provided in an embodiment of this application; Figure 2 This is a top view of the wafer to be cut provided in an embodiment of this application; Figure 3 This is a top view of the chip module provided in the embodiment of this application; Figure 4 This is a schematic diagram of the cutting tape and bracket provided in an embodiment of this application; Figure 5 This is a schematic cross-sectional view along the cutting depth of the dicing groove provided in an embodiment of this application; Figure 6 This is a schematic diagram of a chip module arrangement on the surface of a cut tape according to an embodiment of this application; Figure 7 This is a schematic diagram of another arrangement of chip modules on the surface of a cut tape provided in an embodiment of this application; Figure 8 This is a schematic diagram of the cutting direction provided in the embodiments of this application; Figure 9 This is a schematic diagram of the chip module provided in the embodiment of this application located in the first horizontal position; Figure 10 This is a schematic diagram showing the chip module provided in this application embodiment located in the second horizontal position; Figure 11 This is a schematic diagram of the chamfer trajectory provided in an embodiment of this application; Figure 12 This is a schematic diagram showing the arrangement and spacing of the chip modules provided in the embodiments of this application on the surface of the cut tape. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0019] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0020] To address the issues of poor mechanical reliability and low processing yield of large-size silicon interposers, this application provides the following technical solution: In some embodiments, such as Figure 1 As shown, a chip module cutting method includes: S100: Cut the wafer to be cut to obtain an independent chip module, wherein the wafer to be cut includes several chip modules, and the chip module includes an interposer layer and a die, with the die disposed on the surface of the interposer layer; S200: Chamfer the chip module to obtain the chamfered chip module.

[0021] The chip module dicing method provided in this application is applicable to dicing the interposer layer in the process of manufacturing chip modules using the COWOS process. In the COWOS process, before dicing, the die is encapsulated on the wafer containing the interposer layer. The dies are interconnected through the interposer layer to form a chip module suitable for high-performance computing and artificial intelligence computing. The wafer to be diced refers to the wafer containing the encapsulated die interposer layer. Figure 2 The diagram shows a top view of the wafer to be cut before dicing. Figure 2 The dashed lines in the diagram represent dicing grooves. Before dicing, the wafer to be diced comprises several independent chip modules, with the dies already encapsulated on the surface of the interposer. This application does not limit the process of encapsulating the dies with the interposer or the selection of the dies.

[0022] On the surface of the wafer to be cut, dicing grooves are set between adjacent chip modules. The individual chip modules are cut along the dicing grooves using a cutting device.

[0023] For the cutting of wafers, at least one of the following methods can be used: mechanical cutting, laser stealth cutting, or plasma etching.

[0024] Figure 3 The diagram schematically illustrates the top-down structure of a single, independent chip module. For ease of explanation, Figure 3 The diagram illustrates a single, independent chip module with an architecture consisting of a processor and six high-bandwidth memory modules mounted on an interposer layer. This application does not limit the number of high-bandwidth memory modules mounted on the interposer layer. The chip module 100 includes an interposer layer 110 and a die 120 disposed on the surface of the interposer layer 110.

[0025] The die 120 includes a processor 121 and high-performance memory 122. The processor is schematically a GPU or AI accelerator. A high-density wiring (not shown) is provided on the interposer layer 110 to support high-speed interconnects between the dies packaged thereon.

[0026] For chip modules suitable for high-performance computing and artificial intelligence computing scenarios, silicon is used as the interposer layer. The interposer layer material can also be SiC, GaN, GaAs, SiGe, InP, or glass, etc. This application does not limit the interposer layer material.

[0027] Individual chip modules obtained after wafer dicing are rectangular or square, and stress concentration easily occurs at the four right corners of their interposer, causing cracking. This stress concentration is particularly pronounced when attempting to increase the area of ​​the interposer, leading to a decrease in yield. By chamfering the four corners of the interposer, stress concentration points are eliminated, improving the mechanical stress problem of large-size expensive interposers and increasing product manufacturing yield. This, in turn, enables the manufacture of larger silicon interposers to accommodate high-performance processors and more high-bandwidth memory, further enhancing computing power.

[0028] Preferably, S100: dicing the wafer to be diced to obtain an independent chip module, including: S110: Remove material from the surface of the dicing groove to a first depth with a first width along the dicing groove provided on the surface of the wafer to be diced; S120: Following the trace left after material removal, remove the material from the first depth to the second depth with a second width to obtain an independent chip module, wherein the first width is greater than the second width.

[0029] Before dicing the wafer, it needs to be placed face up on the surface of the dicing tape 200. The dicing tape 200 is an auxiliary material used in the wafer dicing stage; it is adhesive and typically rests on a support 300 to form a support structure. Optionally, the support 300 is made of metal or plastic. Preferably, the support 300 is circular in shape, such as... Figure 4 As shown. However, this application does not limit the material or shape of the bracket.

[0030] During the cutting process, the cutting tape prevents the chips or chip modules from shifting, splashing, or breaking. After cutting, each individual chip or chip module adheres to the surface of the cutting tape, and by stretching the tape, it can be accurately grasped by a robotic arm in subsequent processes. The cutting tape has a certain thickness, illustratively ranging from 80μm to 200μm.

[0031] Because the mechanical properties of each layer of the wafer to be cut differ, a layered cutting method is preferred for safe cutting of the wafer.

[0032] The surface of the wafer to be cut has a passivation layer, and below the passivation layer is an interposer material, such as... Figure 5 As shown. The first depth h1 extends from the surface of the passivation layer to the interface between the passivation layer and the interposer material. The second depth h2 extends from the interface between the passivation layer and the interposer material into the interior of the cutting tape (in the cross-sectional direction), so that the chip module is completely separated and attached to the surface of the cutting tape.

[0033] The specific values ​​of the first depth h1, the second depth h2, the first width Z1, and the second width Z2 are usually set according to the wafer to be diced during the process. This application does not limit the specific values ​​of the above parameters.

[0034] Before chamfering the chip module to obtain the chamfered chip module, the following steps are also included: The obtained individual chip modules are transferred to the cutting tape.

[0035] This application provides two arrangements of chip modules on the surface of cut tape: The first method involves sequentially placing the chip modules onto the cut tape, such as... Figure 6 As shown, several rows of chip modules are evenly spaced on the surface of the cutting tape; within any row, several chip modules are evenly spaced. This method of fixing the chip modules maximizes the utilization of the cutting tape area. However, when using mechanical cutting processes for chamfering, the size of the grinding wheel must be carefully selected. The following section will detail the method for selecting the grinding wheel size.

[0036] The second type involves spacing the chip modules between the cut adhesive tape, such as... Figure 7 As shown, several rows of chip modules are evenly spaced on the surface of the cutting tape; within any row, several chip modules are evenly spaced; and no chip module is placed in the nearest neighbor position of any given chip module. Using this method to fix the chip modules allows for greater freedom of cutting during the chamfering process.

[0037] The chip module is chamfered to obtain the chamfered chip module, including: S210: Set the chip module to the first horizontal position, and chamfer the chip module along the chamfer trajectory in the direction perpendicular to the first horizontal position; S220: Rotate the chip module by a preset angle in the horizontal direction so that the chip module is set in the second horizontal position; S230: Chamfer the chip module along the chamfer trajectory in a direction perpendicular to the second horizontal position to obtain the chamfered chip module.

[0038] Chamfering of chip modules can be performed using at least one of the following methods: mechanical cutting, laser stealth cutting, or plasma etching.

[0039] Typically, dicing equipment performs cutting or positioning along orthogonal directions relative to the wafer coordinate system. Figure 8 For example, the cutting equipment cuts along the X direction and adjusts its position along the Y direction. The reverse is also true. Therefore, the common method is to rotate the workpiece to be cut, aligning the cutting line with the direction parallel to the cutting direction, and then adjust the position of the cutting equipment in a direction orthogonal to the cutting direction to align the cutting equipment with the cutting line.

[0040] In this application, the cutting line refers to the dicing groove or chamfering trajectory.

[0041] Combination Figure 9 Under the above cutting conditions, the chamfering process is described. Figure 9 In the process, the cutting equipment cuts along the X direction and adjusts its position along the Y direction. When the chip module is in the first horizontal position, the chamfering trajectories corresponding to its 100a and 100c angles are parallel to the X direction. By adjusting the position of the cutting equipment in the Y direction, it is made to align with the chamfering trajectories corresponding to the 100a and 100c angles in sequence for cutting, thus completing the chamfering of the 100a and 100c angles.

[0042] The rotating bracket allows the chip module to be housed on the same horizontal plane in a second horizontal position orthogonal to the first horizontal position, such as... Figure 10 As shown, the chamfering trajectories corresponding to angles 100b and 100d are made parallel to the X direction. By adjusting the position of the cutting device in the Y direction, it is made to align with the chamfering trajectories corresponding to angles 100b and 100d in sequence for cutting, thus completing the chamfering of angles 100b and 100d.

[0043] It should be noted that, unlike the dicing groove which has a physical form on the wafer, the chamfering trajectory is determined by equipment positioning during the processing.

[0044] Chamfering the chip module along the chamfering trajectory includes: C100: Focuses the pulsed laser at a predetermined depth in the interlayer; C200: Sets the pulsed laser energy to a preset energy; C300: The intermediate layer is irradiated with a pulsed laser of preset energy along the chamfered trajectory.

[0045] This involves using laser stealth dicing technology to process the interposer layer of the chip module, thereby eliminating stress at the four corners of the interposer layer.

[0046] Using picosecond or femtosecond lasers, the focus is concentrated on the interior of the interposer material, rather than its surface. This causes nonlinear absorption at the focal point within the interposer, creating micro-voids, lattice damage, and a modified layer of localized melting and resolidification. Laser stealth cutting is a non-contact process with no tool wear. It offers advantages such as smooth cutting edges, high mechanical strength, and no need for secondary polishing. It is suitable for cutting ultra-thin materials such as flexible glass and silicon wafers that are only tens of micrometers thick.

[0047] After being irradiated with the pulsed laser along the chamfer path, a modified layer is formed inside the intermediate layer below the chamfer path, while the material in the rest of the wafer remains unaffected, and the wafer surface is free of damage, scratches, and debris.

[0048] Optionally, for the intermediate layer after laser stealth cutting, under the action of mechanical stress or thermal stress, the intermediate layer is neatly arranged along the modified layer that overlaps with the chamfer trajectory, and the material at the four corners of the intermediate layer is removed.

[0049] Under the action of mechanical stress, it means that by expanding the cutting tape, the stress is applied to the laser-cut chip module through the cutting tape, so that the four corners of the chip module are separated along the chamfering trajectory, and the chamfered chip module is obtained.

[0050] After laser stealth cutting of the interposer layer, it is also possible to choose not to remove the material at the four corners. In this case, if the chip module is subjected to mechanical or thermal stress during assembly or use, the four corners will split along the chamfer trajectory to protect the integrity of the chip module.

[0051] The chamfer trajectory is set as follows: perpendicular to the angle bisector of the corner, and at a distance from the corresponding vertex of the corner: S C = S – S S ; Among them, S C S represents the distance from the chamfer trajectory to the vertex of the corresponding corner, and S represents the closest distance from the grain to the vertex of the corresponding corner. S This indicates the minimum safe distance between the chamfered trajectory and the corresponding grain. For example... Figure 11 A schematic diagram of the chamfering trajectory is shown, taking one corner of the chip module as an example.

[0052] The minimum safe distance refers to the distance that will not affect the nearest grain during the cutting process.

[0053] The material removal methods include at least one of the following: mechanical cutting, laser stealth cutting, or plasma etching. Among these, laser stealth cutting technology can achieve a resolution of 50nm, focusing on a specific depth within the wafer, and the cutting process is free of chipping and debris. It is suitable for the manufacture of CPUs, GPUs, AI chips, and high-bandwidth memory; and for the cutting of SiC and GaN semiconductor materials.

[0054] The chip module cutting method provided in this application is compatible with a variety of cutting methods, allowing for flexible selection based on process requirements.

[0055] The maximum radius of the grinding wheel used for mechanical material removal is: Where, l = min [a, b], indicating that the smaller of a and b is used as the value of l, a represents the spacing between adjacent chip modules in the same row on the surface of the cutting tape, b represents the spacing between chip modules in adjacent rows on the surface of the cutting tape, r represents the maximum radius of the grinding wheel, and S CThis represents the distance from the chamfer trajectory to the vertex of the corresponding corner, such as... Figure 12 As shown. By selecting a grinding wheel of the appropriate size using the above method, damage to adjacent chip units can be avoided.

[0056] By implementing the chip module cutting method provided in this application embodiment, stress concentration points are eliminated by chamfering the four corners of the silicon interposer, improving the mechanical stress problem of large-size silicon interposers and increasing product manufacturing yield. This enables the manufacture of larger silicon interposers to accommodate high-performance processors and more high-bandwidth memory, further enhancing computing power. The use of a secondary cutting process avoids damage to the silicon interposer caused by uneven stress at the dielectric interface. The chip module cutting method provided in this application embodiment is highly adaptable and applicable to various cutting processes; especially when dealing with mechanical cutting processes, the optimized placement of the chip module on the cutting tape surface improves the applicability of the grinding wheel size.

[0057] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0058] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

[0059] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0060] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as steps controlled by a computer software program. For example, embodiments of this application include a computer program product comprising a computer program loaded on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from memory, or installed from ROM. When the computer program is executed by an external processor, it performs the functions defined in the methods of embodiments of this application.

[0061] It should be noted that the computer-readable medium in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the embodiments of this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.

[0062] The aforementioned computer-readable medium may be included in the aforementioned server; or it may exist independently and not assembled into the server. The aforementioned computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the peripheral mode of the terminal is not activated, acquire the frame rate of the application on the terminal; when the frame rate meets the screen-off condition, determine whether the user is acquiring the terminal's screen information; and in response to the determination that the user is not acquiring the terminal's screen information, control the screen to enter an immediate dimming mode.

[0063] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0064] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0065] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0066] The data storage method, device, and storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. These embodiments are merely preferred embodiments of this application, used to help understand the method and its core ideas, and are not intended to limit this application. It should be noted that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application without departing from its principles are also within the protection scope of the claims of this application.

Claims

1. A method for cutting a chip module, characterized in that, include: A wafer to be cut is obtained to obtain an independent chip module. The wafer to be cut includes a plurality of chip modules. Each chip module includes an interposer layer and a die. The die is disposed on the surface of the interposer layer. The chip module is chamfered to obtain the chamfered chip module.

2. The chip module cutting method according to claim 1, characterized in that, The step of chamfering the chip module to obtain the chamfered chip module includes: The chip module is positioned at a first horizontal position, and the chip module is chamfered along a chamfering trajectory in a direction perpendicular to the first horizontal position. The chip module is rotated by a preset angle in the horizontal direction so that the chip module is set in the second horizontal position; The chip module is chamfered along the chamfering trajectory in a direction perpendicular to the second horizontal position to obtain the chamfered chip module.

3. The chip module cutting method according to claim 2, characterized in that, The chamfering of the chip module along the chamfer trajectory includes: Focus the pulsed laser at a predetermined depth in the intermediate layer; Set the pulsed laser energy to a preset energy; The intermediate layer is irradiated with a pulsed laser of preset energy along the chamfered trajectory.

4. The chip module cutting method according to claim 2, characterized in that, The chamfer trajectory is set as follows: perpendicular to the angle bisector of the corner, and at a distance of S from the vertex of the corresponding corner. C = S – S S , wherein the S C S represents the distance from the chamfered trajectory to the vertex of the corresponding corner, and S represents the closest distance from the grain to the vertex of the corresponding corner. S This indicates the minimum safe distance between the chamfered trajectory and the corresponding grain.

5. The chip module cutting method according to claim 1, characterized in that, The process of cutting the wafer to be cut to obtain an independent chip module includes: Material is removed from the surface of the dicing groove to a first depth with a first width along the dicing groove provided on the surface of the wafer to be cut; Following the trace left after material removal, the material is removed from the first depth to the second depth with a second width to obtain an independent chip module, wherein the first width is greater than the second width.

6. The chip module cutting method according to claim 1, characterized in that, Before chamfering the chip module to obtain the chamfered chip module, the method further includes: The obtained individual chip modules are transferred to the cutting tape.

7. The chip module cutting method according to claim 6, characterized in that, The process of transferring the obtained independent chip modules to the cutting tape includes: The chip modules are sequentially placed on the cutting tape.

8. The chip module cutting method according to claim 6, characterized in that, The step of transferring the obtained independent chip modules to the cutting tape also includes: The chip modules are spaced apart on the cutting tape.

9. The chip module cutting method according to claim 5, characterized in that, The method of removing the material includes at least one of the following: removing the material by mechanical cutting, removing the material by laser stealth cutting, or removing the material by plasma etching.

10. The chip module cutting method according to claim 9, characterized in that, The maximum radius of the grinding wheel used for mechanically removing material is: Where, l = min [a, b], indicating that the smaller number between a and b is used as the value of l, a represents the spacing between adjacent chip modules in the same row on the surface of the cutting tape, b represents the spacing between chip modules in adjacent rows on the surface of the cutting tape, r represents the maximum radius of the grinding wheel, and S C This indicates the distance from the chamfer trajectory to the vertex of the corresponding corner.

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