Circuit device

Abstract

A circuit device may include: a first cell including a first cell structure on an upper surface of a substrate; a second cell including a second cell structure on the upper surface of the substrate; a signal track on an upper surface of the substrate; a first power transfer rail on a lower surface of the substrate; and a power transmission region defined by the first cells at a first boundary and defined by the second cells at a second boundary, where the second boundary is opposite to the first boundary with respect to the power transmission region in a second direction intersecting the first direction, where the power transmission region includes a first power transmission contact, and where the second power transmission contact includes a second power transmission contact. The first power transfer track is electrically connected to the first cell structure and the second cell structure through the first power transfer contact.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 719,695, filed November 13, 2024, entitled “Integrated Circuit Device Including Backside Power Transmission Network Structure and Method of Forming Thereof,” and U.S. Non-Provisional Patent Application No. 19 / 206,492, filed May 13, 2025, with the United States Patent and Trademark Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to circuit devices. Background Technology

[0003] Integrated circuit (IC) devices, chips, and / or blocks can receive power and data signals from one or more external sources, such as power supplies and data sources. Some IC devices can receive power and data signals via a front-side conductive structure that provides a power distribution network (PDN). For example, an IC device may include a front-side power distribution network (FSPDN) having one or more components formed during back-end process (BEOL) technology, and the conductive structure for data signals may be on the same side of the IC device as the FSPDN. IC devices can include various transistor structures, including, for example, two-dimensional (2D) planar structures, FinFETs, gate-all-around transistors, and multi-bridge channel FETs (MBCFETs). TM ) and stacked transistors (e.g., three-dimensional (3D) stacked transistors).

[0004] Recently, a back-side PDN (BSPDN) in which the back side of the IC device is used as the PDN has been developed. In the BSPDN structure, power rails can be formed on the back side of the semiconductor chip, IC device, or wafer (generally referred to herein as a semiconductor device), rather than on the front side. Thus, the power rails can be on the side of the semiconductor structure opposite to the active components (e.g., transistors) of the IC device (e.g., the side of the IC device's substrate). Furthermore, conductive structures for data signals can be on the front side of the semiconductor device, and therefore the BSPDN and the conductive structures for data signals can be on the opposite side of the semiconductor device. Summary of the Invention

[0005] A circuit device may include: a substrate; a first unit including a first unit structure on an upper surface of the substrate; a second unit including a second unit structure on an upper surface of the substrate; a signal track on the upper surface of the substrate, wherein the signal track is electrically connected to the first unit structure and / or the second unit structure; a first power transmission track on a lower surface of the substrate, wherein the lower surface of the substrate is opposite to the upper surface of the substrate in a first direction; and a power transmission region defined by the first unit at a first boundary and by the second unit at a second boundary, wherein the second boundary is opposite to the first boundary with respect to the power transmission region in a second direction intersecting the first direction, wherein the power transmission region includes a first power transmission contact, and wherein the first power transmission track is electrically connected to the first unit structure and the second unit structure via the first power transmission contact.

[0006] In some embodiments, the first power transmission contact is located in a second direction between the first boundary and the second boundary.

[0007] In some embodiments, the circuit device further includes an active pattern on a substrate and a diffusion interruption pattern extending into the substrate, wherein the first cell structure includes a first active pattern in the active pattern at a first boundary.

[0008] In some embodiments, the first unit has no diffusion interruption pattern at the first boundary.

[0009] In some embodiments, the first unit includes a third boundary, which is opposite to the first boundary in a second direction with respect to the first unit, and wherein the first unit structure further includes at the third boundary a second active pattern in an active pattern or a first diffusion interruption pattern in a diffusion interruption pattern.

[0010] In some embodiments, the second unit structure includes a third active pattern in the active pattern at the second boundary.

[0011] In some embodiments, the second unit structure has no diffusion interruption pattern at the second boundary.

[0012] In some embodiments, the second unit includes a fourth boundary, which is opposite to the second boundary in a second direction with respect to the second unit, and wherein the second unit structure further includes a fourth active pattern in an active pattern or a second diffusion interruption pattern in a diffusion interruption pattern at the fourth boundary.

[0013] In some embodiments, a first signal track in a signal track has a first length in a second direction, and a second signal track in a signal track has a second length in a second direction that is smaller than the first length.

[0014] In some embodiments, the second signal track is not superimposed on the first power transmission contact in the first direction.

[0015] In some embodiments, the first signal track is at least partially overlapped with the first power transmission contact in a first direction.

[0016] In some embodiments, the power transmission area includes a second power transmission contact.

[0017] In some embodiments, the circuit arrangement further includes a second power transmission track electrically connected to the first unit structure and the second unit structure via a second power transmission contact.

[0018] In some embodiments, a first power transmission rail is configured to supply a first voltage, and a second power transmission rail is configured to supply a second voltage different from the first voltage.

[0019] A circuit device may include: a substrate including a diffusion interruption pattern; a first unit including a first unit structure on an upper surface of the substrate; a second unit including a second unit structure on an upper surface of the substrate; a signal track on the upper surface of the substrate, wherein the signal track is electrically connected to the first unit structure and / or the second unit structure; a first power delivery track on a lower surface of the substrate, wherein the lower surface of the substrate is opposite to the upper surface of the substrate in a first direction; and a power delivery region defined by the first unit at a first boundary and by the second unit at a second boundary, wherein the second boundary is opposite to the first boundary in a second direction intersecting the first direction with respect to the power delivery region, wherein the power delivery region includes a first power delivery contact and at least one active pattern, wherein the first power delivery track is electrically connected to the first unit structure and the second unit structure via the first power delivery contact, and wherein the power delivery region has no diffusion interruption pattern.

[0020] In some embodiments, the first unit structure includes a first active pattern of the at least one active pattern at a first boundary, and the second unit structure includes a second active pattern of the at least one active pattern at a second boundary.

[0021] In some embodiments, the first unit includes a third boundary, the third boundary being opposite to the first boundary in a first direction with respect to the first unit, and wherein the first unit structure further includes a first diffusion interruption pattern in a diffusion interruption pattern at the third boundary.

[0022] In some embodiments, the second unit includes a fourth boundary, the fourth boundary being opposite to the second boundary in a second direction with respect to the second unit, and wherein the second unit structure includes a second diffusion interruption pattern in a diffusion interruption pattern at the fourth boundary.

[0023] In some embodiments, the circuit arrangement further includes a second power transmission track electrically connected to the first unit structure and the second unit structure via a second power transmission contact in the power transmission area.

[0024] A circuit device may include: a substrate including a diffused interruption pattern; a first unit including a first unit structure on an upper surface of the substrate; a second unit including a second unit structure on the upper surface of the substrate, wherein the second unit structure is spaced apart from the first unit structure in a first direction; a signal track on the upper surface of the substrate, wherein the signal track is electrically connected to the first unit structure and / or the second unit structure; a power transmission track on a lower surface of the substrate, wherein the lower surface of the substrate is opposite to the upper surface of the substrate in a second direction intersecting the first direction; and a power transmission region defined by the first unit at a first boundary and by the second unit at a second boundary, wherein the second boundary is closed in the first direction. The power transmission area is opposite to a first boundary, wherein the power transmission area includes a power transmission contact and at least one active pattern, and has no diffusion interruption pattern, wherein the power transmission track is electrically connected to a first unit structure and a second unit structure via the power transmission contact, wherein the first unit structure includes a first active pattern of the at least one active pattern at the first boundary, wherein the second unit structure includes a second active pattern of the at least one active pattern at the second boundary, wherein the first unit includes a third boundary, the third boundary being opposite to the first boundary in a first direction with respect to the first unit, and wherein the first unit structure also includes a first diffusion interruption pattern of the diffusion interruption pattern at the third boundary.

[0025] Other apparatuses, devices, and / or methods according to some embodiments will become clear to those skilled in the art after reading the following accompanying drawings and detailed description. It is intended that all such additional embodiments, other than any and all combinations thereof, are included within this specification, within the scope of this disclosure, and protected by the appended claims. Attached Figure Description

[0026] Figure 1A This is a schematic view illustrating an example integrated circuit device including a cell array according to a comparative embodiment.

[0027] Figure 1B This illustrates a comparative embodiment. Figure 1A A schematic plan view of an example cell array.

[0028] Figure 1C This illustrates the combination according to a comparative embodiment. Figure 1B A schematic plan view of the unit.

[0029] Figure 1D Is with Figure 1C The circuit diagram corresponding to the example unit.

[0030] Figure 1E yes Figure 1B A schematic cross-sectional view of the first surface of the unit.

[0031] Figure 2A This is a schematic plan view illustrating an example integrated circuit device according to some embodiments of the present disclosure.

[0032] Figure 2B and Figure 2C It is shown Figure 2A A schematic cross-sectional view of the construction of an example integrated circuit device.

[0033] Figure 3A This is a schematic plan view illustrating an example integrated circuit device according to some embodiments of the present disclosure.

[0034] Figure 3B Is with Figure 3A The circuit diagram corresponding to the example integrated circuit device.

[0035] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H This is a schematic plan view illustrating a method of manufacturing an integrated circuit device according to some embodiments of the present disclosure. Detailed Implementation

[0036] Figure 1A This is a schematic plan view of an example integrated circuit device 1 including a cell array 11 (e.g., a cell array) according to a comparative embodiment. Figure 1B This illustrates a comparative embodiment. Figure 1A Schematic plan view of example cells 10-1 and 10-2 of cell array 11. Figure 1C This illustrates a comparative embodiment. Figure 1B A schematic plan view showing the combination of units 10-1 and 10-2. Figure 1D Is with Figure 1C The example is combined with the circuit diagram corresponding to the unit. Figure 1E The first surface of unit 10-2 is along Figure 1B A schematic cross-sectional view of line AA.

[0037] exist Figures 1A to 1BIn the comparative embodiment shown, the integrated circuit device 1 includes a plurality of cells 10-1, 10-2...10-n (collectively referred to hereinafter as cell 10) coupled together to define a cell array 11 electrically connected to, for example, a memory cell array 12. As used herein, “cell” or “standard cell” refers to having one or more predetermined dimensions (e.g., cell length, cell width, cell area, and / or active region size) and one or more predetermined cell structures (e.g., 2D planar structure, FinFET, gate-all-around transistor, MBCFET). TM The cell may contain a 3D stacked transistor and / or other known cell structures, and one or more predetermined operations (e.g., read operation, write operation, decode operation, sense amplifier control operation, input / output logic operation, clock operation, power supply gating operation and / or well tapping operation and other known operations). As an example, the first cell 10-1 and the second cell 10-2 may each have widths W1 and W2 that are different from each other in the first direction D1, perform different operations, and / or have different cell structures.

[0038] In some embodiments, each of the units 10 may include a diffusion interruption pattern 13, an active gate pattern 14, a source / drain pattern 15, a front-side signal track 16, a power delivery contact 17, an intermediate process (MOL) structure (not shown), and an FSPDN (not shown).

[0039] A diffusion interruption pattern 13 may be disposed on the boundary of cell 10 to electrically insulate the active region between adjacent cells 10. Examples of diffusion interruption patterns 13 include, but are not limited to, single diffusion interruption (SDB) regions or dual diffusion interruption (DDB) regions. In some embodiments, the diffusion interruption pattern 13 may (or may not) include shallow trench isolation (STI) regions, and the diffusion interruption pattern 13 may include one or more dummy gate patterns (e.g., patterns that enhance process consistency (uniformity) and suppress mismatched nonfunctional gate patterns).

[0040] The active gate pattern 14 of the first unit 10-1 can be electrically connected to a logic input or output power supply (not shown) via a first front-side signal rail 16-1 and the MOL structure. The first front-side signal rail 16-1 can be one of the front-side signal rails 16. The source / drain pattern 15 can be electrically connected to a power line (not shown) via a power delivery contact 17, the front-side signal rail 16, and the MOL structure. The active gate pattern 14 and the source / drain pattern 15 can include various types of known conductive materials (such as doped polysilicon (Poly-Si), titanium nitride (TiN), tantalum nitride (TaN), molybdenum (Mo), cobalt (Co), nickel silicide (NiSi), and / or other known conductive materials). The power delivery contact 17 can include a known conductive material and connects the source / drain pattern 15 to the drain voltage (VDD) and source voltage (VSS) generated by an external source.

[0041] The MOL structure (not shown) may include one or more interlayer insulating layers in which one or more conductive lines (e.g., one or more metal lines) and one or more conductive via plugs (e.g., one or more metal via plugs) are disposed. The FSPDN may be spaced apart from the front-side signal track 16 in the first direction D1 and may be adjacent to at least one of the diffusion interruption patterns 13. In some embodiments, the FSPDN may be shared by cells 10-1, 10-2 and may be electrically connected to one or more cell structures of cells 10-1, 10-2, as described in further detail below. In some embodiments, the FSPDN may include a conductive material (such as a metal) and may be configured to provide a power delivery path for the integrated circuit device 1.

[0042] like Figures 1C to 1D As shown, when the first unit 10-1 and the second unit 10-2 are combined with each other (e.g., directly joined or bonded, with filling units or spacer units between the first unit 10-1 and the second unit 10-2) to form a unit array 11 (or a portion of a unit array 11), the first unit 10-1 and the second unit 10-2 can be electrically connected and combined with each other, thereby reducing the number of power supplies. As an example, and as shown by... Figure 1D As indicated by boxes 20 and 30, these include circuit diagram 40-1 corresponding to the first unit 10-1 and circuit diagram 40-2 corresponding to the second unit 10-2. When the first unit 10-1 and the second unit 10-2 are combined, the number of power supplies can be reduced from four to two. Furthermore, a set of diffusion interruption patterns 13A of the first unit 10-1 and the second unit 10-2 on the boundary between the first unit 10-1 and the second unit 10-2 can be combined and / or connected to each other using known SDB / DDB bonding processes.

[0043] Some embodiments of this disclosure may originate from the understanding that combining the first unit 10-1 and the second unit 10-2 can suppress the electrical, operational, and performance characteristics of the unit array 11. As an example, and referring to... Figure 1E The gate contact layer 50 of the MOL structure electrically connects the active gate pattern 14 and the first front-side signal track 16-1, and the power delivery contact via 60 of the MOL structure electrically connects the FSPDN 70 to the first power delivery contact 17-1. The first front-side signal track 16-1 may have a width W3 smaller than the width W4 of the FSPDN 70 in the second direction D2. During the manufacturing process, it may be difficult to implement a cut layer (e.g., a negative mask) on the first front-side signal track 16-1. That is, due to the relatively large width W4 of the FSPDN 70, it may be difficult to implement a mask layer in which vias are electrically connected to the first front-side signal track 16-1 and other portions of the cell 10. Thus, without implementing such... Figure 1B In cases where the marginal length extension (e.g., the minimum additional length or extension added to the front signal track 16-1 to provide sufficient distance between other components) is present, as indicated by the bidirectional arrow 80, it may be difficult to suppress or prevent electrical short circuits and / or manufacturing defects. In some embodiments, a large marginal length extension can increase the total area and / or layout complexity of the cell 10 and cause higher power consumption, thereby suppressing the electrical, operational, and performance characteristics of the cell 10.

[0044] Furthermore, the spacing margin between the power transmission contact via 60 and the gate contact layer 50 (such as...) Figure 1B The electrical, operational, and performance characteristics of cell 10 can be suppressed due to the superposition of the power delivery contact via 60 and the gate contact layer 50 in the second direction D2. As an example, limited spacing margins can cause process variations, yield losses, short nets, and / or parasitic capacitances, which can suppress the electrical, operational, and performance characteristics of cell 10.

[0045] Embodiments of this disclosure provide an integrated circuit device having cells connected to a BSPDN and a common power contact to enhance the electrical, operational, and performance characteristics of the cell array. As an example, since wider PDN tracks are incorporated as part of the BSPDN, the BSPDN and common power contact can simplify the design and implementation of the dicing layer for the first front-side signal track during the manufacturing process. Furthermore, due to the reduced complexity of implementing the dicing layer during manufacturing, the edge length extension can be reduced, thereby reducing the total cell area, layout complexity, and power consumption. As another example, since these components are disposed on different layers (e.g., the power delivery contact and gate contact layer may not be stacked in the second direction D2), the BSPDN and common power contact can increase the spacing margin between the power delivery contact and the gate contact layer.

[0046] Embodiments of this disclosure also provide integrated circuit devices having cells with selectively positioned and / or omitted diffusion interruption patterns to enhance the electrical, operational, and performance characteristics of the cell array. According to exemplary embodiments of this disclosure, diffusion interruption patterns at some cell boundaries may be removed or omitted, and power delivery areas including common power contacts may be incorporated into or combined with a BSPDN structure, which can result in a more compact layout / reduced area of ​​the integrated circuit device.

[0047] Reference Figures 2A to 2C This illustrates an integrated circuit device 100 according to some embodiments of the present disclosure. Figure 2A This is an example plan view relative to the back side or lower surface of the integrated circuit device 100. Figure 2B The integrated circuit device 100 is along Figure 2A Example sectional view with dashed line BB in the middle, and Figure 2C The integrated circuit device 100 is along Figure 2A Example section view with dashed line CC in the figure.

[0048] In some embodiments, the integrated circuit device 100 may include a BSPDN 150 on the lower (or back) surface 202L of the substrate 202. The integrated circuit device 100 may also include a first cell 200, power delivery contacts 240, 242, and a front signal track 212 on the upper surface 202U of the substrate 202. Although one cell 200 is shown, it should be understood that in other embodiments, the integrated circuit device 100 may have any number of cells. In some embodiments, the first cell 200 may include a diffusion interruption pattern 204, a cell structure 206, a MOL structure 214, an active gate pattern 222, and a source / drain pattern 224. Although one source / drain pattern 224 is shown... Figure 2A However, it should be understood that additional source / drain patterns 224 may be included in other embodiments.

[0049] The substrate 202 may include semiconductor materials (such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors). For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. The substrate 202 may be provided as a body wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0050] As shown in the following reference Figures 3A to 3B and Figures 4A to 4H As described in further detail, the diffusion interruption pattern 204 may be selectively positioned on the substrate 202 (e.g., one or more boundaries of cell 200). In some embodiments, the diffusion interruption pattern 204 may include one or more dummy gate patterns and insulating material including, but not limited to, single diffusion interruption (SDB) regions, dual diffusion interruption (DDB) regions, and / or shallow trench isolation (STI) regions.

[0051] In some embodiments, and referring to Figure 2B Cell structure 206 may have a stacked transistor structure including a first transistor and a second transistor vertically stacked on substrate 202. The first transistor may be a first type of transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor), and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), and in some embodiments, cell structure 206 may be or may include a stack of CMOS transistors. The first transistor and the second transistor may be stacked in any order to produce a stack including a top device (also referred to herein as the upper device or the second transistor, relative to the underlying substrate) and a bottom device (also referred to herein as the lower device or the first transistor, relative to the underlying substrate). The gate, channel, and source / drain regions of the upper and lower devices may also be referred to by the terms "upper" and "lower" (e.g., upper gate / lower gate, upper channel / lower channel, upper source / drain region / lower source / drain region, and upper inner spacer / lower inner spacer). While a three-dimensional stacked field-effect transistor (3DSFET) has been described herein, it should be understood that the cell structure 206 is not limited to the embodiments shown and described herein, and may include, for example, planar transistors, gate-all-around field-effect transistors (GAAFETs), recessed channel array transistors (RCATs), fin field-effect transistors (FinFETs), and multi-bridge channel field-effect transistors (MBCFETs). TM ) and / or any other type of transistor structure.

[0052] In some embodiments, the MOL structure 214 may include one or more interlayer insulating layers in which one or more conductive lines (e.g., one or more metal lines) and one or more conductive via plugs (e.g., one or more metal via plugs) are disposed. Various elements of the cell structure 206 may be electrically connected to one of the conductive lines of the MOL structure 214. In some embodiments, the front signal track 212 and the BSPDN 150 may be electrically connected to the cell structure 206 via the MOL structure 214. As an example, the MOL structure 214 may include a front via VA, a front intermediate layer CM, an upper epitaxial contact CA, front and rear contacts TB, a BSPDN contact RV, a lower epitaxial contact CR, and a gate contact layer 330 (in Figure 2C (shown in) and power transmission contact via 370 (in) Figure 2C (as shown in the diagram). However, the MOL structure 214 is not limited to the embodiments described herein.

[0053] In some embodiments, the active gate pattern 222 may be electrically connected to the first front-side signal track 212-1 and to the cell structure 206 via the gate contact layer 330. The source / drain pattern 224 may be electrically connected to the cell structure 206 via the MOL structure 214 (e.g., upper epitaxial contact CA), the front-side signal track 212, and the BSPDN 150. The active gate pattern 222 and the source / drain pattern 224 may comprise various types of conductive materials (such as doped polysilicon (Poly-Si), titanium nitride (TiN), tantalum nitride (TaN), molybdenum (Mo), cobalt (Co), nickel silicide (NiSi), and / or other known conductive materials).

[0054] In some embodiments, power delivery contacts 240, 242 may comprise known conductive materials and selectively connect various elements of cell structure 206 (e.g., source / drain regions of cell structure 206) to front signal rail 212 and / or BSPDN 150. In some embodiments, front signal rail 212 may be on the front (or upper) surface of cell structure 206 / substrate 202 and may comprise elements formed in a back-end process (BEOL) portion of device fabrication. Front signal rail 212 may comprise conductive elements and insulating elements (not shown) between conductive elements. Front signal rail 212 may be electrically connected to, for example, cell structure 206 (described further in detail below) via cell structures such as MOL structure 214, BSPDN 150, and additional cells.

[0055] In some embodiments, BSPDN 150 may include a power delivery network comprising one or more power delivery rails RB, which are electrically insulated from each other by a back-side insulator BILD2 on or within the back side of cell 200 and configured to receive drain voltage (VDD) and / or source voltage (VSS) from an external source. Different methods of front-side connection to the back side may include, for example, power delivery rails RB configured as front via back-side power rails (FV-BPR) and vias BC configured as direct back-side contacts. Power delivery rails RB may be electrically connected to cell structure 206 via MOL structure 214 and a first front-side signal rail 212-1. In some embodiments, an intermediate structure (not shown) may be disposed between substrate 202 and BSPDN 150 and separate substrate 202 from BSPDN 150. BSPDN 150 may increase power delivery efficiency in integrated circuit device 100, reduce the area used for power delivery in integrated circuit device 100, and / or improve voltage drop (i.e., IR drop) in integrated circuit device 100.

[0056] like Figure 2C As shown, the power transmission contact 242 can be electrically connected to one of the power transmission tracks RB of the BSPDN 150 via the power transmission contact via 370 of the MOL structure 214. The first front signal track 212-1 may not overlap with the power transmission contact 242, the power transmission contact via 370, and the BSPDN 150 in the second direction D2.

[0057] Therefore, the wider power delivery track RB of the BSPDN 150 disposed on the back side of cell 200 allows the dicing layer used to form the first front-side signal track 212-1 during the manufacturing process to be implemented with increased simplicity and enhanced efficiency and accuracy. Furthermore, the implementation of the dicing layer causes the active gate pattern 222 to have a reduced edge length extension (as described in further detail below), and thus reduces the total area, layout complexity, and power consumption of cell 200. Moreover, since there is no overlap between the power delivery contact via 370 and the gate contact layer 330 in the second direction D2, the spacing margin between the power delivery contact via 370 and the gate contact layer 330 can be increased relative to cell 10. Therefore, the increased spacing margin can result in reduced process manufacturing variations, yield losses, short networks, and / or parasitic capacitances in cell 200.

[0058] Reference Figures 3A to 3BSchematic plan view and circuit diagram of example integrated circuit device 400 are shown respectively. In some embodiments, integrated circuit device 400 includes units 402, 404 that may be similar to unit 200. In some embodiments, integrated circuit device 400 also includes a plurality of power delivery contacts 410 (e.g., power delivery contacts 240, 242), an active pattern 420 on substrate 405 (e.g., source / drain pattern 224), a diffusion interruption pattern 430 (e.g., diffusion interruption pattern 204) extending in the third direction D3 into substrate 405, a front-side signal track 440, and power delivery tracks 450-1, 450-2 (e.g., power delivery track RB) of BSPDN.

[0059] In some embodiments, units 402 and 404 may be combined (or stacked) with each other such that they together form a power transmission region PDR defined by the boundary 402-1 of unit 402 and the boundary 404-1 of unit 404. Boundaries 402-1 and 404-1 may be opposite each other in the first direction D1 with respect to the power transmission region PDR.

[0060] Unit 402 may also include a boundary 402-2 opposite to boundary 402-1 in the first direction D1, and unit 404 may also include a boundary 404-2 opposite to boundary 404-1 in the first direction D1. In some embodiments, boundaries 402-1 and 404-1 correspond to boundaries where adjacent units can be merged, and boundaries 402-2 and 404-2 correspond to predetermined boundaries where adjacent units are not merged. In some embodiments, one of the diffusion interruption patterns 430 or one of the active patterns 420 may be located on boundaries 402-2 and 404-2 of units 402 and 404, respectively.

[0061] In some embodiments, the power transmission contacts on each of the individual units 402, 404 may be selectively incorporated into the power transmission region PDR, such that they form power transmission contacts 410-1, 410-2 thereon (see below). Figures 4A to 4H As an example, power transmission contacts 410-1 and 410-2 may be disposed between or at boundaries 402-1 and 404-1 to electrically connect power transmission tracks 450-1 and 450-2 to the cell structure of cell 402 (e.g., a PMOS cell structure) and to the cell structure of cell 404 (e.g., a CMOS cell structure), such that the same or different voltages are applied to the respective cell structures of cells 402 and 404. That is, multiple power transmission tracks 450-1 and 450-2 may be configured to supply the same or different voltages. In some embodiments, the cell structure of cell 402 may be spaced apart from the cell structure of cell 404 in a first direction D1.

[0062] Furthermore, some of the active patterns of individual units 402 and 404 can be incorporated into the power transmission area PDR, so that they form active patterns 420-1 and 420-2 thereon (see below). Figures 4A to 4H As an example, active patterns 420-1 and 420-2 are disposed between or at boundaries 402-1 and 404-1. In some embodiments, the power transmission area PDR may not have a diffusion interruption pattern 430. That is, the diffusion interruption pattern 430 is not disposed in or on the power transmission area PDR, and is not between or at boundaries 402-1 and 404-1.

[0063] By merging the power transmission contacts and active patterns (such as) of each individual unit 402, 404 in the power transmission area PDR, Figure 3B As depicted in the circuit diagram 500, which corresponds to the integrated circuit device 400, and by omitting the diffusion interruption pattern 430 in the power delivery region PDR, the integrated circuit device 400 can have a more compact layout / reduced area and / or increased density.

[0064] In some embodiments, some of the front signal tracks 440 may employ a reduced marginal length extension feature relative to other front signal tracks 440. As an example, a front signal track (e.g., a front metal track) 440-1 that at least partially overlaps with power delivery contacts 410-1, 410-2 in the third direction D3 may have a longer length in the first direction D1 than the length of a front signal track 440-2 that does not overlap with power delivery contacts 410-1, 410-2 in the third direction D3. The relatively smaller length of the front signal track 440-2 (and the reduced marginal length extension) can reduce the overall area, layout complexity, and power consumption of the integrated circuit device 400.

[0065] The following is for reference Figures 4A to 4H A method for forming an integrated circuit device 400 is described. Figures 4A to 4H A schematic plan view depicting the intermediate processes for forming integrated circuit device 400 is shown. It should be understood that certain steps may not be performed in various embodiments, and the order of steps for forming integrated circuit device 400 is not limited to the examples shown and described herein.

[0066] Reference Figures 4A to 4BThe method may include removing a diffusion interruption pattern 430-1 from a first portion of the power transmission region, PDR-1. Removing the diffusion interruption pattern 430-1 may include, for example, performing a wet etching process and / or a dry etching process (such as plasma-enhanced etching), and using one or more mask patterns (not shown). The etching process may involve gases including, but not limited to, HBr, Cl2, O2, SF6, and N2. (See reference...) Figure 4C The method may include using a cut layer as a negative mask and reducing the length of the front signal tracks 440-1, 440-2 by performing a wet etching process and / or a dry etching process, thereby forming unit 402. The length may be reduced such that the front signal tracks 440-1, 440-2 do not overlap with the pre-existing power delivery contacts 410-1P, 410-2P on the first portion PDR-1 of the power delivery area in the third direction D3.

[0067] Reference Figures 4D to 4E The method may include a second portion PDR-2 of the power transmission region of alignment unit 404, such that the conductivity of the unit structures of units 402 and 404 enables the electrical connection between them. (Refer to...) Figures 4E to 4F The method may include removing the diffusion interruption pattern 430-2 on the second portion of the power transmission area PDR-2 using a wet etching process and / or a dry etching process. (See reference...) Figures 4F to 4G The method may include using a cut layer as a negative mask and reducing the length of the front signal track 440-3 by performing a wet etching process and / or a dry etching process, thereby forming unit 404. The length may be reduced such that the front signal track 440-3 does not overlap with the pre-existing power delivery contacts 410-3P, 410-4P on the second portion PDR-2 of the power delivery area in the third direction D3.

[0068] Reference Figure 4H Unit 402 may be combined with unit 404. As an example, combining units 402 and 404 may include removing redundant pre-power transmission contacts 410-1P and 410-2P (or pre-power transmission contacts 410-3P and 410-4P) to form power transmission contacts 410-1 and 410-2 and form a power transmission area PDR. Subsequently, power transmission contacts 410-1 and 410-2 may be electrically connected to the unit structure of each of units 402 and 404 and the BSPDN (not shown).

[0069] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, unless expressly defined herein, all terms shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0070] In the foregoing description, each example embodiment has been described with reference to a region of a specific conductivity type. It will be understood that devices with opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the foregoing embodiments. Therefore, it will be understood that this disclosure covers both n-channel and p-channel devices for each different device structure.

[0071] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. The terms “comprising,” “including,” and / or variations thereof indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0072] It will be understood that although the terms “first,” “second,” etc., are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0073] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, the element may be directly on or directly extending to the other element, or intermediate elements may exist. Conversely, when an element is referred to as being "directly on" or "directly" extending "on" another element, no intermediate elements exist. It will also be understood that when an element is referred to as being "connected" or "bonded" to another element, the element may be directly connected or bonded to the other element, or intermediate elements may exist. Conversely, when an element is referred to as being "directly connected" or "directly bonded" to another element, no intermediate elements exist.

[0074] Spatial relative terms such as “below”, “above”, “up”, “down”, “top”, or “bottom” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region based on a frame of reference (e.g., a base), as shown in the accompanying drawings. It will be understood that these terms are intended to cover different orientations of the device other than those depicted in the drawings.

[0075] Example embodiments are described herein with reference to the accompanying drawings, which may include cross-sectional views as schematic illustrations of idealized embodiments (and intermediate structures). Many different forms and embodiments are possible without departing from the teachings of this disclosure. Therefore, this disclosure should not be construed as limited to the example embodiments set forth herein. It will thus be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined herein. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Furthermore, variations in the shape of the illustrations are expected, for example, due to manufacturing techniques and / or tolerances.

[0076] Embodiments of this disclosure are also described with reference to manufacturing operations and flowcharts. It will be understood that the steps shown in the manufacturing operations and flowcharts need not be performed in the order shown.

[0077] The subject matter disclosed above is to be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the scope of this disclosure. Therefore, to the fullest extent permitted by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. A circuit device, comprising: Base; The first unit includes a first unit structure on the upper surface of the substrate; The second unit includes a second unit structure on the upper surface of the substrate; A signal track is located on the upper surface of the substrate, wherein the signal track is electrically connected to the first unit structure and / or the second unit structure; A first power transmission track is located on the lower surface of a base, wherein the lower surface of the base is opposite to the upper surface of the base in a first direction; and The power transmission area is defined by a first unit at a first boundary and by a second unit at a second boundary, wherein the second boundary is opposite to the first boundary in a second direction intersecting the first direction with respect to the power transmission area. The power transmission area includes a first power transmission contact element, and The first power transmission track is electrically connected to the first unit structure and the second unit structure via a first power transmission contact.

2. The circuit device according to claim 1, wherein, The first power transmission contact is located in the second direction between the first boundary and the second boundary.

3. The circuit device of claim 1, further comprising an active pattern on the substrate and a diffusion interruption pattern extending into the substrate. in, The first unit structure includes the first active pattern in the active pattern at the first boundary.

4. The circuit device according to claim 3, wherein, The first unit has no diffusion interruption pattern at the first boundary.

5. The circuit device according to claim 3, wherein, The first unit includes a third boundary, which is opposite to the first boundary in a second direction with respect to the first unit, and The first unit structure also includes, at the third boundary, a second active pattern in the active pattern or a first diffusion interruption pattern in the diffusion interruption pattern.

6. The circuit device according to claim 3, wherein, The second unit structure includes a third active pattern in the active pattern at the second boundary.

7. The circuit device according to claim 6, wherein, The second unit structure has no diffusion interruption pattern at the second boundary.

8. The circuit device according to claim 6, wherein, The second unit includes a fourth boundary, which is opposite to the second boundary in a second direction with respect to the second unit, and The second unit structure also includes, at the fourth boundary, either the fourth active pattern in the active pattern or the second diffusion interruption pattern in the diffusion interruption pattern.

9. The circuit device according to claim 1, wherein, The first signal track in the signal track has a first length in the second direction, and the second signal track in the signal track has a second length in the second direction that is smaller than the first length.

10. The circuit device according to claim 9, wherein, The second signal track does not overlap with the first power transmission contact in the first direction.

11. The circuit arrangement according to claim 10, wherein, The first signal track overlaps at least partially with the first power transmission contact in the first direction.

12. The circuit arrangement according to any one of claims 1 to 11, wherein, The power transmission area includes the second power transmission contact.

13. The circuit device according to claim 12, further comprising: The second power transmission track is electrically connected to the first unit structure and the second unit structure via a second power transmission contact.

14. The circuit arrangement according to claim 13, wherein, The first power transmission rail is configured to supply a first voltage, and wherein the second power transmission rail is configured to supply a second voltage different from the first voltage.

15. A circuit device, comprising: The substrate includes a diffusion interruption pattern; The first unit includes a first unit structure on the upper surface of the substrate; The second unit includes a second unit structure on the upper surface of the substrate; A signal track is located on the upper surface of the substrate, wherein the signal track is electrically connected to the first unit structure and / or the second unit structure; A first power transmission track is located on the lower surface of a base, wherein the lower surface of the base is opposite to the upper surface of the base in a first direction; and The power transmission area is defined by a first unit at a first boundary and by a second unit at a second boundary, wherein the second boundary is opposite to the first boundary in a second direction intersecting the first direction with respect to the power transmission area. The power transmission area includes a first power transmission contact and at least one active pattern. The first power transmission track is electrically connected to the first unit structure and the second unit structure via a first power transmission contact element, and There was no pattern of interruption in the power transmission area.

16. The circuit arrangement according to claim 15, wherein, The first unit structure includes a first active pattern of the at least one active pattern at a first boundary, and the second unit structure includes a second active pattern of the at least one active pattern at a second boundary.

17. The circuit arrangement according to claim 15, wherein, The first unit includes a third boundary, which is opposite to the first boundary in a second direction with respect to the first unit, and wherein the structure of the first unit also includes a first diffusion interruption pattern in the diffusion interruption pattern at the third boundary.

18. The circuit arrangement according to claim 17, wherein, The second unit includes a fourth boundary, which is opposite to the second boundary in a second direction with respect to the second unit, and wherein the structure of the second unit includes a second diffusion interruption pattern in the diffusion interruption pattern at the fourth boundary.

19. The circuit arrangement according to any one of claims 15 to 18, further comprising: The second power transmission track is electrically connected to the first unit structure and the second unit structure via the second power transmission contact in the power transmission area.

20. A circuit device, comprising: The substrate includes a diffusion interruption pattern; The first unit includes a first unit structure on the upper surface of the substrate; The second unit includes a second unit structure on the upper surface of the substrate, wherein the second unit structure is spaced apart from the first unit structure in a first direction; A signal track is located on the upper surface of the substrate, wherein the signal track is electrically connected to the first unit structure and / or the second unit structure; An electric transmission track is located on the lower surface of a base, wherein the lower surface of the base is opposite the upper surface of the base in a second direction intersecting a first direction; and The power transmission area is defined by a first unit at a first boundary and by a second unit at a second boundary, wherein the second boundary is opposite to the first boundary in a first direction with respect to the power transmission area. The power transmission area includes power transmission contacts and at least one active pattern, and has no diffusion interruption pattern. The power transmission track is electrically connected to the first unit structure and the second unit structure via power transmission contact elements. The first unit structure includes a first active pattern from the at least one active pattern at the first boundary. The second unit structure at the second boundary includes the second active pattern from the at least one active pattern. The first unit includes a third boundary, which is opposite to the first boundary in a first direction with respect to the first unit. The first unit structure also includes a first diffusion interruption pattern in the diffusion interruption pattern at the third boundary.

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