Memory access management method and system, multi-level page table structure, device, medium and product

Abstract

The invention provides a memory access management method and system, a multi-level page table structure, equipment, a medium and a product. The management method comprises the following steps: acquiring an access address corresponding to a computing accelerator; the access address comprises a plurality of fields for performing entry indexing on each level of page table in the multi-level page table structure; according to the field corresponding to each level of page table, performing entry indexing on each level of page table level by level until a target entry is indexed from the last level of page table; in the multi-level page table structure, a base address of a sub-page of a next-level page table is stored in an entry of a previous-level page table, and an allocation flag bit for determining whether a corresponding access address in an address space is allocated or not is stored in an entry of a last-level page table; and determining whether the access of the computing accelerator is legal or not according to the allocation flag bit in the target entry. The method can quickly detect whether the computing accelerator accesses an invalid memory address space, accesses an unallocated memory, accesses a released memory and other errors during operation.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a memory access management method, system, multi-level page table structure, device, medium and product. Background Technology

[0002] In heterogeneous computing systems, computing accelerators typically have a storage architecture independent of the host device. Their memory and address spaces are isolated from the host device and allocated and managed by the host device through a dedicated interface. Computing accelerators can execute user-written accelerator programs, such as kernel programs or firmware programs, to perform large-scale parallel computing tasks.

[0003] Because accelerator programs directly read and write memory addresses and typically execute a large number of threads or computing units simultaneously in a highly parallel manner, various memory access anomalies can easily occur when there are defects in the program logic or when the host device's memory management is out of sync with the accelerator's access behavior. These anomalies are difficult to detect in a timely manner. For example, these accelerator programs may encounter various memory access errors during runtime, including accessing unallocated memory, accessing freed memory, and memory out-of-bounds access. These memory access errors often lead to program crashes, data corruption, or unpredictable behavior. Summary of the Invention

[0004] The technical problem this disclosure aims to solve is that abnormal memory access situations are difficult to detect in a timely manner in the prior art. It provides a memory access management method, system, multi-level page table structure, device, medium, and product.

[0005] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0006] In a first aspect, embodiments of this disclosure provide a memory access management method applied to a computing accelerator, the management method comprising:

[0007] Obtain the access address corresponding to the computing accelerator; the access address includes multiple fields used for indexing entries in each level of the page table in the multi-level page table structure;

[0008] The entries in each level of the page table are indexed step by step according to the fields corresponding to each level of the page table until the target entry is indexed from the last level of the page table. In the multi-level page table structure, the entries of the upper level page table store the base address of the subpage of the lower level page table, and the entries of the last level page table store the allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

[0009] The access to the computing accelerator is determined based on the allocation flag in the target entry.

[0010] Optionally, after obtaining the access address corresponding to the computing accelerator, the method further includes:

[0011] Determine whether the access address is within the address space range;

[0012] When the access address is within the range, the step of indexing each level of the page table according to the field corresponding to each level of the page table is executed.

[0013] If the access address is not within the specified range, the access to the computing accelerator is determined to be invalid.

[0014] Optionally, determining whether access to the computing accelerator is legitimate based on the allocation flag bit in the target entry includes:

[0015] When the allocation flag is valid, the access to the computing accelerator is determined to be legitimate;

[0016] Alternatively, if the allocation flag is invalid, the access to the computing accelerator is determined to be illegitimate.

[0017] Optionally, after determining whether the access to the computing accelerator is legitimate based on the allocation flag bit in the target entry, the method further includes:

[0018] If the access to the computing accelerator is determined to be invalid, an error message is output; the error message includes one or more of the following: access address, base address of each page table, length of the access address, permissions of each page table, PC value, and allocation flag.

[0019] Optionally, the step of indexing each level of the page table according to the fields corresponding to each level of the page table until the target entry is indexed from the last level of the page table includes:

[0020] Starting from the initial address, index the current level page table based on the field in the access address that corresponds to the current level page table;

[0021] The base address of the next-level page table is determined from the entries of the current-level page table. The next-level page table is then indexed using the fields corresponding to the next-level page table in the access address, until the target entry in the last-level page table is reached.

[0022] Optionally, the entries in the last-level page table may also include a code segment flag.

[0023] The management method also includes:

[0024] The access to the computing accelerator is determined based on the code segment flag in the target entry and the data attributes of the computing accelerator.

[0025] Optionally, before obtaining the access address corresponding to the computing accelerator, the method further includes:

[0026] In response to a memory access instruction, a memory detection function is inserted before the memory access instruction; the memory detection function is used to call the steps of the memory access management method.

[0027] Secondly, embodiments of this disclosure provide a memory access management method applied to a host device, the management method comprising:

[0028] In response to memory allocation instructions, the address space corresponding to the computing accelerator is obtained;

[0029] A multi-level page table structure is constructed based on the address space; in the multi-level page table structure, the entry of the upper-level page table stores the base address of the subpage of the lower-level page table, and the entry of the last-level page table stores an allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

[0030] Optionally, constructing a multi-level page table structure based on the address space includes:

[0031] The number of subpages in the last-level page table is determined based on the address space and the subpage size of the last-level page table;

[0032] Configure the entries in the parent page table according to the base address of each subpage in the next-level page table, until the configuration of each level of the multi-level page table structure is completed.

[0033] Optionally, after constructing the multi-level page table structure based on the address space, the method further includes:

[0034] The entries of each subpage in the last-level page table are indexed according to the memory size and initial address allocated to the computing accelerator, and the allocation flag bit in each subpage entry is set to be valid.

[0035] Optionally, after obtaining the address space corresponding to the computed accelerator in response to the memory allocation instruction, the method further includes:

[0036] Get environment variables;

[0037] When the environment variable indicator is enabled, the step of constructing a multi-level page table structure based on the address space is executed.

[0038] Optionally, the method further includes:

[0039] In response to a memory release instruction, the allocation flag in the entry of each subpage in the last-level page table is set to invalid.

[0040] Thirdly, embodiments of this disclosure provide a multi-level page table structure, wherein the entries of the upper-level page table store the base address of the subpage of the lower-level page table, and the entries of the last-level page table store an allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

[0041] Fourthly, embodiments of this disclosure provide a memory access management system, the management system comprising:

[0042] The first acquisition module is used to acquire the access address corresponding to the computing accelerator; the access address includes multiple fields for indexing entries in each level of the page table in the multi-level page table structure;

[0043] The first indexing module is used to index entries in each level of the page table according to the fields corresponding to each level of the page table, until the target entry is indexed from the last level of the page table; in the multi-level page table structure, the entry of the upper level page table stores the base address of the subpage of the lower level page table, and the entry of the last level page table stores an allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

[0044] The first determining module is used to determine whether the access to the computing accelerator is legitimate based on the allocation flag bit in the target entry.

[0045] Fifthly, embodiments of this disclosure provide a memory access management system, the management system comprising:

[0046] The allocation module is used to obtain the address space corresponding to the compute accelerator in response to memory allocation instructions. In the multi-level page table structure, the entry of the upper-level page table stores the base address of the subpage of the lower-level page table, and the entry of the last-level page table stores an allocation flag bit to determine whether the corresponding access address in the address space has been allocated.

[0047] A construction module is used to construct a multi-level page table structure based on the address space.

[0048] In a sixth aspect, embodiments of this disclosure provide an electronic device, the electronic device including a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the memory access management method as described in either the first or second aspect.

[0049] In a seventh aspect, embodiments of this disclosure provide a computer-readable storage medium storing at least one instruction, at least one program, a code set, or an instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the memory access management method as described in any one of the first or second aspects.

[0050] Eighthly, this disclosure provides a computer program product, characterized in that, when the computer program is executed by a processor, it implements a memory access management method as described in either the first or second aspect.

[0051] The positive and progressive effects of this disclosure are as follows:

[0052] This disclosure indexes the multi-level page table structure level by level through fields in the access address. Based on the allocation flag in the target entry, it can quickly detect errors such as the computing accelerator accessing invalid memory address space, accessing unallocated memory, and accessing freed memory at runtime. At the same time, by managing the address space through the multi-level page table structure, it can maintain lower memory and time overhead compared to existing memory management methods, and it does not rely on specific hardware support and has good portability.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0054] Figure 1 A flowchart illustrating a memory access management method applied to a computing accelerator, provided as an exemplary embodiment of this disclosure;

[0055] Figure 2 A schematic diagram of a two-level page table structure provided for an exemplary embodiment of this disclosure;

[0056] Figure 3 A schematic diagram illustrating an access address provided for an exemplary embodiment of this disclosure;

[0057] Figure 4 A schematic diagram of subpage entries in a second-level page table provided for an exemplary embodiment of this disclosure;

[0058] Figure 5 A flowchart illustrating step S102 of a memory access management method provided for an exemplary embodiment of this disclosure;

[0059] Figure 6 A flowchart illustrating a memory access management method applied to a host device, provided as an exemplary embodiment of this disclosure;

[0060] Figure 7 A flowchart illustrating step S602 of a memory access management method provided for an exemplary embodiment of this disclosure;

[0061] Figure 8 A flowchart illustrating a memory access management method jointly executed by a user, a host device, and a computing accelerator, as provided in an exemplary embodiment of this disclosure;

[0062] Figure 9 A schematic diagram of a memory access management system applied to a computing accelerator, provided as an exemplary embodiment of this disclosure;

[0063] Figure 10 A schematic diagram of a module for a memory access management system applied to a host device, provided as an exemplary embodiment of this disclosure;

[0064] Figure 11 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of this disclosure. Detailed Implementation

[0065] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0066] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0067] Current detection methods for memory access errors in computing accelerators typically include the following:

[0068] (1) Software simulation-based method.

[0069] For example, the cuda-memcheck tool provided by CUDA runs the accelerator program through a software simulator and monitors and checks every memory access during the simulation. Because the program is not executed on real hardware but simulated instruction by instruction by software, its efficiency is significantly reduced, typically resulting in a speed reduction of 10 to 100 times or more. Therefore, this type of method is mainly suitable for the debugging phase and is difficult to apply to large-scale computing tasks in actual production environments.

[0070] (2) Red zone protection method.

[0071] Examples include AddressSanitizer (ASan) for central processing units (CPUs) and NVIDIA ComputeSanitizer and AMD ROCm Sanitizer r for GPUs. These methods set protected areas (red zones) before and after each allocated memory block and determine if out-of-bounds access has occurred by detecting whether the red zones have been modified.

[0072] To support red zone detection, this type of method requires maintaining shadow memory, i.e., establishing a corresponding state mapping for the original data memory. Typically, every 8 bytes of data requires an additional 1 byte of shadow memory, resulting in a basic memory overhead of approximately 12.5%. Additionally, several bytes of red zone space need to be allocated before and after each allocation block, and an isolation zone mechanism is used to delay the release of freed memory to detect use-after-free errors. Considering all these factors, the memory usage of this type of method in practical applications is typically 2 to 3 times that of the original memory, representing an additional overhead of 100% to 200%.

[0073] (3) Hardware-supported methods.

[0074] These methods rely on Memory Protection Units (MPUs) or similar mechanisms provided in the processor or accelerator hardware to detect unauthorized access by setting access permissions for specific memory regions. However, typical MPUs only support a limited number of protected regions, such as 8 to 16 regions. Each memory allocation region typically requires one protected region, and hardware registers need to be reconfigured every time memory is allocated or freed, involving privileged instruction execution and context switching operations, resulting in high configuration costs. Therefore, these methods are difficult to track large numbers of dynamically allocated memory regions and are only suitable for protecting a small number of critical memory regions.

[0075] (4) Static checking method at compile time.

[0076] This type of method performs static analysis on the program through the compiler to detect potential memory access errors. However, this method can only detect errors that can be deduced during the compilation phase; it cannot effectively detect memory access problems that arise dynamically at runtime based on input data or the execution path.

[0077] In summary, existing memory access detection schemes suffer from drawbacks such as high memory overhead, high time overhead, limited detection capabilities, and unsuitability of existing data structures for large-scale parallel access scenarios.

[0078] Based on this, an exemplary embodiment of the present disclosure provides a memory access management method, which is applied to computing accelerators, such as graphics processing units (GPUs), artificial intelligence accelerators (AI accelerators), neural network processors (NPUs), digital signal processors (DSPs), data processing units (DPUs), and so on. Figure 1 This is a flowchart illustrating a memory access management method provided in an embodiment of this disclosure. This specification provides method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive methods, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual system or server products, the method can be executed sequentially according to the embodiments or drawings, or in parallel (e.g., in a parallel processor or multi-threaded processing environment). Specifically, as shown... Figure 1 As shown, the method may include:

[0079] S101. Obtain the access address corresponding to the computing accelerator.

[0080] The access address includes multiple fields used to index entries in each level of the multi-level page table structure. The access address can be used to access the corresponding memory, and each field indicates the entries that need to be indexed in each level of the page table.

[0081] The multi-level page table structure mentioned in this embodiment will be described in more detail. This structure is typically built based on the memory size allocated to the computing accelerator. It includes two or more levels of page tables, with each level containing one or more subpages and one or more entries. Specifically, in this structure, the entries in the upper-level page table store the base address of the subpage in the lower-level page table, and the entries in the last-level page table store allocation flags to determine whether the corresponding access address in the address space has been allocated.

[0082] by Figure 2 The two-level page table structure in this example is used as an illustration of a multi-level page table structure, but is not limited to it. The two-level page table structure includes a first-level page table and a second-level page table. It is assumed that the address space of the computing accelerator is 64GB and the subpage size of the second-level page table is 4KB.

[0083] The first-level page table contains 4096 entries, each 8 bytes long. Each entry stores the base address of a subpage in the second-level page table, and the total size of the first-level page table is 32KB. The second-level page table contains 4096 subpages, each containing 4096 entries, each 1 byte long. Each entry stores an allocation flag to determine whether the corresponding access address in the address space has been allocated. Each subpage is 4KB in size, and the total size of the second-level page table is 16MB. In this embodiment, the total memory usage of the second-level page table structure is 32KB + 16MB ≈ 16.03MB, which is only 0.024% of the 64GB address space.

[0084] Alternatively, a three-level page table structure can be used as an example. The first-level page table contains 4096 entries, each 8 bytes long, storing the base address of a subpage in the second-level page table. The total size of the first-level page table is 32KB. The second-level page table contains 4096 subpages, each containing 4096 entries, each 8 bytes long, storing the base address of a subpage in the third-level page table. Each second-level page table is 32KB in size, for a total size of 128MB. The third-level page table contains 1,616,777,216 subpages, each containing 4096 entries, each 1 byte long, for a total size of 4KB. Each entry stores an allocation flag to determine whether the corresponding access address in the address space has been allocated. The total size of the third-level page table is 16MB. In this embodiment, the memory size of the three-level page table structure is 332KB + 128MB. The three-level page table structure is typically suitable for address spaces exceeding 64GB or scenarios requiring finer-grained allocation tracking.

[0085] For information on configuring the access address, please refer to [link / reference]. Figure 3 In this implementation, the access address is set to 64 bits (i.e., bits [63:0]). Since the subpage size is 4KB, the lower 12 bits (bits [11:0]) are set as the page offset, and the remaining higher 24 bits (bits [35:12]) are used as the valid address. Bits [35:24] in the access address are used as the field for the first-level page table entry index, corresponding to the 4096 entries in the first-level page table. Bits [23:12] in the access address are used as the field for the second-level page table entry index, corresponding to the 4096 entries in the second-level page table. The last 28 bits (i.e., bits 63:36] in the access address are reserved for future expansion needs.

[0086] In one implementation, after step S101, the following is also included:

[0087] Determine if the access address is within the address space range. Assuming the address space is 64GB, compare the size of the space corresponding to the access address with 64GB, or compare the size of the space corresponding to the access address plus a data length minus 1 with 64GB. This will determine if the access address is within the address space range. If the access address is within the range, proceed to step S102; if the access address is not within the range, determine the access point of the computing accelerator.

[0088] It's illegal.

[0089] S102. Index each level of the page table according to the fields corresponding to each level of the page table, until the target entry is indexed from the last level of the page table.

[0090] Figure 4 As an example of an entry in the last-level page table, bit 0 is the allocation flag (1 = allocated, 0 = unallocated), bit 1 is the code segment flag (1 = code segment, 0 = data segment), and bits 2-7 are reserved for future expansion, but are not limited to this and can be configured according to actual needs.

[0091] In one embodiment, step S102 is described in detail below, see [link to description]. Figure 5 Specifically, it includes:

[0092] S1021. Starting from the initial address, index the current level page table based on the field in the access address that corresponds to the current level page table.

[0093] The initial address is typically sent by the host device to the computing accelerator for storage after the multi-level page table structure is constructed.

[0094] Taking indexing entries in the first-level page table within a second-level page table structure as an example, we first construct the entry index L1 of the first-level page table based on the field corresponding to the first-level page table in the access address. L1 = (access address >> 24) & 0xFFF, where >> 24 is a bitwise operation formula. Since bits [35:24] in the access address are used as the field for the first-level page table entry index, >> 24 shifts the 36-bit access address binary string 24 bits to the right, thus locating the field for the first-level page table entry index. & 0xFFF is a bitwise AND operation; 0xFFF is a hexadecimal number, which is 1111 1111 1111 (12 ones) in binary, ensuring that the final result retains only the last 12 bits of data, clearing all the preceding bits to zero. The entries in the first-level page table store the base address of the subpages in the second-level page table.

[0095] S1022. Determine the base address of the next-level page table from the entries of the current-level page table, and index the next-level page table by combining the corresponding fields in the access address, until the target entry in the last-level page table is indexed.

[0096] Specifically, after determining the base address of the next-level page table from each entry in the parent page table, an index for the next-level page table is first constructed based on the fields corresponding to the access address. Then, the offset corresponding to the index is added to the base address to determine the corresponding entry in the next-level page table. In some cases, after determining the base address of the next-level page table from each entry in the parent page table, the validity of the base address of the next-level page table can be verified first.

[0097] Taking indexing entries in a second-level page table within a second-level page table structure as an example, an index L2 is constructed based on the field corresponding to the second-level page table in the access address, where L2 = (access address >> 12) & 0xFFF. Using the base address of the second-level page table as the starting position of the index, the offset corresponding to the second-level page table index L2 is added to the base address to obtain the position of the corresponding entry in the second-level page table. Since the second-level page table is the last level page table, the indexed entry in the second-level page table is the target entry, which stores an allocation flag.

[0098] S103. Determine whether the access to the computing accelerator is legitimate based on the allocation flag in the target entry.

[0099] The allocation flag is used to determine whether the corresponding access address in the address space has been allocated. When the allocation flag is valid, it indicates that the host device has allocated memory for the corresponding access address; when the allocation flag is invalid, it indicates that the host device has not allocated memory for the corresponding access address. Illegal access to the computing accelerator includes accessing invalid memory address space, accessing unallocated memory, and accessing freed memory.

[0100] In this implementation, setting the allocation flag to 1 indicates validity, and setting it to 0 indicates invalidity. Therefore, step S103 specifically includes: determining that access to the computing accelerator is valid when the allocation flag is valid; or determining that access to the computing accelerator is invalid when the allocation flag is invalid.

[0101] In one embodiment, if it is determined that access to the computing accelerator is illegal, the method further includes: outputting error information. The error information includes one or more of the following: the access address, the base address of each page table level, the length of the access address, the permissions of each page table level, the PC (program counter) value, and allocation flags.

[0102] In one embodiment, such as Figure 4As shown in the example, the entries in the last-level page table also include code segment flags. Based on this, the management method also includes:

[0103] The access to the computing accelerator is determined based on the code segment flags in the target entry and the data attributes of the computing accelerator.

[0104] Specifically, the code segment flag is used to indicate whether the allocated memory attribute is code or data. Typically, a code segment flag of 1 indicates code, and a code segment flag of 0 indicates data. Only when both the memory attribute and the data attribute match can the accelerator access be determined to be legitimate. For example, if the memory attribute is code and the data attribute is data, the accelerator access is determined to be illegitimate; if both the memory attribute and the data attribute are code, the accelerator access is determined to be legitimate. Similarly, if the memory attribute is data and the data attribute is code, the accelerator access is determined to be illegitimate; if both the memory attribute and the data attribute are data, the accelerator access is determined to be legitimate.

[0105] In one embodiment, before step S101, a memory detection function is inserted before the memory access instruction in response to the memory access instruction; the memory detection function is used to call all steps of the memory access management method in this embodiment.

[0106] Specifically, memory access instructions are typically generated by the computing accelerator. The compiler identifies all memory access instructions that access the global memory of the computing accelerator device and automatically inserts memory detection functions into these instructions to invoke code that executes all steps of the aforementioned memory access management methods. The compiler can be located in the host device or within the computing accelerator. The compiler inserts a memory detection function before each memory access instruction. This function can execute all steps of the memory access management methods described in the above embodiments and can also be used to pass data such as PC values, access addresses, access lengths, and access permissions. During instrumentation, the compiler does not replace the original instructions; it only inserts them before the instructions to ensure that the program logic remains unchanged while increasing the access management capabilities of the computing accelerator.

[0107] In this embodiment, the multi-level page table structure is indexed level by level through the fields in the access address. Based on the allocation flag in the target entry, errors such as whether the computing accelerator accesses invalid memory address space, accesses unallocated memory, or accesses freed memory can be quickly detected at runtime. At the same time, the address space is managed through the multi-level page table structure, which can maintain lower memory and time overhead compared to existing memory management methods, and does not rely on specific hardware support, and has good portability.

[0108] An exemplary embodiment of this disclosure also provides a method for managing memory access, see [link to relevant documentation]. Figure 6Applied to the host device, the management methods include:

[0109] S601: In response to a memory allocation instruction, obtain the address space corresponding to the computing accelerator.

[0110] Specifically, the host device needs an independent multi-level page table structure for each process and / or each compute accelerator to achieve memory detection isolation between processes and compute accelerators. On the host device side, a page table memory block is allocated for each device within each process. This page table memory stores the multi-level page table structure. The multi-level page table structures of different processes are independent of each other, and each multi-level page table structure manages the memory of its corresponding compute accelerator. Furthermore, since each device has an independent address space, different multi-level page table structures within the same process also require independent multi-level page table structures.

[0111] S602. Construct a multi-level page table structure based on the address space.

[0112] In the multi-level page table structure, the entries of the upper-level page table store the base address of the subpage of the lower-level page table, and the entries of the last-level page table store an allocation flag bit that determines whether the corresponding access address in the address space has been allocated. For details of the multi-level page table structure, please refer to the content described in the above embodiments.

[0113] For details, see Figure 7 Step S602 includes:

[0114] S6021. Determine the number of subpages in the last-level page table based on the address space and the subpage size of the last-level page table.

[0115] Taking an address space of 64GB as an example and a subpage size of 4KB in the last-level page table as an example, the number of subpages is 64GB÷4KB=4096. At the same time, the entries in each subpage of the last-level page table are cleared to initialize the last-level page table.

[0116] S6022. Configure the entries in the upper-level page table according to the base address of each subpage in the lower-level page table, until the configuration of each level of the page table in the multi-level page table structure is completed.

[0117] Taking a two-level page table structure as an example, all entries in the page tables of the two-level page table structure are cleared to zero, and 4096 entries are filled in the first-level page table according to the base address of each subpage in the second-level page table, thus completing the configuration of each level of page table in the multi-level page table structure.

[0118] In one embodiment, after step S602, the entries of each subpage in the last-level page table are marked to indicate that memory has been allocated. Specifically, this includes indexing the entries of each subpage in the last-level page table according to the memory size allocated to the computing accelerator and the initial address, and setting the allocation flag bit in each subpage entry to be valid. The memory size is obtained by the user or host device from the address space according to the actual needs of the computing accelerator.

[0119] Using a two-level page table structure as an example, based on the initial address and memory size (assuming 1MB and 4KB per subpage), the number of subpages in the two-level page table is calculated to be 256. The ending address (0x200000) can be calculated from the initial address (0x100000) and the number of subpages. First, the entry indexes for each level of the two-level page table are constructed based on the initial address: the index L1 = (address >> 24) & 0xFFF is constructed for the first-level page table. The base address of the subpage in the second-level page table is obtained from the first-level page table, and then the index L2 = (address >> 12) & 0xFFF is calculated to obtain the entry for the subpage in the second-level page table. Next, for each entry in the second-level page table, the allocation flag is set to 1. Additionally, if the memory attribute is code, the code segment flag is set to 1. The indexes are iterated through all subpages in 4KB increments until the ending address is reached, ensuring that all allocated subpages are marked.

[0120] In one embodiment, after the computing accelerator finishes using memory, the entries for each subpage in the last-level page table are cleared to indicate that the memory has been released. The method further includes: in response to a memory release instruction, setting the allocation flag bit in the entry for each subpage in the last-level page table to invalid.

[0121] Using a two-level page table structure as an example, based on the initial allocated address and page size (assuming a subpage size of 4KB), the process begins by constructing the entry index for each level of the two-level page table structure based on the initial address: The first-level page table index L1 = (address >> 24) & 0xFFF is constructed. The base address of the subpage in the second-level page table is obtained from the first-level page table, and then the second-level page table index L2 = (address >> 12) & 0xFFF is calculated to obtain the subpage entry in the second-level page table. Next, for each subpage entry in the second-level page table, the allocation flag is set to 0. This process is repeated for all subpages in 4KB increments until the end address, ensuring that the allocation flag is invalidated in every subpage entry in the last-level page table. By setting the allocation flag to 0 after a memory release, errors caused by reusing the released memory are detected. The released memory is marked as unallocated, and subsequent access will trigger an error.

[0122] In one embodiment, after step S601, the following is also included:

[0123] Obtain environment variables. If the environment variable indicator is enabled, proceed to step S601.

[0124] Specifically, when the environment variable is set to 1, it is determined that the multi-level page table structure is enabled, and step 601 is executed. By setting the environment variable, users can enable the multi-level page table structure during development and debugging phases and disable it in the production environment, providing flexibility.

[0125] The following is combined Figure 8 This document provides an overall description of the memory management method in the above embodiments from three perspectives: the user, the host device, and the computing accelerator. In this embodiment, the multi-level page table structure is a two-level page table structure. Specifically:

[0126] (a) Initialization.

[0127] 1. Before launching the application, users should set the environment variable: export MEMCHECK=1.

[0128] 2. In response to memory allocation instructions, obtain the environment variable, and if the environment variable is 1, construct a multi-level page table structure.

[0129] 3. Construct a multi-level page table structure:

[0130] a. Calculate page table memory:

[0131] First-level page table: 4096 entries, each entry is 8 bytes, and the memory size is 32KB.

[0132] Second-level page table: 4096 subpages, each subpage is 4KB, and the memory size is 16MB.

[0133] The total memory usage of the page tables in the two-level page table structure is 16.03MB.

[0134] b. Initialize the page table:

[0135] The first-level page table starts at the initial address and occupies the first 32KB. The second-level page table starts at an offset of 32KB from the initial address, with each subpage being 4KB. It iterates through 4096 entries in the first-level page table, storing the base address of the corresponding subpage in the second-level page table within each entry.

[0136] c. Send the initial address to the computing accelerator.

[0137] (ii) Memory allocation.

[0138] 1. Call the computing accelerator memory allocation interface to allocate 1MB of memory to the computing accelerator. The subpage size of the second-level page table is calculated based on the memory size and the subpage size, resulting in 256 subpages in the second-level page table.

[0139] 2. The accelerator obtains its initial address: 0x100000.

[0140] 3. Update the second-level page table structure: process each subpage in a loop (256 times in total), where the address of the first iteration is equal to the initial address 0x100000.

[0141] The first-level page table entry index L1 is constructed based on the address: (0x100000 >> 24) & 0xFFF = 0

[0142] The index of the second-level page table is constructed based on the address and the base address of the subpage in the second-level page table stored in the first-level page table entry: (0x100000 >> 12) & 0xFFF = 256. Specifically, an offset of 256 is added to the base address of the subpage in the second-level page table to obtain the corresponding entry in the second-level page table subpage, and the allocation flag bit 0 in the entry is set to 1, indicating that it has been allocated.

[0143] Continuing the iteration, the address of the 256th iteration is equal to 0x1FF000. 0x1FF000 + 4096 = 0x200000, which is equal to the end address, and the loop ends.

[0144] 4. Send the initial address 0x100000 to the user.

[0145] (iii) Compiling the code for the computing accelerator.

[0146] 1. Obtain the memory detection function of the user-written memory management method.

[0147] 2. The compiler identifies memory allocation instructions and automatically instrumentes memory detection functions.

[0148] (iv) Detection during accelerator operation: legitimate access.

[0149] 1. Responds to memory access instructions.

[0150] 2. The heterogeneous computing accelerator obtains access address 0x100000.

[0151] 3. Execution:

[0152] a. Determine whether the access address is within the address space range.

[0153] 0x100000 < 64GB, passed.

[0154] 0x100000 + 4 - 1 = 0x100003 < 64GB, passed.

[0155] b. Check the allocation status:

[0156] Determine the initial address: 0x100000, and the ending address: 0x100000.

[0157] The entry index L1 of the first-level page table is constructed based on the access address: (0x100000 >> 24) & 0xFFF = 0.

[0158] The index L2 of the second-level page table is constructed based on the address and the base address of the subpage in the second-level page table stored in the first-level page table entry: (0x100000 >> 12) & 0xFFF = 256.

[0159] Based on index L2, retrieve the allocation flag bit 0 = 1 stored in the entry of the subpage of the second-level page table, indicating that it has been allocated and access is legal.

[0160] c. Test passed.

[0161] 4. Continue executing memory access instructions to read data from memory according to the access address.

[0162] (v) During the operation of the computing accelerator: illegal access.

[0163] 1. Responds to memory access instructions.

[0164] 2. Obtain the access address for the heterogeneous computing accelerator: 0x223880.

[0165] 2. Execution:

[0166] a. Determine if the access address is within the address space range:

[0167] 0x223880 < 64GB, passed.

[0168] 0x223880 + 4 - 1 = 0x223883 < 64GB, passed.

[0169] d. Check the allocation status:

[0170] Initial address: 0x223000, end address: 0x223000.

[0171] The entry index L1(0x223880 >> 24) & 0xFFF = 0 is constructed based on the access address to build the first-level page table entry index.

[0172] The index L2 of the second-level page table is constructed based on the address and the base address of the subpage in the second-level page table stored in the first-level page table entry: (0x223880 >> 12) & 0xFFF = 563.

[0173] Based on index L2, retrieve the allocation flag bit 0 = 0 stored in the entry of the subpage of the second-level page table, indicating that it is unallocated and an illegal access.

[0174] Output error message.

[0175] (vi) Memory release.

[0176] 1. Responds to memory release commands.

[0177] 2. Clear the markers for entries in the subpages of the second-level page table:

[0178] Determine the initial address: 0x100000, determine the ending address: 0x100000, and process each subpage in a loop (256 times in total).

[0179] First time: Index L1=0, Index L2=256, clear the allocation flag bit;

[0180] Second time: Index L1=0, Index L2=257, clear the allocation flag bit; ...

[0182] 256th time: Index L1=0, Index L2=511, memory markers are cleared.

[0183] The memory access management method provided in this embodiment has the following advantages: First, it has low memory overhead. The memory usage of a single process and a single device is 16.03MB (0.024% of the 64GB address space). The memory usage of a single process and N devices is 16.03MB × N. The memory usage of M processes and a single device is 16.03MB × M. The memory usage of M processes and N devices is 16.03MB × M × N. In actual scenarios, even if 10 processes each use 2 devices (total overhead of about 320MB), the overhead is still very small (usually <1%) compared to the GB-level memory that each device may use. The memory overhead is far lower than 2-3 times (100-200%) of the red zone protection method. Second, it isolates processes. Each computing accelerator of each process independently establishes a multi-level page table structure to achieve memory detection isolation between processes and computing accelerators and avoid interference. Third, it is more efficient. Taking the two-level page table structure as an example, each memory access only requires 2 array indices, with a time complexity of O(1). Compared with the software simulation method, it is 10-100 times slower, with higher efficiency and better performance. Fourth, it has strong detection capabilities. By setting allocation flags, it can detect errors such as accessing unallocated memory, reusing memory after freeing it, and address range overflow. Fifth, it has strong real-time performance. It detects and reports errors immediately upon occurrence, making it easy to pinpoint the root cause of the problem. Sixth, it has strong versatility. It does not rely on specific hardware support and can be applied to various computing accelerator architectures. Seventh, it has good scalability. Eight bits are set in the entries of the second-level page table, with bits 2-7 reserved for future expansion. This allows for recording more memory attributes (such as code segment flags), and the second-level page table structure can be extended to three or four levels, supporting larger address spaces. Eighth, it has strong ease of use. Controlled by environment variables, it requires no modification to the source code. Memory detection functions perform automatic instrumentation, eliminating the need for manual checking code additions by the user. Furthermore, it provides detailed error information for easy debugging. Ninth, it is parallel-friendly. The second-level page table structure is naturally suitable for parallel access, preventing conflicts when different threads query different addresses. Tenth, it provides precise location. The PC value included in the error message allows users to accurately locate the erroneous instruction, and combined with disassembly, the source code location can be found.

[0184] This disclosure provides an exemplary embodiment of a multi-level page table structure, which can be found in the following examples: Figure 2 In a multi-level page table structure, the entries of the upper-level page table store the base address of the subpage of the lower-level page table, and the entries of the last-level page table store allocation flags used to determine whether the last-level page table has been allocated.

[0185] The advantages of the multi-level page table structure provided in this embodiment compared to existing technologies are as follows: Compared to hash tables: no hash collisions, strict O(k) access time (k is the page table level), good cache locality, suitable for large-scale parallel access; Compared to BST / balanced tree: no need for dynamic balancing operations, fixed query path, no lock contention; Compared to bitmaps: can be flexibly extended to any large address space, no need to pre-allocate the entire bitmap; Compared to allocation block metadata tables: no need to store the base address and size of each allocation, only a fixed overhead of 1 byte / 4KB page.

[0186] An exemplary embodiment of this disclosure also provides a memory access management system, see [link to relevant documentation]. Figure 9 The management system includes:

[0187] The first acquisition module 91 is used to acquire the access address corresponding to the computing accelerator; the access address includes multiple fields for indexing entries in each level of the page table in the multi-level page table structure.

[0188] The first index module 92 is used to index entries in each level of the page table according to the fields corresponding to each level of the page table, until the target entry is indexed from the last level of the page table; in the multi-level page table structure, the entry of the upper level page table stores the base address of the subpage of the lower level page table, and the entry of the last level page table stores an allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

[0189] The first determining module 93 is used to determine whether the access to the computing accelerator is legitimate based on the allocation flag bit in the target entry.

[0190] In one embodiment, the system further includes:

[0191] The second determining module is used to determine whether the access address is within the range of the address space; when the access address is within the range, the first indexing module 82 is executed; when the access address is not within the range, the access to the computing accelerator is determined to be invalid.

[0192] In one embodiment, the first determining module 93 is further configured to:

[0193] When the allocation flag is valid, the access to the computing accelerator is determined to be legitimate;

[0194] Alternatively, if the allocation flag is invalid, the access to the computing accelerator is determined to be illegitimate.

[0195] In one embodiment, the system further includes:

[0196] The output module is used to output error information when it is determined that the access to the computing accelerator is illegal; the error information includes one or more of the following: access address, base address of each page table, length of access address, permissions of each page table, PC value, and allocation flag.

[0197] In one embodiment, the first indexing module 92 is further configured to:

[0198] Starting from the initial address, index the current level page table based on the field in the access address that corresponds to the current level page table;

[0199] The base address of the next-level page table is determined from the entries of the current-level page table. The next-level page table is then indexed using the fields corresponding to the next-level page table in the access address, until the target entry in the last-level page table is reached.

[0200] In one embodiment, the entries in the last-level page table further include a code segment flag; the system also includes:

[0201] The access to the computing accelerator is determined based on the code segment flag in the target entry and the data attributes of the computing accelerator.

[0202] In one embodiment, the system further includes:

[0203] In response to a memory access instruction, a memory detection function is inserted before the memory access instruction; the memory detection function is used to call the module of the management system that performs the memory access.

[0204] An exemplary embodiment of this disclosure also provides a memory access management system, see [link to relevant documentation]. Figure 10 The management system includes:

[0205] The allocation module 101 is used to obtain the address space corresponding to the computed accelerator in response to memory allocation instructions.

[0206] The construction module 102 is used to construct a multi-level page table structure based on the address space. In this multi-level page table structure, the entries of the upper-level page table store the base address of the subpage of the lower-level page table, and the entries of the last-level page table store an allocation flag bit that determines whether the corresponding access address in the address space has been allocated. For details of the multi-level page table structure, please refer to the description in the above embodiments.

[0207] In one embodiment, the building module 102 is further configured to:

[0208] The number of subpages in the last-level page table is determined based on the address space and the subpage size of the last-level page table;

[0209] Configure the entries in the parent page table according to the base address of each subpage in the next-level page table, until the configuration of each level of the multi-level page table structure is completed.

[0210] In one embodiment, the system further includes:

[0211] The second indexing module is used to index the entries of each subpage in the last-level page table according to the memory size and initial address allocated by the computing accelerator, and to set the allocation flag bit in the entries of each subpage to be valid.

[0212] In one embodiment, the system further includes:

[0213] The second acquisition module is used to acquire environment variables. When the environment variable indicates that the environment is enabled, the construction module 102 is executed.

[0214] In one embodiment, the system further includes:

[0215] The release module is used to set the allocation flag bit in the entry of each subpage in the last-level page table to invalid in response to a memory release instruction.

[0216] For the system embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The system embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this disclosure according to actual needs.

[0217] This disclosure also provides an electronic device in one example embodiment. Figure 11 This is a schematic diagram of the structure of an electronic device according to an example embodiment of the present disclosure. The electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor. When the processor executes the computer program, it implements the method of any of the above embodiments. Figure 11 The electronic device 110 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0218] like Figure 11 As shown, the electronic device 110 can be manifested as a general-purpose computing device, such as a server device. The components of the electronic device 110 may include, but are not limited to: at least one processor 111, at least one memory 112, and a bus 113 connecting different system components (including memory 112 and processor 111).

[0219] Bus 113 includes a data bus, an address bus, and a control bus.

[0220] The memory 112 may include volatile memory, such as random access memory (RAM) 1121 and / or cache memory 1122, and may further include read-only memory (ROM) 1123.

[0221] The memory 112 may also include a program tool 1125 (or utility) having a set (at least one) program module 1124, such program module 1124 including but not limited to: an operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0222] The processor 111 performs various functional applications and data processing, such as the methods provided in any of the above embodiments, by running computer programs stored in the memory 112.

[0223] Electronic device 110 can also communicate with one or more external devices 114 (e.g., keyboard, pointing device, etc.). This communication can be performed via input / output (I / O) interface 115. Furthermore, electronic device 110 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public network, such as the Internet) via network adapter 116. As shown, network adapter 116 communicates with other modules of electronic device 110 via bus 113. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 110, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems.

[0224] It should be noted that although several units / modules or sub-units / modules of the electronic device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0225] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method provided in any of the above embodiments.

[0226] The readable storage medium may be more specifically adopted, including but not limited to: portable disk, hard disk, random access memory, read-only memory, erasable programmable read-only memory, optical storage device, magnetic storage device, or any suitable combination thereof.

[0227] In possible implementations, embodiments of this disclosure can also be implemented as a program product including program code, which, when the program product is run on a terminal device, causes the terminal device to execute the method implementing any of the above embodiments.

[0228] The program code for executing this disclosure can be written in any combination of one or more programming languages. The program code can be executed entirely on a user device, partially on a user device, as a standalone software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0229] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A memory access management method, characterized in that, The management method, applied to computing accelerators, includes: Obtain the access address corresponding to the computing accelerator; the access address includes multiple fields used for indexing entries in each level of the page table in the multi-level page table structure; The entries in each level of the page table are indexed step by step according to the fields corresponding to each level of the page table until the target entry is indexed from the last level of the page table. In the multi-level page table structure, the entries of the upper level page table store the base address of the subpage of the lower level page table, and the entries of the last level page table store the allocation flag bit that determines whether the corresponding access address in the address space has been allocated. The access to the computing accelerator is determined based on the allocation flag in the target entry.

2. The management method as described in claim 1, characterized in that, After obtaining the access address corresponding to the computing accelerator, the process further includes: Determine whether the access address is within the address space range; When the access address is within the range, the step of indexing each level of the page table according to the field corresponding to each level of the page table is executed. If the access address is not within the specified range, the access to the computing accelerator is determined to be invalid.

3. The management method as described in claim 1, characterized in that, The step of determining whether access to the computing accelerator is legitimate based on the allocation flag bit in the target entry includes: When the allocation flag is valid, the access to the computing accelerator is determined to be legitimate; Alternatively, if the allocation flag is invalid, the access to the computing accelerator is determined to be illegitimate.

4. The management method as described in claim 1, characterized in that, After determining whether the access to the computing accelerator is legitimate based on the allocation flag bit in the target entry, the method further includes: If the access to the computing accelerator is determined to be invalid, an error message is output; the error message includes one or more of the following: access address, base address of each page table, length of the access address, permissions of each page table, PC value, and allocation flag.

5. The management method as described in claim 1, characterized in that, The process of indexing entries in each level of the page table according to the fields corresponding to each level of the page table, until the target entry is indexed from the last level of the page table, includes: Starting from the initial address, index the current level page table based on the field in the access address that corresponds to the current level page table; The base address of the next-level page table is determined from the entries of the current-level page table. The next-level page table is then indexed using the fields corresponding to the next-level page table in the access address, until the target entry in the last-level page table is reached.

6. The management method as described in claim 1, characterized in that, The entries in the last-level page table also include code segment flags; The management method also includes: The access to the computing accelerator is determined based on the code segment flag in the target entry and the data attributes of the computing accelerator.

7. The management method as described in claim 1, characterized in that, Before obtaining the access address corresponding to the computing accelerator, the process also includes: In response to a memory access instruction, a memory detection function is inserted before the memory access instruction; the memory detection function is used to call the steps of the memory access management method.

8. A method for managing memory access, characterized in that, The management method, applied to host devices, includes: In response to memory allocation instructions, the address space corresponding to the computing accelerator is obtained; A multi-level page table structure is constructed based on the address space; in the multi-level page table structure, the entry of the upper-level page table stores the base address of the subpage of the lower-level page table, and the entry of the last-level page table stores an allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

9. The management method as described in claim 8, characterized in that, The construction of a multi-level page table structure based on the address space includes: The number of subpages in the last-level page table is determined based on the address space and the subpage size of the last-level page table; Configure the entries in the parent page table according to the base address of each subpage in the next-level page table, until the configuration of each level of the multi-level page table structure is completed.

10. The management method as described in claim 8, characterized in that, After constructing the multi-level page table structure based on the address space, the method further includes: The entries of each subpage in the last-level page table are indexed according to the memory size and initial address allocated to the computing accelerator, and the allocation flag bit in each subpage entry is set to be valid.

11. The management method as described in claim 8, characterized in that, After obtaining the address space corresponding to the computed accelerator in response to the memory allocation instruction, the process further includes: Get environment variables; When the environment variable indicator is enabled, the step of constructing a multi-level page table structure based on the address space is executed.

12. The management method as described in claim 8, characterized in that, The method further includes: In response to a memory release instruction, the allocation flag in the entry of each subpage in the last-level page table is set to invalid.

13. A multi-level page table structure, characterized in that, In the multi-level page table structure, the entries of the upper-level page table store the base address of the subpage of the lower-level page table, and the entries of the last-level page table store an allocation flag bit that determines whether the corresponding access address in the address space has been allocated.

14. A memory access management system, characterized in that, The management system, applied to a computing accelerator, includes: The first acquisition module is used to acquire the access address corresponding to the computing accelerator; the access address includes multiple fields for indexing entries in each level of the page table in the multi-level page table structure; The first indexing module is used to index entries in each level of the page table according to the fields corresponding to each level of the page table, until the target entry is indexed from the last level of the page table; in the multi-level page table structure, the entry of the upper level page table stores the base address of the subpage of the lower level page table, and the entry of the last level page table stores an allocation flag bit that determines whether the corresponding access address in the address space has been allocated. The first determining module is used to determine whether the access to the computing accelerator is legitimate based on the allocation flag bit in the target entry.

15. A memory access management system, characterized in that, The management system, applied to host devices, includes: The allocation module is used to obtain the address space corresponding to the computing accelerator in response to memory allocation instructions; A construction module is used to construct a multi-level page table structure based on the address space.

16. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the memory access management method as described in any one of claims 1-12.

17. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the memory access management method as described in any one of claims 1-12.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements a memory access management method as described in any one of claims 1-12.

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