FLASH prefetching and caching system based on AHB and implementation method of FLASH prefetching and caching system
By designing an AHB-based FLASH prefetch cache system, the problems of slow Flash storage access speed and high resource consumption were solved, achieving efficient Flash reading and low-power data management.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HAISUXIN MICROELECTRONICS CO LTD
- Filing Date
- 2026-02-25
- Publication Date
- 2026-05-19
AI Technical Summary
In existing technologies, Flash storage has a large capacity but slow access speed. When adding prefetch circuits and cache circuits, there are problems such as high resource consumption, inability to save prefetched data, and high power consumption, which cannot effectively improve reading efficiency.
Design an AHB-based FLASH prefetch cache system, including AHB parsing, address comparison, cache control, prefetch control, and read operation. Prefetch control determines whether to prefetch, and a save function is added by borrowing from the cache circuit structure to reduce hardware resource consumption and improve read efficiency.
This approach achieves improved Flash read efficiency and reduced power consumption while minimizing hardware resource consumption, ensuring fast data access and management.
Smart Images
Figure CN122064609A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, specifically to an AHB-based FLASH prefetch cache system and its implementation method. Background Technology
[0002] Flash memory has a large storage capacity but slow access speed. Current MCUs address this by adding prefetch circuits and cache circuits. The faster the system clock, the more efficient the cache. However, it performs poorly when the system clock speed is close to the flash memory speed. On one hand, the short wait time when reading from flash negates the cache's biggest advantage; on the other hand, the cache's high resource consumption becomes apparent. Prefetch circuits are simple in structure but lack storage functionality; prefetched data cannot be saved. Therefore, even when the CPU cycles through two instructions, it needs to fetch data from flash memory every time, which is time-consuming and consumes a lot of power when reading from flash. Thus, this approach does not meet current requirements. To address this, we propose an AHB-based flash prefetch cache system and its implementation method. Summary of the Invention
[0003] The purpose of this invention is to provide an AHB-based FLASH prefetch cache system and its implementation method. By adding a storage function to the prefetch circuit, the consumption of hardware resources can be reduced, the efficiency of reading FLASH can be improved, and the reading of FLASH can be reduced to reduce power consumption, thus solving the problems mentioned in the background art.
[0004] To achieve the above objectives, the present invention provides the following technical solution: an AHB-based FLASH prefetch cache system, comprising: AHB parsing is used to parse AHB bus behavior. Address comparison is used to compare two addresses and the comparison results are sent to the read operation and cache control respectively. The cache control includes a storage area for storing FLASH data, which is divided into four parts: storage area 1, storage area 2, storage area 3 and storage area 4. Each storage area corresponds to a flag bit, namely V1, V2, V3 and V4; Prefetch control is used to determine whether to perform a prefetch operation. It receives information parsed by the AHB parsing circuit and performs prefetching when the AHB bus is idle. It also includes an instruction parsing module to determine whether the previous instruction was a jump instruction. Prefetching is only performed if the previous instruction was not a jump instruction. The read operation is used to receive the results from address comparison and prefetch control. A read operation is performed when FLASH needs to be read. The AHB slave output is used to control the HREADY signal, thereby controlling the timing of data delivery to the AHB bus.
[0005] Furthermore, in the address comparison, the two types of addresses being compared are the prefetch address and the current access address, and the cached address and the current access address.
[0006] Furthermore, the cache control also stores an address, which is the address corresponding to storage area 1, and storage areas 2, 3 and 4 do not have corresponding addresses stored. The addresses of storage areas 2, 3 and 4 are the addresses corresponding to storage area 1 plus 1, plus 2 and plus 3 respectively.
[0007] The implementation method of AHB-based FLASH prefetch cache, applied to an AHB-based FLASH prefetch cache system, includes the following steps: Step 1: When idle, the prefetch operation is determined based on the last read instruction when the AHB bus is idle; If the address of the next instruction is a jump-related instruction, no prefetching is performed; otherwise, a prefetch is initiated. If there is no AHB bus access during the prefetch, proceed to step two. If there is an AHB bus access, proceed to step three; Step 2: Wait for the reading to finish, put the data into the storage area, and update the corresponding flag bit; If the data is written to memory area 1, the address is also written to the address cache controlled by the cache. Step 3: Determine if the address to be read from the AHB bus matches the cache address; If a match is found, it is read directly from the storage area; If there is no match, proceed to step four; Step 4: Determine if the address to be read from the AHB bus matches the prefetch address; If a match is found, wait for the prefetch to complete before reading the data. If there is no match, proceed to step five; Step 5: Wait for the prefetch to complete, then perform another read operation. After the read is complete, remove the data. The prefetched data is not written to the storage area. Step Six: Operation complete, proceed to Step One.
[0008] Furthermore, the behavior on the AHB bus is divided into two cases: idle and read. When idle, the process proceeds to step one, and when read, the process proceeds to step three.
[0009] Furthermore, AHB read access is divided into the following three cases: The first type is cache matching, which means that the data is written into the cache after the previous prefetch ends, and the prefetched data is the same as the data accessed by AHB. In this case, it can be read directly from the cache. When reading from the cache, the next prefetch is performed, that is, the next data is read from FLASH. The second scenario: If the first condition is not met, the FLASH is idle and no read operation is performed. In this case, the data is read directly from the FLASH, and the AHB bus takes away the data after the read is completed. The third scenario: If neither the first nor the second condition is met, i.e. the cache is not matched, the FLASH is being prefetched.
[0010] Furthermore, in the third case, the cache does not match, and the FLASH is being prefetched. This can be divided into the following two situations: The data to be prefetched is exactly the data required for AHB read access. At this point, we can wait for the read to complete and then retrieve the data, while the data is simultaneously written to the cache. If the data to be fetched is not the data required for AHB read access, then you need to wait for the operation to complete. After the operation is completed, you can read the FLASH again and then retrieve the data.
[0011] Furthermore, the prefetch operation is divided into the following two cases: The first method: During the prefetch operation, there is no access to the AHB bus. In this case, simply wait for the read to complete and write the data into the buffer. The second method involves performing a read access operation on the AHB bus during the prefetch operation.
[0012] Furthermore, in the first case, if the data being written is to storage area 1, the address is written simultaneously with the data being written.
[0013] Furthermore, in the second case, during the prefetch operation, the AHB bus performs a read access operation, which specifically falls into two categories: The data to be prefetched is the data required for AHB read access. Once the read is complete, the AHB bus can take the data away, and the data is simultaneously written to the buffer. If the data being written is to storage area 1, the address is written to the address cache controlled by the cache when writing data; The data to be fetched is not the data required for AHB read access. We need to wait for this read FLASH operation to complete. The read data is discarded directly, and all valid bits in the cache are cleared at the same time. Then read again. After reading the FLASH, pull the READY signal high to let the AHB bus take the data and write the data to the buffer at the same time. If the data to be written is to storage area 1, the address is written to the address cache controlled by the cache when writing data.
[0014] Compared with the prior art, the beneficial effects of the present invention are: The AHB parsing mechanism of this invention is responsible for parsing the AHB bus behavior, comparing two addresses and sending the results to the read operation and cache control respectively. The cache control storage area is divided into four parts with corresponding flag bits, which can be used to record the status information of each storage area. The prefetch control is responsible for determining whether a prefetch operation is needed. The read operation is responsible for receiving the results from the address comparison and prefetch control and performing the corresponding read operation. The AHB slave output is responsible for controlling the HREADY signal to control the timing of data delivery to the AHB bus. This invention borrows the structure of the cache circuit and adds a storage function to the prefetch circuit, which can achieve fast FLASH reading while reducing hardware resource consumption and FLASH reading. Attached Figure Description
[0015] Figure 1 This is an overall structural diagram of the AHB-based FLASH prefetch cache system of the present invention; Figure 2 This is a flowchart of the AHB read access process of the present invention; Figure 3 This is a flowchart of the prefetching process of the present invention. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] To address the technical problem that existing technologies cannot improve the efficiency of reading FLASH, which is not only time-consuming but also consumes a lot of power during FLASH reading, please refer to [link to relevant documentation]. Figures 1-3 This embodiment provides the following technical solution: AHB-based FLASH prefetch cache system includes: AHB parsing is used to parse AHB bus behavior. Address comparison is used to compare two addresses and the comparison results are sent to the read operation and cache control respectively. The cache control includes a storage area for storing FLASH data, which is divided into four parts: storage area 1, storage area 2, storage area 3 and storage area 4. Each storage area corresponds to a flag bit, namely V1, V2, V3 and V4; Prefetch control is used to determine whether to perform a prefetch operation. It receives information parsed by the AHB parsing circuit and performs prefetching when the AHB bus is idle. It also includes an instruction parsing module to determine whether the previous instruction was a jump instruction. Prefetching is only performed if the previous instruction was not a jump instruction. The read operation is used to receive the results from address comparison and prefetch control. A read operation is performed when FLASH needs to be read. The AHB slave output is used to control the HREADY signal, thereby controlling the timing of data delivery to the AHB bus.
[0018] The technical effects of the above are as follows: AHB parsing is responsible for parsing the AHB bus behavior and obtaining the current AHB bus state for subsequent operations such as address comparison and prefetch control. Address comparison compares two different addresses and then, based on the comparison result, passes the corresponding information to the read operation and cache control. This allows the read operation and cache control to determine the operation to be performed based on the address comparison result, thereby achieving efficient data management and access. The cache control includes a storage area for storing FLASH data, which is divided into four parts, each with a corresponding flag bit. These flag bits are used to indicate the state of each storage area. Only when the cache control needs to read or write data will it operate on the corresponding flag bit to obtain or update the state of the storage area, effectively improving the efficiency of cache control. The prefetch control is responsible for determining whether to perform a prefetch operation. It receives information parsed by the AHB parsing circuit and then, based on the information... The prefetch control determines whether to perform a prefetch. Prefetching occurs when the AHB bus is idle. The prefetch control also includes an instruction parsing module, which determines whether the previously executed instruction was a jump instruction. Prefetch control only performs a prefetch operation if the previously executed instruction was not a jump instruction, ensuring that prefetching only occurs when truly needed, thus avoiding unnecessary resource waste. The read operation, after receiving the results from the address comparison and prefetch control, performs the actual FLASH read operation and retrieves the required data. The AHB slave output controls the HREADY signal, indicating whether the AHB slave is ready for the data the master needs to access. When the AHB slave output receives a request, it controls the HREADY signal to indicate that the AHB slave is ready for the data required by the master, allowing it to begin processing the new data and thus enabling fast data access and processing.
[0019] This invention draws on the structure of cache circuits and adds a storage function to the prefetch circuit, which can reduce the consumption of hardware resources, improve the efficiency of reading FLASH, reduce the reading of FLASH, and reduce power consumption.
[0020] In address comparison, the two types of addresses being compared are the prefetch address and the currently accessed address, and the cached address and the currently accessed address.
[0021] The technical effects of the above are as follows: the prefetch address and the current access address are mainly for the purpose of prefetching, that is, data can be prefetched when it is not necessary to read data from the flash memory, thereby reducing waiting time and improving performance. The cache address and the current access address are mainly for the purpose of caching, that is, before the actual read and write operation, the current access address and the cache address can be compared to determine whether to read or directly use the cached data.
[0022] The cache controller also stores an address, which is the address corresponding to storage area 1. Storage areas 2, 3, and 4 do not have corresponding addresses stored. The addresses of storage areas 2, 3, and 4 are the addresses corresponding to storage area 1 plus 1, 2, and 3, respectively.
[0023] The technical effect of the above is as follows: In cache control, in addition to storing a specific address, namely the address corresponding to storage area 1, the addresses of the other three storage areas (storage area 2, storage area 3, and storage area 4) are obtained by adding a certain value to the address corresponding to storage area 1. These three values are 1, 2, and 3 respectively. If data needs to be found in storage area 2, storage area 3, or storage area 4, it is only necessary to add the corresponding value to the address corresponding to storage area 1 to obtain the correct target address. This address mapping method can facilitate data access and improve the efficiency of data organization and management.
[0024] The implementation method of AHB-based FLASH prefetch cache, applied to an AHB-based FLASH prefetch cache system, includes the following steps: Step 1: When idle, the prefetch operation is determined based on the last read instruction when the AHB bus is idle; If the address of the next instruction is a jump-related instruction, no prefetching is performed; otherwise, a prefetch is initiated. If there is no AHB bus access during the prefetch, proceed to step two. If there is an AHB bus access, proceed to step three; Step 2: Wait for the reading to finish, then put the data into the storage area, starting from the corresponding valid flag bits (V1, V2, V3, and V4); If the data is written to memory area 1, the address is also written to the address cache controlled by the cache. Step 3: Determine if the address to be read from the AHB bus matches the cache address; If a match is found, it is read directly from the storage area; If there is no match, proceed to step four; Step 4: Determine if the address to be read from the AHB bus matches the prefetch address; If a match is found, wait for the prefetch to complete before reading the data. If there is no match, proceed to step five; Step 5: Wait for the prefetch to complete, then perform another read operation. After the read is complete, remove the data. The prefetched data is not written to the storage area. Step Six: Operation complete, proceed to Step One.
[0025] The technical effects of the above content are as follows: The implementation method of FLASH prefetch cache based on AHB ensures the effectiveness and accuracy of prefetching operations when the AHB bus is idle, thereby avoiding unnecessary bus access and additional read operations. At the same time, by marking the data in different memory areas, it is also convenient for subsequent address comparison and data reading. The above-mentioned caching method based on prefetch strategy can improve the operating efficiency of the system while ensuring data continuity.
[0026] The behavior on the AHB bus is divided into two cases: idle and read. When idle, the process proceeds to step one, and when reading, the process proceeds to step three.
[0027] The technical effect of the above content is as follows: The two behavior modes of the AHB bus are idle and read. When it is in the idle state, a prefetch operation is performed and the process jumps to step one. When it is in the read state, a read operation is performed and the process jumps to step three. This design can have different execution strategies when handling different tasks, so as to improve the system flexibility and response speed.
[0028] like Figure 2 As shown, AHB performs read access in the following three ways: The first method is cache matching, which means that the data is written to the cache after the previous prefetch ends, and the prefetched data is the same as the data accessed by AHB. In this case, it can be read directly from the cache. When reading from the cache, the next prefetch is performed, and the next data is read from the FLASH. This operation is to reduce the idle time of the FLASH to improve efficiency. The second method: If the first condition is not met, the FLASH is idle and no reading operation is performed. In this case, the data is read directly from the FLASH. After the reading is completed, the data is written to the cache. If AHB accesses the same address, there is no need to read from the FLASH again. This not only improves the reading efficiency, but also saves the power consumption of reading from the FLASH. The third scenario: If neither the first nor the second condition is met, i.e. the cache is not matched and the FLASH is being prefetched; In the third case, the cache does not match and the FLASH is being prefetched. This can be further divided into the following two situations: First, the data to be prefetched is exactly the data required for AHB read access. At this point, we can wait for the read to complete and then retrieve the data, while simultaneously writing the data into the cache. Second, if the data to be prefetched is not the data required for AHB read access, then it is necessary to wait for the operation to complete. After the operation is completed, the FLASH is read again, and the data is taken away after the read is completed. This is to prevent the FLASH from making errors due to sudden timing interruption. After the operation is completed, the FLASH is read again, and the data is taken away after the read is completed.
[0029] The technical effects of the above are as follows: When the most recent prefetch operation writes data to the cache, and the current AHB access data is the same as the prefetched data, the data can be read directly from the cache, and then prefetched again to reduce the time slice occupation of FLASH, thereby improving efficiency. When the cache does not match and FLASH is not prefetched, the data can be read directly from FLASH, thereby avoiding unnecessary prefetching, improving reading efficiency and saving power. When FLASH is prefetched, it cannot be read directly from FLASH, and it is necessary to wait for the prefetch to be completed before reading. The purpose is to ensure that the data in the cache is up-to-date, and at the same time, it can avoid the impact of frequent prefetching and reading on performance.
[0030] like Figure 3 As shown, the prefetch operation is divided into the following two cases: The first method: During the prefetch operation, there is no access to the AHB bus. In this case, simply wait for the read to complete and write the data into the buffer. In the first case, if the data being written is to storage area 1, the address is written at the same time as the data is written. The second method involves performing a read access operation on the AHB bus during the prefetch operation. In the second scenario, during the prefetch operation, the AHB bus performs a read access operation, which specifically falls into two categories: First, the data to be prefetched is the data required for AHB read access. Once the read is complete, the AHB bus can take the data away, and at the same time, the data is written to the buffer. If the data being written is to storage area 1, the address is written to the address cache controlled by the cache when writing data; Second, the data to be prefetched is not the data required for AHB read access. It is necessary to wait for the current read FLASH operation to be completed, and the read data will be discarded directly. At the same time, all valid bits in the cache will be cleared. Then read again. After reading the FLASH, pull the READY signal high to let the AHB bus take the data and write the data to the buffer at the same time. If the data to be written is to storage area 1, the address is written to the address cache controlled by the cache when writing data.
[0031] The technical effects of the above are as follows: When there is no AHB bus access operation during the prefetch operation, the system can directly wait for the read to complete and write the data into the buffer. In this case, if the data is written to buffer 1, the address will also be written at the same time. When there is an AHB bus read operation during the prefetch operation, two situations need to be considered: If the prefetched data is exactly the data required by AHB for reading, then the AHB bus can directly take the data after the read is completed, and the data will also be written into the buffer. If the prefetched data is not the data required by AHB for reading, then the system needs to wait for the read operation to complete before rereading the FLASH. After the read is completed, the new data is written into the buffer, and the READY signal is pulled high to allow the AHB bus to take the data. The above design can ensure timely response to AHB bus read operations, effectively utilize buffer space, reduce unnecessary prefetch operations, and improve system performance.
[0032] Working Principle: AHB parsing is responsible for parsing the AHB bus behavior to facilitate subsequent operations such as address comparison and prefetch control. Address comparison compares two addresses and sends the results to read operation and cache control respectively, so that read operation and cache control can determine the operation to be performed based on the address comparison result. Cache control includes a storage area for storing FLASH data, divided into four parts, and each storage area has a corresponding flag bit. The flag bit can be used to record the status information of each storage area. Prefetch control is responsible for determining whether a prefetch operation is needed, ensuring that prefetching is only performed when it is truly needed, avoiding unnecessary resource waste. Read operation receives the results from address comparison and prefetch control and performs the corresponding read operation. The AHB slave output is responsible for controlling the HREADY signal to control the timing of data delivery to the AHB bus. Based on the above design, this invention borrows the structure of cache circuits and adds a storage function to the prefetch circuit, which can reduce hardware resource consumption, improve the efficiency of reading FLASH, and reduce FLASH reads, thereby reducing power consumption.
[0033] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0034] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention.
Claims
1. A FLASH prefetch cache system based on AHB, characterized in that, include: AHB parsing is used to parse AHB bus behavior. Address comparison is used to compare two addresses and the comparison results are sent to the read operation and cache control respectively. The cache control includes a storage area for storing FLASH data, which is divided into four parts: storage area 1, storage area 2, storage area 3 and storage area 4. Each storage area corresponds to a flag bit, namely V1, V2, V3 and V4; Prefetch control is used to determine whether to perform a prefetch operation. It receives information parsed by the AHB parsing circuit and performs prefetching when the AHB bus is idle. It also includes an instruction parsing module to determine whether the previous instruction was a jump instruction. Prefetching is only performed if the previous instruction was not a jump instruction. The read operation is used to receive the results from address comparison and prefetch control. A read operation is performed when FLASH needs to be read. The AHB slave output is used to control the HREADY signal, thereby controlling the timing of data delivery to the AHB bus.
2. The AHB-based FLASH prefetch cache system according to claim 1, characterized in that: In the address comparison, the two types of addresses being compared are the prefetch address and the currently accessed address, and the cached address and the currently accessed address.
3. The AHB-based FLASH prefetch cache system according to claim 1, characterized in that: The cache control also stores an address, which is the address corresponding to storage area 1. Storage areas 2, 3, and 4 do not have corresponding addresses stored. The addresses of storage areas 2, 3, and 4 are the addresses corresponding to storage area 1 plus 1, 2, and 3, respectively.
4. A method for implementing an AHB-based FLASH prefetch cache, applied to the AHB-based FLASH prefetch cache system described in any one of claims 1-3, characterized in that, Includes the following steps: Step 1: When idle, the prefetch operation is determined based on the last read instruction when the AHB bus is idle; If the address of the next instruction is a jump-related instruction, no prefetching is performed; otherwise, a prefetch is initiated. If there is no AHB bus access during the prefetch, proceed to step two. If there is an AHB bus access, proceed to step three; Step 2: Wait for the reading to finish, put the data into the storage area, and update the corresponding flag bit; If the data is written to memory area 1, the address is also written to the address cache controlled by the cache. Step 3: Determine if the address to be read from the AHB bus matches the cache address; If a match is found, it is read directly from the storage area; If there is no match, proceed to step four; Step 4: Determine if the address to be read from the AHB bus matches the prefetch address; If a match is found, wait for the prefetch to complete before reading the data. If there is no match, proceed to step five; Step 5: Wait for the prefetch to complete, then perform another read operation. After the read is complete, remove the data. The prefetched data is not written to the storage area. Step Six: Operation complete, proceed to Step One.
5. The implementation method of AHB-based FLASH prefetch cache according to claim 4, characterized in that: The behavior on the AHB bus is divided into two cases: idle and read. When idle, the process proceeds to step one, and when reading, the process proceeds to step three.
6. The implementation method of AHB-based FLASH prefetch cache according to claim 4, characterized in that: When accessing AHB during a read operation, there are three scenarios: The first type is cache matching, which means that the data is written into the cache after the previous prefetch ends, and the prefetched data is the same as the data accessed by AHB. In this case, it can be read directly from the cache. When reading from the cache, the next prefetch is performed, that is, the next data is read from FLASH. The second scenario: If the first condition is not met, the FLASH is idle and no read operation is performed. In this case, the data is read from the FLASH, and after the read is completed, the AHB bus takes away the data. The third scenario: If neither the first nor the second condition is met, i.e. the cache is not matched, the FLASH is being prefetched.
7. The implementation method of AHB-based FLASH prefetch cache according to claim 6, characterized in that: In the third case, the cache does not match and the FLASH is being prefetched. This can be divided into the following two situations: The data to be prefetched is exactly the data required for AHB read access. At this point, we can wait for the read to complete and then retrieve the data, while the data is simultaneously written to the cache. If the data to be fetched is not the data required for AHB read access, then you need to wait for the operation to complete. After the operation is completed, you can read the FLASH again and then retrieve the data.
8. The implementation method of AHB-based FLASH prefetch cache according to claim 4, characterized in that: During prefetching, there are two scenarios: The first method: During the prefetch operation, there is no access to the AHB bus. In this case, wait for the read to complete and write the data into the buffer. The second method involves performing a read access operation on the AHB bus during the prefetch operation.
9. The implementation method of AHB-based FLASH prefetch cache according to claim 8, characterized in that: In the first case, if the data being written is to storage area 1, the address is written at the same time as the data is written.
10. The implementation method of AHB-based FLASH prefetch cache according to claim 8, characterized in that: In the second case, during the prefetch operation, the AHB bus performs a read access operation, which is specifically divided into two cases: The data to be prefetched is the data required for AHB read access. Once the read is complete, the AHB bus can take the data away, and the data is simultaneously written to the buffer. If the data being written is to storage area 1, the address is written to the address cache controlled by the cache when writing data; The data to be fetched is not the data required for AHB read access. We need to wait for this read FLASH operation to complete. The read data is discarded directly, and all valid bits in the cache are cleared at the same time. Then read again. After reading the FLASH, pull the READY signal high to let the AHB bus take the data and write the data to the buffer at the same time. If the data to be written is to storage area 1, the address is written to the address cache controlled by the cache when writing data.