Image system adaptive QoS arbitration method and device

Abstract

The invention discloses a self-adaptive QoS arbitration method and device for an image system, and belongs to the field of computer hardware and data communication. According to the method, a priority locking mechanism and a credit refreshing mechanism triggered by authorization switching are introduced, so that the bus utilization rate is improved, the arbitration logic overhead is reduced, and concurrent access management of multiple channels on shared memory resources is realized. According to the structural design, a channel transaction management module and a GST-WA core arbitration module are designed, high decoupling of read-write transactions and arbitration logic is achieved, and standardized processing is conducted on data streams with channels as units. Meanwhile, an arbiter combines credit depletion forced propulsion and a deadlock prevention mechanism to realize effective balance between QoS guarantee and long-term fairness of a high-weight channel.

Description

Technical Field

[0001] This invention belongs to the field of computer hardware and data communication, and particularly relates to an adaptive QoS arbitration method and apparatus for an image system. Background Technology

[0002] In high-performance real-time data processing systems, such as infrared imaging, machine vision, or industrial control systems, it is often necessary to manage contentious access to shared memory resources with a single access port from multiple data streams. These data streams exhibit significant heterogeneity, primarily manifested in the substantial differences in their access to shared memory resources. These include continuous data streams requiring high throughput and low jitter, as well as bursty control or conditional calibration streams demanding instantaneous low latency and high real-time performance. As the primary bandwidth constraint of the system, the shared memory interface's access scheduling must meet the heterogeneous Quality of Service (QoS) requirements of all channels, particularly addressing the risk of data loss and latency jitter caused by resource contention under congested conditions.

[0003] To achieve efficient access scheduling of shared memory resources, currently used arbitration methods often employ fixed-priority arbitration, which lacks fairness and can easily lead to low-priority channels being starved for extended periods. While round-robin arbitration (RR) provides basic fairness, it ignores the QoS requirements of each channel and fails to allocate resources to critical channels. Weighted round-robin arbitrators (WRR) are currently the mainstream solution, allocating bandwidth proportionally by assigning weight values ​​to each channel. However, traditional WRR structures exhibit significant inherent shortcomings when applied to high-burst, high-concurrency scenarios: First, due to the lack of an explicit priority locking mechanism in its arbitration logic, arbitration decisions must still be executed every cycle during continuous channel transmission, increasing the logical burden. Furthermore, the arbitrator only performs priority transfer when channel credits are exhausted, failing to meet the demand of high-bandwidth channels for optimized long-burst transmission. Second, traditional WRR structures typically employ a mechanism of unified refresh only at the end of a cycle or when all credits are exhausted. This non-instant credit recovery prevents channels from immediately restoring their maximum burst capacity after completing a short burst, severely impacting the arbitrator's real-time response speed and adaptability to irregular, intermittent burst requests.

[0004] In summary, existing arbitration methods and structures struggle to achieve an effective balance between heterogeneous QoS guarantees, long burst transmission efficiency, and instantaneous low-latency response. Therefore, there is an urgent need for an adaptive QoS arbitration method and apparatus that addresses these shortcomings through strategic and structural innovations. Summary of the Invention

[0005] The purpose of this invention is to provide an adaptive QoS arbitration method and apparatus for image systems, overcoming the shortcomings of existing technologies in handling heterogeneous data streams, such as low burst efficiency, poor adaptability, and insufficient real-time guarantees. To address these shortcomings, this invention introduces a priority locking mechanism and a credit refresh mechanism triggered by authorization switching to improve bus utilization and reduce arbitration logic overhead, enabling concurrent access management of shared memory resources across multiple channels. Structurally, it includes a channel transaction management module and a GST-WA core arbitration module, achieving a high degree of decoupling between read / write transactions and arbitration logic, and standardizing data stream processing on a channel-by-channel basis. Simultaneously, the arbitrator combines credit exhaustion-driven forced advancement and deadlock prevention mechanisms to achieve an effective balance between QoS guarantees and long-term fairness for high-weight channels.

[0006] The technical solution of this invention is as follows: This invention provides an adaptive QoS arbitration device for an image system. Its logical structure consists of two core parts: a Channel Transaction Management (CTM) module responsible for front-end data stream processing and a GST-WA core arbitration device responsible for resource allocation and QoS assurance. The device achieves multi-level decoupling through modular and layered design to isolate heterogeneous data streams from the core arbitration logic, and supports parameterized configuration of parameters such as granularity, number of channels, original weights of each channel, and credit count bit width.

[0007] The channel transaction management module is a front-end structure of the GST-WA core arbitration device, used to receive and standardize complex requests from external heterogeneous data channels. It achieves a high degree of decoupling between read / write transactions and core arbitration logic, and encapsulates standardized request signals representing a single arbitration intent on a channel-by-channel basis, thereby adapting to the standardized input requirements of the GST-WA core arbitration device. This module includes: 1. Asynchronous Adaptation and Buffering Unit: Includes a read buffer RD_Buffer and a write buffer WR_Buffer based on an asynchronous cache structure, used to receive read and write requests from different clock domains and realize cross-clock domain (CDC) data transmission. Its buffer depth is parameterized according to the burst length of the external data source and the system QoS constraints to cope with the back pressure generated by the lower-level GST-WA core arbitration device.

[0008] 2. Internal Transaction State Machine (FSM): The FSM is the core control unit for half-duplex read and write access within the channel. It arbitrates read and write transactions based on the back pressure signal of the lower-level bus, the state of the read and write buffer, and the preset internal arbitration strategy to determine whether the current channel is in a read, write, or idle state, and outputs a decision signal Sel; and drives the standardized request encapsulation unit to generate and output a standardized arbitration request signal.

[0009] 3. Standardized Request Encapsulation Unit (PACK): This unit mainly consists of request selection logic, data path control unit, and encapsulation logic. Based on the FSM's decision signal Sel, it enables the write buffer path or read buffer path and establishes the corresponding data flow direction. For write requests, it directs the data flow from the write buffer to the GST-WA core arbitration device; for read requests, it prepares to receive the data flow from the GST-WA core arbitration device and direct it to the read buffer. Simultaneously, it formats and encapsulates information such as read / write instructions to generate a standardized arbitration request signal representing a single arbitration intent. ( (For the number of channels), and submit it to the GST-WA core arbitration device.

[0010] The GST-WA core arbitration unit is a key component for implementing adaptive QoS arbitration strategies. It is responsible for allocating shared memory bus resources and satisfying QoS constraints across multiple channels. The GST-WA core arbitration unit receives standardized arbitration request signals from the channel transaction management module. It arbitrates and assigns an authorization channel, sending the transaction request contained in the authorization channel to the lower-level memory controller. Its structure and function employ a priority locking and authorization switching-triggered credit refresh mechanism. The device specifically comprises: 1. Register Management Module: Used to store and manage key parameters required for the operation of the GST-WA core arbitration device, including the raw weights of each channel. (Define QoS weight quotas), credit counter Priority pointer (Used to determine the scanning start point and enforcement logic of the arbitration award), maximum idle tolerance threshold The system includes the authorized and locked channels from the previous arbitration round, as well as the base address and region range corresponding to each channel. Parameters in the register management module are called in real time by other functional modules within the GST-WA core arbitration device. Simultaneously, the bit width design of the relevant parameters supports parameterized configuration, adjusting according to system QoS granularity and maximum burst transmission length to adapt to the long burst transmission requirements of heterogeneous channels.

[0011] 2. Priority Decision and Locking Module: This module performs classification decisions and outputs arbitration results based on the current state of the GST-WA core arbitration device. First, it determines whether the GST-WA core arbitration device is in a priority-locked state, i.e., whether the transaction request for the current authorized channel has not yet ended and the credit counter has not been exhausted. If it is in a priority-locked state, the module skips the global priority decision logic and directly outputs the decision result of the current authorized channel through the bypass path to ensure the continuity of burst transmissions and reduce arbitration latency. If it is not in a priority-locked state, the module executes the global priority decision logic and calls the priority pointer in the register management module. and credit counters for each channel It combines the input standardized arbitration request signal to calculate, in order to generate a new judgment result and determine the authorized channel.

[0012] 3. **Dynamic Strategy Update Module:** This module monitors the decision results of the priority and locking modules in real time and dynamically updates the parameters in the register management module accordingly. Its function is to execute the credit refresh mechanism triggered by authorization switching: when an authorization channel switch is detected or the GST-WA core arbitration device is idle for an extended period, the module immediately reloads the credit counter of the previous authorization channel to its original weight to ensure rapid response for each channel in intermittent request scenarios. Simultaneously, when the credit counter of an authorization channel is exhausted, the module triggers the priority pointer... The system is updated to cyclically shift according to the physical order of the channels, thereby redefining the scanning starting point for the next round of arbitration.

[0013] 4. Bus Protocol Adaptation Module: This module receives transaction requests from authorized channels output by the priority decision and locking module and converts them into a standard format compatible with the bus protocol of the lower-level memory controller. The bus protocol adaptation module consists of a protocol encapsulation unit and a transaction tracking unit. The protocol encapsulation unit calls the base addresses and region ranges configured in the register management module, calculates the base address offset, converts the logical address in the transaction request into a physical memory address, and performs data stream encapsulation. The transaction tracking unit monitors and records the execution progress and completion status of transaction requests sent to the memory controller in real time, and generates a backpressure signal to feed back to the channel transaction management module.

[0014] The adaptive QoS arbitration method for image systems provided by this invention specifically includes the following steps: Step 1: Use the channel transaction management module to receive, buffer, and internally arbitrate external heterogeneous requests, and convert them into standardized signals required by the GST-WA core arbitration device. Step 1.1: The channel transaction management module of each channel receives heterogeneous data streams from different clock domains; using the asynchronous FIFO mechanism, the write transaction data stream is input and buffered into the write buffer WR_Buffer, and the read transaction data stream is read from the read buffer RD_Buffer for output; Step 1.2: The internal transaction state machine (FSM) performs internal arbitration on read and write transactions based on the backpressure signal returned by the bus protocol adaptation module, the read and write buffer status, and the preset internal arbitration strategy. It determines whether the current channel is in a read, write, or idle state and outputs the decision signal Sel. Step 1.3: Based on the FSM's decision, the data path control unit MUX guides the write request data stream from the write buffer to the GST-WA core arbitration device, or establishes a path for the read request data stream from the GST-WA core arbitration device to the read buffer. Simultaneously, the standardized request encapsulation unit PACK formats and encapsulates the read / write instruction information, generating a standardized arbitration request signal. ,in It is the number of channels; Furthermore, in step 1.3, the standardized request encapsulation unit PACK is responsible for performing parameterized address mapping, allocating different storage areas for transaction requests according to the channel number, with each storage area pre-set to hold a complete frame of data. A state machine-level space is reserved before each storage area as a protected area.

[0015] Furthermore, the standardized arbitration request signal contains only a one-bit valid signal and a one-bit transaction type indicator signal, where Type=0 indicates a read request and Type=1 indicates a write request.

[0016] Furthermore, in step 1.3, the standardized request encapsulation unit PACK stores the write transaction data and sends it down after the lower level obtains authorization.

[0017] Step 2: Execute priority decisions and resource authorizations within the GST-WA core arbitration device, and dynamically update the priority pointer. and credit counters for each channel ; Step 2.1: Initialize the priority pointer And credit counters for all channels Set to the corresponding original weight. By default, the GST-WA core arbitration device is set to an unlocked priority state upon first power-on. Step 2.2: The GST-WA core arbitration device executes a global priority decision based on the standardized arbitration request signal. Priority pointer and credit counters for each channel Select authorized channels The authorized channel will be used as the locked channel, and the GST-WA core arbitration device will be updated to a priority locked state. Step 2.3: Proceed to the next round of arbitration, based on the current standardized arbitration request signal. The signal is compared with the locked channel in step 2.2. If the locked channel in step 2.2 does not exist in the channel to which the current standardized arbitration request signal belongs, it is considered a mismatch, and the process proceeds to step 2.2. Otherwise, it is considered a match, and the process continues to check whether the credit counter of the locked channel is greater than zero. If the check conditions are met, skip the arbitration logic and update the locked channel to the authorized channel; if the check conditions are not met, proceed to step 2.2. Step 2.4, if authorized channel Selected, enable the credit counter Perform a decrement operation. When When the value is reduced to zero, the priority pointer is triggered. Update, make the priority pointer The pointing position is switched cyclically according to the channel sequence. Meanwhile, if If it is still valid, then Immediately reload to initial weights ;like invalid, No overload; Step 2.5: If this is not the first round of arbitration, record the authorization channel of the previous round of arbitration. The results will be compared with the authorized channels for this round of arbitration to determine whether the arbitration outcome has changed. If a change has occurred, the authorized channels will be triggered immediately. of Restore to its initial weights ; Step 2.6: Separately count consecutive periods without valid authorization (multiple consecutive periods without valid standardized arbitration request signal input) and bus idle periods. If at least one exceeds the maximum idle tolerance threshold... This will trigger an emergency global credit refresh, affecting all channels. Restore to its initial weights ; Step 3: The bus protocol adaptation module is responsible for encapsulating and converting the arbitration result into a bus protocol transaction, and sending a bus backpressure signal to the channel transaction management module. Step 3.1: The protocol encapsulation unit receives the transaction request (which includes a logical address and a data stream) carried by the authorized channel in Step 2; the protocol encapsulation unit performs base address offset calculation according to the parameterizable base address and region range of each channel, converts the logical address into the physical storage address corresponding to the lower-level memory; performs address encapsulation, packing, or unpacking operations on the data stream to meet the format requirements of the lower-level memory controller bus protocol, and sends the processed transaction request to the memory controller; Step 3.2: The transaction tracking unit monitors and records the execution progress and completion status of the transaction requests sent to the memory controller in step 3.1 in real time, and generates a backpressure signal based on this, which is fed back to the upper-level channel transaction management module as the basis for the internal transaction state machine execution decision in step 1.2.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention proposes and implements a Grant Switching Triggered Weighted Trigger-WA (GST-WA) strategy. This strategy divides arbitration into a priority locking burst phase and a switching refresh phase, so that channel credit recovery no longer depends on global credit depletion, but is triggered instantly by the grant switching event. This core innovation significantly improves the response speed and adaptability to irregular, intermittent burst requests, effectively solving the arbitration inefficiency problem caused by slow credit recovery in the traditional WRR (Weighted Round Robin) strategy. Simultaneously, the priority locking mechanism introduced in arbitration adapts to the memory controller's requirements for long burst transmissions, effectively avoiding unnecessary periodic logical operations and frequent grant switching, and significantly improving bus bandwidth utilization.

[0019] This invention fundamentally guarantees the stable operation and fairness of the system by designing a credit exhaustion forced push and an emergency global refresh mechanism. The forced push logic ensures that requests on low-priority channels receive continuous service opportunities in long burst scenarios, eliminating the risk of localized starvation. Simultaneously, the global activity monitor can detect consecutive periods without valid authorization or bus idle periods and promptly trigger an emergency global credit refresh, thereby ensuring the QoS of critical channels is guaranteed during periods of high contention and bandwidth constraints, and eliminating the risk of system deadlock.

[0020] This invention achieves multi-layered decoupling in its structure. The channel transaction management module highly decouples read / write transactions from the core arbitration logic, is responsible for isolating and buffering external heterogeneous data channels, and encapsulating complex read / write transactions into a single standardized arbitrator request. This isolation greatly improves the system's robustness, making the core arbitration logic independent of the timing and protocol complexity of the front end. Simultaneously, arbitration status updates (such as...) and The logic for packing and unpacking the bus protocol is separated from the logic for packing and unpacking. This decoupled logic design avoids the spread of local faults in the system and improves the reliability and robustness of the overall design.

[0021] The entire arbitration structure and front-end modules employ a highly parameterized design (e.g., number of channels, original weights, parameter bit width, etc.). This results in extremely high system reconfigurability, facilitating the addition or removal of channels and rapid adjustment of system resources based on different data channels and memory interfaces, significantly shortening the development cycle and demonstrating strong engineering application value. Furthermore, this arbitration strategy is universally applicable; it effectively meets system-level QoS requirements while also being flexibly compatible with traditional polling arbitrators in regular use, greatly enhancing its deployment flexibility across different SoC platforms. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the channel transaction management module of the present invention; Figure 3 This is a schematic diagram of the structure of the GST-WA core arbitration module of the present invention; Figure 4 This is a flowchart illustrating the overall method of the present invention; Figure 5 This is a schematic diagram of the infrared thermal imaging system structure in an embodiment. Figure 6 A diagram illustrating the choice of arbitration pathway. Detailed Implementation

[0023] To make the technical solution of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] The core arbitration device of the license switching weighted trigger (GST-WA) described in this invention is deployed on a programmable logic device (e.g., an FPGA platform) and is designed to provide QoS-guaranteed shared memory access services for multiple heterogeneous data channels in an infrared thermal imaging system. Therefore, the arbitration logic is implemented in Verilog.

[0025] In infrared thermal imaging systems, the data flow includes multiple channels such as front-end acquisition, real-time video output, image processing, and calibration / control data. These channels operate in different clock domains and impose significantly different QoS requirements on the shared Hyperram memory, including bandwidth, latency, and real-time performance. For example, channel A (digital video driver) requires extremely low, guaranteed access latency, while channel E (time-domain filtering) prioritizes data throughput. This resource contention between high-priority, high-bandwidth channels and low-priority, burstable channels is a core challenge that traditional fixed-priority or standard polling arbitrators struggle to address. This invention, through the GST-WA strategy, effectively solves the technical challenge of achieving stable and fair arbitration in heterogeneous environments with multiple clock domains and multiple QoS requirements using traditional arbitration mechanisms.

[0026] Step 1: The Channel Transaction Management (CTM) module is designed to manage heterogeneous transaction requests across five channels. For example... Figure 1 As shown, five CTM modules are instantiated and deployed at the top layer of the system. The key function of these modules is to receive external requests from different clock domains and... (80MHz, specific settings depend on channel QoS characteristics and memory clock frequency) Data caching and internal arbitration decisions are completed within the clock domain, ultimately converting complex read / write transactions into standardized signals required by the GST-WA core arbitration device. .

[0027] The CST-WA core arbitration device serves as a crucial module between the five data channels (channels A to E) and the Hyperram memory controller. The read / write paths and QoS characteristics of each channel are shown in Table 1, and the data access granularity for all channels is 16 bits / address. In this embodiment, the initial weights for each channel are set as shown in Table 2, with the initial priority order being A>B>C>D>E. To cover the maximum weight of 5, the bit width of the credit counter and the initial weight is configured to be 3 bits.

[0028] Table 1. Channel Configuration and Data Characteristics

[0029] Table 2 Channel Priority and set up

[0030] Step 1.1: As Figure 2 As shown, the channel transaction management module includes a read buffer RD_Buffer and a write buffer WR_Buffer, both of which are constructed using asynchronous FIFOs as their core storage structure. Each channel's buffer utilizes the asynchronous FIFO mechanism to enable data flow between external heterogeneous clock domains and... The transition of the clock domain achieves complete clock domain isolation. For the 640×512 resolution of the infrared imaging system, the buffer depth in this embodiment is configured by row (640 pixels). Regarding the read / write bit width of the asynchronous FIFO, the interface closer to the external data stream is configured with 16 bits, while the interface closer to the arbiter (i.e.,...)... The interface of the clock domain is configured to be 128-bit, thereby achieving a 1:8 bit width conversion to match the high burst transfer efficiency of the memory controller bus protocol.

[0031] Step 1.2: The internal transaction state machine (FSM) is responsible for making internal decisions on read and write transactions based on various conditions, determining whether the channel is currently in a read, write, or idle state. The FSM's decision must comprehensively consider the backpressure signal fed back from the lower-level bus protocol adaptation module, the status flags of the WR_Buffer (e.g., wr_flag), and the status flags of the RD_Buffer (e.g., rd_flag). For example, when the WR_Buffer's fullness exceeds a preset high-level threshold, the FSM tends to prioritize write operations to avoid data overflow; conversely, when the RD_Buffer is nearly empty, it tends to prioritize read operations. Furthermore, in this infrared thermal imaging system, because read data (e.g., digital video drive for channel A) has higher real-time requirements, the FSM internally presets a strategy that prioritizes read requests over write requests, thereby ensuring the accuracy of the output decision signal (Sel).

[0032] Step 1.3: Based on the Sel generated by the FSM, the Data Path Control Unit (MUX) guides the data flow, and the Standardized Request Encapsulation Unit (PACK) generates a standardized arbitration request signal. The PACK module is responsible for performing parameterized address mapping, allocating different storage areas for transaction requests based on the channel number. Each storage area is pre-set to hold a complete frame of data (640×512 pixels). Specifically, for channels A and B, due to their three-frame buffer design to support image processing or display, they are allocated storage areas three times the size of a single frame. Simultaneously, to avoid memory overflows or data crosstalk during burst transmissions, a state machine-level space (i.e., a line of 640 pixels of data space) is reserved before each storage area as a protection zone. The PACK module simplifies the handshake protocol and the results of internal processing into a concise and unified arbitration request signal. The signal consists of only one bit for a valid signal and one bit for a transaction type indicator signal, where Type=0 indicates a read request and Type=1 indicates a write request. Specifically, the module first stores the write transaction data and then sends it down the hierarchy only after the lower level has been authorized. This encapsulation achieves a high degree of decoupling between the details of read and write transactions and the core GST-WA arbitration logic.

[0033] Step 2: The GST-WA core arbitration device is the core of this invention, and its main task is to arbitrate transaction requests from five channels according to the GST-WA strategy. The core arbitration logic of this device relies on the credit counters of each channel (…). ) and priority pointer ( The core arbitration device passes through Implement a polling mechanism, while utilizing Ensure the weighted service ratio of each channel.

[0034] In this embodiment, the core arbitration device operates in The clock domain, while the lower-level Hyperram memory's clock frequency is set to... Ideally, the memory controller can achieve a maximum theoretical utilization of approximately 60% using the APP protocol. The goal of the core arbiter's GST-WA strategy is to approach and maintain this theoretical utilization to the greatest extent possible in a multi-channel contention environment.

[0035] Step 2.1: The core arbitration device's decision logic is based on the current priority lock status and the credit counters of each channel. Arbitration decisions will be made. When the system is locked, the lock signal... Effective; the arbitrator does not arbitrate other channels, and authorization will continue to be granted to the currently locked channel. until Exhausted or The process is revoked to accommodate the Hyperram controller's requirements for efficient long burst transmissions. When the system is in an unlocked state, the arbitrator initiates the weighted polling logic of GST-WA to make a decision; in this case, the decision must consider the priority pointer. Starting position, channel request The effectiveness and Constraints. Authorized channels. The judgment is expressed mathematically as follows: The arbitrator will switch from during the refresh phase. The pointer begins a loop search of the channel, selecting the first one that satisfies the condition. and Effective channels It is then marked as the locking channel for the next cycle. .

[0036] Step 2.2: The key advantage of the GST-WA strategy of this invention lies in the credit value update mechanism, which explicitly divides the operation of the arbitrator into a priority locking burst phase and an authorization switching refresh phase. In the hardware implementation of the locking burst phase, whenever a channel is locked... To complete the data transmission of one unit, The register is decremented by one. When the channel... When an authorization is released due to credit depletion or a request for revocation, i.e., when an authorization switching event occurs, the core arbitration device immediately performs a credit refresh and priority pointer adjustment. Proceed with the operation. Originally locked channel. Credit score Immediately reset to its original weight This instant refresh mechanism greatly accelerates credit recovery and ensures a rapid response to intermittent bursts of requests to the channel. Meanwhile, the priority pointer... They were immediately pushed into the original locked passage. The next channel's propagation logic is implemented in hardware as a modulo-5 counter. For a more detailed explanation... The pointer's progression and credit refresh effect, assuming valid request input in each cycle, from... Taking the initial polling as an example, the channel polling order is A→B→C→D→E: Table 3. Priority Update and State Transition Explanation

[0037] As shown in the example above, the arbitrator... Constraints are implemented to weight channel services, and through Improve the logic to ensure the fairness of polling.

[0038] Step 2.3: To eliminate system starvation and potential deadlock risks, this device integrates forced push logic and an emergency global refresh mechanism around the GST-WA core logic. The forced push logic is implemented based on... Temporary ignoring of constraints: If, in a round of arbitration, all request channels... All have been exhausted; the forced push logic will ignore the constraints of the credit counter and proceed according to the priority pointer. The system selects the next channel with a valid request and grants authorization, ensuring that low-priority channels can also obtain service opportunities in long-burst scenarios. Furthermore, the global activity monitor can track the number of consecutive idle periods or consecutive periods without valid authorization on the bus. Once this number of periods exceeds the preset maximum idle tolerance threshold... In this embodiment, it is set 256 During a given period, the system will trigger an emergency global credit refresh. Under this mechanism, the credit values ​​of all channels are immediately reloaded to their original weights, ensuring that the QoS of critical channels is guaranteed during periods of high contention and bandwidth constraints, while also avoiding potential system deadlock risks.

[0039] Step 3: The core function of the bus protocol adaptation module is to achieve bidirectional conversion between the arbitrator's standardized signals and the Hyperram-specific APP protocol through the protocol packing and unpacking module. When the GST-WA core arbitration device authorizes a channel, the protocol packing module immediately starts, responsible for reformatting the transaction requests (including read / write addresses, burst lengths, etc.) from that channel and encapsulating them into commands and data packets that conform to the APP protocol requirements. For example, it is responsible for adapting the 128-bit data width inside the arbitrator to the data format required by the controller and generating key APP control signals such as command enable, address, and read / write indication.

[0040] Meanwhile, to ensure the integrity of Hyperram burst transmissions and the system's QoS, the bus protocol adaptation module integrates a transaction tracking unit. This module starts after a channel is authorized, maintaining a tracking counter to accurately record the length of commands sent and data returned in the current burst transaction. It is responsible for strictly adhering to burst length requirements and feeding back credit consumption signals to the GST-WA core arbitration logic, ensuring that the credit value counter for that channel can be accurately deducted at the burst granularity. Furthermore, the protocol unpacking module is also responsible for parsing the responses returned by the Hyperram controller, converting its busy and completed states into internal bus backpressure signals, and feeding these signals back to the FSMs of all channel transaction management modules in real time, serving as an important basis for their internal arbitration decisions.

Claims

1. An adaptive QoS arbitration device for an image system, the logical structure of which consists of two core parts: a channel transaction management module responsible for front-end data stream processing and a GST-WA core arbitration device responsible for resource allocation and QoS guarantee; The channel transaction management module includes: 1.1 Asynchronous Adaptation and Buffering Unit: Includes a read buffer RD_Buffer and a write buffer WR_Buffer based on an asynchronous cache structure, used to receive read and write requests from different clock domains and realize cross-clock domain data transmission. Its buffer depth is parameterized according to the burst length of the external data source and the system QoS constraints to cope with the back pressure generated by the lower-level GST-WA core arbitration device. 1.2 Internal Transaction State Machine (FSM): The FSM is the core control unit for half-duplex read and write access within the channel. It arbitrates read and write transactions based on the back pressure signal of the lower-level bus, the state of the read and write buffer, and the preset internal arbitration strategy to determine whether the current channel is in a read, write, or idle state, and outputs a decision signal Sel; and drives the standardized request encapsulation unit to generate and output a standardized arbitration request signal. 1.3 Standardized Request Encapsulation Unit: This unit mainly consists of request selection logic, data path control unit, and encapsulation logic. Based on the FSM's decision signal Sel, it enables the write buffer path or read buffer path and establishes the corresponding data flow direction. For write requests, it directs the data flow from the write buffer to the GST-WA core arbitration device. For read requests, it prepares to receive the data flow from the GST-WA core arbitration device and direct it to the read buffer. Simultaneously, it formats and encapsulates read / write instructions and other information to generate a standardized arbitration request signal representing a single arbitration intent. And submitted to the GST-WA core arbitration device, ; The GST-WA core arbitration device includes: 2.1 Register Management Module: Used to store and manage key parameters required for the operation of the GST-WA core arbitration device, including the raw weights of each channel. Credit counter Priority pointer Maximum idle tolerance threshold The authorized and locked channels of the previous arbitration, as well as the base address and region range corresponding to each channel; the parameters in the register management module are called in real time by other functional modules in the GST-WA core arbitration device; at the same time, the bit width design of the relevant parameters supports parameterized configuration and can be adjusted according to the system QoS granularity and the maximum burst transmission length to adapt to the long burst transmission requirements of heterogeneous channels. 2.2 Priority Decision and Locking Module: This module performs classification decisions and outputs arbitration results based on the current state of the GST-WA core arbitration device. First, it determines whether the GST-WA core arbitration device is in a priority-locked state, i.e., whether the transaction request for the current authorized channel has not yet ended and the credit counter has not been exhausted. If it is in a priority-locked state, the module skips the global priority decision logic and directly outputs the decision result of the current authorized channel through the bypass path to ensure the continuity of burst transmissions and reduce arbitration latency. If it is not in a priority-locked state, the module executes the global priority decision logic and calls the priority pointer in the register management module. and credit counters for each channel The standardized arbitration request signal input is combined with calculations to generate a new judgment and determine the authorized channel; 2.

3. Strategy Dynamic Update Module: This module monitors the decision results of the priority and locking modules in real time and dynamically updates the parameters in the register management module accordingly. Its function is to execute the credit refresh mechanism triggered by authorization switching: when an authorization channel switch is detected or the GST-WA core arbitration device is idle for an extended period, the strategy dynamic update module immediately reloads the credit counter of the previous authorization channel to its original weight to ensure rapid response for each channel in intermittent request scenarios. Simultaneously, when the credit counter of an authorization channel is exhausted, the strategy dynamic update module triggers the priority pointer. The update allows for cyclical shifting according to the physical order of the channels, thereby redefining the scanning starting point for the next round of arbitration; 2.4 Bus Protocol Adaptation Module: This module receives transaction requests from authorized channels output by the priority decision and locking module and converts them into a standard format compatible with the bus protocol of the lower-level memory controller. The bus protocol adaptation module consists of a protocol encapsulation unit and a transaction tracking unit. The protocol encapsulation unit calls the base addresses and region ranges configured in the register management module, calculates the base address offset, converts the logical address in the transaction request into a physical storage address, and performs data stream encapsulation. The transaction tracking unit monitors and records the execution progress and completion status of transaction requests sent to the memory controller in real time, and generates a backpressure signal to feed back to the channel transaction management module.

2. An adaptive QoS arbitration method for image systems, characterized in that, The method implemented using the apparatus of claim 1 specifically includes the following steps: Step 1: Use the channel transaction management module to receive, buffer, and internally arbitrate external heterogeneous requests, and convert them into standardized signals required by the GST-WA core arbitration device. Step 1.1: The channel transaction management module of each channel receives heterogeneous data streams from different clock domains; using the asynchronous FIFO mechanism, the write transaction data stream is input and buffered into the write buffer WR_Buffer, and the read transaction data stream is read from the read buffer RD_Buffer for output; Step 1.2: The internal transaction state machine (FSM) performs internal arbitration on read and write transactions based on the backpressure signal returned by the bus protocol adaptation module, the read and write buffer status, and the preset internal arbitration strategy. It determines whether the current channel is in a read, write, or idle state and outputs the decision signal Sel. Step 1.3: Based on the FSM's decision, the data path control unit MUX guides the write request data stream from the write buffer to the GST-WA core arbitration device, or establishes a path for the read request data stream from the GST-WA core arbitration device to the read buffer; simultaneously, the standardized request encapsulation unit PACK formats and encapsulates the read / write instruction information to generate a standardized arbitration request signal. ,in It is the number of channels; Step 2: Execute priority decisions and resource authorizations within the GST-WA core arbitration device, and dynamically update the priority pointer. and credit counters for each channel ; Step 2.1: Initialize the priority pointer And credit counters for all channels Set to the corresponding original weight. By default, the GST-WA core arbitration device is set to an unlocked priority state upon first power-on. Step 2.2: The GST-WA core arbitration device executes a global priority decision based on the standardized arbitration request signal. Priority pointer and credit counters for each channel Select authorized channels The authorized channel will be used as the locked channel, and the GST-WA core arbitration device will be updated to a priority locked state. Step 2.3: Proceed to the next round of arbitration, based on the current standardized arbitration request signal. The signal is compared with the locked channel in step 2.

2. If the locked channel in step 2.2 does not exist in the channel to which the current standardized arbitration request signal belongs, it is considered a mismatch, and the process proceeds to step 2.

2. Otherwise, it is considered a match, and the process continues to check whether the credit counter of the locked channel is greater than zero. If the check conditions are met, skip the arbitration logic and update the locked channel to the authorized channel; if the check conditions are not met, proceed to step 2.

2. Step 2.4, if authorized channel Selected, enable the credit counter Perform a decrement operation; when When the value is reduced to zero, the priority pointer is triggered. Update, make the priority pointer The pointing position is switched cyclically according to the channel sequence; at the same time, if If it is still valid, then Immediately reload to initial weights ;like invalid, No overload; Step 2.5: If this is not the first round of arbitration, record the authorization channel of the previous round of arbitration. The results will be compared with the authorized channels for this round of arbitration to determine whether the arbitration outcome has changed. If a change has occurred, the authorized channels will be triggered immediately. of Restore to its initial weights ; Step 2.6: Separately count consecutive periods without valid authorization and bus idle periods. If at least one exceeds the maximum idle tolerance threshold... This will trigger an emergency global credit refresh, affecting all channels. Restore to its initial weights ; Step 3: The bus protocol adaptation module is responsible for encapsulating and converting the arbitration result into a bus protocol transaction, and sending a bus backpressure signal to the channel transaction management module. Step 3.1: The protocol encapsulation unit receives the transaction request carried by the authorized channel in Step 2; the protocol encapsulation unit performs base address offset calculation according to the parameterizable base address and region range of each channel, converts the logical address into the physical storage address corresponding to the lower-level memory; performs address encapsulation, packing or unpacking operations on the data stream to meet the format requirements of the lower-level memory controller bus protocol, and sends the processed transaction request to the memory controller; Step 3.2: The transaction tracking unit monitors and records the execution progress and completion status of the transaction requests sent to the memory controller in step 3.1 in real time, and generates a backpressure signal based on this, which is fed back to the upper-level channel transaction management module as the basis for the internal transaction state machine execution decision in step 1.

2.

3. The adaptive QoS arbitration method for image systems according to claim 2, characterized in that, In step 1.3, the standardized request encapsulation unit PACK is responsible for performing parameterized address mapping, allocating different storage areas for transaction requests according to the channel number, and each storage area is preset to be able to hold a complete frame of data; a state machine-level space is reserved in front of each storage area as a protection zone.

4. The adaptive QoS arbitration method for image systems according to claim 2, characterized in that, In step 1.3, the standardized arbitration request signal contains only one valid signal and one transaction type indicator signal, where Type=0 indicates a read request and Type=1 indicates a write request.

5. The adaptive QoS arbitration method for image systems according to claim 2, characterized in that, In step 1.3, the standardized request encapsulation unit PACK stores the write transaction data and sends it down after the lower level obtains authorization.

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