Chip, chip pin state identification method and electronic equipment

Abstract

The invention relates to the technical field of electronic equipment hardware configuration, and discloses a chip, the chip is electrically connected with a host through a clock signal line and a data signal line, the chip comprises a positive and negative connection identification circuit, the positive and negative connection identification circuit is electrically connected with the host, and the positive and negative connection identification circuit is configured to receive a positive and negative connection identification code sent by the host; generating a pin identification mark according to the positive and negative connection identification code; the identification mechanism module is electrically connected with the positive and negative connection identification circuit; the identification mechanism module is configured to obtain a first device identifier according to the pin identification identifier, wherein the first device identifier represents the access state of a target pin of the chip. The chip can automatically identify the access state of the target pin of the chip. Therefore, the target pin of the chip can normally communicate with the host no matter the target pin is connected to the clock signal line or the data signal line. And in the SMT chip mounting link, the chip mounting error probability is reduced, and the production yield of the electronic equipment is improved. The invention also discloses a chip pin state identification method and electronic equipment.

Description

Technical Field

[0001] This application relates to the field of electronic device hardware configuration technology, such as a chip, a method for identifying chip pin states, and an electronic device. Background Technology

[0002] Currently, in the hardware configurations of some electronic devices, a host, such as an application processor (AP), shares the same I²C (Inter-Integrated Circuit) bus with two chips (slave devices). However, typically for optimized PCB layout and signal integrity, the physical locations of the clock and data pins of the two chips are reversed in the PCB layout of electronic devices. This necessitates two types of chips: one where the first pin is the clock pin and the second pin is the data pin, and the other where the first pin is the data pin and the second pin is the clock pin. For example, in camera module manufacturing, discrete optical image stabilization (OIS) chips are widely used due to their cost advantage. The host in the camera module shares the same I²C bus with two OIS chips. In the PCB layout of the camera module, the physical locations of the clock and data pins of the two OIS chips are reversed. During the SMT (Surface Mount Technology) assembly process in electronic device manufacturing, the physical locations of the chip clock and data pins are usually manually distinguished to differentiate between different types of chips. Manual identification is prone to errors, which can easily lead to incorrect chip placement. Furthermore, in related technologies, the chip cannot recognize the connection status of its own pins. This results in the chip being unable to communicate properly with the host in the event of a placement error, thus reducing the production yield of electronic devices.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0005] This disclosure provides a chip, a method for identifying chip pin states, and an electronic device to improve the production yield of the electronic device.

[0006] In some embodiments, the chip is electrically connected to a host via clock signal lines and data signal lines. The chip includes: a reversible connection identification circuit electrically connected to the host, configured to receive a reversible connection identification code sent by the host and generate a pin identification identifier based on the reversible connection identification code; and an identification mechanism module electrically connected to the reversible connection identification circuit. The identification mechanism module is configured to obtain a first device identifier based on the pin identification identifier, the first device identifier representing the access status of a target pin of the chip. The target pin includes a clock pin and a data pin, and the access status represents the type of signal lines connected to the clock pin and the data pin, respectively.

[0007] In some embodiments, the method for identifying chip pin states is applied to the aforementioned chip, and the method includes: receiving a positive / reverse connection identification code sent by a host; generating a pin identification identifier based on the positive / reverse connection identification code; obtaining a first device identifier based on the pin identification identifier; the first device identifier characterizing the access state of a target pin of the chip; wherein the target pin includes a clock pin and a data pin, and the access state characterizes the type of signal lines to which the clock pin and the data pin are respectively connected.

[0008] In some embodiments, the method for identifying chip pin states is applied to a host, the method comprising: sending a positive / negative connection identification code to the chip, triggering the chip to generate a pin identification identifier based on the positive / negative connection identification code; and triggering the chip to obtain a first device identifier based on the pin identification identifier, the first device identifier representing the access state of a target pin of the chip; wherein the target pin includes a clock pin and a data pin, and the access state represents the type of signal lines to which the clock pin and the data pin are respectively connected.

[0009] In some embodiments, the method for identifying chip pin status includes: a host sending a reversible connection identification code to the chip; the chip receiving the reversible connection identification code sent by the host; the chip generating a pin identification identifier based on the reversible connection identification code; and the chip obtaining a first device identifier based on the pin identification identifier, wherein the first device identifier represents the access status of the target pin; wherein the target pin includes a clock pin and a data pin, and the access status represents the type of signal lines to which the clock pin and the data pin are respectively connected.

[0010] In some embodiments, the electronic device includes the chip described above.

[0011] The chip, method for chip pin status identification, and electronic device provided in this disclosure can achieve the following technical effects: The chip, through a reversible connection identification circuit, can generate a pin identification identifier based on the reversible connection identification code sent by the host, and obtain a device identifier representing the target pin's connection status based on the pin identification identifier through a set identification mechanism module. This enables the chip to automatically identify the connection status of its target pins. Consequently, the chip's target pins can communicate normally with the host regardless of whether they are connected to a clock signal line or a data signal line. Thus, in the SMT (Surface Mount Technology) placement process, manual identification of the chip's pins is unnecessary, reducing the probability of placement errors and improving the production yield of the electronic device.

[0012] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0013] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the format of a communication frame encapsulated with a positive / negative connection identification code, provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a positive / negative connection identification circuit provided in an embodiment of this disclosure; Figure 4 This is a flowchart illustrating a method for identifying the state of chip pins provided in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating another method for identifying chip pin states provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a camera module provided in an embodiment of this disclosure; Figure 7 This is a flowchart illustrating another method for identifying chip pin states provided in an embodiment of this disclosure. Detailed Implementation

[0014] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0015] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0016] Unless otherwise stated, the term "multiple" means two or more.

[0017] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0018] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0019] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0020] In this embodiment, the electronic device includes a smartphone, tablet computer, camera, drone, vehicle imaging system, etc. The electronic device includes a camera module, which integrates a chip and a host. The chip is a slave device, such as a discrete optical image stabilization (OIS) chip. The host is the master device, such as a master control chip or a System-on-a-Chip (SoC) with an integrated I²C master controller. The host and the chip are electrically connected via a serial clock signal line and a serial data signal line. The clock signal line transmits a clock signal generated by the host to synchronize data transmission between the host and the chip. The data signal line is used for bidirectional transmission of serial data and address information between the host and the chip.

[0021] Combination Figure 1As shown, this embodiment of the disclosure provides a chip 1, which is electrically connected to a host computer via clock signal lines and data signal lines. The chip 1 includes a positive / negative connection identification circuit 2 and an identification mechanism module 3. The positive / negative connection identification circuit is electrically connected to the host computer, and the identification mechanism module 3 is electrically connected to the positive / negative connection identification circuit 2.

[0022] Reversible connection identification circuit 2 is configured to receive a reversible connection identification code sent by the host and generate a pin identification identifier based on the code. Identification mechanism module 3 is configured to obtain a first device identifier based on the pin identification identifier. The first device identifier characterizes the access status of the target pin of chip 1. The target pin includes clock pins and data pins. The access status characterizes the type of signal lines connected to the clock pin and data pin respectively. Figure 1 The first pin 4 shown is the clock pin, and the second pin 5 is the data pin.

[0023] The chip provided in this disclosure can generate a pin identification identifier based on the reversible connection identification code sent by the host through an internal reversible connection identification circuit. The identification mechanism module then obtains a device identifier representing the target pin's connection status based on this identifier. This allows the chip to automatically identify the connection status of its target pins. Consequently, the chip's target pins can communicate normally with the host regardless of whether they are connected to a clock signal line or a data signal line, improving the chip's fault tolerance. Furthermore, during the SMT (Surface Mount Technology) placement process, manual pin identification is no longer required, reducing the probability of placement errors and improving the production yield of electronic devices.

[0024] In some embodiments, the connection state of the target pin includes a positive connection state and a negative connection state. In the positive connection state, the chip's clock pin is connected to the clock signal line, and the chip's data pin is connected to the data signal line. In the negative connection state, the chip's clock pin is connected to the data signal line, and the chip's data pin is connected to the clock signal line.

[0025] In some embodiments, the host broadcasts a reversible connection identification code to the chip. This code is a preset number of binary digits. The reversible connection identification code triggers the chip to identify the connection status of its target pin based on this code. The code is encapsulated in a communication frame, which includes: a start flag, a command code, the reversible connection identification code, a checksum, and an end flag. For example, as shown... Figure 2 As shown, Figure 2 This is a schematic diagram of the communication frame format, which includes: a 1-bit start flag, an 8-bit instruction code, a 128-bit positive / negative identification code, an 8-bit check code, and a 1-bit end flag.

[0026] Optionally, the reversible connection identification circuit includes a forward identification circuit and a reverse identification circuit. The pin identification identifier includes a forward identification identifier or a reverse identification identifier. The reversible connection identification circuit is configured to generate a pin identification identifier based on the reversible connection identification code in the following manner: When the forward identification circuit receives the forward / reverse identification code sent by the host, it compares the forward / reverse identification code with a preset identification code. If the comparison is successful, a forward identification identifier is generated.

[0027] When the reverse identification circuit receives the positive and negative connection identification code sent by the host, it compares the positive and negative connection identification code with the preset identification code. If the comparison is successful, a reverse identification identifier is generated.

[0028] Further, the reversible identification code is compared with a preset identification code, including: if the reversible identification code and the preset identification code are exactly the same, the comparison is determined to be successful. In some embodiments, the forward identification code is "1" and the reverse identification code is "0".

[0029] The forward identification circuit includes a preset number of first registers, a preset number of first XOR gates, and a first AND gate. The preset number is 128. Figure 3 This is a schematic diagram of the positive / negative connection identification circuit. (Combined with...) Figure 3As shown, the forward / reverse identification circuit includes a forward identification circuit 21 and a reverse identification circuit 22. The forward identification circuit 21 includes 128 first registers 211, 128 first XOR gates 212, and one first AND gate 213. The clock terminal of each first register 211 is connected to the first pin 4 of the chip, i.e., connected to the clock pin. The data input terminal D of the first first register is connected to the second pin 5 of the chip, i.e., connected to the data pin. The data output terminal Q of the first first register is connected to the data input terminal D of the second first register and the first input terminal of the first first XOR gate. The data output terminal Q of the second first register is connected to the data input terminal D of the third first register and the first input terminal of the second first XOR gate. The data output terminal Q of the third first register is connected to the data input terminal D of the fourth first register and the first input terminal of the third first XOR gate, and so on, until the data output terminal Q of the (n-1)th first register is connected to the data input terminal D of the nth first register and the first input terminal of the (n-1)th first XOR gate, and the data output terminal Q of the nth first register is connected to the first input terminal of the nth first XOR gate. n is a preset number. The second input terminals of each first XOR gate 212 are connected to ground or power supply respectively. When the second input terminal of a first XOR gate is connected to ground, the input data of the second input terminal of the first XOR gate is "0"; when the second input terminal of a first XOR gate is connected to power supply, the input data of the second input terminal of the first XOR gate is "1". The output terminals of each first XOR gate are sequentially connected to the input terminals of each first AND gate 213, and the output terminals of the first AND gate 213 are connected to the identification mechanism module. The connection status of the second input terminals of each first XOR gate, i.e., whether connected to ground or power supply, is preset. Each first register is used to store one bit of data in the positive / negative identification code and transmits the stored data to the first input terminal of the corresponding first XOR gate. Each first XOR gate compares the input data of its first and second input terminals and generates corresponding output data based on the comparison result. When the input data of the first and second input terminals of the first XOR gate are the same, the output data of the first XOR gate is "1". This output data is then transmitted to the first AND gate. The first AND gate generates corresponding output data based on the input data at each input terminal. Specifically, if all input data to the first AND gate are "1", the output data will be "1", indicating a successful match between the positive and negative identification code and the preset identification code, thus generating a positive identification identifier. For example, Figure 3The first register output data P_Q1 is given to the first input of the first XOR gate, the second register output data P_Q2 is given to the first input of the second XOR gate, and so on, until the 128th register output data P_Q128 is given to the first input of the 128th XOR gate. The second input of the first XOR gate is a preset identification code bit 1, the second XOR gate is a preset identification code bit 2, and so on, until the 128th XOR gate is a preset identification code bit 128. When P_Q1~P_Q128 are exactly the same as the preset identification code bits 1~128, the output data of each XOR gate is "1", and consequently, the output data of the first AND gate is also "1". This confirms that the positive and negative identification codes have successfully matched with the preset identification codes, generating a positive identification identifier, for example, "1".

[0030] The preset identification code is a preset number of binary digits, such as a 128-bit binary number. The preset identification code sequentially corresponds to the input data of the second input terminal of each first XOR gate. That is, the first bit of the preset identification code, i.e., the preset identification code bit 1, corresponds to the input data of the second input terminal of the first first XOR gate, and so on, with the nth bit of the preset identification code, i.e., the preset identification code bit n, corresponding to the input data of the second input terminal of the nth first XOR gate. For example, if the second input terminal of the mth first XOR gate is connected to ground, i.e., the input data of the second input terminal of the first XOR gate is "0", the corresponding data of the mth preset identification code bit is "0". As another example, if the second input terminal of the mth first XOR gate is connected to a power source, i.e., the input data of the second input terminal of the first XOR gate is "1", the corresponding data of the mth preset identification code bit is "1". Where 1 ≤ m ≤ n, and m and n are both positive integers.

[0031] The reverse identification circuit includes a preset number of second registers, a preset number of second XOR gates, and one second AND gate. Combined with... Figure 3As shown, the inverting identification circuit 22 includes 128 second registers 221, 128 second XOR gates 222, and one second AND gate 223. The clock input of each second register 221 is connected to the second pin 5 of the chip, i.e., the data pin. The data input D of the first second register is connected to the first pin 4 of the chip, i.e., the clock pin. The data output Q of the first second register is connected to the data input D of the second second register and the first input of the first second XOR gate. The data output Q of the second second register is connected to the data input D of the third second register and the first input of the second second XOR gate. The data output Q of the third second register is connected to the data input D of the fourth second register and the first input of the third second XOR gate, and so on, until the (n-1)th second register's data output Q is connected to the data input D of the nth second register and the first input of the (n-1)th second XOR gate, and the data output Q of the nth second register is connected to the first input of the nth second XOR gate. The second input of each second XOR gate 222 is connected to ground or power supply. When the second input of the second XOR gate is connected to ground, the input data of the second input of the second XOR gate is "0"; when the second input of the second XOR gate is connected to power, the input data of the second input of the second XOR gate is "1". The outputs of each second XOR gate are sequentially connected to the inputs of the second AND gate 223, and the outputs of the second AND gate 223 are connected to the identification mechanism module. The connection status of the second inputs of each second XOR gate, i.e., whether connected to ground or power, is preset. Each second register is used to store one bit of data in the positive / negative identification code and transmits the stored data to the first input of the corresponding second XOR gate. Each second XOR gate compares the input data of the first and second inputs and generates corresponding output data based on the comparison result. When the input data of the first and second inputs of the second XOR gate are the same, the output data of the second XOR gate is "1" and the output data is transmitted to the second AND gate. The second AND gate generates corresponding output data based on the input data of each input. In this configuration, if all input data to the second AND gate are "1", then the output data of the second AND gate is "1", indicating that the forward and reverse identification codes have been successfully compared with the preset identification codes, and a reverse identification identifier is generated. For example, Figure 3The first second register outputs data N_Q1, which is then fed to the first input of the first second XOR gate; the second second register outputs data N_Q2, which is fed to the first input of the second second XOR gate; and so on, until the 128th second register outputs data N_Q128, which is fed to the first input of the 128th second XOR gate. The input data to the second input of the first second XOR gate is a preset identification code bit 1; the input data to the second input of the second second XOR gate is a preset identification code bit 2; and so on, until the input data to the second input of the 128th second XOR gate is a preset identification code bit 128. When N_Q1~N_Q128 are exactly the same as the preset identification code bits 1~128, the output data of each second XOR gate is "1", and consequently, the output data of the second AND gate is also "1". This confirms that the positive and negative identification codes have successfully matched the preset identification codes, generating a reverse identification flag, for example, "0".

[0032] The preset identification codes sequentially correspond to the input data at the second input terminals of each second XOR gate. That is, the first bit of the preset identification code, i.e., preset identification code bit 1, corresponds to the input data at the second input terminal of the first second XOR gate, and so on. The nth bit of the preset identification code, i.e., preset identification code bit n, corresponds to the input data at the second input terminal of the nth second XOR gate. For example, if the second input terminal of the mth second XOR gate is connected to ground, i.e., the input data at the second input terminal of this second XOR gate is "0", the corresponding data at the mth preset identification code bit is "0". As another example, if the second input terminal of the mth second XOR gate is connected to a power source, i.e., the input data at the second input terminal of this second XOR gate is "1", the corresponding data at the mth preset identification code bit is "1".

[0033] If the target pin of the chip is connected in the positive connection state (i.e., the chip's clock pin is connected to the clock signal line and the chip's data pin is connected to the data signal line), and the clock terminals of each first register of the forward identification circuit are connected to the clock pins, then each first register can receive the clock signal sent by the host. The data input terminal of the first first register is connected to the data pin. Therefore, when the host sends the positive / negative connection identification code to the chip, each first register of the forward identification circuit can sequentially store the binary values ​​in the positive / negative connection identification code, meaning the forward identification circuit can receive the positive / negative connection identification code sent by the host. In this case, each first register outputs the stored data to the first input terminal of the corresponding first XOR gate. Each first XOR gate compares the input data at its first input terminal with the input data at its second input terminal. If the comparison result is the same, the output data of the first XOR gate is "1". Each first XOR gate then transmits the output data corresponding to the comparison result to the first AND gate. If the output data of all the first XOR gates is "1", and the output data of the first AND gate is also "1", then the positive / negative identification code has been successfully matched with the preset identification code. A positive identification identifier "1" is then generated. However, in the positive connection state, because the clock terminals of each second register in the negative identification circuit are connected to the data signal line, none of the second registers can receive the clock signal sent by the host. Furthermore, the data input terminal of the first second register is connected to the clock signal line. Therefore, in this case, the negative identification circuit cannot receive the positive / negative identification code sent by the host.

[0034] If the target pin of the chip is connected in reverse (i.e., the chip's clock pin is connected to the data signal line, and the chip's data pin is connected to the clock signal line), and the clock terminals of each second register in the reverse identification circuit are connected to the data pins, then each second register can receive the clock signal sent by the host. The data input terminal of the first second register is connected to the clock pin, so when the host sends a positive / reverse identification code to the chip, each second register in the reverse identification circuit can sequentially store the binary values ​​of the positive / reverse identification code, meaning the reverse identification circuit can receive the positive / reverse identification code sent by the host. In this case, each second register outputs the stored data to the first input terminal of the corresponding second XOR gate. Each second XOR gate compares the input data at the first input terminal with the input data at the second input terminal. If the comparison results are the same, the output data of the second XOR gate is "1". Each second XOR gate then transmits the output data corresponding to the comparison result to the second AND gate. If the output data of all the second XOR gates is "1", and the output data of the second AND gate is also "1", then the forward / reverse identification code has been successfully matched with the preset identification code, and a reverse identification flag "0" is generated. However, in the reverse state, since the clock terminals of each first register in the forward identification circuit are connected to the clock signal line, none of the first registers can receive the clock signal sent by the host. Furthermore, the data input terminal of the first first register is connected to the data signal line. Therefore, in this situation, the forward identification circuit cannot receive the forward / reverse identification code sent by the host.

[0035] Combination Figure 1 As shown, the identification mechanism module 3 includes a device identifier selection module 31. The device identifier selection module 31 is electrically connected to the positive / negative connection identification circuit 2. The identification mechanism module is configured to obtain a first device identifier based on the pin identification identifier in the following manner: the device identifier selection module 31 is configured to receive the pin identification identifier sent by the positive / negative connection identification circuit, and select the first device identifier corresponding to the pin identification identifier according to a preset logical correspondence.

[0036] In some embodiments, the first device identifier is an identifier number. It represents the connection state of the target pin of the chip. The preset logical correspondence is as follows: when the pin identification identifier is a positive identification identifier, the corresponding first device identifier is ID1, where ID1 indicates that the connection state of the target pin of the chip is positive, that is, the chip's clock pin is connected to the clock signal line, and the chip's data pin is connected to the data signal line. When the pin identification identifier is a negative identification identifier, the corresponding first device identifier is ID2, where ID2 indicates that the connection state of the target pin of the chip is reversed, that is, the chip's clock pin is connected to the data signal line, and the chip's data pin is connected to the clock signal line.

[0037] Combination Figure 1 As shown, the identification mechanism module 3 includes a logic control module 32, and a device identifier selection module 31 electrically connected to the logic control module 32. The device identifier selection module 31 is also configured to send the selected first device identifier to the logic control module. The logic control module 32 is electrically connected to the positive / negative identification circuit 2. The logic control module 32 includes a read control module 321, a write control module 322, a first cache module 323, a second cache module 324, and a third cache module 325. The first cache module 323 is electrically connected to the device identifier selection module 31, and the second cache module 324 is electrically connected to the device identifier selection module 31. The first cache module 323 is used to store the first device identifier ID1, and the second cache module 324 is used to store the first device identifier ID2.

[0038] In some embodiments, when the device identifier selection module receives a positive identification identifier "1", it selects ID1 stored in the first cache module 323 according to the logical correspondence. When the device identifier selection module receives a negative identification identifier "0", it selects ID2 stored in the second cache module according to the logical correspondence. The device identifier selection module then sends the selected first device identifier to the logic control module. Thus, because the first device identifier represents the access state of the chip's target pin, the selection of the corresponding device identifier by the device identifier selection module enables the chip to automatically identify the access state of its target pin.

[0039] The chip also includes a storage module 6. The storage module is a non-volatile memory module. The storage module 6 is electrically connected to the read control module 321 and write control module 322 of the logic control module 32. The storage module 6 stores first device identifiers ID1 and ID2. When the electronic device is powered on, the logic control module reads the first device identifiers from the storage module through the read control module and stores them in a first cache module and a second cache module, respectively. Specifically, the first device identifier ID1 is stored in the first cache module, and the first device identifier ID2 is stored in the second cache module. This facilitates the device identifier selection module in selecting the corresponding first device identifier from either the first cache module or the second cache module.

[0040] The logic control module 32 is configured to receive an address registration request sent by the host. This address registration request includes a second device identifier and address information. The logic control module 32 is configured to match the first device identifier with the second device identifier. If the match is successful, the address information is stored, and a completion message is sent back to the host. The second device identifier is an identifier number stored in the host that represents the access status of a target pin of the chip. For example, if the second device identifier is ID1, the access status of the target pin of the chip is positive; if the second device identifier is ID2, the access status of the target pin of the chip is negative.

[0041] Optionally, the logic control module is configured to match the first device identifier with the second device identifier by comparing the first device identifier with the second device identifier, and determining that the match is successful if the first device identifier and the second device identifier are exactly the same.

[0042] In related technologies, address allocation is performed using I²C address hard encoding. This method results in a high address conflict rate. In this embodiment, the host initiates an address registration request carrying a second device identifier and allocates a unique logical address to the chip. If the first device identifier and the second device identifier match successfully, the chip stores the address information and sends a preset completion message back to the host. This achieves address allocation for the chip. Furthermore, upon receiving the completion message, the host can identify the connection status of the target pin of the chip. In this way, regardless of whether the target pin of the chip is connected to a clock signal line or a data signal line, it can be automatically identified, and address registration can be successful, improving the address registration success rate. This enables normal communication with the host and improves the fault tolerance of the chip.

[0043] In some embodiments, when the logic control module receives a first device identifier of ID1 (indicating that the target pin of the chip is in a positive state) and simultaneously receives a second device identifier of ID1 in the address registration request sent by the host (meaning the first device identifier and the second device identifier are identical), a successful match is determined. The logic control module writes the address information to the storage module 6 via the write control module 322 for storage. It then sends a preset completion message back to the host to trigger the host to recognize that the target pin of the chip is in a positive state.

[0044] Combination Figure 1 As shown, the identification mechanism module 3 also includes an adaptive routing switch matrix 33. The adaptive routing switch matrix 33 is electrically connected to the logic control module 32.

[0045] The logic control module 32 is configured to receive a pin mapping table corresponding to the second device identifier sent by the host; compare the received pin mapping table with the current state of all pins; and store the pin mapping table if the comparison is successful. The logic control module 32 is also configured to send the pin mapping table to the adaptive routing switch matrix 33. The adaptive routing switch matrix 33 is configured to reconstruct the functional allocation of all pins of the chip based on the pin mapping table.

[0046] The pin mapping table stores multiple pins and their corresponding function selections. If the function selection for a pin stored in the pin mapping table is exactly the same as the current function selection for all pins on the chip, the matching is considered successful. Otherwise, the matching is considered unsuccessful.

[0047] For example, the pin mapping table stores: pin 1 corresponds to the clock signal, pin 2 corresponds to the data signal, pin 1 corresponds to the first function, and pin 2 corresponds to the second function. The current state of all pins is the current function selection state of all pins in the chip. For example, all pins of the chip include pin 1, pin 2, first driver pin, second driver pin, etc. The current state of all pins of the chip is: pin 1 corresponds to the clock signal, pin 2 corresponds to the data signal, first driver pin corresponds to the first function, and second driver pin corresponds to the second function. Therefore, it is determined that the pin mapping table and the current state of all pins have been successfully matched.

[0048] If the comparison is successful, the logic control module 32 writes the pin mapping table to the storage module 6 via the write control module 322 for storage. If the comparison fails, the logic control module 32 returns an error message to the host.

[0049] Optionally, after storing the pin mapping table, the logic control module 32 is also configured to send preset response information back to the host, enabling the host to confirm the function selection of the chip pins. After the chip restarts, the logic control module sends the pin mapping table to the adaptive routing switch matrix.

[0050] In one embodiment, upon receiving a response from the logic control module, the host controls the power supply to disconnect and reconnect, thereby restarting the chip. After restarting, the chip activates the address information and pin mapping table stored in the storage module 6. Specifically, the storage module 6 stores a registration completion identifier. After restarting, the control logic module reads the registration completion identifier from the storage module 6 via the read control module 321, automatically making the latest stored address information and pin mapping table effective. The logic control module reads the pin mapping table from the storage module 6 via the read control module 321 and stores it in the third cache module 325. The logic control module then sends the pin mapping table to the adaptive routing switch matrix 33 via the third cache module 325.

[0051] To prevent misidentification by the host, the pin mapping table sent by the host is authenticated and written into non-volatile memory, taking effect after a restart, which can prevent pin instability during switching.

[0052] Combination Figure 1 As shown, the adaptive routing switch matrix 33 includes a first selector 331, a second selector 332, a third selector 333, and a fourth selector 334. The control input of the first selector 331 is connected to the third buffer circuit 325 of the logic control module. Its first and second data inputs are connected to the second pin and the first pin, respectively, and its output is connected to the protocol processing module 7. The control input of the second selector 332 is connected to the third buffer circuit 325 of the logic control module. Its first and second data inputs are connected to the first pin and the second pin, respectively, and its output is connected to the protocol processing module 7. The control input of the third selector 333 is connected to the third buffer circuit 325 of the logic control module. Its first and second data inputs are connected to a preset second functional module and a preset first functional module, respectively, and its output is connected to the second drive pin 9. The control input of the fourth selector 334 is connected to the third buffer circuit 325 of the logic control module. Its first and second data inputs are connected to a preset first functional module and a preset second functional module, respectively, and its output is connected to the first drive pin 8. The first selector 331 is used to select the pin for the data input signal according to the received pin mapping table; the second selector 332 is used to select the pin for the clock input signal according to the received pin mapping table; the third selector 333 is used to select the function of the second drive pin according to the received pin mapping table; and the fourth selector 334 is used to select the function of the first drive pin according to the received pin mapping table.

[0053] After the chip restarts, it uses the newly stored pin mapping table, and the adaptive routing switch matrix dynamically switches internal signal paths according to the pin mapping table. This enables automatic functional adaptation and reliable operation of pins in both positive and negative connection states.

[0054] Optionally, the logic control module is further configured to receive confirmation information sent by the host and feed back the address information and preset update flag information to the host. The update flag information indicates that the pin mapping table of the chip has been updated. In this way, by having the host send confirmation information and feed back the address information and update flag information, the host can reconfirm the pin function selection status of the chip, achieving secondary verification.

[0055] Combination Figure 4 As shown, this disclosure provides a method for identifying the pin status of a chip, applied to the aforementioned chip. The method includes: Step S101: The chip receives the positive / negative connection identification code sent by the host.

[0056] In step S102, the chip generates a pin identification mark based on the positive / negative connection identification code.

[0057] In step S103, the chip obtains a first device identifier based on the pin identification identifier. The first device identifier indicates the access status of the target pin of the chip. The target pin includes clock pins and data pins. The access status indicates the type of signal lines connected to the clock pins and data pins, respectively.

[0058] The method for chip pin status identification provided in this disclosure can generate a pin identification identifier based on the positive / negative connection identification code sent by the host, and obtain a device identifier representing the target pin connection status based on the pin identification identifier. This enables the chip to automatically identify the connection status of its target pins. Consequently, the chip's target pins can communicate normally with the host regardless of whether they are connected to a clock signal line or a data signal line, improving the chip's fault tolerance. Furthermore, during the SMT (Surface Mount Technology) placement process, manual pin identification is no longer required, reducing the probability of placement errors and thus improving the production yield of electronic devices.

[0059] The chip includes a forward identification circuit and a reverse identification circuit; the pin identification identifier includes a forward identification identifier or a reverse identification identifier.

[0060] Optionally, the chip generates a pin identification identifier based on the reversible connection identification code, including: when the forward identification circuit receives the reversible connection identification code sent by the host, the chip compares the reversible connection identification code with a preset identification code; if the comparison is successful, the chip generates a forward identification identifier. When the reverse identification circuit receives the reversible connection identification code sent by the host, the chip compares the reversible connection identification code with a preset identification code; if the comparison is successful, the chip generates a reverse identification identifier.

[0061] Optionally, the chip obtains the first device identifier based on the pin identification identifier, including: the chip selects the first device identifier corresponding to the pin identification identifier according to a preset logical correspondence.

[0062] Optionally, after obtaining the first device identifier, the process further includes: the chip receiving an address registration request sent by the host, the address registration request including a second device identifier and address information. The chip matches the first device identifier with the second device identifier; if the match is successful, the chip stores the address information and sends a completion message back to the host.

[0063] Optionally, the chip matches the first device identifier with the second device identifier, including: the chip compares the first device identifier with the second device identifier, and if the first device identifier and the second device identifier are exactly the same, the chip determines that the match is successful.

[0064] Optionally, after sending completion information to the host, the process further includes: the chip receiving a pin mapping table corresponding to the second device identifier sent by the host. The chip compares the pin mapping table with the current state of all pins, and if the comparison is successful, the chip stores the pin mapping table.

[0065] Optionally, after storing the pin mapping table, the chip further includes: sending a preset response message to the host and performing a restart. After restarting, the chip uses the newly stored address information and pin mapping table, and reconstructs the functional allocation of all chip pins based on this pin mapping table.

[0066] Optionally, after restarting, the chip further includes: receiving confirmation information sent by the host, and feeding back address information and preset update flag information to the host. The update flag information indicates that the chip's pin mapping table has been updated.

[0067] This disclosure provides a method for identifying chip pin states, applied to a host computer, comprising: The host sends a positive / negative connection identification code to the chip, triggering the chip to generate a pin identification identifier based on the positive / negative connection identification code; and triggers the chip to obtain a first device identifier based on the pin identification identifier, the first device identifier representing the access status of the target pin of the chip; wherein, the target pin includes a clock pin and a data pin, and the access status represents the type of signal line to which the clock pin and the data pin are respectively connected.

[0068] The method for chip pin status identification provided in this disclosure can trigger the chip to generate a pin identification identifier by sending a positive / negative connection identification code to the chip, and obtain a device identifier representing the access status of the target pin based on the pin identification identifier. This allows the chip to automatically identify the access status of its target pins. Consequently, the chip's target pins can communicate normally with the host regardless of whether they are connected to a clock signal line or a data signal line, improving the chip's fault tolerance. Furthermore, during the SMT (Surface Mount Technology) placement process, manual pin identification of the chip is no longer required, reducing the probability of placement errors and thus improving the production yield of electronic devices.

[0069] In some embodiments, the host sends a reversible connection identification code to the chip via broadcast. After broadcasting the identification code, at a preset time interval (e.g., 1 ms), the host sends an address registration request to the chip. This request includes a second device identifier and address information. The chip is triggered to match the first device identifier with the second device identifier. If a match is successful, the address information is stored, and a completion message is sent back to the host. Upon receiving the completion message from the chip, the host determines the connection status of the target pin and sends a pin mapping table corresponding to the second device identifier to the chip. The chip is triggered to compare the pin mapping table with the current status of all pins. If a match is successful, the chip stores the pin mapping table and sends a preset response message to the host. Upon receiving the response message from the chip, the host disconnects and reconnects the chip's power supply to restart the chip and triggers the chip to activate the newly stored address information and pin mapping table. The host sends an acknowledgment message to the chip and receives the address information and preset update flag information from the chip.

[0070] Combination Figure 5 As shown, this disclosure provides a method for identifying the state of chip pins, including: Step S201: The host sends a positive / negative connection identification code to the chip.

[0071] In step S202, the chip receives the positive / negative connection identification code sent by the host.

[0072] In step S203, the chip generates a pin identification mark based on the positive / negative connection identification code.

[0073] In step S204, the chip obtains a first device identifier based on the pin identification identifier. The first device identifier indicates the access status of the target pin. The target pin includes a clock pin and a data pin, and the access status indicates the type of signal lines to which the clock pin and the data pin are respectively connected.

[0074] In step S205, the host sends an address registration request to the chip, the address registration request including a second device identifier and address information.

[0075] Step S206: The chip receives the address registration request sent by the host; matches the first device identifier with the second device identifier, and if the match is successful, stores the address information.

[0076] In step S207, the chip sends a completion message back to the host.

[0077] In step S208, the host receives the completion information fed back by the chip.

[0078] In step S209, the host sends the pin mapping table corresponding to the second device identifier to the chip.

[0079] In step S210, the chip receives the pin mapping table corresponding to the second device identifier; and compares the pin mapping table with the current status of all pins. If the comparison is successful, the chip stores the pin mapping table.

[0080] In step S211, the chip sends a preset response message back to the host.

[0081] In step S212, the host receives the response information and controls the chip to restart.

[0082] In step S213, the chip is restarted and the functional allocation of all pins of the chip is reconstructed according to the pin mapping table.

[0083] In step S214, the host sends an acknowledgment message to the chip.

[0084] In step S215, the chip receives the confirmation information and sends the address information and the preset update flag information back to the host.

[0085] In step S216, the host receives the address information and preset update flag information fed back by the chip.

[0086] This embodiment integrates a reversible connection identification circuit, an identification mechanism module, and an adaptive routing switch matrix within the chip, while establishing a multi-layered interactive verification mechanism between the host and slave devices. The reversible connection identification circuit automatically detects the connection status of the target pins on the chip, and combined with a triple interactive mechanism of address registration, pin mapping table matching, and registration completion response, a complete configuration verification chain is formed. Based on the identification result and the mapping configuration issued by the host, the slave device dynamically adjusts its internal signal path through the adaptive routing switch, achieving automatic functional adaptation and reliable operation of the pins in both reversible and forward connection states. The chip includes a non-volatile memory module for reliably storing device identifiers, logical addresses, pin mapping tables, and configuration parameters, ensuring rapid recovery after a chip restart. This embodiment effectively solves the pin configuration error and fault tolerance problems during equipment soldering and production processes, significantly improving the production yield, equipment reliability, and maintenance efficiency of electronic devices.

[0087] This disclosure provides an electronic device, including an electronic device body and the aforementioned chip. The chip is mounted on the electronic device body. The mounting relationship described herein is not limited to placement within the electronic device, but also includes mounting connections with other components of the electronic device, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the chip can be adapted to suitable electronic device bodies to achieve other feasible embodiments.

[0088] In some embodiments, an electronic device is provided with a camera module, combined with Figure 6 As shown, Figure 6 This is a schematic diagram of the camera module. The camera module integrates a host 10 and two chips, namely a first chip 12 and a second chip 13, both of which are chips provided in this embodiment. The host 10 communicates with the two chips via a 2-wire clock and data interface, sharing a single bus. Figure 6 As shown, the clock signal line of the host 10 is interconnected with the first pin 121 of the first chip 12 and the second pin 132 of the second chip 13. The data signal line of the host 10 is interconnected with the second pin 122 of the first chip 12 and the first pin 131 of the second chip 13. The first drive pin 127 and the second drive pin 128 of the first chip 12 drive the X-direction position of the camera motor 11, and the first drive pin 137 and the second drive pin 138 of the second chip 13 drive the Y-direction position of the camera motor 11. Both the first chip 12 and the second chip 13 are OIS chips, with the first pin of both chips being clock pins and the second pin of both chips being data pins.

[0089] The first chip 12 also includes a reversibility identification circuit 123, an identification mechanism module 125, a storage module 124, a protocol processing module 126, power pins, and ground pins. The identification mechanism module 125 includes a device identifier selection module 1251, a logic control module 1253, and an adaptive routing switch matrix 1252. The storage module 124 is a non-volatile memory module. In the first chip 12, the first port of the reversibility identification circuit 123 is connected to the first pin 121, the second port is connected to the second pin 122, and the output is connected to the control input of the device identifier selection module 1251. The output of the device identifier selection module 1251 is connected to the logic control module 1253. The first port of the logic control module 1253 is connected to the first pin 121 via the reversibility identification circuit 123, and the second port is connected to the second pin 122 via the reversibility identification circuit 123. The logic control module 1253 is also electrically connected to the storage module 124 and the adaptive routing switch matrix 1252. The adaptive routing switch matrix 1252 is connected to the protocol processing module 126, the first drive pin 127, and the second drive pin 128, respectively.

[0090] The second chip 13 also includes a reversibility identification circuit 133, an identification mechanism module 135, a storage module 134, a protocol processing module 136, power supply pins, and ground pins. The identification mechanism module 135 includes a device identifier selection module 1351, a logic control module 1353, and an adaptive routing switch matrix 1352. The storage module 134 is a non-volatile memory module. In the second chip 13, the first port of the reversibility identification circuit 133 is connected to the first pin 131, the second port is connected to the second pin 132, and the output is connected to the control input of the device identifier selection module 1351. The output of the device identifier selection module 1351 is connected to the logic control module 1353. The first port of the logic control module 1353 is connected to the first pin 131 via the reversibility identification circuit 133, and the second port is connected to the second pin 132 via the reversibility identification circuit 133. The logic control module 1353 is also electrically connected to the storage module 134 and the adaptive routing switch matrix 1352, respectively. The adaptive routing switch matrix 1352 is connected to the protocol processing module 136, the first drive pin 137, and the second drive pin 138, respectively.

[0091] Since the first and second chips both have clock pins as their first pins and data pins as their second pins, and the first chip's first pin is connected to the clock signal line and the second pin to the data signal line, when the host broadcasts the positive / negative connection identification code, the first chip's positive identification circuit receives the code and generates a positive identification identifier. The first chip's device identifier selection module selects the corresponding first device identifier ID1 based on the positive identification identifier and sends it to the logic control module, enabling the first chip to recognize that its target pin is in the positive connection state. The second chip, on the other hand, has its first pin connected to the data signal line and its second pin connected to the clock signal line. When the host broadcasts the positive / negative connection identification code, the second chip's reverse identification circuit receives the code and generates a reverse identification identifier. The second chip's device identifier selection module selects the corresponding first device identifier ID2 based on the reverse identification identifier and sends it to the logic control module, enabling the second chip to recognize that its target pin is in the reverse connection state. When the host broadcasts an address registration request carrying the second device identifier ID1, the first chip receives the request. The first device identifier ID1 in the first chip matches the second device identifier ID1, the first chip stores the corresponding address information, and sends a completion message to the host, achieving successful address registration. The host then identifies the target pin of the first chip as being in the positive connection state. When the second chip receives the same address registration request, the first device identifier ID2 in the second chip does not match the second device identifier ID1, and the second chip does not respond. Conversely, when the host broadcasts an address registration request carrying the second device identifier ID2, the second chip receives the request. The first device identifier ID2 in the second chip matches the second device identifier ID2, the second chip stores the corresponding address information, and sends a completion message to the host, achieving successful address registration. The host then identifies the target pin of the second chip as being in the reverse connection state. When the first chip receives the same address registration request, the first device identifier ID1 in the first chip does not match the second device identifier ID2, and the first chip does not respond. This achieves address allocation between the first and second chips.

[0092] In this way, the chip can automatically recognize whether the target pin is connected to a clock signal line or a data signal line, and successfully register the address, thus improving the address registration success rate. This enables normal communication with the host and improves the chip's fault tolerance.

[0093] Combination Figure 6 As shown in the application scenarios, this disclosure provides a method for identifying the state of chip pins, such as... Figure 7 As shown, the method includes: In step S301, the host broadcasts the positive / negative connection identification code to the first chip and the second chip.

[0094] In step S302, both the first chip and the second chip receive the positive / negative connection identification code sent by the host.

[0095] In step S303, the first chip generates a forward identification mark based on the forward / reverse connection identification code; the second chip generates a reverse identification mark based on the forward / reverse connection identification code.

[0096] In step S304, the first chip obtains the first device identifier ID1 based on the forward identification identifier; the second chip obtains the first device identifier ID2 based on the reverse identification identifier.

[0097] In step S305, the host sends an address registration request carrying the second device identifier ID1 to the first chip and the second chip respectively. The address registration request also includes the first address information.

[0098] In step S306, the first chip receives the address registration request sent by the host; and if the first device identifier ID1 and the second device identifier ID1 are successfully matched, the first address information is stored. The second chip receives the address registration request sent by the host; however, if the first device identifier ID2 and the second device identifier ID1 are not successfully matched, no response is sent.

[0099] In step S307, the first chip sends a completion message back to the host.

[0100] In step S308, the host receives the completion information from the first chip.

[0101] In step S309, the host sends the pin mapping table corresponding to the second device identifier ID1 to the first chip and the second chip. Specifically, the host sends the pin mapping table to the first chip and the second chip through the first address information.

[0102] In step S310, the first chip receives the pin mapping table sent by the host; and the pin mapping table is successfully compared with the current status of all pins, so the first chip stores the pin mapping table. The second chip does not respond because the address information does not match.

[0103] In step S311, the first chip sends a preset response message back to the host.

[0104] In step S312, the host receives the response information from the first chip and controls the first chip to restart.

[0105] In step S313, the first chip performs a restart, enabling the newly stored first address information and pin mapping table.

[0106] In step S314, the host sends confirmation information to the first chip and the second chip through the first address information.

[0107] In step S315, the first chip receives the confirmation information and sends the first address information and the preset update flag information back to the host. The second chip does not respond because the address information does not match.

[0108] In step S316, the host receives the first address information and the preset update flag information fed back by the first chip to confirm that the first chip address registration is successful.

[0109] In step S317, the host sends an address registration request carrying the second device identifier ID2 to both the first chip and the second chip. The address registration request also includes second address information.

[0110] In step S318, the second chip receives the address registration request sent by the host; and if the first device identifier ID2 and the second device identifier ID2 are successfully matched, the second address information is stored. The first chip receives the address registration request sent by the host; however, if the first device identifier ID1 and the second device identifier ID2 are not successfully matched, no response is given.

[0111] In step S319, the second chip sends a completion message back to the host.

[0112] In step S320, the host receives the completion information from the second chip.

[0113] In step S321, the host sends the pin mapping table corresponding to the second device identifier ID2 to the first chip and the second chip. Specifically, the host sends the pin mapping table to the first chip and the second chip through the second address information.

[0114] In step S322, the second chip receives the pin mapping table sent by the host; and the pin mapping table is successfully compared with the current status of all pins. The second chip then stores the pin mapping table. The first chip does not respond because the address information does not match.

[0115] In step S323, the second chip sends a preset response message back to the host.

[0116] In step S324, the host receives the response information from the second chip and controls the second chip to restart.

[0117] In step S325, the second chip performs a restart, enabling the newly stored second address information and pin mapping table.

[0118] In step S326, the host sends confirmation information to the first chip and the second chip via the second address information.

[0119] In step S327, the second chip receives the confirmation information and sends back the second address information and the preset update flag information to the host. The first chip does not respond because the address information does not match.

[0120] In step S328, the host receives the second address information and the preset update flag information fed back by the second chip to confirm that the second chip address registration is successful.

[0121] In this way, address registration and authentication are performed on all slave devices, ensuring the reliability of all devices.

[0122] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0123] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0124] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0125] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0126] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A chip, characterized in that, The chip is electrically connected to the host computer via clock signal lines and data signal lines. The chip includes: A positive / negative connection identification circuit is electrically connected to the host. The positive / negative connection identification circuit is configured to receive a positive / negative connection identification code sent by the host and generate a pin identification identifier based on the positive / negative connection identification code. An identification mechanism module is electrically connected to the positive / negative connection identification circuit; the identification mechanism module is configured to obtain a first device identifier based on the pin identification identifier, the first device identifier representing the access status of the target pin of the chip; wherein, the target pin includes a clock pin and a data pin, and the access status represents the type of signal line to which the clock pin and the data pin are respectively connected.

2. The chip according to claim 1, characterized in that, The positive / negative connection identification circuit includes a positive identification circuit and a negative identification circuit; the pin identification identifier includes a positive identification identifier or a negative identification identifier; the positive / negative connection identification circuit is configured to generate a pin identification identifier based on the positive / negative connection identification code in the following manner: When the forward identification circuit receives the forward / reverse identification code, it compares the forward / reverse identification code with a preset identification code. If the comparison is successful, a forward identification identifier is generated. When the reverse identification circuit receives the positive and negative connection identification code, it compares the positive and negative connection identification code with a preset identification code. If the comparison is successful, a reverse identification identifier is generated.

3. The chip according to claim 1, characterized in that, The identification mechanism module includes a device identifier selection module, which is configured to obtain a first device identifier based on the pin identification identifier in the following manner: The device identifier selection module is configured to receive the pin identification identifier sent by the positive / negative connection identification circuit, and select the first device identifier corresponding to the pin identification identifier according to a preset logical correspondence.

4. The chip according to claim 3, characterized in that, The identification mechanism module includes: a logic control module, and a device identifier selection module electrically connected to the logic control module; The device identifier selection module is configured to send the first device identifier to the logic control module; The logic control module is configured to receive an address registration request sent by the host, the address registration request including a second device identifier and address information, and match the first device identifier with the second device identifier. If the match is successful, the address information is stored and a completion message is sent back to the host.

5. The chip according to claim 4, characterized in that, The logic control module is configured to match the first device identifier with the second device identifier in the following manner: The first device identifier is compared with the second device identifier. If the first device identifier and the second device identifier are exactly the same, the match is determined to be successful.

6. The chip according to claim 5, characterized in that, The identification mechanism module also includes an adaptive routing switch matrix, which is electrically connected to the logic control module. The logic control module is configured to receive a pin mapping table corresponding to a second device identifier sent by the host; compare the pin mapping table with the current state of all pins; and store the pin mapping table if the comparison is successful; the logic control module is also configured to send the pin mapping table to the adaptive routing switch matrix. An adaptive routing switch matrix is ​​configured to reconstruct the functional allocation of all pins of the chip based on the pin mapping table.

7. The chip according to claim 6, characterized in that, The logic control module is also configured to receive confirmation information sent by the host and feed back the address information and preset update flag information to the host; the update flag information indicates that the pin mapping table of the chip has been updated.

8. A method for identifying the state of chip pins, characterized in that, Applied to the chip according to any one of claims 1 to 7, the method comprises: Receive the positive / negative connection identification code sent by the host; Generate pin identification identifiers based on the positive / negative connection identification codes; A first device identifier is obtained based on the pin identification identifier; the first device identifier represents the access status of the target pin of the chip; wherein, the target pin includes a clock pin and a data pin, and the access status represents the type of signal line to which the clock pin and the data pin are respectively connected.

9. The method according to claim 8, characterized in that, The chip includes: a forward identification circuit and a reverse identification circuit; the pin identification identifier includes a forward identification identifier or a reverse identification identifier; generating the pin identification identifier based on the forward / reverse connection identification code includes: When the forward identification circuit receives the forward / reverse connection identification code sent by the host, it compares the forward / reverse connection identification code with a preset identification code. If the comparison is successful, a forward identification identifier is generated. When the reverse identification circuit receives the positive and negative connection identification code sent by the host, it compares the positive and negative connection identification code with the preset identification code. If the comparison is successful, a reverse identification identifier is generated.

10. The method according to claim 8, characterized in that, Obtaining the first device identifier based on the pin identification identifier includes: Based on a preset logical correspondence, select the first device identifier corresponding to the pin identification identifier.

11. The method according to claim 8, characterized in that, After obtaining the first device identifier, the following is also included: Receive an address registration request sent by the host, the address registration request including a second device identifier and address information; The first device identifier is matched with the second device identifier. If the match is successful, the address information is stored and a completion message is sent back to the host.

12. The method according to claim 11, characterized in that, Matching the first device identifier with the second device identifier includes: The first device identifier is compared with the second device identifier. If the first device identifier and the second device identifier are exactly the same, the match is determined to be successful.

13. The method according to any one of claims 8 to 12, characterized in that, After sending the completion information back to the host, it also includes: Receive the pin mapping table corresponding to the second device identifier sent by the host; The pin mapping table is compared with the current state of all pins. If the comparison is successful, the pin mapping table is stored. The functional assignments of all pins of the chip are reconstructed based on the pin mapping table.

14. A method for identifying the state of chip pins, characterized in that, Applied to the host, including: A positive / negative connection identification code is sent to the chip, triggering the chip to generate a pin identification identifier based on the positive / negative connection identification code; and triggering the chip to obtain a first device identifier based on the pin identification identifier, wherein the first device identifier represents the access status of the target pin of the chip; wherein the target pin includes a clock pin and a data pin, and the access status represents the type of signal line to which the clock pin and the data pin are respectively connected.

15. A method for identifying the state of chip pins, characterized in that, include: The host sends a positive / negative connection identification code to the chip; The chip receives the positive / negative connection identification code sent by the host; The chip generates a pin identification identifier based on the positive / negative connection identification code; The chip obtains a first device identifier based on the pin identification identifier, the first device identifier representing the access status of the target pin; wherein, the target pin includes a clock pin and a data pin, and the access status represents the type of signal lines to which the clock pin and the data pin are respectively connected.

16. An electronic device, characterized in that, include: The chip according to any one of claims 1 to 7.

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