Recording module and integral-differential modulator thereof

Abstract

The invention provides a recording module and an integral-differential modulator thereof. The integral-differential modulator is coupled to the driving circuit through a first input end and receives an intermediate signal output by the driving circuit. The integral-differential modulator comprises an operational amplifier, a first sampling capacitor, a second sampling capacitor, a first integrating capacitor and a second integrating capacitor. The operational amplifier is provided with a second input end, a third input end and an output end. Two ends of the first sampling capacitor are respectively coupled with the first input end and the second input end, and the first sampling capacitor is used for sampling the intermediate signal. The two ends of the second sampling capacitor are respectively coupled with the first input end and the second input end, and the second sampling capacitor is used for sampling the intermediate signal. Two ends of the first integrating capacitor are respectively coupled with the second input end and the output end. The two ends of the second integrating capacitor are respectively coupled with the second input end and the output end.

Description

Technical Field

[0001] This disclosure relates to integral-differential modulators, and more particularly to integral-differential modulators with adjustable resolution. Background Technology

[0002] Please see Figure 1 , Figure 1 This is a circuit diagram of a conventional Sigma-Delta Modulator (SDM). The SDM 100 includes integrator 110 and integrator 120. Integrator 110 includes operational amplifier 112, capacitor C1, capacitor C2, and switches SW1 to SW4.

[0003] Integrator 110 receives the input signal Sin from input terminal 102 and outputs the output signal Sout from the output terminal of operational amplifier 112. By switching switches SW1 to SW4, integrator 110 alternately operates in the sampling and integration phases. In the sampling phase, switches SW1 and SW3 are turned on while switches SW2 and SW4 are turned off, allowing capacitor C1 to sample the input signal Sin. In the integration phase, switches SW1 and SW3 are turned off while switches SW2 and SW4 are turned on, integrating the sampling result onto capacitor C2. Vref, V+, and V- are reference voltages. The operating principle of integrator 110 is well known to those skilled in the art and will not be described further.

[0004] The overall thermal noise of integrator 110 depends on the size of capacitor C1: the larger the capacitance of capacitor C1, the lower the thermal noise. However, increasing the capacitance of capacitor C1 will increase the power consumption of operational amplifier 112 (in order to maintain linear operation), which is detrimental to the competitiveness of the circuit. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this disclosure is to provide a recording module and its integral-differential modulator to improve the shortcomings of the prior art.

[0006] One embodiment of this disclosure provides an integral-differential modulator. The integral-differential modulator is coupled to a driving circuit via a first input terminal and receives an intermediate signal output by the driving circuit. The integral-differential modulator includes an operational amplifier, a first sampling capacitor, a second sampling capacitor, a first integrating capacitor, and a second integrating capacitor. The operational amplifier has a second input terminal, a third input terminal, and an output terminal. The two ends of the first sampling capacitor are respectively coupled to the first input terminal and the second input terminal for sampling the intermediate signal. The two ends of the second sampling capacitor are respectively coupled to the first input terminal and the second input terminal for sampling the intermediate signal. The two ends of the first integrating capacitor are respectively coupled to the second input terminal and the output terminal. The two ends of the second integrating capacitor are respectively coupled to the second input terminal and the output terminal.

[0007] Another embodiment of this disclosure provides a recording module applied to an audio device and including a driving circuit and an integral-differential modulator. The driving circuit is used to receive an input signal and generate an intermediate signal. The integral-differential modulator is coupled to the driving circuit and includes an operational amplifier, a first sampling capacitor, a second sampling capacitor, a first integrating capacitor, and a second integrating capacitor. The operational amplifier has a first input terminal, a second input terminal, and an output terminal. The two ends of the first sampling capacitor are respectively coupled to the driving circuit and the first input terminal for sampling the intermediate signal. The two ends of the second sampling capacitor are respectively coupled to the driving circuit and the first input terminal for sampling the intermediate signal. The two ends of the first integrating capacitor are respectively coupled to the first input terminal and the output terminal. The two ends of the second integrating capacitor are respectively coupled to the first input terminal and the output terminal.

[0008] The technical means embodied in the embodiments of this disclosure can improve at least one of the disadvantages of the prior art, and therefore this disclosure can save power consumption compared to the prior art.

[0009] The features, implementation, and effects of this disclosure will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of a familiar integral-differential modulator; Figure 2 This is a functional block diagram of one embodiment of the audio device 200 disclosed herein; Figure 3 This is a circuit diagram of one embodiment of the recording module 210 disclosed herein; Figure 4 This is a waveform diagram of multiple frequencies disclosed in this publication; Figure 5 This is a circuit diagram of another embodiment of the SDM 214 disclosed herein; Figure 6This is a circuit diagram of another embodiment of the driving circuit disclosed herein; Figure 7 This is a functional block diagram of another embodiment of the driving circuit disclosed herein. Detailed Implementation

[0011] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions in this specification.

[0012] This disclosure includes a recording module and its integral-differential modulator. Since some components of the recording module and its integral-differential modulator may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0013] Please see Figure 2 , Figure 2 This is a functional block diagram of one embodiment of the audio device 200 disclosed herein. The audio device 200 includes a recording module 210, a digital audio processing circuit 220, a digital-to-analog converter (DAC) 230, and an amplifier circuit 240, which are coupled to each other.

[0014] The recording module 210 is coupled to the input terminal 202 to receive the input signal Vin from the input terminal 202 and generate a digital code D1. The recording module 210 includes a driver circuit 212 and an SDM 214 coupled to each other. The driver circuit 212 enhances the driving capability of the input signal Vin and generates an intermediate signal V1. The SDM 214 converts the intermediate signal V1 into the digital code D1.

[0015] Digital audio processing circuit 220 performs audio processing such as filtering and equalization on digital code D1, and generates digital code D2. DAC 230 converts digital code D2 into an intermediate signal V2. Amplifier circuit 240 amplifies the intermediate signal V2 to generate an output signal Vout. The output signal Vout can be output to headphones or a speaker.

[0016] In some embodiments, the input signal Vin is generated by a microphone or input to the audio device 200 via a line-in interface of the audio device 200.

[0017] Please see Figure 3 , Figure 3This is a circuit diagram of one embodiment of the recording module 210 disclosed herein. The driving circuit 212 includes an operational amplifier 305, resistors Rf and Rs. One end of resistor Rs is coupled or electrically connected to input terminal 202 to receive the input signal Vin; the other end of resistor Rs is coupled or electrically connected to input terminal Nx (e.g., inverting input terminal) of operational amplifier 305. One end of resistor Rf is coupled or electrically connected to input terminal Nx of operational amplifier 305; the other end of resistor Rf is coupled or electrically connected to output terminal Nz of operational amplifier 305. Input terminal Ny (e.g., non-inverting input terminal) of operational amplifier 305 is coupled or electrically connected to a reference voltage Vref.

[0018] SDM 214 includes integrator 310 and integrator 320. It should be noted that the two-stage integrator of SDM 214 is for illustrative purposes only and is not intended to limit this disclosure. In some embodiments, SDM 214 may include more integrators. Integrator 310 is the first-stage integrator of SDM 214.

[0019] Integrator 310 has an input terminal Nf and an output terminal Ne (i.e., the output terminal of operational amplifier 312), and includes operational amplifier 312, sampling capacitors Cs1 and Cs2, integrating capacitors Ci1 and Ci2, switches Sa1, Sb1, Sc1, Sd1, Sa2, Sb2, Sc2, Sd2, and SEL2. The input terminal Nd of operational amplifier 312 (e.g., the non-inverting input terminal) is coupled or electrically connected to a reference voltage Vref; the output terminal Ne of operational amplifier 312 is coupled or electrically connected to integrator 320.

[0020] The sampling capacitor Cs1 is connected to nodes Na1 and Nb1, respectively, and is used to sample the intermediate signal V1. One end of switch Sa1 is coupled or electrically connected to the input terminal Nf (i.e., the output terminal Nz); the other end of switch Sa1 is coupled or electrically connected to node Na1. One end of switch Sb1 is coupled or electrically connected to node Na1; the other end of switch Sb1 is coupled or electrically connected to the reference voltage V+ or reference voltage V-. One end of switch Sc1 is coupled or electrically connected to node Nb1; the other end of switch Sc1 is coupled or electrically connected to the reference voltage Vref. One end of switch Sd1 is coupled or electrically connected to node Nb1; the other end of switch Sd1 is coupled or electrically connected to the input terminal Nc (e.g., the inverting input terminal) of operational amplifier 312.

[0021] The sampling capacitor Cs2 is connected to nodes Na2 and Nb2 respectively, and is used to sample the intermediate signal V1. One end of switch Sa2 is coupled or electrically connected to the input terminal Nf (i.e., the output terminal Nz); the other end of switch Sa2 is coupled or electrically connected to node Na2. One end of switch Sb2 is coupled or electrically connected to node Na2; the other end of switch Sb2 is coupled or electrically connected to the reference voltage V+ or reference voltage V-. One end of switch Sc2 is coupled or electrically connected to node Nb2; the other end of switch Sc2 is coupled or electrically connected to the reference voltage Vref. One end of switch Sd2 is coupled or electrically connected to node Nb2; the other end of switch Sd2 is coupled or electrically connected to the input terminal Nc of operational amplifier 312.

[0022] One end of the integrating capacitor Ci1 is coupled to or electrically connected to the input terminal Nc of the operational amplifier 312; the other end of the integrating capacitor Ci1 is coupled to or electrically connected to the output terminal Ne of the operational amplifier 312. One end of the integrating capacitor Ci2 is coupled to or electrically connected to the switch SEL2; the other end of the integrating capacitor Ci2 is coupled to or electrically connected to the output terminal Ne of the operational amplifier 312.

[0023] One end of switch SEL2 is coupled to or electrically connected to the input terminal Nc of operational amplifier 312; the other end of switch SEL2 is coupled to or electrically connected to integrating capacitor Ci2.

[0024] It should be noted that, Figure 3 The circuit is an embodiment corresponding to a single-ended signal, and the reference voltage Vref can be ground. Those skilled in the art can base their understanding on... Figure 3 The above description applies the recording module 210 to differential signals, and the reference voltage Vref can be the common-mode voltage of the differential signal.

[0025] SDM 214 is based on non-overlapping frequencies CLK1 and CLK2 (e.g. Figure 4 (As shown) operation. That is, frequency CLK1 and frequency CLK2 are not both at the first level (e.g., high level) or not both at the second level (e.g., low level).

[0026] The SDM 214 can operate in (1) high resolution mode or (2) low resolution mode.

[0027] (1) High resolution mode When switch SEL2 is turned on, integrating capacitors Ci1 and Ci2 are connected in parallel. Therefore, the capacitance of the equivalent integrating capacitor of integrator 310 is essentially equal to the sum of the capacitances of integrating capacitors Ci1 and Ci2. In high-resolution mode, the integration coefficient of integrator 310 is (Cs1+Cs2) / (Ci1+Ci2).

[0028] During the sampling phase Ph1 (e.g.) Figure 4 As shown, frequency CLK1 is at the first level and frequency CLK2 is at the second level. Switches SEL2, Sa1, Sa2, Sc1 and Sc2 are turned on, while switches Sb1, Sb2, Sd1 and Sd2 are not turned on, so that sampling capacitors Cs1 and Cs2 actually sample the intermediate signal V1 simultaneously.

[0029] During the integration phase of Ph2 (e.g.) Figure 4 As shown, frequency CLK1 is at the second level and frequency CLK2 is at the first level), switches Sa1, Sa2, Sc1 and Sc2 are not conducting, while switches SEL2, Sb1, Sb2, Sd1 and Sd2 are conducting, causing integrator 310 to perform integration (at this time, integrating capacitors Ci1 and Ci2 both participate in the integration operation) to generate integration signal Vint.

[0030] (2) Low resolution mode Switches SEL2, Sa2, Sb2, Sc2, and Sd2 are not conducting, so sampling capacitor Cs2 does not participate in signal sampling, and integrating capacitor Ci2 does not participate in integration. In this case, integrating capacitor Ci1 is not connected in parallel with integrating capacitor Ci2. Therefore, the capacitance value of the equivalent integrating capacitor of integrator 310 is essentially equal to the capacitance value of integrating capacitor Ci1. In low-resolution mode, the integration coefficient of integrator 310 is Cs1 / Ci1.

[0031] During the sampling phase Ph1, switches Sa1 and Sc1 are turned on, while switches Sb1 and Sd1 are turned off, allowing sampling capacitor Cs1 to sample the intermediate signal V1.

[0032] During the integration phase Ph2, switches Sa1 and Sc1 are not conducting, while switches Sb1 and Sd1 are conducting, causing integrator 310 to perform integration to generate the integration signal Vint. During the integration phase Ph2, integrating capacitor Ci2 does not participate in the integration operation, while only integrating capacitor Ci1 participates in the integration operation.

[0033] Please note that the SDM 214 can be operated based on either frequency CLK1 or frequency CLK2.

[0034] As described above, integrator 310 has a larger equivalent integrating capacitor (Ci1+Ci2) in high-resolution mode and a smaller equivalent integrating capacitor (Ci1) in low-resolution mode. That is, SDM 214 has lower thermal noise (but higher power consumption) in high-resolution mode and higher thermal noise (but lower power consumption) in low-resolution mode. Therefore, the SDM 214 of this disclosure can determine the operating mode according to actual needs to reduce the overall power consumption of the audio device 200 as appropriate. For example, when an application scenario has a high tolerance for thermal noise, the audio device 200 can operate in low-resolution mode to save power.

[0035] The ratio of the capacitance values ​​of sampling capacitor Cs1, sampling capacitor Cs2, integrating capacitor Ci1, and integrating capacitor Ci2 can be: Cs1:Cs2=Ci1:Ci2=X:Y (where X and Y are positive integers). In this way, the power consumption of integrator 310 in low-resolution mode is essentially X / (X+Y) of the power consumption in high-resolution mode, and the integration coefficient of integrator 310 is the same in both modes. In some embodiments, X=Y=1.

[0036] In some embodiments, the sum of the capacitance values ​​of sampling capacitors Cs1 and Cs2 is substantially equal to the capacitance value of capacitor C1, and the sum of the capacitance values ​​of integrating capacitors Ci1 and Ci2 is substantially equal to the capacitance value of capacitor C2. In other words, in high-resolution mode, the power consumption of integrator 310 is substantially the same as that of integrator 110; however, in low-resolution mode, the power consumption of integrator 310 is less than that of integrator 110.

[0037] Please see Figure 5 , Figure 5 This is a circuit diagram of another embodiment of SDM 214 disclosed herein. SDM 214 includes integrator 510 and integrator 320. Integrator 510 is similar to integrator 310, except that integrator 510 includes k sampling capacitors (Cs1, Cs2, ..., Csk) and k integrating capacitors (Ci1, Ci2, ..., Cik) (k>2). The two ends of the sampling capacitor Csk are node Nak and node Nbk, respectively.

[0038] One end of switch Sak is coupled or electrically connected to input terminal Nf (more specifically, output terminal Nz of operational amplifier 305); the other end of switch Sak is coupled or electrically connected to node Nak. One end of switch Sbk is coupled or electrically connected to node Nak; the other end of switch Sbk is coupled or electrically connected to reference voltage V+ or reference voltage V-. One end of switch Sck is coupled or electrically connected to node Nbk; the other end of switch Sck is coupled or electrically connected to reference voltage Vref. One end of switch Sdk is coupled or electrically connected to node Nbk; the other end of switch Sdk is coupled or electrically connected to input terminal Nc of operational amplifier 312.

[0039] One end of the integrating capacitor Cik is coupled or electrically connected to the switch SELk; the other end of the integrating capacitor Cik is coupled or electrically connected to the output terminal Ne of the operational amplifier 312. One end of the switch SELk is coupled or electrically connected to the input terminal Nc of the operational amplifier 312; the other end of the switch SELk is coupled or electrically connected to the integrating capacitor Cik.

[0040] Because integrator 510 contains more sampling capacitors and integrating capacitors, it can more accurately adjust resolution and power consumption compared to integrator 310.

[0041] In some embodiments, the sampling capacitors Cs1, Cs2, ..., Csk have substantially the same capacitance value, while the integrating capacitors Ci1, Ci2, ..., Cik have substantially the same capacitance value.

[0042] Please see Figure 6 , Figure 6 This is a circuit diagram of another embodiment of the driving circuit disclosed herein. The driving circuit 600 includes an operational amplifier 605, a current source 610, resistors Rf and Rs. The current source 610 provides a bias current to the operational amplifier 605. Figure 2 The driving circuit 212 can also be implemented by the driving circuit 600.

[0043] In some embodiments, when the resolution of the SDM 214 is relatively low (i.e., the equivalent sampling capacitance of integrator 310 or integrator 510 is relatively small), the power consumption of the drive circuit 600 can be reduced by decreasing the current supplied by the current source 610. That is, the current source 610 is adjustable, and its current is proportional to the equivalent sampling capacitance of the integrator.

[0044] For example, when integrator 310 samples using both sampling capacitors Cs1 and Cs2 (i.e., high-resolution mode, where the equivalent sampling capacitance value equals Cs1 + Cs2), current source 610 provides a first bias current; when integrator 310 samples using only sampling capacitor Cs1 (i.e., low-resolution mode, where the equivalent sampling capacitance value equals Cs1), current source 610 provides a second bias current. In some embodiments, the first bias current is greater than the second bias current.

[0045] Please see Figure 7 , Figure 7 This is a functional block diagram of another embodiment of the driving circuit disclosed herein. The driving circuit 700 includes an operational amplifier 705, a resistor Rf, and a resistor Rs. The operational amplifier 705 has an input terminal Nx (e.g., an inverting input terminal) and an output terminal Nz, and includes multiple input stages 710 and multiple output stages 720. Resistor Rf is coupled or electrically connected between the input terminal Nx and the output terminal Nz. Resistor Rs is coupled or electrically connected between the input terminal 202 and the input terminal Nx.

[0046] Figure 2 The driving circuit 212 can also be implemented by the driving circuit 700. The output stage 720 can be class-A, class-B, or class-AB. The internal circuits of the input stage 710 and the output stage 720 are well known to those skilled in the art and will not be described in detail here.

[0047] In some embodiments, when the resolution of the SDM 214 is relatively low, the driving capability of the drive circuit 700 can be reduced by connecting fewer input stages 710 and / or output stages 720 in parallel, so as to save power.

[0048] For example, when integrator 310 samples using both sampling capacitors Cs1 and Cs2 simultaneously, there are M parallel input stages 710 and / or N parallel output stages 720 (M and N are integers greater than or equal to 2, and M may or may not be equal to N). When integrator 310 samples using only sampling capacitor Cs1, there are X parallel input stages 710 and / or Y parallel output stages 720. X and Y are integers greater than or equal to 1, and X may or may not be equal to Y. In some embodiments, M is greater than X, and N is greater than Y.

[0049] In summary, this disclosure provides a resolution-adjustable SDM that can achieve a balance between power consumption and performance (e.g., tolerance to thermal noise), thereby enhancing the overall competitiveness of the audio device 200.

[0050] Please note that the shapes, sizes, and proportions of the components in the icons disclosed above are for illustrative purposes only, intended for those skilled in the art to understand this disclosure, and not for limiting this disclosure.

[0051] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on the express or implied content of this disclosure. All such changes may fall within the scope of patent protection claimed by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the scope of the claims in this specification.

Claims

1. An integral-differential modulator, coupled to a driving circuit via a first input terminal and receiving an intermediate signal output by the driving circuit, the integral-differential modulator comprising: An operational amplifier has a second input terminal, a third input terminal, and an output terminal; The first sampling capacitor has its two ends coupled to the first input terminal and the second input terminal, respectively, and is used to sample the intermediate signal. The second sampling capacitor is coupled to the first input terminal and the second input terminal respectively, and is used to sample the intermediate signal. The first integrating capacitor has its two ends coupled to the second input terminal and the output terminal, respectively. as well as The second integrating capacitor has its two ends coupled to the second input terminal and the output terminal, respectively.

2. The integral-differential modulator of claim 1, wherein, The first integrating capacitor and the second integrating capacitor are connected in parallel. During the sampling phase, the first sampling capacitor and the second sampling capacitor sample the intermediate signal, and during the integration phase, the first integrating capacitor and the second integrating capacitor participate in the integration operation.

3. The integral-differential modulator of claim 2, wherein, The integral coefficient of the integral-differential modulator is the sum of the capacitance values ​​of the first sampling capacitor and the second sampling capacitor divided by the sum of the capacitance values ​​of the first integrating capacitor and the second integrating capacitor.

4. The integral-differential modulator of claim 2, wherein, The first sampling capacitor has two terminals, a first node and a second node, respectively, and the second sampling capacitor has two terminals, a third node and a fourth node, respectively. The integral-differential modulator also includes: A first switch is coupled between the first input terminal and the first node; The second switch is coupled between the first node and the first reference voltage; The third switch is coupled between the second node and the second reference voltage; A fourth switch is coupled between the second node and the second input terminal; The fifth switch is coupled between the first input terminal and the third node; The sixth switch is coupled between the third node and the first reference voltage; The seventh switch is coupled between the fourth node and the second reference voltage; The eighth switch is coupled between the fourth node and the second input terminal; as well as The ninth switch is coupled between the second input terminal and the second integrating capacitor.

5. The integral-differential modulator of claim 4, wherein, During the sampling phase, the first switch, the third switch, the fifth switch, the seventh switch, and the ninth switch are turned on, while the second switch, the fourth switch, the sixth switch, and the eighth switch are not turned on; during the integration phase, the first switch, the third switch, the fifth switch, and the seventh switch are not turned on, while the second switch, the fourth switch, the sixth switch, the eighth switch, and the ninth switch are turned on.

6. The integral-differential modulator of claim 1, further comprising: A third sampling capacitor, whose two ends are respectively coupled to the first input terminal and the second input terminal; and The third integrating capacitor has its two ends coupled to the second input terminal and the output terminal, respectively.

7. The integral-differential modulator of claim 1, wherein, The ratio of the first sampling capacitor to the second sampling capacitor is essentially equal to the ratio of the first integrating capacitor to the second integrating capacitor.

8. The integral-differential modulator of claim 1, wherein, The first integrating capacitor is not connected in parallel with the second integrating capacitor. During the sampling phase, the first sampling capacitor samples the intermediate signal, while the second sampling capacitor does not sample the intermediate signal. During the integration phase, the first integrating capacitor participates in the integration operation, while the second integrating capacitor does not participate in the integration operation.

9. A recording module, applied to an audio device, comprising: A drive circuit is used to receive input signals and generate intermediate signals; and An integral-differential modulator, coupled to the drive circuit, includes: An operational amplifier has a first input terminal, a second input terminal, and an output terminal; The first sampling capacitor is coupled to the driving circuit and the first input terminal respectively, and is used to sample the intermediate signal. The second sampling capacitor is coupled to the driving circuit and the first input terminal respectively, and is used to sample the intermediate signal. The first integrating capacitor has its two ends coupled to the first input terminal and the output terminal, respectively. as well as The second integrating capacitor has its two ends coupled to the first input terminal and the output terminal, respectively.

10. The recording module of claim 9, wherein, The operational amplifier is a first operational amplifier, the output terminal is a first output terminal, and the driving circuit includes: The second operational amplifier has a third input terminal, a fourth input terminal, and a second output terminal; A first resistor is coupled between the third input terminal and the second output terminal; A second resistor has a first terminal and a second terminal, wherein the first terminal receives the input signal, and the second terminal is coupled to the third input terminal; and A current source is coupled to the second operational amplifier; Specifically, when the integral-differential modulator uses both the first sampling capacitor and the second sampling capacitor to sample the intermediate signal, the current source provides a first bias current; when the integral-differential modulator uses only one of the first sampling capacitor and the second sampling capacitor to sample the intermediate signal, the current source provides a second bias current.

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