Data read-write method and system based on physical layer circuit

Abstract

The invention discloses a data read-write method and system based on a physical layer circuit. The data read-write method and system are suitable for the physical layer circuit comprising a configurable function module, a global phase-locked loop module and a data phase-locked loop module. The data read-write method comprises the following steps: selecting a data function module, an address function module, a target global phase-locked loop module and a target data phase-locked loop module according to a configuration file of a physical layer circuit; analyzing the received data interaction instruction to obtain a to-be-processed data signal, a to-be-processed address signal and a first clock signal, and generating a second clock signal through a target global phase-locked loop module; sending the second clock signal to a target data phase-locked loop module to obtain a third clock signal with the same frequency as the first clock signal; the to-be-processed address signal and the first clock signal are sent to the address function module, and the to-be-processed data signal and the third clock signal are sent to the data function module, so that the target memory is controlled to execute data read-write operation, and the data read-write flexibility is improved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically to a data read / write method and system based on physical layer circuits. Background Technology

[0002] DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is widely used in data processing as a data storage chip. Due to the high data transfer rate and numerous pins of DDR chips, designing functionalities using large-bit-width DDR chips results in a large number of pins, making PCB routing difficult. This often involves routing the DDR pins through multiple vias to reach the controller. However, these vias can cause severe crosstalk to high-speed signals. Therefore, dedicated PHY circuits (Physical Interface Circuits) for DDR were developed.

[0003] Existing PHY circuits perform a large number of serial-to-parallel data conversions. To ensure data stability, the AC (address) pin position of the PHY is fixed, while the DX (data) pin can be flexibly added or removed. However, because the AC pin is fixed, it is not possible to flexibly route the data on the PCB board, which limits the application scenarios and prevents the use of multiple channels to make multiple DDR widths applicable to the same PHY circuit, resulting in high data read and write costs for DDR. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention discloses a data read / write method and system based on physical layer circuits, which improves the flexibility of data read / write.

[0005] To achieve the above objectives, this invention discloses a data read / write method based on physical layer circuits, applicable to physical layer circuits; wherein the physical layer circuit includes multiple configurable functional modules, several global phase-locked loop modules, and several data phase-locked loop modules; wherein each of the configurable functional modules is signal-connected to a target memory; the data read / write method includes: Obtain the configuration file of the physical layer circuit, and select the data function module and the address function module from a plurality of configurable function modules according to the configuration file, and determine the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit; The received data interaction instructions are parsed to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module; The address signal to be processed and the first clock signal are sent to the address function module and the second clock signal is sent to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal; The data signal to be processed and the third clock signal are sent to the data function module so that the address function module and the data function module can output the data read / write signals required by the target memory so that the target memory can perform data read / write operations.

[0006] This invention discloses a data read / write method based on physical layer circuits. It obtains a configuration file of the physical layer circuit and selects data and address function modules, as well as a target phase-locked loop (PLL) module, based on this configuration file. Utilizing the configuration file to dynamically configure module functions avoids the fixation of address pins, allowing for flexible adjustment of address and data modules to adapt to different memory bit widths and PCB routing requirements. Secondly, the received data interaction commands are parsed to obtain the signal to be processed. A first clock signal and a second clock signal are generated through the target global PLL module. The clock signal is dynamically generated based on the command type, ensuring that the clock frequency matches the operational requirements and providing a precise timing basis for subsequent signal processing. Then, the address signal to be processed and the first clock signal are sent to the address function module, while the second clock signal is sent to the target data PLL module. The target data PLL module outputs a third clock signal with the same frequency as the first clock signal. Clock synchronization is achieved by multiplying the second clock signal, reducing crosstalk and deviation in high-speed signal transmission. Finally, the data signal to be processed and the third clock signal are sent to the data function module, and the address function module outputs the data read and write signals required by the target memory. Through the collaborative processing of the function modules, efficient data read and write operations are achieved, improving the system's flexibility and compatibility.

[0007] As a preferred example, the step of obtaining the configuration file of the physical layer circuit, and selecting a data function module and an address function module from a plurality of configurable functional modules according to the configuration file, and determining the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit, includes: Obtain the binary encoding configuration file of the physical layer circuit, and parse the binary encoding configuration file to obtain the function type of each configurable functional module in the physical layer circuit; The data function module and the address function module are determined from the plurality of configurable function modules according to the function type; The target global phase-locked loop module is determined from several global phase-locked loop modules based on the binary encoding configuration file and the circuit position of the address function module in the physical layer circuit; Based on the binary encoding configuration file and the circuit position of the data function module in the physical layer circuit, the target data phase-locked loop module corresponding to each of the several data phase-locked loop modules is obtained.

[0008] The above scheme obtains the binary encoded configuration file and parses it to obtain the function type of each configurable functional module. This step ensures the accurate reading of configuration information and the clear identification of module types, providing a reliable foundation for subsequent classification. Secondly, based on the parsed function types, data function modules and address function modules are determined. By distinguishing function types, targeted allocation of modules is achieved, optimizing the signal processing path. Next, the target global phase-locked loop (PLL) module is determined by combining the binary encoded configuration file and the circuit location of the address function modules. The circuit location information is used to achieve localized matching of PLL modules, reducing signal delay and enhancing synchronization accuracy. Finally, based on the same principle, the corresponding target data PLL module is obtained for each data function module. Through position-aware dynamic allocation, parallel processing of multiple data channels is supported, adapting to the needs of different bit-width memories. Overall, the limitations of fixed pin layout are eliminated, improving configuration efficiency and system scalability.

[0009] As a preferred example, before parsing the received data interaction command to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module, the process includes: Construct a first clock signal channel between the target global phase-locked loop module and the address function module; For any one of the target data phase-locked loop modules, a second clock signal channel is constructed between the target global phase-locked loop module and the target data phase-locked loop module; Match the data function module corresponding to the target data phase-locked loop module, and construct a third clock signal channel between the target data phase-locked loop module and the data function module.

[0010] The above scheme constructs a first clock signal channel between the target global phase-locked loop (PLL) module and the address function module. By directly connecting to the address function module, it ensures that the clock related to the address signal can be transmitted quickly and without interference, reducing the delay in the address processing stage. For any target data PLL module, a second clock signal channel is constructed between the target global PLL module and the target data PLL module. By providing a dedicated clock source for the data PLL, it lays the foundation for subsequent frequency multiplication processing and avoids clock signal attenuation during transmission. A third clock signal channel is constructed between the target data PLL module and the corresponding data function module. By establishing a dedicated clock link for the data function module, it ensures the synchronization of the data signal and the clock, improving the accuracy of data conversion. These features work together to eliminate uncertainties in the signal transmission path by pre-establishing channels rather than dynamically configuring them, thus enhancing the overall system stability.

[0011] As a preferred example, the step of parsing the received data interaction command to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module includes: Data interaction instructions are obtained through a preset physical layer protocol interface, and the data interaction instructions are parsed to obtain the data signal to be processed, the address signal to be processed, and the first clock signal. The first clock signal is sent to the target global phase-locked loop module so that the target global phase-locked loop module generates a second clock signal according to a preset frequency reduction factor; wherein the frequency of the first clock signal is higher than that of the second clock signal.

[0012] The above scheme obtains data interaction commands through a preset physical layer protocol interface, ensuring the standardization and reliability of command acquisition and avoiding signal distortion caused by external interference. Then, the data interaction commands are parsed to obtain the data signal to be processed, the address signal to be processed, and the first clock signal. This provides a precise information foundation for subsequent operations, ensuring that signal processing is consistent with command requirements. Next, the command type is sent to the target global phase-locked loop (PLL) module, enabling clock generation to be dynamically adjusted based on the command type, avoiding the lack of flexibility caused by a fixed clock mode. The target PLL module generates the first clock signal, a high-frequency signal suitable for the high-speed requirements of address processing. Simultaneously, a second clock signal is generated based on the first clock signal and a preset frequency reduction factor. This frequency reduction based on the first clock signal ensures that the second clock signal remains synchronized with the first clock signal, while reducing the frequency to decrease noise and power consumption during data transmission. The design of the first clock signal having a higher frequency than the second clock signal optimizes the clock allocation strategy and improves the synchronization and adaptability of data read / write operations.

[0013] As a preferred example, the step of sending the address signal to be processed and the first clock signal to the address function module and sending the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal, includes: The address signal to be processed is sent to the address function module, and the target global phase-locked loop module is controlled to send the first clock signal to the address function module according to the first clock signal channel; The target global phase-locked loop module is controlled by the second clock signal channel to send the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module performs frequency multiplication on the second clock signal and outputs a third clock signal.

[0014] The above scheme sends the address signal to be processed to the address function module, ensuring that the address information is directly input into the address function module for processing, avoiding address signal delay or loss. Secondly, based on the first clock signal channel, the target global phase-locked loop module is controlled to send the first clock signal to the address function module. Utilizing a dedicated channel for clock signal transmission reduces external interference and improves the accuracy and stability of clock signal transmission. Then, based on the second clock signal channel, the target global phase-locked loop module is controlled to send the second clock signal to the target data phase-locked loop module. Optimized paths ensure signal quality and prevent signal attenuation or distortion. Finally, the target data phase-locked loop module performs frequency multiplication on the second clock signal, outputting a third clock signal with the same frequency as the first clock signal. This ensures that the clock of the data function module is synchronized with that of the address function module, avoiding data read / write errors and improving the overall system reliability and efficiency.

[0015] As a preferred example, the target data phase-locked loop module performs frequency multiplication on the second clock signal and outputs a third clock signal, including: The target data phase-locked loop module amplifies the second clock signal according to a preset frequency amplification factor to output a third clock signal with the same frequency as the first clock signal; wherein, the frequency amplification factor is the reciprocal of the frequency reduction factor.

[0016] In the above scheme, the target data phase-locked loop module operates according to a preset frequency amplification factor, ensuring clear parameter guidance for the frequency multiplication process, avoiding uncertainties in the processing, and thus improving synchronization accuracy. Frequency amplification directly targets the second clock signal, amplifying it to the required frequency to output a third clock signal with the same frequency as the first clock signal. This directly addresses the core requirement of clock signal synchronization. The frequency amplification factor is set to the reciprocal of the frequency reduction factor. This design mathematically ensures that the amplification factor strictly matches the reduction factor used when generating the second clock signal, ensuring consistency in frequency conversion, since the first clock signal is generated from the target global phase-locked loop module using the reduction factor. Overall, this technique achieves efficient and reliable clock signal generation and optimizes the stability of the data read / write process.

[0017] As a preferred example, the step of sending the data signal to be processed and the third clock signal to the data function module, so as to output the data read / write signals required by the target memory through the address function module and the data function module, so as to enable the target memory to perform data read / write operations, includes: For any target data phase-locked loop module, the target data phase-locked loop module is controlled to send the third clock signal to the data function module corresponding to the target data phase-locked loop module according to the third clock signal channel; The data signal to be processed is sent to the data function module, and the data function module is controlled to perform serial-to-parallel conversion on the data signal to be processed according to the third clock signal to generate a data signal that matches the data pins of the target memory. The control address function module performs serial-to-parallel conversion on the address signal to be processed according to the first clock signal, and generates an address signal that matches the address pin of the target memory; The data signal and the address signal are sent to the target memory so that the target memory can perform data read and write operations according to the data signal and the address signal.

[0018] The above scheme, for any target data PLL module, controls the target data PLL module to send the third clock signal to the corresponding data function module according to the third clock signal channel. This design utilizes a pre-built channel to ensure directional transmission of the clock signal, avoiding signal cross-interference and thus supporting flexible multi-channel configuration. The data signal to be processed is sent to the data function module, and the data function module is controlled to perform serial-to-parallel conversion on the data signal to be processed according to the third clock signal to generate a data signal matching the data pins of the target memory. By relying on the third clock signal for conversion, the timing synchronization and compatibility of the data signal are guaranteed, adapting to the bit width requirements of different memories. The address function module is controlled to perform serial-to-parallel conversion on the address signal to be processed according to the first clock signal to generate an address signal matching the address pins of the target memory. This step uses the first clock signal to independently process the address signal, simplifying the routing design of the address pins. The data signal and address signal are sent to the target memory so that the target memory can perform data read and write operations according to these matching signals. Finally, efficient and stable data transmission is achieved, reducing the routing complexity and signal distortion risk on the PCB board.

[0019] On the other hand, the present invention discloses a data read / write system based on physical layer circuits, applicable to physical layer circuits; wherein, the physical layer circuit includes multiple configurable functional modules, several global phase-locked loop modules, and several data phase-locked loop modules; wherein, each of the configurable functional modules is signal-connected to the target memory; the data read / write system includes a function configuration module, a clock parsing module, a clock frequency multiplication module, and a data read / write module; The function configuration module is used to obtain the configuration file of the physical layer circuit, so as to select the data function module and the address function module from a plurality of configurable function modules according to the configuration file, and determine the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit. The clock parsing module is used to parse the received data interaction instructions to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module. The clock multiplication module is used to send the address signal to be processed and the first clock signal to the address function module and the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal; The data read / write module is used to send the data signal to be processed and the third clock signal to the data function module, so as to output the data read / write signal required by the target memory through the address function module and the data function module, so as to enable the target memory to perform data read / write operations.

[0020] This invention discloses a data read / write system based on physical layer circuits. It acquires a configuration file of the physical layer circuit and selects data and address function modules, as well as a target phase-locked loop (PLL) module, based on this configuration file. Utilizing the configuration file to dynamically configure module functions avoids the fixation of address pins, allowing the address and data modules to be flexibly adjusted to adapt to different memory bit widths and PCB routing requirements. Secondly, it parses the received data interaction commands to obtain the signal to be processed. A first clock signal and a second clock signal are generated through the target global PLL module. The clock signal is dynamically generated based on the command type, ensuring that the clock frequency matches the operational requirements and providing a precise timing basis for subsequent signal processing. Then, the address signal to be processed and the first clock signal are sent to the address function module, while the second clock signal is sent to the target data PLL module. The target data PLL module outputs a third clock signal with the same frequency as the first clock signal. Clock synchronization is achieved by multiplying the second clock signal, reducing crosstalk and deviation in high-speed signal transmission. Finally, the data signal to be processed and the third clock signal are sent to the data function module, and the address function module outputs the data read and write signals required by the target memory. Through the collaborative processing of the function modules, efficient data read and write operations are achieved, improving the system's flexibility and compatibility.

[0021] As a preferred example, the function configuration module includes a function parsing unit, a module classification unit, and a clock matching unit; The function parsing unit is used to obtain the binary encoding configuration file of the physical layer circuit and parse the binary encoding configuration file to obtain the function type of each configurable function module in the physical layer circuit. The module classification unit is used to determine the data function module and the address function module from a plurality of configurable function modules according to the function type; The clock matching unit is used to determine the target global phase-locked loop module from a plurality of global phase-locked loop modules according to the binary encoding configuration file and the circuit position of the address function module in the physical layer circuit; and to obtain the target data phase-locked loop module corresponding to each of the data function modules from a plurality of data phase-locked loop modules according to the binary encoding configuration file and the circuit position of the data function module in the physical layer circuit.

[0022] The above scheme obtains the binary encoded configuration file and parses it to obtain the function type of each configurable functional module. This step ensures the accurate reading of configuration information and the clear identification of module types, providing a reliable foundation for subsequent classification. Secondly, based on the parsed function types, data function modules and address function modules are determined. By distinguishing function types, targeted allocation of modules is achieved, optimizing the signal processing path. Next, the target global phase-locked loop (PLL) module is determined by combining the binary encoded configuration file and the circuit location of the address function modules. The circuit location information is used to achieve localized matching of PLL modules, reducing signal delay and enhancing synchronization accuracy. Finally, based on the same principle, the corresponding target data PLL module is obtained for each data function module. Through position-aware dynamic allocation, parallel processing of multiple data channels is supported, adapting to the needs of different bit-width memories. Overall, the limitations of fixed pin layout are eliminated, improving configuration efficiency and system scalability.

[0023] As a preferred example, the data read / write system based on physical layer circuitry further includes a clock channel module; wherein the clock channel module includes a first clock unit, a second clock unit, and a third clock unit; The first clock unit is used to construct the first clock signal channel between the target global phase-locked loop module and the address function module; The second clock unit is used to construct a second clock signal channel between the target global phase-locked loop module and the target data phase-locked loop module for any one of the target data phase-locked loop modules; The third clock unit is used to match the data function module corresponding to the target data phase-locked loop module and to construct a third clock signal channel between the target data phase-locked loop module and the data function module.

[0024] The above scheme constructs a first clock signal channel between the target global phase-locked loop (PLL) module and the address function module. By directly connecting to the address function module, it ensures that the clock related to the address signal can be transmitted quickly and without interference, reducing the delay in the address processing stage. For any target data PLL module, a second clock signal channel is constructed between the target global PLL module and the target data PLL module. By providing a dedicated clock source for the data PLL, it lays the foundation for subsequent frequency multiplication processing and avoids clock signal attenuation during transmission. A third clock signal channel is constructed between the target data PLL module and the corresponding data function module. By establishing a dedicated clock link for the data function module, it ensures the synchronization of the data signal and the clock, improving the accuracy of data conversion. These features work together to eliminate the uncertainty of the signal transmission path by pre-establishing channels rather than dynamically configuring them, thus enhancing the overall system stability. Attached Figure Description

[0025] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a schematic flowchart of a data read / write method based on physical layer circuits disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a data read / write system based on physical layer circuits disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of the physical layer circuit disclosed in another embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a physical layer interface control circuit based on FPGA disclosed in another embodiment of the present invention; Figure 5 This is a schematic diagram of the receiving function of the MCU module disclosed in another embodiment of the present invention; Figure 6 This is a timing diagram of parallel data to serial data conversion disclosed in another embodiment of the present invention; Figure 7 This is a flowchart illustrating a data read / write method based on physical layer circuits, as disclosed in another embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Example 1 Reference Figure 1 To improve the flexibility of data reading and writing, this embodiment discloses a data reading and writing method based on physical layer circuits, applicable to physical layer circuits; wherein, the physical layer circuit includes multiple configurable functional modules, several global phase-locked loop modules, and several data phase-locked loop modules; wherein, each of the configurable functional modules is signal-connected to the target memory; the data reading and writing method includes: Step S1: Obtain the configuration file of the physical layer circuit, and select the data function module and address function module from the multiple configurable function modules according to the configuration file, and determine the target global phase-locked loop module and target data phase-locked loop module of the physical layer circuit.

[0029] In this embodiment, the steps mainly include: obtaining the binary encoding configuration file of the physical layer circuit and parsing the binary encoding configuration file to obtain the function type of each configurable functional module in the physical layer circuit; determining the data function module and the address function module from the plurality of configurable functional modules according to the function type; determining the target global phase-locked loop module from a plurality of global phase-locked loop modules according to the binary encoding configuration file and the circuit position of the address function module in the physical layer circuit; and obtaining the target data phase-locked loop module corresponding to each of the data function modules from the plurality of data phase-locked loop modules according to the binary encoding configuration file and the circuit position of the data function module in the physical layer circuit.

[0030] This embodiment acquires the binary encoded configuration file and parses it to obtain the function type of each configurable functional module. This step ensures accurate reading of configuration information and clear identification of module types, providing a reliable foundation for subsequent classification. Secondly, data function modules and address function modules are determined based on the parsed function types. Targeted allocation of modules is achieved through the differentiation of function types, optimizing the signal processing path. Next, the target global phase-locked loop (PLL) module is determined by combining the binary encoded configuration file and the circuit location of the address function modules. Localized matching of PLL modules is achieved using circuit location information, reducing signal delay and enhancing synchronization accuracy. Finally, based on the same principle, the corresponding target data PLL module is acquired for each data function module. Position-aware dynamic allocation supports parallel processing of multiple data channels, adapting to the needs of different bit-width memories. Overall, it eliminates the limitations of fixed pin layouts, improving configuration efficiency and system scalability.

[0031] Step S2: Parse the received data interaction command to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module.

[0032] In this embodiment, the step mainly includes: constructing a first clock signal channel between the target global phase-locked loop module and the address function module; for any target data phase-locked loop module, constructing a second clock signal channel between the target global phase-locked loop module and the target data phase-locked loop module; matching the data function module corresponding to the target data phase-locked loop module, and constructing a third clock signal channel between the target data phase-locked loop module and the data function module.

[0033] Data interaction instructions are obtained through a preset physical layer protocol interface and parsed to obtain a data signal to be processed, an address signal to be processed, and a first clock signal. The first clock signal is sent to the target global phase-locked loop module so that the target global phase-locked loop module generates a second clock signal according to a preset frequency reduction factor. The frequency of the first clock signal is higher than that of the second clock signal.

[0034] This embodiment constructs a first clock signal channel between the target global phase-locked loop (PLL) module and the address function module. By directly connecting to the address function module, it ensures that the clock related to the address signal can be transmitted quickly and without interference, reducing the delay in the address processing stage. For any target data PLL module, a second clock signal channel is constructed between the target global PLL module and the target data PLL module. By providing a dedicated clock source for the data PLL, it lays the foundation for subsequent frequency multiplication processing and avoids clock signal attenuation during transmission. A third clock signal channel is constructed between the target data PLL module and the corresponding data function module. By establishing a dedicated clock link for the data function module, it ensures the synchronization of the data signal and the clock, improving the accuracy of data conversion. These features work together to eliminate the uncertainty of the signal transmission path by pre-establishing channels rather than dynamically configuring them, thus enhancing the stability of the overall system. Data interaction commands are obtained through a preset physical layer protocol interface, ensuring the standardization and reliability of command acquisition and avoiding signal distortion caused by external interference. Then, the data interaction instructions are parsed to obtain the data signal to be processed, the address signal to be processed, and the first clock signal. This provides a precise information basis for subsequent operations, ensuring that signal processing is consistent with instruction requirements. Next, the instruction type is sent to the target global phase-locked loop (PLL) module, enabling clock generation to be dynamically adjusted based on the instruction type, avoiding the lack of flexibility caused by a fixed clock mode. The target PLL module generates the first clock signal, a high-frequency signal suitable for the high-speed requirements of address processing. Simultaneously, a second clock signal is generated based on the first clock signal and a preset frequency reduction factor. This frequency reduction based on the first clock signal ensures that the second clock signal remains synchronized with the first clock signal, while reducing the frequency to reduce noise and power consumption in data transmission. The design of the first clock signal having a higher frequency than the second clock signal optimizes the clock allocation strategy and improves the synchronization and adaptability of data read and write operations.

[0035] Step S3: Send the address signal to be processed and the first clock signal to the address function module and send the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal.

[0036] In this embodiment, the step mainly includes: sending the address signal to be processed to the address function module, and controlling the target global phase-locked loop module to send the first clock signal to the address function module according to the first clock signal channel; controlling the target global phase-locked loop module to send the second clock signal to the target data phase-locked loop module according to the second clock signal channel, so that the target data phase-locked loop module performs frequency multiplication processing on the second clock signal and outputs a third clock signal; wherein, the target data phase-locked loop module performs frequency amplification processing on the second clock signal according to a preset frequency amplification factor, so as to output a third clock signal with the same frequency as the first clock signal; wherein, the frequency amplification factor is the reciprocal of the frequency reduction factor.

[0037] In this embodiment, the address signal to be processed is sent to the address function module, ensuring that the address information is directly input into the address function module for processing, avoiding address signal delay or loss. Secondly, the target global phase-locked loop module is controlled to send the first clock signal to the address function module according to the first clock signal channel. Utilizing a dedicated channel for clock signal transmission reduces external interference and improves the accuracy and stability of clock signal transmission. Then, the target global phase-locked loop module is controlled to send the second clock signal to the target data phase-locked loop module according to the second clock signal channel. Optimized paths ensure signal quality and prevent signal attenuation or distortion. Finally, the target data phase-locked loop module performs frequency multiplication on the second clock signal, outputting a third clock signal with the same frequency as the first clock signal. This ensures that the clock of the data function module is synchronized with that of the address function module, avoiding data read / write errors and improving the overall system reliability and efficiency.

[0038] Step S4: Send the data signal to be processed and the third clock signal to the data function module, so that the address function module and the data function module can output the data read / write signals required by the target memory, so that the target memory can perform data read / write operations.

[0039] In this embodiment, the steps mainly include: for any target data phase-locked loop module, controlling the target data phase-locked loop module to send a third clock signal to the data function module corresponding to the target data phase-locked loop module according to the third clock signal channel; sending the data signal to be processed to the data function module, and controlling the data function module to perform serial-to-parallel conversion on the data signal to be processed according to the third clock signal to generate a data signal matching the data pins of the target memory; controlling the address function module to perform serial-to-parallel conversion on the address signal to be processed according to the first clock signal to generate an address signal matching the address pins of the target memory; and sending the data signal and the address signal to the target memory so that the target memory can perform data read and write operations according to the data signal and the address signal.

[0040] In this embodiment, for any target data PLL module, the third clock signal channel controls the target data PLL module to send the third clock signal to the corresponding data function module. This design utilizes a pre-built channel to ensure directional transmission of the clock signal, avoiding signal cross-interference and thus supporting flexible multi-channel configuration. The data signal to be processed is sent to the data function module, and the data function module is controlled to perform serial-to-parallel conversion on the data signal to be processed according to the third clock signal to generate a data signal matching the data pins of the target memory. By relying on the third clock signal for conversion, the timing synchronization and compatibility of the data signal are ensured, adapting to the bit width requirements of different memories. The address function module is controlled to perform serial-to-parallel conversion on the address signal to be processed according to the first clock signal to generate an address signal matching the address pins of the target memory. This step uses the first clock signal to independently process the address signal, simplifying the routing design of the address pins. The data signal and address signal are sent to the target memory so that the target memory can perform data read and write operations according to these matching signals, ultimately achieving efficient and stable data transmission and reducing the complexity of wiring on the PCB board and the risk of signal distortion.

[0041] On the other hand, refer to Figure 2 This embodiment also discloses a data read / write system based on physical layer circuits, applicable to physical layer circuits; wherein, the physical layer circuit includes multiple configurable functional modules, several global phase-locked loop modules, and several data phase-locked loop modules; wherein, each of the configurable functional modules is signal-connected to the target memory; the data read / write system includes a function configuration module 1, a clock parsing module 2, a clock frequency multiplication module 3, and a data read / write module 4.

[0042] The function configuration module 1 is used to obtain the configuration file of the physical layer circuit, so as to select the data function module and the address function module from a plurality of configurable function modules according to the configuration file, and determine the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit.

[0043] The clock parsing module 2 is used to parse the received data interaction instructions to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module.

[0044] The clock multiplier module 3 is used to send the address signal to be processed and the first clock signal to the address function module and the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal.

[0045] The data read / write module 4 is used to send the data signal to be processed and the third clock signal to the data function module, so as to output the data read / write signal required by the target memory through the address function module and the data function module, so as to enable the target memory to perform data read / write operations.

[0046] In this embodiment, the function configuration module 1 includes a function parsing unit, a module classification unit, and a clock matching unit.

[0047] The function parsing unit is used to obtain the binary encoding configuration file of the physical layer circuit and parse the binary encoding configuration file to obtain the function type of each configurable function module in the physical layer circuit.

[0048] The module classification unit is used to determine the data function module and the address function module from a plurality of configurable function modules according to the function type.

[0049] The clock matching unit is used to determine the target global phase-locked loop module from a plurality of global phase-locked loop modules according to the binary encoding configuration file and the circuit position of the address function module in the physical layer circuit; and to obtain the target data phase-locked loop module corresponding to each of the data function modules from a plurality of data phase-locked loop modules according to the binary encoding configuration file and the circuit position of the data function module in the physical layer circuit.

[0050] In this embodiment, as Figure 2 The data read / write system based on physical layer circuits shown also includes a clock channel module; wherein the clock channel module includes a first clock unit, a second clock unit, and a third clock unit.

[0051] The first clock unit is used to construct the first clock signal channel between the target global phase-locked loop module and the address function module.

[0052] The second clock unit is used to construct a second clock signal channel between the target global phase-locked loop module and the target data phase-locked loop module for any one of the target data phase-locked loop modules.

[0053] The third clock unit is used to match the data function module corresponding to the target data phase-locked loop module and to construct a third clock signal channel between the target data phase-locked loop module and the data function module.

[0054] The data read / write method and system based on physical layer circuits provided in this embodiment obtains the configuration file of the physical layer circuit and selects the data function module, address function module, and target phase-locked loop module according to the configuration file. Utilizing the configuration file to dynamically configure module functions avoids the fixation of address pins, allowing the address and data modules to be flexibly adjusted to adapt to different memory bit widths and PCB routing requirements. Secondly, the received data interaction instructions are parsed to obtain the signal to be processed. A first clock signal and a second clock signal are generated through the target global phase-locked loop module. The clock signal is dynamically generated based on the instruction type, ensuring that the clock frequency matches the operational requirements and providing a precise timing basis for subsequent signal processing. Then, the address signal to be processed and the first clock signal are sent to the address function module, while the second clock signal is sent to the target data phase-locked loop module. The target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal. Clock synchronization is achieved by multiplying the second clock signal, reducing crosstalk and deviation in high-speed signal transmission. Finally, the data signal to be processed and the third clock signal are sent to the data function module, and the address function module outputs the data read and write signals required by the target memory. Through the collaborative processing of the function modules, efficient data read and write operations are achieved, improving the system's flexibility and compatibility.

[0055] Example 2 To address the limitations of existing technologies where the fixed AC pins in the PHY (physical layer) circuit restrict flexible routing on the PCB, thus limiting application scenarios and preventing the use of multiple channels to form a single PHY for DDR applications with varying bit widths, this embodiment provides a data read / write method based on the physical layer circuit. This method allows for flexible configuration of the function type of each configurable functional module in the physical layer circuit, enabling flexible routing. Furthermore, by configuring the clock routing between phase-locked loop (PLL) modules and between PLL modules and functional modules within the physical layer circuit according to the functional modules, crosstalk within the internal data is reduced. This enables serial-to-parallel conversion of multi-bit wide signals, improving the flexibility of data read / write.

[0056] Specifically, refer to Figure 4 This embodiment provides a BANK (physical layer) circuit, mainly including multiple Byte (configurable function) modules, which can be named Byte0, Byte1...Byte2n, etc., several GPLL (global phase-locked loop) modules, and several DPLL (data phase-locked loop) modules. Each of the Byte modules can output address signals or data signals according to user configuration. Figure 3 It is understood that each of the Byte modules is signal-connected to the target memory (DDR) to output the address signal and data signal required by the target memory, so that the target memory can perform data reading operations according to the address signal and data signal.

[0057] Preferably, in such Figure 3 Based on the BANK module shown, to control the BANK module and enable DDR data read / write through it, this embodiment also provides a control circuit to connect to the BANK module and form the PHY (Physical Layer Interface) circuit corresponding to the DDR. Specifically, as shown... Figure 4 As shown, the control circuit comprises a PPC (Physical Layer Controller) module, an MCU (Microcontroller Unit) module, FLASH (Flash Memory), LOGIC (Logical Interface Card), and other peripheral circuits. It is important to note that the modules in the DDR PHY structure diagram formed by the control circuit and the BANK module all utilize internal FPGA resources. Furthermore, from... Figure 3 It can be seen that each GPLL clock module has two corresponding data function modules formed based on bytes, and each byte corresponds to one DPLL clock module.

[0058] In this embodiment, as Figure 4 In the physical layer interface control circuit shown, the PPC module is a data channel used to receive DFI (Memory Interface) data from the LOGIC module and parse the DFI data to obtain data including instruction content, read / write instructions, data signals, and address signals. Specifically, after parsing and obtaining the identification result of each DFI packet, the PPC module sends the address signal to the connected Byte-AC module via the address line connecting the PPC module and the Byte-DX module, and sends the data signal to the data Byte-DX via the data line connecting the PPC module and the Byte-DX module. After frequency multiplication, the data is then sent to the physical function pins for convenient PCB wiring.

[0059] like Figure 5 As shown, the MCU module includes a MUX address translation module, a MUX data translation module, and a MUX clock selection module. The MUX address translation module parses the address signal in the DFI and sends it to the corresponding Byte-AC; the MUX data translation module parses the data signal in the DFI and sends it to the corresponding Byte-DX; and the MUX clock selection module parses the clock signal in the DFI and sends it to the corresponding GPLL as input to the system clock module. Specifically, the MCU module reads the user-executable file from the FLASH module, parses it, and sends it to the PPC to execute the circuit connections of the relevant modules. Users can rationally select whether a Byte functions as AC or DX based on the AC and DX functional relationships of the actual circuit board, improving the flexibility of external circuit board design. In contrast, SOC chips often only allow fixed selection of a fixed Byte for DDR data read / write, lacking expandability.

[0060] The function of each byte is user-defined. During PCB design, different bytes are selected for AC or DX functions to facilitate pin routing of the DDR chips. During binary code compilation, the user can pre-set the function of a byte as either AC or DX. After the binary file is downloaded to the chip, the FPGA automatically controls the switching function. When designing the PCB, the user pre-determines the function of each byte, determining whether the corresponding DDR line is for address or data, based on the routing complexity. The edited DFI instructions then perform physical switching connections based on the function feedback of each byte.

[0061] The BANK module comprises Byte modules that perform serial-to-parallel conversion of data and address signals. Each Byte can function as both an AC address and a DX data conversion module. When GPLL0 is selected as the system clock, the address conversion modules are the nearest Bytes 0 and 1, and the data conversion modules are Bytes 2 and 3. Since the Bytes are not limited by DDR pin functions, multi-channel schemes can be implemented, meaning multiple independent DDR schemes can be formed by calling Bytes. It should be noted that the GPLL position can be determined first, followed by the Byte-AC function determination; these two are not conflicting and are both controlled by instructions in the binary file. The Bytes are used to expand the large-width address and data signals transmitted from the PPC in a 4:1 ratio. This converts large-width, low-frequency data into small-width, high-frequency data that interacts with the DDR chips, reducing external circuit pin connections and optimizing timing. Data is sampled internally within the Byte DX module, with timing as follows... Figure 6 As shown, `data_all` represents the parallel data `dx`. After being multiplied by the Byte, the large 128-bit data is converted into eight groups of 16-bit data. The 16-bit width is exactly the same as the x16 pin of the chip for data interaction. The Byte AC module performs the same serial-to-parallel conversion on the address signal.

[0062] The GPLL module is used for signal connection with the PPC module. The PPC has a reserved user interface for data interaction with the FPGA user logic. The user logic clock can come from the crystal oscillator signal on the PCB board. The PPC has an instruction parsing function. By parsing the DFI packet header from the LOGIC, it obtains whether a packet's function is a read DDR operation, a write DDR operation, or other refresh instructions. It then generates address and data signals based on the instructions and sends them to Byte-AC and Byte-DX. It is important to note that the GPLL should ideally be located near a Byte-AC; otherwise, the trace distances for fast and slow clocks will increase, failing to achieve optimal performance. Since the actual location of the PPC may be far from the GPLL, the PPC uses the slow clock (shown as a dashed line) to process the data. The selected system clock module receives its input clock from an external Logic module. It outputs two clock signals: a high-frequency clka clock and a low-frequency clkb clock, where the clka clock frequency is four times that of clkb. Taking the serial-to-parallel conversion in the DDR direction as an example, since GPLL0 is close to the two AC address modules Byte0 and Byte1, high-frequency signals can be sent to the module for address frequency multiplication with the shortest possible distance, without causing signal interference to other modules. DPLLs are adjacent to their respective Byte modules. DX requires the farthest Byte, so a low-frequency clock clkb is used to transmit the clock to the DPLL module and then multiply it to Byte DX. Here, clkb originates from the GPLL0 selected in the binary file, the clock input comes from LOGIC, and the output clock is transmitted to the PPC module and DPLL module through the binary file and the switch of the selected line. GPLL1, which is not selected, does not work.

[0063] The DPLL module is a simplified version of the GPLL clock module. Its advantage is a smaller FPGA logic area footprint, but it has fewer functions than the GPLL. In scenarios where only frequency multiplication is required, the DPLL is more suitable. Upon receiving a low-frequency clock signal, the DPLL multiplies the clock signal by 1:4 to four times the clock speed (clka), achieving the same frequency for both data processing and address processing. This allows the signals to reach the DDR chip simultaneously for data read and write operations. The GPLL is a global clock resource module, generating a clock signal that can reach any location on the FPGA. However, it occupies a larger chip area and has greater clock latency and jitter, and its number is limited. In contrast, the DPLL is a dedicated clock multiplier module with fewer resources and a simpler function, making it more suitable for high-speed data frequency multiplication in DDR.

[0064] The LOGIC module is a user logic module that transmits user-defined data types to the DDR chip and uses the DFI interface to interact with the PPC.

[0065] The Flash module is a storage module used to store data for configuring the PPC DDR PHY.

[0066] Reference Figure 7 The physical layer interface control circuit shown in this embodiment also provides a data read / write method based on the physical layer circuit to improve the flexibility of data read / write. The data read / write method is as follows: Figure 7 As shown, it mainly includes: Step 1: Start the physical layer interface control circuit so that the MCU module reads the data stored in the FLASH module and determines the data function module, address function module, global phase-locked loop module and target data phase-locked loop module in the physical layer interface control circuit.

[0067] In this embodiment, after powering on the physical layer interface control circuit, the MCU reads data from the external FLASH memory to configure the physical layer interface control circuit inside the FPGA. The FLASH memory stores binary codes of the FPGA's internal structure circuitry generated by software. The FPGA first parses the binary codes to enable the required DPLL, GPLL, and Byte resources, and controls the physical connections between modules. The pathways between any two devices are connected by switches. The binary file includes on / off signals controlling each switch. By enabling the switches between modules, target modules can be connected and the data flow direction can be determined, thereby achieving specific functions. First, the functional type of each Byte module in the physical layer interface control circuit is determined based on the read binary code configuration file, dividing the Byte modules into data function modules (Byte DX modules) and address function modules (Byte AC modules). Next, the global phase-locked loop (GPLL) module in the physical layer interface control circuit is determined based on the binary code configuration file and the location of the Byte AC module. Simultaneously, the target data phase-locked loop (DPLL) module corresponding to each Byte DX module is determined based on the Byte DX module.

[0068] Step 2: Configure the connections between the data function module, the target data phase-locked loop module, the address function module, and the target global phase-locked loop module.

[0069] In this embodiment, after selecting modules, the PPC module achieves electrical connection between modules by controlling switches on the inter-module connection lines. Preferably, in this embodiment, as... Figure 5As shown, after selecting GPLL0 as the target global phase-locked loop module, a first clock signal channel is constructed between GPLL0 and its corresponding address function module Byte0-AC0, enabling GPLL0 to send a high-frequency clock signal to the Byte0-AC0 module. After determining Byte3-DX1 and Byte2-DX0 modules as the data function modules, the DPLL3 module corresponding to the Byte3-DX1 module is matched as the target data phase-locked loop module corresponding to the Byte3-DX1 module, and the DPLL2 module corresponding to the Byte2-DX0 module is matched as the target data phase-locked loop module corresponding to the Byte2-DX0 module. Next, a third clock signal channel is constructed between Byte2-DX0 and the DPLL2 module, and between the Byte3-DX1 module and the DPLL3 module. A second clock signal channel is also constructed between GPLL0 and the DPLL3 module, and between GPLL0 and the DPLL2 module. The construction of these clock signal channels enables the transmission of clock signals between modules.

[0070] In this embodiment, to ensure data interaction between the functional module and the PPC module, a data channel can be established between the PPC module and the Byte module, allowing the PPC module to send data signals to the Byte-DX module and address signals to the Byte-AC module. Simultaneously, based on module clock control, a clock channel can be established between the LOGIC module and the GPLL0 module, allowing the LOGIC module to send a high-frequency clock signal to the GPLL0 module according to the clock channel. Specifically, after connecting the relevant modules according to a set connection relationship to form different combinations of DDR functional circuits, the connection method between the modules in the circuit is as follows: Figure 4 As shown in the diagram. The dashed lines are clock lines, and the solid lines are data lines, both of which are configured and generated by the FPGA.

[0071] Step 3: According to the connection, send the data signal to be processed to the data function module, send the address signal to be processed to the address function module, and send the first clock signal to the target global phase-locked loop module.

[0072] In this embodiment, based on the connection, the PPC parses the user interaction command sent by the LOGIC module to obtain the data signal to be processed and the address signal to be processed. The PPC then sends the data signal to be processed to the Byte-DX module and the address signal to be processed to the Byte-AC module via the data line. Simultaneously, the LOGIC module sends a first clock signal to the target global phase-locked loop module, i.e., to the GPLL0 module, based on the user interaction command.

[0073] Step 4: Based on the connection and the target global phase-locked loop module, send the second clock signal to the target data phase-locked loop module so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal.

[0074] In this embodiment, a specific GPLL module is identified by the MCU program as the target global phase-locked loop module and sent to the selected system GPLL clock module. This module then generates two clock signals of different frequencies. The high-frequency clock output is directly sent to the two nearest Byte-AC modules. For the two more distant Byte-DX modules, due to the distance, using a high-frequency clock would cause severe system interference. Therefore, a separate low-frequency clock is sent to the corresponding DPLL clock modules of the two Byte-DX modules. The DPLL modules then multiply the clock frequency before sending it to the Byte-DX modules. This reduces the convergence difficulties caused by the setup and hold times of the high-frequency clock and enhances the system's anti-interference performance.

[0075] Step 5: Generate read / write signals for the target memory based on the first clock signal, the third clock signal, the data function module, and the address function module.

[0076] In this embodiment, the internal PPC further parses the data in the DFI into address (AC) signals and data (DX) signals. Taking an x16 DDR chip as an example, the chip pins require 2 bytes for transmitting address signals and 2 bytes for transmitting data signals. The data signal is multiplied by the Byte-DX module and then output to the DDR chip. Similarly, the address signal is multiplied by the Byte-AC module and then output to the DDR chip to enable the DDR chip to perform read and write operations.

[0077] The data read / write method based on physical layer circuits provided in this embodiment separates high and low frequency clocks to reduce crosstalk in internal data. It also incorporates a byte module multiplexing function, allowing bytes in the FPGA to freely switch between AC and DX functions for data conversion, facilitating the routing of DDR chip addresses and data on the board.

[0078] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A data read / write method based on physical layer circuits, characterized in that, This method is applicable to physical layer circuits; wherein the physical layer circuit includes multiple configurable functional modules, several global phase-locked loop modules, and several data phase-locked loop modules; wherein each of the configurable functional modules is signal-connected to the target memory; the data read / write method includes: Obtain the configuration file of the physical layer circuit, and select the data function module and the address function module from a plurality of configurable function modules according to the configuration file, and determine the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit; The received data interaction instructions are parsed to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module; The address signal to be processed and the first clock signal are sent to the address function module and the second clock signal is sent to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal; The data signal to be processed and the third clock signal are sent to the data function module so that the address function module and the data function module can output the data read and write signals required by the target memory so that the target memory can perform data read and write operations.

2. The data read / write method based on physical layer circuits according to claim 1, characterized in that, The step of obtaining the configuration file of the physical layer circuit, and selecting a data function module and an address function module from a plurality of configurable functional modules according to the configuration file, and determining the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit, includes: Obtain the binary encoding configuration file of the physical layer circuit, and parse the binary encoding configuration file to obtain the function type of each configurable functional module in the physical layer circuit; The data function module and the address function module are determined from the plurality of configurable function modules according to the function type; Based on the binary encoding configuration file and the circuit position of the address function module in the physical layer circuit, the target global phase-locked loop module is determined from a number of global phase-locked loop modules; Based on the binary encoding configuration file and the circuit position of the data function module in the physical layer circuit, the target data phase-locked loop module corresponding to each of the several data phase-locked loop modules is obtained.

3. The data read / write method based on physical layer circuits according to claim 2, characterized in that, Before parsing the received data interaction instructions to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module, the process includes: Construct a first clock signal channel between the target global phase-locked loop module and the address function module; For any one of the target data phase-locked loop modules, a second clock signal channel is constructed between the target global phase-locked loop module and the target data phase-locked loop module; Match the data function module corresponding to the target data phase-locked loop module, and construct a third clock signal channel between the target data phase-locked loop module and the data function module.

4. The data read / write method based on physical layer circuits according to claim 3, characterized in that, The step of parsing the received data interaction instructions to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module includes: Data interaction instructions are obtained through a preset physical layer protocol interface, and the data interaction instructions are parsed to obtain the data signal to be processed, the address signal to be processed, and the first clock signal. The first clock signal is sent to the target global phase-locked loop module so that the target global phase-locked loop module generates a second clock signal according to a preset frequency reduction factor; wherein the frequency of the first clock signal is higher than that of the second clock signal.

5. The data read / write method based on physical layer circuits according to claim 3, characterized in that, The step of sending the address signal to be processed and the first clock signal to the address function module and sending the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal, includes: The address signal to be processed is sent to the address function module, and the target global phase-locked loop module is controlled to send the first clock signal to the address function module according to the first clock signal channel; The target global phase-locked loop module is controlled by the second clock signal channel to send the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module performs frequency multiplication on the second clock signal and outputs a third clock signal.

6. The data read / write method based on physical layer circuits according to claim 5, characterized in that, The target data phase-locked loop module performs frequency multiplication on the second clock signal and outputs a third clock signal, including: The target data phase-locked loop module amplifies the second clock signal according to a preset frequency amplification factor to output a third clock signal with the same frequency as the first clock signal; wherein, the frequency amplification factor is the reciprocal of the frequency reduction factor.

7. The data read / write method based on physical layer circuits according to any one of claims 1-6, characterized in that, The step of sending the data signal to be processed and the third clock signal to the data function module, so as to output the data read / write signals required by the target memory through the address function module and the data function module, so as to enable the target memory to perform data read / write operations, includes: For any target data phase-locked loop module, the target data phase-locked loop module is controlled to send the third clock signal to the data function module corresponding to the target data phase-locked loop module according to the third clock signal channel; The data signal to be processed is sent to the data function module, and the data function module is controlled to perform serial-to-parallel conversion on the data signal to be processed according to the third clock signal to generate a data signal that matches the data pin of the target memory. The control address function module performs serial-to-parallel conversion on the address signal to be processed according to the first clock signal, and generates an address signal that matches the address pin of the target memory; The data signal and the address signal are sent to the target memory so that the target memory can perform data read and write operations according to the data signal and the address signal.

8. A data read / write system based on physical layer circuits, characterized in that, This is applicable to physical layer circuits; wherein the physical layer circuit includes multiple configurable functional modules, several global phase-locked loop modules, and several data phase-locked loop modules; wherein each of the configurable functional modules is signal-connected to the target memory; the data read / write system includes a function configuration module, a clock parsing module, a clock multiplication module, and a data read / write module; The function configuration module is used to obtain the configuration file of the physical layer circuit, so as to select the data function module and the address function module from a plurality of configurable function modules according to the configuration file, and determine the target global phase-locked loop module and the target data phase-locked loop module of the physical layer circuit. The clock parsing module is used to parse the received data interaction instructions to obtain the data signal to be processed, the address signal to be processed, the first clock signal, and the second clock signal generated by the target global phase-locked loop module. The clock multiplication module is used to send the address signal to be processed and the first clock signal to the address function module and the second clock signal to the target data phase-locked loop module, so that the target data phase-locked loop module outputs a third clock signal with the same frequency as the first clock signal; The data read / write module is used to send the data signal to be processed and the third clock signal to the data function module, so as to output the data read / write signal required by the target memory through the address function module and the data function module, so as to enable the target memory to perform data read / write operations.

9. The data read / write system based on physical layer circuitry according to claim 8, characterized in that, The functional configuration module includes a functional parsing unit, a module classification unit, and a clock matching unit; The function parsing unit is used to obtain the binary encoding configuration file of the physical layer circuit and parse the binary encoding configuration file to obtain the function type of each configurable function module in the physical layer circuit. The module classification unit is used to determine the data function module and the address function module from a plurality of configurable function modules according to the function type; The clock matching unit is used to determine the target global phase-locked loop module from a plurality of global phase-locked loop modules according to the binary encoding configuration file and the circuit position of the address function module in the physical layer circuit; Based on the binary encoding configuration file and the circuit position of the data function module in the physical layer circuit, the target data phase-locked loop module corresponding to each of the several data phase-locked loop modules is obtained.

10. The data read / write system based on physical layer circuitry according to claim 9, characterized in that, It also includes a clock channel module; wherein the clock channel module includes a first clock unit, a second clock unit and a third clock unit; The first clock unit is used to construct the first clock signal channel between the target global phase-locked loop module and the address function module; The second clock unit is used to construct a second clock signal channel between the target global phase-locked loop module and the target data phase-locked loop module for any one of the target data phase-locked loop modules; The third clock unit is used to match the data function module corresponding to the target data phase-locked loop module and to construct a third clock signal channel between the target data phase-locked loop module and the data function module.

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