Memory assembly
By introducing a sensing amplifier circuit and a voltage supply circuit into the memory component, and utilizing a combination of negative and high voltages, the problem of increased sensing bit data offset voltage is solved, thus achieving a low-power memory design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2025-06-26
- Publication Date
- 2026-05-19
AI Technical Summary
As semiconductor component sizes and technology nodes shrink, the input offset voltage for sensing bit data increases, making it difficult to reduce the high voltage potential for storing data, thus hindering the achievement of low-power memory goals.
By introducing a sense amplifier circuit and a voltage supply circuit into the memory component, and using a combination of negative and high voltages, the voltage potential of the stored bit data is reduced. This includes the first bit line, the second bit line, the sense amplifier circuit, and the voltage supply circuit. The combination of negative and high voltages is used to repair the voltage difference, thereby achieving a low-power design.
This effectively reduces the voltage potential of the stored data, decreases leakage current, and enables a low-power memory design.
Smart Images
Figure CN122067574A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an electronic component, and more particularly to a memory component. Background Technology
[0002] Memory components (such as dynamic random access memory) can store bit data in an array of memory cells. An array of memory cells consists of multiple memory bits, configured corresponding to multiple word lines and bit lines. A memory cell can be composed of a transistor and a capacitor connected in series. Generally, bit data 1 and bit data 0 are implemented by storing high and low voltage potentials on the capacitor node, respectively.
[0003] However, as the size of semiconductor components and technology nodes shrink, the input offset voltage of the sensing bit data also increases. In order to overcome the increased input offset voltage of the sensing data, it is difficult to reduce the high voltage potential of the stored data, and therefore it is not easy to achieve the goal of low-power memory. Summary of the Invention
[0004] This invention relates to a memory component that can achieve low-power design by reducing the voltage potential of the stored data bits.
[0005] The memory component of this invention includes a first bit line, a first word line, a second bit line and a second word line, a sense amplifier circuit, and a voltage supply circuit. The first bit line and the second bit line are respectively coupled to a first memory cell and a second memory cell. The second bit line is complementary to the first bit line. The sense amplifier circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected in series between the first bit line and the second bit line. The sense amplifier circuit includes a first node located between the first bit line and the second bit line. The gate terminal of the first transistor is coupled to the second bit line, and the gate terminal of the second transistor is coupled to the first bit line. The voltage supply circuit is coupled to the sense amplifier circuit. The voltage supply circuit provides a first voltage to the first node during a post-repair period for stored bit voltage data. The first voltage is negative, and the post-repair period for stored bit voltage data occurs between the bit voltage data sensing and pre-repair period and the bit line pre-charging period.
[0006] To make the above content easier to understand, several embodiments accompanying the accompanying drawings will be described in detail below. Attached Figure Description
[0007] Figure 1 A circuit diagram of a memory component according to an embodiment of the present invention is shown;
[0008] Figure 2A Show Figure 1 A timing diagram illustrating the memory component performing sensing operations in the embodiment;
[0009] Figure 2B Show Figure 2A Diagrams of corresponding control signals during different periods of the embodiment;
[0010] Figure 3A A schematic diagram illustrating the storage voltage of a memory component in a related technology is shown.
[0011] Figure 3B A circuit diagram of a memory component according to an embodiment of the present invention is shown.
[0012] Explanation of icon numbers
[0013] 100: Memory components
[0014] 111, 112: Memory units
[0015] 120: Sensing Amplifier Circuit
[0016] 130: Equalizer circuit
[0017] 140: Voltage supply circuit
[0018] 141: First voltage supply unit
[0019] 142: Second voltage supply unit
[0020] BL: First Line
[0021] BLB: Second Line
[0022] CS: Capacitor
[0023] EQL, NPRS, NSET, PSETA, PSETB: Control signals
[0024] GND: Grounding voltage
[0025] MN1: First transistor
[0026] MN2: Second transistor
[0027] MP1: Third transistor
[0028] MP2: Fourth transistor
[0029] MN5: Fifth transistor
[0030] MN6: Sixth transistor
[0031] MN7: The seventh transistor
[0032] MN8: Eighth transistor
[0033] MN9: First equalized transistor
[0034] MN10: Second equalization transistor
[0035] N1, N1, SN: Nodes
[0036] T1: During charge sharing
[0037] T2: Storage bit voltage data sensing and pre-repair period
[0038] T3: During the recovery period after storing bit voltage data
[0039] T4: Bit line precharge period
[0040] V1, V2, V3, VDD, VSS: Voltage
[0041] VBL, VBL': Bit line voltage
[0042] VBLH: Bit line high voltage
[0043] VPL: Plate Voltage
[0044] VSN0, VSN1: Voltage changes
[0045] VSN0', VSN1': Storage voltage
[0046] WL1: First line
[0047] WL2: Second letter line
[0048] ΔVBL: Voltage difference shared by potential line charge
[0049] VPP: High Voltage for Word Lines
[0050] VNWL: Word line low voltage Detailed Implementation
[0051] Please refer to Figure 1 In this embodiment, the memory component 100 includes a first bit line BL, a first word line WL1, a second bit line BLB, a second word line WL2, memory cells 111 and 112, a sense amplifier circuit 120, an equalizer circuit 130, and a voltage supply circuit 140.
[0052] Memory cells 111 and 112 are used to store data. Memory cell 111 is the selected memory cell, and memory cell 112 is the unselected memory cell. The first bit line BL and the second bit line BLB are coupled to memory cells 111 and 112, respectively, wherein the second bit line BLB is complementary to the first bit line BL. One end of the capacitor CS of memory cells 111 and 112 is coupled to the plate voltage VPL. The plate voltage VPL is, for example, half of the bit line high voltage VBLH.
[0053] The equalizer circuit 130 includes a first equalizing transistor MN9 and a second equalizing transistor MN10. A control signal EQL is coupled to the gates of the first equalizing transistor MN9 and the second equalizing transistor MN10. The first equalizing transistor MN9 and the second equalizing transistor MN10 equalize the first bit line BL and the second bit line BLB according to the control signal EQL.
[0054] The sensing amplifier circuit 120 includes a first transistor MN1, a second transistor MN2, a third transistor MP1, and a fourth transistor MP2. The first transistor MN1 and the second transistor MN2 are NMOS transistors, and the third transistor MP1 and the fourth transistor MP2 are PMOS transistors.
[0055] A first transistor MN1 and a second transistor MN2 are connected in series between a first bit line BL and a second bit line BLB. The sense amplifier circuit 120 includes a first node N1 located between the first bit line BL and the second bit line BLB. The gate of the first transistor MN1 is coupled to the second bit line BLB, and the gate of the second transistor MN2 is coupled to the first bit line BL.
[0056] The third transistor MP1 and the fourth transistor MP2 are connected in series between the first bit line BL and the second bit line BLB. The sense amplifier circuit 120 includes a second node N2 located between the first bit line BL and the second bit line BLB. The gate of the third transistor MP1 is coupled to the second bit line BLB, and the gate of the fourth transistor MP2 is coupled to the first bit line BL.
[0057] The voltage supply circuit 140 includes a first voltage supply unit 141 and a second voltage supply unit 142. The first voltage supply unit 141 is coupled to a first node N1. The second voltage supply unit 142 is coupled to a second node N2.
[0058] The first voltage providing unit 141 includes a fifth transistor MN5 and a sixth transistor MN6. The fifth transistor MN5 provides a first power supply voltage VSS to the first node N1 according to a control signal NSET. In this embodiment, the first power supply voltage VSS is, for example, a ground voltage. The sixth transistor MN6 provides a first voltage V1 to the first node N1 according to a control signal NPRS. In this embodiment, the first voltage V1 is a negative voltage.
[0059] The second voltage providing unit 142 includes a seventh transistor MN7 and an eighth transistor MN8. The seventh transistor MN7 and the eighth transistor MN8 can be implemented using transistor components with a thin oxide channel layer structure to reduce the chip area occupied by the transistor components. The seventh transistor MN7 provides a second power supply voltage VDD to the second node N2 according to the control signal PSETA. In this embodiment, the second power supply voltage VDD is, for example, an externally supplied high power supply voltage. The eighth transistor MN8 provides a second voltage V2 to the second node N2 according to the control signal PSETB. In this embodiment, the second voltage V2 is greater than the first voltage V1. For example, the second voltage V2 can be the absolute value of a reference voltage minus the first voltage V1, i.e., V2 = VBLH - |V1|, where VBLH is the bit line high voltage, and as an example of a reference voltage, |V1| is the absolute value of the first voltage V1.
[0060] Please refer to Figures 1 to 2B The sensing operation timing of memory component 100 includes a pre-charge period T4, a charge sharing period T1, a sensing and pre-repair period T2, and a post-restoration period T3. After the post-repair period T3, it returns to the pre-charge period T4. Figure 2A The timing diagram shows the voltage changes between the first bit line BL and the second bit line BLB in each period, as well as the voltage changes VSN0 and VSN1 of node SN when memory cell 111 stores data "0" (first bit value) and data "1" (second bit value).
[0061] During the pre-charge period T4, due to the action of the equalizer circuit 130, the first bit line BL and the second bit line BLB are pre-charged to a predetermined voltage V3 that is greater than the first power supply voltage VSS and less than the second power supply voltage VDD. In this example, the predetermined voltage V3 is, for example, half of VBLH-|V1|, that is:
[0062]
[0063] During charge sharing period T1, the word line WL coupled to the selected memory cell 111 is activated, and the first bit line BL shares charge with the capacitor CS of the selected memory cell 111. Therefore, when the data is "0" (first bit value), the voltage of the first bit line BL decreases by ΔVBL; when the data is "1" (second bit value), the voltage of the first bit line BL increases by ΔVBL, where ΔVBL is the potential difference of the bit line charge sharing.
[0064] During the storage bit voltage data sensing and pre-recovery period T2, control signals NSET and PSETB turn on the fifth transistor MN5 and the eighth transistor MN8, respectively. Therefore, the voltage supply circuit 140 can supply a first power supply voltage VSS to the first node N1 of the sensing amplifier circuit 120 and a second voltage V2 to the second node N2. Consequently, the voltage difference between the first bit line BL and the second bit line BLB is amplified. That is, when the stored bit data is "0", the voltage of the first bit line BL decreases to the first power supply voltage VSS, and the voltage of the second bit line BLB increases to the second voltage V2. When the stored bit data is "1", the voltage of the first bit line BL increases to the second voltage V2, and the voltage of the second bit line BLB decreases to the first power supply voltage VSS. Therefore, the voltage difference between the first bit line BL and the second bit line BLB is V2, i.e., VBLH - |V1| < VBLH, thereby reducing the voltage potential decrease of the stored bit data "1" and reducing the leakage current of the sensing amplifier between the first and second bit lines at this time.
[0065] During the recovery period T3 after storing the bit voltage data, control signals NPRS and PSETA turn on the sixth transistor MN6 and the seventh transistor MN7, respectively. Therefore, the voltage supply circuit 140 can supply a first voltage V1 to the first node N1 of the sensing amplifier circuit 120, where the first voltage V1 is a negative voltage. Furthermore, the voltage supply circuit 140 supplies a second power supply voltage VDD minus the threshold voltage of the seventh transistor MN7 to the second node N2. That is, when the stored bit data is "0", the voltage of the first bit line BL will further decrease from VSS to the first voltage V1. When the stored bit data is "1", the voltage of the first bit line BL is the second voltage V2.
[0066] After the storage bit voltage data recovery period T3, the process returns to the pre-charge period T4. The equalizer circuit 130 pre-charges the first bit line BL and the second bit line BLB to a predetermined voltage V3, which is half of VBLH-|V1|. In this way, the memory component 140 completes the storage bit voltage data sensing and recovery operation.
[0067] In this embodiment, the timing of the sensing operation is as follows: the charge sharing period T1, the storage bit voltage data sensing and pre-recovery period T2 can be triggered by the ACT instruction provided by the memory controller, while the storage bit voltage data post-recovery period T3 and the bit line pre-charge period T4 can be triggered by the PRE instruction provided by the memory controller. Additionally, in Figure 2A In this context, the second voltage V2 is greater than the predetermined voltage V3, the predetermined voltage V3 is greater than the first power supply voltage VSS, and the first power supply voltage VSS is greater than the first voltage V1. Figure 2B In this context, VPP represents the word line high voltage, VNWL represents the word line low voltage, and GND represents the ground voltage.
[0068] Figure 3A A schematic diagram of the storage voltage of a memory component in a related technology is shown. Figure 3B A circuit diagram of a memory component according to an embodiment of the present invention is shown. Please refer to... Figure 3A and Figure 3B VBL and VBL' are bit line voltages. Figure 3A In the memory module, when the data is "1", the storage voltage VSN1' of the memory module is the bit line high voltage VBLH; when the data is "0", the storage voltage VSN0' of the memory module is the first power supply voltage VSS.
[0069] exist Figure 3B In China, according to Figure 1 Circuit architecture of memory component 100 and Figure 2A The sensing operation timing is as follows: when the data is "1", the storage voltage VSN1 of the memory component 100 is the second voltage V2, i.e., V2 = VBLH - |V1|; when the data is "0", the storage voltage VSN0 of the memory component 100 is the first voltage V1. Here, VSN1 and VSN0 are the voltages of node SN when the storage bit value is 1 and 0, respectively.
[0070] In summary, in the embodiments of the present invention, during the storage bit voltage data sensing and pre-recovery period T2, the voltage supply circuit provides a second voltage V2 to the second node of the sensing amplifier circuit, i.e., V2 = VBLH - |V1| < VBLH, thereby reducing the voltage potential of the storage bit data "1" and reducing the leakage current of the first and second bit lines during this time. During the storage bit voltage data post-recovery period T3, a negative voltage V1 is provided to the first node of the sensing amplifier circuit to store the storage bit data "0", thereby reducing the memory data storage operation voltage and achieving a low-power memory design.
[0071] For those skilled in the art, various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In summary, this disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.
Claims
1. A memory component, comprising: The first bit line, the first word line, the second bit line, and the second word line are respectively coupled to the first memory cell and the second memory cell, wherein the second bit line is complementary to the first bit line; A sensing amplifier circuit includes a first transistor and a second transistor, which are connected in series between the first bit line and the second bit line. The sensing amplifier circuit includes a first node located between the first bit line and the second bit line. The gate terminal of the first transistor is coupled to the second bit line, and the gate terminal of the second transistor is coupled to the first bit line. as well as A voltage supply circuit, coupled to the sensing amplifier circuit, is used to provide a first voltage to the first node during the post-recovery period of the stored bit voltage data, wherein the first voltage is a negative voltage, and the post-recovery period of the stored bit voltage data occurs between the storage bit voltage data sensing and pre-recovery period and the bit line pre-charge period.
2. The memory assembly of claim 1, wherein the first memory cell stores a first bit value at the first voltage provided by the voltage providing circuit during the recovery of the stored bit voltage data.
3. The memory component of claim 2, wherein the sense amplifier circuit further comprises a third transistor and a fourth transistor connected in series between the first bit line and the second bit line, wherein the sense amplifier circuit includes a second node located between the first bit line and the second bit line, the gate terminal of the third transistor is coupled to the second bit line, and the gate terminal of the fourth transistor is coupled to the first bit line.
4. The memory component of claim 3, wherein the voltage providing circuit is further configured to provide a second voltage to the second node during the storage bit voltage data sensing and pre-recovery, wherein the second voltage is the absolute value of a reference voltage minus the first voltage.
5. The memory component of claim 4, wherein the first memory cell stores the second bit value at the second voltage.
6. The memory component of claim 5, wherein the second voltage is greater than the first voltage.
7. The memory component of claim 5, wherein the reference voltage is a bit line high voltage.
8. The memory component according to claim 4, further comprising: An equalizer circuit is coupled between the first bit line and the second bit line and is used to precharge the first bit line to a predetermined voltage during the bit line precharging period, wherein the predetermined voltage is half of the second voltage.
9. The memory component of claim 8, wherein during the storage bit voltage data sensing and pre-recovery, the voltage supply circuit provides a first power supply voltage to the first node of the sensing amplifier circuit and provides the second voltage to the second node.
10. The memory component of claim 9, wherein the second voltage is greater than the predetermined voltage, the predetermined voltage is greater than the first power supply voltage, and the first power supply voltage is greater than the first voltage.