Low-crosstalk control method for single-transistor NOR storage array

Abstract

The invention discloses a low-crosstalk control method for a single-transistor NOR storage array, and belongs to the technical field of semiconductor memories. According to the method, aiming at the problems of serious inter-unit crosstalk and dispersed programming initial states in a single-transistor storage array, an operation voltage is determined by acquiring a device transfer characteristic, all units reach a unified high-resistance state by adopting two-step reset operation, and suppression voltages are applied to adjacent rows to block crosstalk when a target unit is programmed, so that the high-resistance state of the single-transistor storage array is ensured. And low-crosstalk and high-reliability operation under high-density integration is realized, and the method is suitable for storage and calculation fusion application of high-performance calculation and edge intelligence.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, and particularly relates to a low crosstalk control method for a single-transistor NOR memory array. Background Technology

[0002] In-memory computing technology is a crucial direction for overcoming the bottlenecks of the von Neumann architecture, with single-transistor in-memory arrays becoming a research hotspot due to their extremely high cell density and excellent energy efficiency potential. Each in-memory cell in this type of array contains only one ferroelectric or floating-gate transistor, eliminating the need for a separate selector. This greatly simplifies the architecture, facilitates integration with standard CMOS processes, and provides an ideal physical platform for high-parallelism analog computing, making it particularly suitable for scenarios with stringent energy efficiency and latency requirements, such as artificial intelligence inference and edge intelligence.

[0003] However, this highly simplified structure introduces significant technical challenges in practical applications. The primary challenge is severe inter-cell electrical crosstalk. Due to the lack of independent gating devices for physical isolation, when a programming or reading voltage is applied to the target cell, this voltage leaks to adjacent non-target cells through parasitic paths such as shared word lines, bit lines, and substrate coupling, causing unexpected changes in their storage state or distortion of the computational signal. In applications requiring high-precision multi-value storage or analog vector-matrix multiplication, this crosstalk directly leads to computational errors, weight distortion, and data loss, severely limiting the system's reliability and computational accuracy. Secondly, there is the issue of programmed state consistency. Process variations and the inherent non-ideal characteristics of the devices cause inherent dispersion in key parameters such as the initial threshold voltage and programming sensitivity of each memory cell in the array. This non-uniformity makes it difficult to achieve a preset uniform conductance state for all cells when performing parallel writing or weight mapping on the array, resulting in a discrete distribution of the programmed state, which significantly reduces the accuracy of analog calculations and the reliability of multi-value storage.

[0004] For a long time, the industry's efforts to solve these problems have faced a dilemma. Introducing additional selectors can suppress crosstalk, but it sacrifices the high-density advantage of a single-transistor structure and increases process complexity and cost. On the other hand, maintaining a minimalist single-transistor architecture requires innovation in circuit design and timing. However, achieving precise electrical isolation of the target cell under a shared wiring structure while overcoming inherent device inconsistencies has always been a technical challenge. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a low crosstalk control method for a single-transistor NOR memory array, thereby resolving the issues present in the prior art.

[0006] In a first aspect, to achieve the above objective, the present invention provides a low crosstalk control method for a single-transistor NOR memory array, comprising the following steps:

[0007] The transfer characteristics of the memory devices constituting the memory array are obtained to determine the programming voltage, reset voltage, and suppression voltage.

[0008] A reset operation is performed on all memory devices in the memory array to bring them to a uniform high-impedance state;

[0009] After performing a reset operation, the total current of each column of memory computing devices in the memory array is read to verify the array status;

[0010] Perform a programming operation on a target memory device, the programming operation including applying the programming voltage to the word line where the target memory device is located, and applying the suppression voltage to two word lines adjacent to the word line;

[0011] A read operation is performed on the target memory device to obtain its storage state.

[0012] Optionally, the process of acquiring transfer characteristics includes:

[0013] The transfer curve of the memory device was obtained through electrical testing;

[0014] Based on the transfer curve, the first voltage for the set operation, the second voltage for the reset operation, the third voltage for turning off adjacent row devices, and the fourth voltage for individual programming are extracted.

[0015] Optionally, the process of performing the reset operation includes:

[0016] Apply the set voltage from the reset voltage to all word lines, while simultaneously setting all bit lines and source lines to the reference potential, thus switching all memory devices to a low-impedance state.

[0017] Maintain the potential of the bit line and the source line, and apply the reset voltage from the reset voltage to all word lines, so that all memory devices change from the low-resistance state to the high-resistance state.

[0018] Optionally, the process of reading the total current includes:

[0019] Apply the read reference voltage to all word lines;

[0020] Apply read bias voltage to all bit lines and apply the reference potential to all source lines;

[0021] By sensing the current on each bit line, the sum of the currents of all memory devices in the corresponding column is obtained.

[0022] Optionally, the process of performing programming operations further includes:

[0023] A programming bias potential is applied only to the bit line where the target memory device is located, while all other bit lines and all source lines are left floating.

[0024] Optionally, the process of performing the read operation includes:

[0025] The read reference voltage is applied to the word line where the target memory device is located, and the suppression voltage is applied to the two word lines adjacent to the word line.

[0026] Apply the read bias voltage to the bit line where the target memory device is located, and apply the reference potential to other bit lines and all source lines;

[0027] The storage state of the target memory device is obtained by sensing the current on the bit line where the target memory device is located.

[0028] Secondly, the present invention also provides a low crosstalk control system for a single-transistor NOR memory array, used to implement a low crosstalk control method for a single-transistor NOR memory array, the system comprising:

[0029] A voltage parameter determination module is used to obtain the transfer characteristics of the memory devices constituting the memory array in order to determine the programming voltage, reset voltage and suppression voltage.

[0030] The reset control module is used to perform a reset operation on all memory devices in the memory array to make them reach a uniform high impedance state.

[0031] The verification and reading module is used to read the total current of each column of memory devices in the memory array after the reset control module is operated, so as to verify the array status.

[0032] The programming control module is used to perform programming operations on the target memory device, including applying the programming voltage to the word line where the target memory device is located, and applying the suppression voltage to the two word lines adjacent to the word line;

[0033] The status reading module is used to perform a read operation on the target in-memory computing device to obtain its storage status.

[0034] Thirdly, the present invention also provides a computer terminal device, comprising:

[0035] One or more processors;

[0036] A memory, coupled to the processor, for storing one or more programs;

[0037] When the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the low crosstalk control method for a single-transistor NOR memory array in the first aspect described above.

[0038] Fourthly, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the low crosstalk control method for a single-transistor NOR memory array described in the first aspect are implemented.

[0039] Fifthly, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the low crosstalk control method for a single-transistor NOR memory array described in the first aspect.

[0040] Compared with the prior art, the present invention has the following advantages and technical effects:

[0041] This invention provides a low-crosstalk control method for a single-transistor NOR in-memory array. By employing a pure single-transistor cell structure, eliminating the need for integrated independent selectors, this invention achieves high-density integration and simplified manufacturing of the in-memory array. Utilizing a two-step reset operation—writing a low-resistance state followed by a high-resistance state—all in-memory cells reach a unified high-resistance initial state, effectively overcoming the problem of dispersed initial programming states and significantly improving programming consistency. When programming or reading a target cell, applying a specific suppression voltage to adjacent row word lines effectively shuts off the channels of adjacent row transistors, blocking crosstalk paths between cells and significantly reducing crosstalk during operation. Combined with a row- and column-independent voltage collaborative control strategy, precise and independent operation of the target in-memory cell is achieved, ensuring the stability of non-target cell states and improving operational reliability and data integrity. This method supports accurate reading of individual devices and column current and verification, improving the accuracy of state identification and the overall measurability of the array. All operating voltages are designed within the conventional CMOS voltage range, eliminating the need for high-voltage devices, and possessing good process compatibility and scalability, providing an effective solution for realizing high-efficiency in-memory computing systems. Attached Figure Description

[0042] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0043] Figure 1 This is a schematic equivalent circuit diagram of a single-transistor NOR memory array structure according to an embodiment of the present invention;

[0044] Figure 2This is a transfer curve diagram of a single floating gate transistor in an implementation example of the control scheme for a floating gate NOR memory array according to an embodiment of the present invention;

[0045] Figure 3 This is the equivalent circuit diagram of all devices in the low-resistance state according to an embodiment of the present invention;

[0046] Figure 4 This is the equivalent circuit diagram of all devices in a high-impedance state according to an embodiment of the present invention;

[0047] Figure 5 This is an equivalent circuit diagram for reading the current of each column of the memory devices in an embodiment of the present invention;

[0048] Figure 6 This is an equivalent circuit diagram for programming a single device in a memory array according to an embodiment of the present invention;

[0049] Figure 7 This is an equivalent circuit diagram for reading the state of a programmed single device according to an embodiment of the present invention;

[0050] Figure 8 This is a comparison chart of crosstalk suppression effects under different suppression voltages in an embodiment of the present invention. Detailed Implementation

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0053] Example 1

[0054] This embodiment provides a low crosstalk control method for a single-transistor NOR memory array, including:

[0055] The transfer characteristics of the memory devices constituting the memory array are obtained to determine the programming voltage, reset voltage, and suppression voltage.

[0056] A reset operation is performed on all memory devices in the memory array to bring them to a uniform high-impedance state;

[0057] After performing a reset operation, the total current of each column of memory computing devices in the memory array is read to verify the array status;

[0058] Perform a programming operation on a target memory device, the programming operation including applying the programming voltage to the word line where the target memory device is located, and applying the suppression voltage to two word lines adjacent to the word line;

[0059] A read operation is performed on the target memory device to obtain its storage state.

[0060] As one implementation method in this embodiment, the process of obtaining transfer characteristics includes:

[0061] The transfer curve of the memory device was obtained through electrical testing;

[0062] Based on the transfer curve, the first voltage for the set operation, the second voltage for the reset operation, the third voltage for turning off adjacent row devices, and the fourth voltage for individual programming are extracted.

[0063] As one implementation method in this embodiment, the process of performing the reset operation includes:

[0064] Apply the set voltage from the reset voltage to all word lines, while simultaneously setting all bit lines and source lines to the reference potential, thus switching all memory devices to a low-impedance state.

[0065] Maintain the potential of the bit line and the source line, and apply the reset voltage from the reset voltage to all word lines, so that all memory devices change from the low-resistance state to the high-resistance state.

[0066] As one implementation method in this embodiment, the process of reading the total current includes:

[0067] Apply the read reference voltage to all word lines;

[0068] Apply read bias voltage to all bit lines and apply the reference potential to all source lines;

[0069] By sensing the current on each bit line, the sum of the currents of all memory devices in the corresponding column is obtained.

[0070] As one implementation method in this embodiment, the process of performing programming operations further includes:

[0071] A programming bias potential is applied only to the bit line where the target memory device is located, while all other bit lines and all source lines are left floating.

[0072] As one implementation method in this embodiment, the process of performing the read operation includes:

[0073] The read reference voltage is applied to the word line where the target memory device is located, and the suppression voltage is applied to the two word lines adjacent to the word line.

[0074] Apply the read bias voltage to the bit line where the target memory device is located, and apply the reference potential to other bit lines and all source lines;

[0075] The storage state of the target memory device is obtained by sensing the current on the bit line where the target memory device is located.

[0076] To address the severe inter-cell crosstalk and poor programming state consistency issues caused by the lack of independent select transistors in traditional 1T NOR memory arrays, and to further improve computing density and operational reliability, this invention proposes a 1T NOR memory array and its control method. This array consists of ferroelectric / floating gate memory cells arranged repeatedly along rows and columns. Each memory cell contains only a single transistor-type memory device, eliminating the need for additional integrated select transistors, thus significantly improving computing density and manufacturing feasibility. Memory cells in the same row share a word line (WL) and a source line (SL), while memory cells in the same column share a bit line (BL). WL and SL are parallel to each other, and WL and BL are perpendicular to each other. By employing the control method proposed in this invention, all devices can be placed in a highly consistent high-impedance state through a two-step reset operation before programming, effectively overcoming the problem of dispersed initial programming states. Furthermore, when programming or reading a single device, a specific suppression voltage (V0) is applied to adjacent rows. supp Reduce crosstalk between units, V supp The specific transfer curve needs to be determined based on the specific device, and will be provided in the detailed implementation plan. Precise and independent operation of the target in-memory computing device is achieved without adding any switching transistors, combining high integration with high reliability.

[0077] Determine the operating voltage of the memory device: Obtain the device's transfer curve through multimeter testing, and obtain the device's V value from the transfer curve. set V reset V supp V wirte Operating voltage.

[0078] Write all devices to a low-impedance state: Apply V to all WL in the array set The voltage, BL and SL, are applied with a reference voltage (such as 0V) to set all memory devices to a basically uniform low-resistance state.

[0079] Write all devices to a high-impedance state: Keep all WL and SL voltages constant, apply V to all WL. reset The voltage is applied to change all memory devices from a low-resistance state to a basically uniform high-resistance state. Through the above two steps, the "erase" or "reset" of all memory devices is completed, bringing them to a unified initial high-resistance state, laying the foundation for subsequent accurate programming.

[0080] Read the current of each column of memory devices: apply a voltage of 0 V to all word lines, apply a read voltage (e.g., 0.1 V) to all BLs, and apply a reference voltage (e.g., 0 V) ​​to SLs. By sensing the total current on each column of BLs, it is possible to determine whether the state of the entire column of memory devices is uniform, thus verifying the effectiveness of the reset operation.

[0081] Programming a single device in a memory array: Select the row containing the target device (apply programming voltage V) write ), and apply a suppression voltage (V) to the two adjacent word lines above and below it. supp The V supp The selection should be based on the transfer characteristics of the memory devices to ensure effective shutdown of adjacent row devices, reduce crosstalk during programming, and avoid changing the original conductance state of other devices. Apply a programming bias voltage (e.g., 0 V) ​​to the bit line where the target device is located, and leave other relevant bit lines and all source lines floating, thereby achieving precise programming only for the target device and setting it to a low-impedance state.

[0082] To read the status of a single programmed device: Select the row containing the target device and apply the same V-value to the word lines of the two adjacent rows above and below it. supp Voltage. Apply a read voltage (e.g., 0.1 V) to the bit line containing the target device, and apply a reference voltage (e.g., 0 V) ​​to other bit lines and all source lines. By reading the current on the bit line, the programming information stored in the target device can be obtained, enabling independent and accurate reading of the state of a single memory cell.

[0083] Furthermore, after completing the programming operations for all target units, step three can be executed again to read the current of each column of storage devices to verify the overall programming results.

[0084] The in-memory computing array and its control method described in this invention ensure the consistency of the array's initial state by employing a two-step reset operation and effectively isolate inter-cell interference during the programming and reading processes by utilizing inter-row voltage suppression operations. This significantly improves programming accuracy, reliability, and reading accuracy, making it particularly suitable for in-memory computing fusion applications aimed at high-performance computing and edge intelligence.

[0085] The above content will be explained in detail below with reference to the accompanying drawings:

[0086] Figure 1 This invention provides a schematic equivalent circuit diagram of a single-transistor NOR memory array structure, which is constructed by repeatedly arranging ferroelectric / floating gate memory cells. Ferroelectric / floating gate memory cells in the same row share a WL and a SL, and ferroelectric / floating gate memory cells in the same column share a BL. WL and SL are parallel to each other and perpendicular to each other.

[0087] The control method proposed in this invention can be used to... Figure 1 The in-memory array structure shown operates as follows. An example is presented here, where the in-memory array consists of floating-gate in-memory devices. The transfer characteristic curve of a single floating-gate in-memory device is shown below. Figure 2 As shown.

[0088] Based on the transfer characteristic curve, the key operating voltage parameters of the device can be extracted, including V. set V reset V supp and V wirte etc. Among them, V set With V reset Typically, a higher voltage needs to be applied; in this example, V set The selection range is -16 V to -13 V. reset The selected range is 13 V to 15 V, and the application time is approximately 1 second to 10 seconds. supp The operating voltage should be selected within V. th1 With V th2 In principle, they should be as close as possible to V. th2 This ensures that the transistor is completely turned off without affecting the existing state of other devices. In this example, V supp The amplitude range is -4 V to -6 V.

[0089] Figures 3-7 The diagram below illustrates the control of the in-memory array. The specific steps are as follows:

[0090] First, such as Figure 3 and Figure 4 As shown, all devices in the memory array are set to essentially the same high-impedance state. Figure 3 In the middle, for WL m-1 WL m and WL m+1 Apply V set Voltage, according to Figure 2 The transfer curve shown indicates a negative voltage. For BL... n-1 BL n BL n+1 SL n-1 SL n and SL n+1 Apply a 0 V voltage. At this point, all devices are set to essentially the same low-impedance state. After writing is complete, all bit line and source line voltages remain unchanged at 0 V for WL. m-1 WL m and WL m+1 Apply V reset Voltage. At this point, all devices are set to essentially the same high-resistance state. Compared to a one-step reset method, the two-step reset method described above can bring the conductance values ​​of all devices to essentially the same level.

[0091] Secondly, such as Figure 5 As shown, the sum of the currents of each column of devices in the memory array is read. For WL m-1 WL m and WL m+1 Apply 0 V voltage to BL. n-1 BL n and BL n+1 Apply a reading voltage of 0.1 V to SL. n-1 SL n and SL n+1 Apply a 0V voltage. At this point, the sum of the currents of each column of devices in the memory array can be read after the reset operation. The sum of the currents of each column of devices can determine whether all memory devices are set to a high-impedance state. If all devices are set to a high-impedance state, the next programming step can be performed.

[0092] Next, as Figure 6 As shown, select the nth row and nth column in the memory array, and program the device at the row-column intersection to a low-impedance state. For WL... m Apply V wirte Voltage, and simultaneously for WL m-1 and WL m+1 Apply V supp Voltage. For BL n Apply 0 V voltage and BL n-1 BL n+1 SL n-1 SL n and SL n+1 The pin is left floating. At this point, only the selected device is programmed, without changing the state of other memories.

[0093] Next, as Figure 7 As shown, continue selecting the memory cell that has already been programmed, in the nth row and nth column, and read the information stored in that cell. For WL m Apply 0 V voltage while simultaneously applying WL m-1 and WL m+1 Apply V supp Voltage. For BL n Apply a reading voltage of 0.1 V and apply it to BL. n-1 BL n+1 SL n-1 SL n and SL n+1 Apply 0 V voltage. Read BL. n The leakage current on the column can be used to obtain the programming information stored in the selected device.

[0094] Finally, in accordance with Figure 6 The scheme in the text, after programming all units, such as Figure 5 As shown, the current sum of all memories in each column is read.

[0095] Figure 8 The text uses a 2×2 array to demonstrate and compare the programming effects of different programming schemes. The values ​​are V... supp Suspended, V supp =-5 V、V supp When the voltage is -10 V, the current values ​​of the four devices in the array at a read voltage of 0.1 V after programming transistor T1 are shown. It can be found that this scheme has a better effect on suppressing crosstalk.

[0096] Based on this, the low crosstalk control method for a single-transistor NOR memory array provided by this invention has significant advantages in terms of integration, programming consistency, and operational reliability. These advantages are specifically reflected in the following aspects: First, high integration and simplified structure, stemming from the use of a pure single-transistor (1T) cell structure, eliminating the need for additional select transistors, thus increasing storage density while reducing process complexity; Second, high programming consistency and initial state controllability, achieved by employing a two-step reset operation (first writing to a low-resistance state, then writing to a high-resistance state), resetting all cells to a unified high-resistance reference state, effectively reducing programming errors introduced by initial state dispersion; Third, low crosstalk and high operational reliability, based on applying a suppression voltage (V0) to the two adjacent rows when programming or reading a row of cells. supp The inter-row isolation strategy blocks crosstalk paths between cells, ensuring that only the target cell is operated on. Fourth, high read accuracy and state distinguishability are achieved by isolating non-target rows during reads and supporting full column current and detection, enabling accurate reading of individual cells and rapid verification of the overall array state. Fifth, process compatibility and scalability are ensured because all operating voltages are designed within the conventional CMOS voltage range, eliminating the need for high-voltage devices and facilitating integration with existing logic processes and adaptation to more advanced process nodes. In summary, without introducing any physical select transistors, this invention systematically solves the problems of severe crosstalk and inconsistent programming states in traditional 1T arrays through core technologies such as simplified cell structure, two-step reset initialization, inter-row voltage suppression, and independent row and column voltage control. It achieves non-volatile in-memory computing operations with high density, high consistency, and high reliability, providing effective device and architecture support for high-efficiency embedded storage and in-memory computing systems.

[0097] Example 2

[0098] In this embodiment, a computer terminal device is provided, including:

[0099] One or more processors;

[0100] A memory, coupled to the processor, for storing one or more programs;

[0101] When the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the low crosstalk control method for the single-transistor NOR memory array described above.

[0102] In this embodiment, a computer-readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the low crosstalk control method for the single-transistor NOR memory array described above.

[0103] In this embodiment, an electronic device is also provided, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps of the low crosstalk control method for the single-transistor NOR memory array described above.

[0104] In this embodiment, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the low crosstalk control method for the single-transistor NOR memory array described above.

[0105] The aforementioned program can run on a processor or be stored in memory (or a computer-readable medium). Computer-readable media includes both permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), other types of random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0106] These computer programs may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes can be implemented by different modules for different steps.

[0107] This embodiment provides such a device or system. The system, referred to as a low crosstalk control system for a single-transistor NOR memory array, includes:

[0108] A voltage parameter determination module is used to obtain the transfer characteristics of the memory devices constituting the memory array in order to determine the programming voltage, reset voltage and suppression voltage.

[0109] The reset control module is used to perform a reset operation on all memory devices in the memory array to make them reach a uniform high impedance state.

[0110] The verification and reading module is used to read the total current of each column of memory devices in the memory array after the reset control module is operated, so as to verify the array status.

[0111] The programming control module is used to perform programming operations on the target memory device, including applying the programming voltage to the word line where the target memory device is located, and applying the suppression voltage to the two word lines adjacent to the word line;

[0112] The status reading module is used to perform a read operation on the target in-memory computing device to obtain its storage status.

[0113] As one implementation method in this embodiment, the voltage parameter determination module includes:

[0114] A transfer characteristic testing unit is used to perform electrical tests on the memory device to obtain its transfer curve;

[0115] The voltage parameter extraction unit is used to extract, based on the transfer curve, a first voltage for setting operation, a second voltage for resetting operation, a third voltage for turning off adjacent row devices, and a fourth voltage for individual programming.

[0116] As one implementation method in this embodiment, the reset control module includes:

[0117] The set control unit is used to apply the set voltage from the reset voltage to all word lines, while simultaneously setting all bit lines and source lines to the reference potential, so that all memory devices are switched to a low-resistance state.

[0118] The reset execution unit is used to maintain the potential of the bit line and the source line, and apply the reset voltage from the reset voltage to all word lines, so that all memory devices change from the low impedance state to the high impedance state.

[0119] As one implementation method in this embodiment, the verification reading module includes:

[0120] The first voltage application unit is used to apply a read reference voltage to all word lines, a read bias voltage to all bit lines, and the reference potential to all source lines.

[0121] The column total current sensing unit is used to obtain the sum of the currents of all memory devices in the corresponding column by sensing the current on each bit line.

[0122] As one implementation method in this embodiment, the programming control module further includes a bit line bias control unit, which is used to apply a programming bias potential only to the bit line where the target memory device is located during the programming operation, and to leave all other bit lines and all source lines in a floating state.

[0123] As one implementation method in this embodiment, the status reading module includes:

[0124] The second voltage application unit is used to apply the read reference voltage to the word line where the target memory device is located, apply the suppression voltage to the two word lines adjacent to the word line, apply the read bias voltage to the bit line where the target memory device is located, and apply the reference potential to other bit lines and all source lines.

[0125] A single-device current sensing unit is used to obtain the storage state of the target memory device by sensing the current on the bit line where the target memory device is located.

[0126] The system or apparatus is used to implement the functions of the methods in the above embodiments. Each module in the system or apparatus corresponds to each step in the method, as has been described in the method and will not be repeated here.

[0127] The above implementation method solves the problem of low crosstalk control in single-transistor NOR memory arrays in related technologies, thereby ensuring that the problems existing in the prior art are resolved.

[0128] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low crosstalk control method for a single-transistor NOR memory array, characterized in that, Includes the following steps: The transfer characteristics of the memory devices constituting the memory array are obtained to determine the programming voltage, reset voltage, and suppression voltage. A reset operation is performed on all memory devices in the memory array to bring them to a uniform high-impedance state; After performing a reset operation, the total current of each column of memory computing devices in the memory array is read to verify the array status; Perform a programming operation on a target memory device, the programming operation including applying the programming voltage to the word line where the target memory device is located, and applying the suppression voltage to two word lines adjacent to the word line; A read operation is performed on the target memory device to obtain its storage state.

2. The method according to claim 1, characterized in that, The process of acquiring transfer characteristics includes: The transfer curve of the memory device was obtained through electrical testing; Based on the transfer curve, the first voltage for the set operation, the second voltage for the reset operation, the third voltage for turning off adjacent row devices, and the fourth voltage for individual programming are extracted.

3. The method according to claim 1, characterized in that, The process of performing the reset operation includes: Apply the set voltage from the reset voltage to all word lines, while simultaneously setting all bit lines and source lines to the reference potential, thus switching all memory devices to a low-impedance state. Maintain the potential of the bit line and the source line, and apply the reset voltage from the reset voltage to all word lines, so that all memory devices change from the low-resistance state to the high-resistance state.

4. The method according to claim 3, characterized in that, The process of reading the total current includes: Apply the read reference voltage to all word lines; Apply read bias voltage to all bit lines and apply the reference potential to all source lines; By sensing the current on each bit line, the sum of the currents of all memory devices in the corresponding column is obtained.

5. The method according to claim 4, characterized in that, The process of performing programming operations also includes: A programming bias potential is applied only to the bit line where the target memory device is located, while all other bit lines and all source lines are left floating.

6. The method according to claim 5, characterized in that, The process of performing the read operation includes: The read reference voltage is applied to the word line where the target memory device is located, and the suppression voltage is applied to the two word lines adjacent to the word line. Apply the read bias voltage to the bit line where the target memory device is located, and apply the reference potential to other bit lines and all source lines; The storage state of the target memory device is obtained by sensing the current on the bit line where the target memory device is located.

7. A low crosstalk control system for a single-transistor NOR memory array, characterized in that, The system for implementing the method of any one of claims 1-6 comprises: A voltage parameter determination module is used to obtain the transfer characteristics of the memory devices constituting the memory array in order to determine the programming voltage, reset voltage and suppression voltage. The reset control module is used to perform a reset operation on all memory devices in the memory array to make them reach a uniform high-impedance state. The verification and reading module is used to read the total current of each column of memory devices in the memory array after the reset control module is operated, so as to verify the array status. The programming control module is used to perform programming operations on the target memory device, including applying the programming voltage to the word line where the target memory device is located, and applying the suppression voltage to the two word lines adjacent to the word line; The status reading module is used to perform a read operation on the target in-memory computing device to obtain its storage status.

8. A computer terminal device, characterized in that, include: One or more processors; A memory, coupled to the processor, for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors perform the steps of the method as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-6.

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