Memory system for performing post-package repair and method of operating same

Abstract

A memory system performing post-package repair (PPR) and an operating method of the memory system are provided. The memory system includes at least one memory device and a controller. The controller includes an input path for transferring a data input / output (I / O) request input from an external device to the at least one memory device, and an output path for transferring a response corresponding to the data I / O request. The controller is configured to selectively couple the output path to the input path for a post-package repair (PPR) operation.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of priority to Korean Patent Application No. 10-2024-0164837, filed on November 19, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure described herein relate to a memory system, and more specifically, to a memory system providing post-packaging repair (PPR) and a method of operating the memory system. Background Technology

[0004] The computing system increases its computational load in response to user demands. As the computational load increases, the amount of data generated or stored also increases. The memory system within the computing system performs input and output data operations in response to requests from external devices such as the host. The memory system may include at least one memory device. The memory device may include at least one of volatile memory cells and non-volatile memory cells for storing data.

[0005] A memory device may include multiple memory cells arranged in a matrix of multiple rows and columns. The memory device includes redundant memory cells for replacing defective memory cells among the multiple memory cells, and performs a repair operation by replacing the memory rows to which the defective memory cells are connected with redundant rows. Post-Package Repair (PPR) refers to the repair operation performed after the memory device has been packaged. Summary of the Invention

[0006] Embodiments of this disclosure may provide an apparatus and method that can perform post-packaging repair (PPR) operations on a memory device using input / output (I / O) buffers established for data input / output operations without establishing or setting up additional buffers.

[0007] Furthermore, embodiments of this disclosure may provide an apparatus and method that allow a memory system to perform post-packaging repair (PPR) operations based on the operating environment and operating state without consuming additional resources for PPR operations, thereby improving and enhancing the data input / output (I / O) performance and operational security of the memory system by allowing more internal resources to be allocated for data I / O operations.

[0008] In embodiments of this disclosure, a memory system may include: at least one memory device; and a controller including an input path and an output path, the input path for transmitting data input / output (I / O) requests from an external device to the at least one memory device, and the output path for transmitting responses corresponding to the data I / O requests. The controller may be configured to selectively connect the output path to the input path for post-packaging repair (PPR) operations.

[0009] The controller may further include: a request buffer, included in the input path and configured to store data I / O requests; a response buffer, included in the output path and configured to store responses; a first multiplexer configured to transmit the output of the response buffer to an external device, or to activate a loopback for routing the output of the response buffer to the request buffer; and a second multiplexer configured to transmit one of the data I / O requests and the output of the first multiplexer to the request buffer.

[0010] The controller may include a layered structure, comprising: a first interface layer configured to perform data communication with an external device; a second interface layer configured to perform data communication with at least one memory device; and a control logic layer disposed between the first and second interface layers and configured to control or manage operations to be performed through the first and second interface layers.

[0011] The control logic layer may include: data input / output circuitry configured to handle or process data input / output requests; post-packaging repair control circuitry configured to perform PPR operations; and memory management circuitry configured to check, track, or manage the operating status of the memory system.

[0012] The post-packaging repair control circuit can be configured to: determine whether to perform a post-packaging repair operation in an idle state; and control the output of the first multiplexer to the loopback response buffer of the second multiplexer, and control the second multiplexer to transmit the output of the first multiplexer to the request buffer to enable the PPR operation.

[0013] The memory management circuit can be configured to: check whether the memory system is in an idle state, transmit the state of the memory system to the post-packaging repair control circuit; and transmit a read request to at least one memory device regarding data stored at a first location that needs to be repaired for PPR operation.

[0014] The controller can be configured to: store data in a second location different from the first location in at least one memory device; and replace the address of the first location with the address of the second location.

[0015] The controller may further include volatile memory configured to store the input / output results of tasks processed or transmitted in the first interface layer, the second interface layer, and the control logic layer. Each of the request buffer and the response buffer may be established or set in the volatile memory.

[0016] The controller may further include a third multiplexer configured to transmit one of the output of a request buffer and a meaningless signal to at least one memory device.

[0017] The controller can be configured to perform error correction operations on data output from at least one memory device based on read requests generated by or sent from the memory management circuitry. The controller can be configured not to have a dedicated buffer for PPR operations only.

[0018] In one embodiment, a controller may include at least one processor and at least one memory. The controller may be configured to perform a post-packaging repair (PPR) operation on at least one memory device and, during the PPR operation, activate a loopback to connect an output path to an input path. The input path may be configured to transmit data input / output (I / O) requests from an external device to at least one memory device, and the output path may be configured to transmit responses corresponding to the data I / O requests to the external device.

[0019] The controller may further include: a request buffer located on the input path and configured to store data I / O requests; a response buffer located on the output path and configured to store responses; a first multiplexer configured to transmit the output of the response buffer to an external device, or to activate a loopback for routing the output of the response buffer to the request buffer; and a second multiplexer configured to transmit one of the data I / O requests and the output of the first multiplexer to the request buffer.

[0020] The controller may further include a hierarchical structure comprising: a first interface layer configured to perform data communication with an external device; a second interface layer configured to perform data communication with at least one memory device; and a control logic layer disposed between the first and second interface layers and configured to control or manage operations to be performed through the first and second interface layers.

[0021] The control logic layer may include: data input / output circuitry configured to handle or process data input / output requests; post-packaging repair control circuitry configured to perform PPR operations; and memory management circuitry configured to check, track, or manage the operating status of at least one memory and at least one processor.

[0022] The post-packaging repair control circuit can be configured to: determine whether to perform a post-packaging repair operation in an idle state; and control the output of the first multiplexer to the loopback response buffer of the second multiplexer, and control the second multiplexer to transmit the output of the first multiplexer to the request buffer to enable the PPR operation.

[0023] The memory management circuitry can be configured to: check whether a data input / output request has been received from an external device to transmit the status of the check to the post-packaging repair control circuitry; and transmit a read request to at least one memory device regarding data stored at a first location that needs to be repaired for PPR operation.

[0024] The controller may further include volatile memory configured to store the input / output results of tasks processed or transmitted in the first interface layer, the second interface layer, and the control logic layer. Each of the request buffer and the response buffer may be established or set in the volatile memory.

[0025] The controller may further include a third multiplexer configured to transmit one of the output of a request buffer and a meaningless signal to at least one memory device.

[0026] In another embodiment, a method of operating a memory system may include activating a loopback for connecting an output path to an input path during a post-packaging repair (PPR) operation on at least one memory device included in the memory system. The input path may be configured to transmit a data input / output (I / O) request from an external device to the at least one memory device. The output path may be configured to transmit a response corresponding to the data I / O request to the external device.

[0027] The method may further include: checking whether at least one memory device is in an idle state; performing a read operation on data stored at a first location of the at least one memory device, wherein the first location is subjected to a PPR operation; storing data returned via an output path and an input path at a second location of the at least one memory device; and replacing the address of the first location with the address of the second location.

[0028] These and other features and advantages of the present invention will become apparent from the detailed description and accompanying drawings of the embodiments disclosed herein. Attached Figure Description

[0029] The description herein refers to the accompanying drawings, in which the same reference numerals denote the same parts throughout the drawings.

[0030] Figure 1 A first data processing apparatus according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A memory device according to an embodiment of the present disclosure is shown.

[0032] Figure 3 A first memory controller according to an embodiment of the present disclosure is shown.

[0033] Figure 4 This illustrates data input / output operations performed in a memory controller according to an embodiment of the present disclosure.

[0034] Figure 5 The illustration shows the configuration of a volatile memory device included in a memory controller according to an embodiment of the present disclosure.

[0035] Figure 6 A second memory controller according to an embodiment of the present disclosure is shown.

[0036] Figure 7 Show Figure 6 The post-packaging repair (PPR) operation of the memory controller described in [the document].

[0037] Figure 8 A second data processing apparatus according to an embodiment of the present disclosure is shown.

[0038] Figure 9 A third data processing apparatus according to an embodiment of the present disclosure is shown. Detailed Implementation

[0039] Various embodiments of this disclosure are described below with reference to the accompanying drawings. In this disclosure, elements and features may be configured or arranged in different ways to form other embodiments, which may be variations of any of the disclosed embodiments.

[0040] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiments.

[0041] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0042] In this disclosure, various units, circuits, or other components may be described or claimed to be "configured" to perform one or more tasks. In such a context, "configured" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even if a specified block / unit / circuit / component is not currently operational, e.g., not turned on or activated, it can be said that the block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuits used with the "configured" language include hardware, circuits, memory storing program instructions that can be executed to perform the operation, etc. Additionally, "configured" can include general structures, such as general-purpose circuits manipulated by software and / or firmware (e.g., FPGAs), or general-purpose processors that execute software to operate in a manner capable of performing the relevant tasks. "Configured" can also include adjusting manufacturing processes, such as semiconductor manufacturing facilities, to manufacture means suitable for performing or implementing one or more tasks, such as integrated circuits.

[0043] As used in this disclosure, the terms “machine,” “circuit,” or “logic” mean all of the following: (a) hardware circuitry implementations only, such as implementations in analog and / or digital circuitry only; (b) combinations of circuitry with software and / or firmware, such as (if applicable): (i) combinations of processors or (ii) portions of processor / software, including digital signal processors, software, and memory, which work together to enable a device such as a mobile phone or server to perform various functions; and (c) circuitry, such as a microprocessor or a portion of a microprocessor, which requires software or firmware to operate, even if the software or firmware is not physically present. This definition of “machine,” “circuit,” or “logic” applies to all uses of the term in this application, including in any claim. As a further example, as used in this application, the terms “machine,” “circuit,” or “logic” also cover implementations of processors or portions of processors and their accompanying software and / or firmware only. If applicable to a particular claim element, the terms “machine,” “circuit,” or “logic” also cover integrated circuits, such as memory devices.

[0044] As used herein, the terms “first,” “second,” “third,” etc., used as labels for the nouns that follow them do not imply any kind of order, such as spatial, temporal, logical, etc. The terms “first” and “second” do not necessarily mean that the first value must precede the second. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0045] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on these factors or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the determination of A from also being based on C. In other cases, A may be determined solely based on B.

[0046] Embodiments will now be described with reference to the accompanying drawings, wherein the same numbers denote the same elements.

[0047] Figure 1 A first data processing apparatus according to an embodiment of the present disclosure is shown.

[0048] Reference Figure 1 The first data processing device may include a host 110 and a memory system 150.

[0049] The memory system 150 can perform write or read operations based on data input / output (I / O) requests received from the host 110. The memory system 150 may include a memory controller 160 and a memory device 180, which can communicate with each other via a data path or channel (CH). According to an embodiment, the memory device 180 may include at least one of a plurality of volatile memory cells and a plurality of non-volatile memory cells.

[0050] Host 110 may include electronic devices such as computers, laptops, smartphones, smart tablets, smart TVs, netbooks, etc. Host 110 can access memory system 150 in conjunction with the operation of application 114 and operating system 112.

[0051] Host 110 can send a request (REQ) and an address (ADDR) to memory system 150. Memory system 150 can send a response (REP) corresponding to the request (REQ) to host 110. The request (REQ) sent by host 110 to memory system 150 may include a data input / output request, such as a read request for reading data stored in memory device 180, a write request for storing data in memory device 180, etc. Furthermore, according to an embodiment, host 110 can send a request or command to memory system 150 that can help maintain the performance of memory system 150 or manage, interrupt, or control the internal operations of memory system 150.

[0052] The memory controller 160 may include memory management circuitry 162, data input / output circuitry 164, and post-packaging repair control circuitry 166. The configuration of the memory controller 160 may vary based on the requested or designed performance of the memory system 150. According to embodiments, each of the memory management circuitry 162, data input / output circuitry 164, and post-packaging repair control circuitry 166 within the memory controller 160 may be configured as an independent module. Furthermore, according to embodiments, each of the memory management circuitry 162, data input / output circuitry 164, and post-packaging repair control circuitry 166 within the memory controller 160 may be implemented as a functional unit or block capable of performing the designed operations via internal resources (e.g., at least one processor, core, or logic) and at least one memory or buffer operably coupled to at least one processor, core, or logic.

[0053] Data input / output circuitry 164 can process or handle data input / output requests transmitted from host 110. For example, based on a read request and address input from host 110, data input / output circuitry 164 can output data stored in memory device 180 to host 110. Additionally, in response to a write request and address input from host 110, data input / output circuitry 164 can store data at a location corresponding to the address (e.g., a memory cell accessed via a row / column address). Since memory system 150 is a device for storing and outputting data, the operation of data input / output circuitry 164 has the greatest impact on the performance of memory system 150. Data input / output circuitry 164 can preferentially utilize the internal resources included in memory system 150 to efficiently and quickly process or handle data input / output requests from host 110.

[0054] Post-packaging repair control circuit 166 can perform or control post-packaging repair (PPR) operations. Post-packaging repair (PPR) operations can include a memory self-repair process that replaces access to defective memory cells, rows, or columns with access to spare memory cells, rows, or columns in the memory device 180. Post-packaging repair (PPR) can be broadly categorized into soft post-packaging repair (sPPR) and hard post-packaging repair (hPPR). Soft post-packaging repair (sPPR) can repair defective cells, rows, or columns in the current startup cycle. Therefore, when the power supply to the data processing device or memory system 150 is removed or the data processing device or memory system 150 is restarted or reset, the memory system 150 can return to its original state. On the other hand, hard post-packaging repair (hPPR) can permanently repair defective cells, rows, or columns.

[0055] According to an embodiment, the memory system 150 can perform a PPR operation based on a request REQ from the host 110, or the memory system 150 can perform a PPR operation without any request REQ input from the host 110. For example, a hard-packed repair (hPPR) operation can be performed based on a request REQ input from the host 110. The host 110 can send a request REQ and the address ADDR of a defective cell, row, or column in the memory device 180 to the memory system 150. In this case, as a response REP to the request REQ from the host 110, the memory system 150 can send the address of a cell, row, or column that can replace the address of the defective cell, row, or column to the host 110 after the hard-packed repair (hPPR) operation. The host 110 can then use the address of the replaced cell, row, or column instead of the address of the defective cell, row, or column. This process can improve or enhance the operational stability of the data processing device.

[0056] According to an embodiment, the memory system 150 can perform a soft post-packaging repair (sPPR) operation based on a request (REQ) from the host 110. Additionally, according to an embodiment, the memory system 150 can perform a hard post-packaging repair (hPPR) operation or a soft post-packaging repair (sPPR) operation without a request (REQ) from the host 110. Furthermore, when a request (REQ) is received from the host 110, the memory system 150 can check if there is a data input / output request transmitted from the host 110 to perform a hard post-packaging repair (hPPR) operation or a soft post-packaging repair (sPPR) operation. The memory system 150 can perform a PPR operation on a memory device 180 that is in an idle state.

[0057] Memory management circuitry 162 can check, track, or manage the operational status of memory devices 180 and memory controller 160 in memory system 150. To improve the data input / output performance of memory system 150, memory controller 160 and memory devices 180 may include various devices or components for enhancing data input / output performance. To systematically link these various devices or components, memory management circuitry 162 can check the operational status of each device or component and check whether multiple detailed tasks or jobs are executed sequentially. Memory management circuitry 162 can be used to prevent faults in memory system 150 and improve the overall performance of memory system 150.

[0058] Figure 2 A memory device according to an embodiment of the present disclosure is shown. Specifically, Figure 2 Show Figure 1 Several examples of the memory device 180 described herein.

[0059] Reference Figure 1 and Figure 2 The memory device 180 may include multiple memory chips, multiple memory dies, or multiple memory banks. For example, the multiple memory banks in the memory device 180 may include structures or components that support post-package repair (PPR) operations.

[0060] The first memory device 180A may include a redundant unit RC for supporting post-packaging repair (PPR) operations. The redundant unit RC can be accessed via redundant word lines RWL0 and RWL1. For data input / output operations, a plurality of memory cells MC included in the first memory bank BANK0 of the first memory device 180A can be accessed via word lines WL0 to WLm and bit lines BL0 to BLn. If at least some of the memory cells MC accessed via word lines WL0 to WLm are defective, the redundant unit RC can be used to replace the defective memory cells through the PPR operation. For example, if a memory cell MC connected to the first word line WL0 is defective, the first word line WL0 can be replaced with the first redundant word line RWL0.

[0061] The second memory device 180B may include a redundant unit RC for supporting post-packaging repair (PPR) operations. The redundant unit RC can be accessed via redundant bit lines RBL0 and RBL1. For data input / output operations, a plurality of memory cells MC included in the first memory bank BANK0 of the second memory device 180B can be accessed via word lines WL0 to WLm and bit lines BL0 to BLn. If at least some of the memory cells MC accessed via bit lines BL0 to BLn are defective, the redundant unit RC can be used to replace the defective memory cells through the PPR operation. For example, if a memory cell MC connected to the first bit line BL0 is defective, the first bit line BL0 can be replaced with the first redundant bit line RBL0.

[0062] According to an embodiment, the number of redundant cells RC included in the memory device 180 and the arrangement position of the redundant cells RC can be changed. Based on the structure of the redundant cells RC, the post-packaging repair (PPR) operation can include a task or job of repairing each memory bank or each memory die row by row or column by column.

[0063] Figure 3 A first memory controller 160A according to an embodiment of the present disclosure is shown. Specifically, Figure 3 Showing with Figure 1 The first example corresponds to the memory controller 160 described herein.

[0064] Reference Figure 3The first memory controller 160A may have a hierarchical structure. Here, a hierarchical structure is a system architecture in which various services, operations, or tasks of the memory controller 160A can be assigned to multiple layers. Each layer may have at least one component for performing the specific or designed services, operations, or tasks assigned to it.

[0065] The first memory controller 160A may include a host interface layer 202, a control logic layer 204, and a memory interface layer 208. The host interface layer 202, the control logic layer 204, and the memory interface layer 208 may interact with each other through means for temporarily storing and transferring data, tasks, or results (e.g., buffers, queues, etc.).

[0066] According to an embodiment, the control logic layer 204 may include at least one processor or core 212 and at least one semiconductor intellectual property core (SIP) core 214. Here, a semiconductor intellectual property core is also referred to as an IP core or IP block. A semiconductor intellectual property core can refer to a logic, cell, integrated circuit, or layout design implemented at least based on specific intellectual property (IP). For example, semiconductor intellectual property core 214 may include part or all of logic, cells, circuit layout, or a (micro)processor.

[0067] The control logic layer 204 can be divided into multiple components or units for specific or designed services, operations, or tasks to be dispatched or assigned to it. The divided blocks can be executed by at least one processor or core 212 or at least one semiconductor intellectual property core 214. At least one processor or core 212 or at least one semiconductor intellectual property core 214 can be connected to internal resources 206 via a system bus (BUS). According to an embodiment, Figure 1 The memory management circuit 162, data input / output circuit 164, and post-packaging repair control circuit 166 described herein may be components included in the control logic layer 204.

[0068] According to an embodiment, internal resource 206 may include at least one of volatile memory 216 and non-volatile memory 218. Non-volatile memory 218 may store firmware, etc., and is designed and configured to perform operations of the first memory controller 160A. Additionally, within internal resource 206, volatile memory 216 may serve as a buffer, queue, etc., used or associated with the host interface layer 202, control logic layer 204, and memory interface layer 208. For example, volatile memory 216 may include SRAM, and non-volatile memory 218 may include NAND flash memory. Reference will be made later. Figure 5 Description of internal resource 206.

[0069] The host interface layer 202 can support data communication between the first memory controller 160A and external devices. For example, the host interface layer 202 can receive... Figure 1 The host 110, as described, transmits a request REQ or an address ADDR and sends the request REQ or address ADDR to the control logic layer 204. Additionally, the host interface layer 202 can send a response REP prepared by the control logic layer 204 to the host 110, which is an external device.

[0070] The memory interface layer 208 can perform operations to support data communication between the first memory controller 160A and the memory device 180. For example, the memory interface layer 208 can send data input / output requests or post-packaging repair (PPR) requests to the memory device 180. Additionally, the memory interface layer 208 can receive data from the memory device 180 or receive completion signals corresponding to requests sent to the memory device 180. The control logic layer 204 can generate or configure response replies (REPs) for currently executing or executed tasks or requests. Furthermore, the control logic layer 204 can terminate operations corresponding to requests based on data transmitted through the memory interface layer 208, completion signals, etc.

[0071] Figure 4 This illustrates data input / output operations performed in a memory controller according to an embodiment of the present disclosure.

[0072] Reference Figure 4 The memory device 180 may include multiple DRAMs. The memory interface layer 208 may send requests, write data, etc. to the multiple DRAMs in the memory device 180, or receive and read data from the multiple DRAMs in the memory device 180.

[0073] When data input / output operations are performed in the memory system, input paths and output paths can be formed in the host interface layer 202, the data input / output circuit 164A, and the memory interface layer 208. An input path refers to the processing line or path that transmits a request REQ sent from the host interface layer 202 to the data input / output circuit 164A to the memory interface layer 208. Depending on the performance of the memory system, the process or operation of transmitting the request REQ from the host interface layer 202 to the memory interface layer 208 can be complex. For example, the data input / output circuit 164A can verify the validity of the request REQ or security-related information associated with the request REQ. Furthermore, the data input / output circuit 164A can schedule multiple data input / output operations, such as reads and writes, performed in multiple DRAMs, and can detect and resolve various types of risks.

[0074] The data input / output circuitry 164A can be configured to detect and resolve various types of risks (e.g., data risks, control risks, structural risks, etc.) that may occur during pipelined processing, which improves the processing speed of the memory system by dividing and allocating tasks or operations corresponding to requests or commands into multiple stages and processing these tasks or operations simultaneously within the memory controller. One of the representative components included in the input path may be a request buffer 232. The request buffer 232 can temporarily store multiple data input / output requests that have been or are planned to be sent to multiple DRAMs in the memory device 180.

[0075] Furthermore, the output path refers to the processing line or path that transmits information from the memory interface layer 208 to the host interface layer 202. For example, a read request (REQ) and an address can be sent to the DRAM in the memory device 180 via the input path. The memory device 180 can send the read data stored in the memory cell corresponding to the address sent along with the read request to the memory interface layer 208. The memory interface layer 208 can then send the data sent from the memory device 180 to the data input / output circuit 164A.

[0076] According to an embodiment, the memory interface layer 208 can check and correct errors in the data output from the memory device 180 based on error correction codes (ECC), parity checks, etc. The data input / output circuit 164A can generate a response based on the read data output from the memory interface layer 208 and the read request stored in the request buffer 232. This response can be temporarily stored in the response buffer 234. The response stored in the response buffer 234 can be transmitted to the host interface layer 202. According to an embodiment, the output path can have different components depending on the operating performance of the memory system. One of the representative components included in the output path can be the response buffer 234.

[0077] According to embodiments, the memory controller can be implemented as a system-on-a-chip (SoC). Figure 3 As shown, the memory controller may include at least one of a processor or core 212 and at least one of a semiconductor intellectual property core 214, and at least one of volatile memory 216 and non-volatile memory 218. Request buffer 232 and response buffer 234 may be disposed in volatile memory 216. If the aforementioned input paths and output paths refer to a sequential process of performing services, operations, and tasks, the actual data or signal flow and control within the memory controller of the system-on-chip (SoC) may include the interaction or exchange of data and signals between internal components (e.g., volatile memory 216, processor or core 212, memory interface layer 208, etc.) connected via a bus or interface (e.g., an AXI interface, etc.).

[0078] Once a memory controller is manufactured and implemented as a System-on-Chip (SoC), it can be difficult to change or modify it. Therefore, a memory controller can improve data input / output performance when limited internal resources (e.g., memory, processor, etc.) are used efficiently. Furthermore, the performance of the memory system can be improved or enhanced when limited internal resources are efficiently allocated to each layer or functional configuration block or unit included in the memory controller.

[0079] Figure 5 The illustration shows the configuration of a volatile memory device included in a memory controller according to an embodiment of the present disclosure.

[0080] Reference Figure 5 ,Apart from Figure 4 In addition to the request buffer 232 and response buffer 234 described herein, multiple buffers may also be provided in the volatile memory 216.

[0081] According to an embodiment, volatile memory 216 may include a status information buffer 240. For example, memory management circuitry 162 may store operational information about a memory controller or memory device in the status information buffer 240. Other components may determine whether to perform a service, task, or operation based on the values ​​stored in the status information buffer 240.

[0082] According to an embodiment, the volatile memory 216 may include a write data buffer 242 and a read data buffer 244. The write data buffer 242 may temporarily store data to be stored in the memory device 180. The read data buffer 244 may temporarily store data output from the memory device 180. According to an embodiment, the write data buffer 242 and the read data buffer 244 may be combined or included in the request buffer 232 and the response buffer 234.

[0083] According to an embodiment, volatile memory 216 may include an error correction code operation (ECC) buffer 246. When data output from memory device 180 may contain errors, the memory controller can detect and correct the errors in the data. The error correction code operation may include multiple logical operations. The error correction code operation buffer 246 can be used to execute multiple logical operations and store the results of the multiple logical operations.

[0084] According to an embodiment, volatile memory 216 may include defective address buffer 236. When the address of a memory cell with a permanent or temporary fault in the memory cells included in memory device 180 is stored in defective address buffer 236, the memory controller may perform a post-packaging repair (PPR) operation on the address stored in defective address buffer 236.

[0085] According to an embodiment, the volatile memory 216 may include a post-packaging repair (PPR) buffer 238. The PPR buffer 238 can be used to temporarily store data during a PPR operation before storing the data corresponding to the address of the defective memory cell in the memory cell corresponding to the replacement address.

[0086] According to an embodiment, the volatile memory 216 may also include other buffers (first buffer, second buffer) 248, 250 for various purposes.

[0087] According to an embodiment, the memory controller can set up multiple buffers in the volatile memory 216 as needed. The memory controller can remove the buffers by releasing or canceling their setup when the corresponding operation terminates. In this case, the use of the volatile memory 216 can be very efficient, but repeatedly setting up and releasing buffers may incur overhead. Additionally, according to an embodiment, when the memory controller has set up all buffers in the volatile memory 216 and the buffers occupy a portion of the storage area of ​​the volatile memory 216, the use of the volatile memory 216 may be inefficient due to buffers that are not frequently used or accessed. Therefore, the performance of the memory system can be optimized based on how much of the limited data storage capacity of the volatile memory 216 is allocated to each of the multiple buffers.

[0088] According to this embodiment, the number of buffers that need to be set in the volatile memory 216 can be reduced. For example, the post-packaging repair (PPR) buffer 238 may be unnecessary when post-packaging repair (PPR) operations are not performed. In addition, PPR operations are rarely performed compared to data input / output operations. To efficiently utilize internal resources, the memory system can have a structure of volatile memory 216 without the PPR buffer 238, and allocate some space corresponding to the PPR buffer 238 for other buffers, such as request buffer 232 and response buffer 234 that can be used for data input / output operations.

[0089] Figure 6 A second memory controller according to an embodiment of the present disclosure is shown. For convenience, [the following will be used]. Figure 4 and Figure 6 The memory controllers described in the text are compared and the differences are highlighted.

[0090] Reference Figures 4 to 6The memory device 180 may include multiple DRAMs. The memory interface layer 208 may send requests, write data, etc., to the multiple DRAMs in the memory device 180, or receive and read data from the multiple DRAMs. The host interface layer 202 may support data communication between an external device (e.g., a host) and the memory controller.

[0091] When performing data input / output operations in the memory system, input paths and output paths can be formed in the host interface layer 202, the data input / output circuit 164B, and the memory interface layer 208.

[0092] The address corresponding to the location of the defective cell in memory device 180 can be stored in defective address buffer 236. In order to replace the memory cell accessed by the address stored in defective address buffer 236 with another memory cell (e.g., a redundant cell), the memory system can perform a post-packaging repair (PPR) operation.

[0093] The memory controller can use the input and output paths used in data input / output operations when performing post-packaging repair (PPR) operations. This eliminates the need to set up a post-packaging repair (PPR) buffer 238 in the volatile memory 216.

[0094] For example, since soft post-packaging repair (sPPR) operations can typically be performed during the current boot cycle of the memory system to repair defective cells or rows without a request from the host, data requested by the host to be stored is likely to be stored in the memory cell in memory device 180 that is the target of the soft post-packaging repair (sPPR) operation. Specifically, when an error is detected in the data read from the corresponding memory cell by error detection and correction based on error detection codes or parity checks, the memory controller can determine or check whether a soft post-packaging repair (sPPR) operation should be performed at the address of the corresponding memory cell. Therefore, if a post-packaging repair (PPR) buffer 238 is not provided in volatile memory 216, additional means may be required to move or migrate the read and corrected data stored in the corresponding memory cell to another memory cell designated to replace the corresponding memory cell.

[0095] During a Post-Package Repair (PPR) operation, if data is stored in a memory cell accessed via an address stored in the defective address buffer 236, that data can be read and then stored in another memory cell to be replaced. Although the PPR buffer 238 is not set or established in the volatile memory 216, the PPR operation can be understood as a process involving sequentially executed read and write operations, since the PPR operation includes reading data from memory device 180 and then storing the read data back into memory device 180. Therefore, the data input / output circuit 164B is configured such that the output path can be selectively coupled to the input path to activate a loopback for converting read data into write data.

[0096] The data input / output circuit 164B may include a request buffer 232 configured to store data input / output requests on the input path and a response buffer 234 configured to store responses on the output path. According to an embodiment, the data input / output circuit 164B may include: a first multiplexer 264 configured to transmit the output of the response buffer 234 to an external device or loop back the output of the response buffer 234 to the request buffer 232; and a second multiplexer 262 configured to transmit to the request buffer 232 one of the output of the first multiplexer 264 and the data input / output request from the external device.

[0097] Furthermore, the data input / output circuitry 164B may include a third multiplexer 266 configured to selectively transmit the output of the request buffer 232 to the memory device 180. According to embodiments, the third multiplexer 266 may transmit the output of the request buffer 232 to the memory interface layer 208 in response to a request block signal (Req Block) or transmit a meaningless signal (e.g., a signal with a '0' value) to the memory interface layer 208. For example, the request block signal (Req Block) may be activated by the operating state of the memory device 180 or by an interrupt signal generated within the memory system.

[0098] The following describes the process through... Figure 6 The method described in the document for performing a post-package repair (PPR) operation on the data input / output circuit 164B is as follows. Figure 7 Show Figure 6 The post-packaging repair (PPR) operation of the memory controller described in [the document].

[0099] According to an embodiment, a post-packaging repair (PPR) operation for defective or faulty memory cells in the memory device 180 can be performed without performing data input / output operations via the data input / output circuit 164B. For example, if a PPR operation is performed while performing data input / output operations via the data input / output circuit 164B, the data input / output performance of the memory system may be degraded.

[0100] When performing a post-packaging repair (PPR) operation based on a request from an external device or the operating conditions or state of the memory system, the data input / output circuit (164B) can selectively perform either a data input / output operation or a post-packaging repair (PPR) operation.

[0101] Reference Figure 7 To perform post-package repair (PPR) operations, the PPR control circuit 166 can control the data input / output circuit 164B. The PPR control circuit 166 can transmit at least one control signal CTRL to the data input / output circuit 164B.

[0102] First, when the Post-Package Repair (PPR) operation begins, the PPR control circuit 166 can transmit control signals to the first multiplexer 264 and the second multiplexer 262 (①). The first multiplexer 264 can be configured to transmit the output from the response buffer 234 back to the second multiplexer 262 via an activation loop, instead of transmitting the output from the response buffer 234 to the host interface layer 202, thereby transmitting the output from the response buffer 234 to an external device (①). Additionally, the second multiplexer 262 can be configured to transmit the output of the first multiplexer 264 to the request buffer 232, instead of transmitting the request from the external device input through the host interface layer 202 to the request buffer 232 (①).

[0103] The memory management circuit 162 can transmit a request to the memory interface layer 208 for reading data stored in a defective or erroneous memory cell that has undergone a post-packaging repair (PPR) operation (②). The memory interface layer 208 can transmit the request to the memory device 180 and transmit data read from and output from the memory device 180 to the response buffer 234 (③).

[0104] During the post-packaging repair (PPR) operation, data stored in the response buffer 234 can be transmitted to the request buffer 232 via the first multiplexer 264 and the second multiplexer 262 (④).

[0105] The third multiplexer 266 can prevent data input to the request buffer 232 from being transmitted to the memory interface layer 208 (⑤). Data read during the post-packaging repair (PPR) operation should be stored in a memory cell other than the defective or erroneous memory cell that originally stored the data. Therefore, data can be stored in the request buffer 232 until a replacement memory cell is determined.

[0106] The post-packaging repair control circuit 166 can perform operations through the memory interface layer 208 to select or determine which memory cell can replace the defective or faulty memory cell (⑥). For example, the memory interface layer 208 can locate available redundant cells in the memory device 180 and check the operational status of the located redundant cells. In addition, the address (e.g., row address or column address) of the defective or faulty memory cell can be mapped to the address (e.g., row address or column address) of the redundant cell to be replaced.

[0107] Subsequently, the data stored in the request buffer 232 can be transmitted to the memory interface layer 208 (⑦) via the third multiplexer 266. The memory interface layer 208 can store the data in a memory cell at a replacement location (e.g., a redundant cell replacing a defective or faulty memory cell) based on address mapping information.

[0108] As described above, in the memory system, post-packaging repair (PPR) operations can be performed by data input / output circuitry 164B, which is designed and configured to perform data input / output operations, eliminating the need for the memory system to include or establish a PPR buffer 238 in the volatile memory 216. In this way, the storage space in the volatile memory 216 that could otherwise be allocated to the PPR buffer 238 can be used for another buffer (e.g., a request buffer 232 or a response buffer 234) for another operation. This improves the data input / output performance of the memory system.

[0109] Figure 8 A second data processing device 400 according to an embodiment of the present disclosure is shown.

[0110] Reference Figure 8 The second data processing device 400 may be implemented in the form of a multi-chip package including multiple semiconductor devices or multiple semiconductor chips. According to an embodiment, the second data processing device 400 may include a high-bandwidth memory (HBM) module 410. The HBM module 410 may correspond to... Figure 1 The memory system 150 described herein.

[0111] The second data processing device 400 may include an interposer 406 disposed on a package substrate 408. The interposer 406 can provide a path for data communication between multiple devices or components. The interposer 406 can be used to simplify the manufacturing process of multi-chip packages supporting high-speed data communication and improve the signal quality of high-speed data communication. The HBM module 410 disposed on the interposer 406 may include multiple memory dies 414A to 414D and a logic die 412. Figure 8 The HBM module 410 described herein may include four memory dies 414A to 414D, but the number of memory dies may be 8, 12, 16, etc., depending on the desired performance included in the HBM module 410. According to an embodiment, each of the memory dies 414A to 414D may include a data storage region comprising volatile memory cells (e.g., DRAM, SRAM, etc.). According to an embodiment, multiple memory dies 414A to 414D may include data storage regions comprising different types of memory cells (e.g., volatile memory cells and non-volatile memory cells). For example, some of the multiple memory dies 414A to 414D may be DRAM memory dies, and others may be NAND memory dies.

[0112] Multiple memory dies 414A to 414D can be stacked vertically and can correspond to Figure 1 The memory device 180 described herein. A plurality of memory dies 414A to 414D may transmit and receive data or signals via through-silicon vias (TSVs) to enable vertical electrical connections between the memory dies. Additionally, each of the plurality of memory dies 414A to 414D may include a microbump to maintain a gap with adjacent dies and ensure electrical contact.

[0113] A host 402, connected to the HBM module 410 and configured to process data, can be placed on the intermediary layer 406. The host 402 may include a central processing unit (CPU), a graphics processing unit (GPU), or a system-on-a-chip (SoC). The host 402 may correspond to an external device (e.g., Figure 1(As described in the document, the host 110 is connected to the memory system 150). According to an embodiment, the HBM module 410 can be directly connected to the host 402, such as a CPU or GPU, and can increase bandwidth to bypass the memory controller. This architecture can reduce data transfer latency and improve system performance. For example, the host 402, such as a CPU or GPU, can send data read / write requests to the HBM module 410, and the HBM controller included in the logic die 412 can analyze the request input from the host 402 and send the request to a specific memory bank included in a plurality of memory dies 414A to 414D. The specific memory bank included in the plurality of memory dies 414A to 414D can read or write the requested data via a TSV and send the read data to the host 402, such as a CPU or GPU, via an intermediary layer 406. Additionally, the host 402, such as a CPU or GPU, can process the data output from the HBM module 410 and return results (e.g., data) to the HBM module 410.

[0114] According to an embodiment, the HBM controller included in the logic die 412 may include Figure 1 The memory controller 160 described herein. The HBM controller included in the logic die 412 can efficiently control the memory banks included in multiple memory dies 414A to 414D and manage data transfer based on the priority assigned to multiple data input / output requests.

[0115] In addition, each of the logic die 412 and the host 402 may include at least one component corresponding to the physical layer PHY, which is responsible for sending and receiving data or signals between them.

[0116] Figure 9 A third data processing apparatus according to an embodiment of the present disclosure is shown.

[0117] Reference Figure 9 The third data processing device may include a host 302 and a memory system 310 (e.g., a compute fast link (CXL) based device). The host 302 and memory system 310 may perform data communication via a protocol or interface based on a computer memory link (e.g., CXL). A controller 312 within the memory system 310 may include... Figure 1 The memory controller 160 is described in the document. The controller 312 can manage and control the data I / O operations performed in the memory device (or CXL-based memory device) 314 based on the priority of multiple data I / O requests assigned to it.

[0118] The memory system 310 can be designed to support memory-centric computing technologies. Memory-centric computing technologies can provide dynamically scalable shared memory, overcoming the limitations of performance and capacity for large-capacity data processing found in CPU-centric systems, and meeting the needs or requirements of memory-decomposed systems. Therefore, system scalability can be flexibly maintained according to the requirements of the data processing device. Due to the explosive growth in data volume from emerging applications such as big data and artificial intelligence (AI), a third data processing device, including at least one computing unit, can be designed or built to meet the demands of large-capacity, high-bandwidth memory or innovative architectural changes. The number of servers and memory devices can continue to increase to meet enormous memory demands. Protocols or interfaces based on computer memory links can be provided to support large-capacity, high-bandwidth memory.

[0119] Memory decomposition can be an architectural solution that separates memory (e.g., memory devices) from compute nodes (e.g., compute devices), allowing system designers to flexibly expand additional memory capacity independently of each compute server while meeting the memory requirements of user applications. For example, a compute server with high memory utilization can use memory devices located further away from other nodes included in the decomposition group. Therefore, this decomposition scheme can manage or utilize resources more efficiently than a previously proposed dedicated CPU and memory architecture.

[0120] It can provide computer memory links (e.g., Compute Express Link, CXL) TM This accelerates the shift towards memory decomposition architectures. Computer memory links (CXLs) are industry-supported cache coherent interconnects (CCIs) used to enable various processors to efficiently expand memory capacity via memory semantic protocols. Unlike host memory 306, which is entirely dependent on the host central processing unit (CPU) 304, memory devices 314 connected to the host 302 via CXL-based protocols or interfaces can include additional data or values, such as data processing engines communicating via handshakes, as shared memory or processing in memory (PIM).

[0121] Host 302 may include host CPU 304 and host memory 306. The number and configuration of host CPU 304 and host memory 306 may vary depending on the performance, operational requirements, operating speed, and data I / O speed of host 302. Host CPU 304 and host memory 306 can send and receive data through a mutually agreed communication interface protocol. Various communication standards or interfaces exist, such as Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect High Speed ​​(PCIe), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), and Mobile Industry Processor Interface (MIPI), as examples of agreed standards for sending and receiving data. According to an embodiment, host 302 and host memory 306 may be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) can include scalable, hot-pluggable plug-and-play serial interfaces that ensure cost-effective connectivity to peripherals such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, and video conferencing cameras.

[0122] exist Figure 9 In this context, host 302 can perform data communication with memory system 310 via a computer memory link-based protocol or interface (e.g., a CXL-based protocol or interface). TM Both Compute Express Link (CXL) and PCIe (Peripheral Component Interconnect Express) are standard interfaces used to connect peripheral devices and the CPU in a computer system. However, CXL... TM There are several differences between CXL and PCIe. First, PCIe was designed as a standard for general-purpose input / output devices, while CXL... TM It is an interface specifically designed for memory access and high-speed data transfer in high-performance computing environments. Therefore, CXL TM Designed to allow the CPU direct access to the device's memory, PCIe's functionality in this regard may be limited. Furthermore, PCIe uses a unidirectional communication method, while CXL... TM It supports bidirectional communication. For example, CXL-based devices can support simultaneous data transmission and reception. Because of CXL... TM Designed to maintain backward compatibility with PCIe, CXL-based devices can be designed or implemented by leveraging a proposed PCIe infrastructure.

[0123] According to embodiments, data communication of memory devices 314 (e.g., CXL-based memory devices) distributed to the host central processing unit (e.g., CPU) 304 may have limited interface bandwidth compared to host memory 306. For example, when using DDR4 DIMMs and DDR5 DIMMs as host memory 306, the DIMM has a 64-bit (i.e., 8-byte) data width. The maximum bandwidth of DDR4 can be 25.6 GB / s (= 3.2 Gbps × 8 bytes), and the maximum bandwidth of DDR5 can be 38.4 GB / s (= 4.8 Gbps × 8 bytes) or 51.2 GB / s (= 6.4 Gbps × 8 bytes). Therefore, when the storage capacity of each chip is 64 Gb, the interface bandwidth can be 0.4 s. -1 (=25.6GB / s / 64GB) and 0.6s -1 (=38.4GB / s / 64GB) or 0.8s -1 (=51.2GB / s / 64GB). On the other hand, the interface bandwidth of the memory system 310 may be limited to 0.0625s. -1 (=32GB / s (@PCIe 5.0 x 8) / 512GB). This bandwidth difference may limit the input / output performance of data processing devices.

[0124] To overcome the aforementioned problems, the memory system 310 may include a controller 312 (e.g., a CXL-based core) designed and used for near data processing (NDP). Near data processing (NDP) can be a computing scheme for improving or enhancing data processing efficiency. Near data processing (NDP) may be based on a configuration in which the controller 312 (e.g., at least one processor or core that processes data) is arranged or located near a data storage device or memory (e.g., memory device 314).

[0125] In one proposed computing model, the host CPU 304 retrieves data from a memory device 314 connected to expand the host memory 306, processes the data, and stores the results back into the memory device 314. However, in applications that require processing large amounts of data, this approach can lead to a bandwidth bottleneck between the memory device 314 and the host CPU 304. To address this issue, near-data processing (NDP) can be designed to place the controller 312 (e.g., a processor that processes the data) near the memory device 314 where the processed data is stored. That is, instead of moving data from the memory device 314 to the host CPU 304, the controller 312, which acts as the processor performing data processing, can be contained within the memory system 310 where the data is located. This configuration can significantly reduce or avoid latency and energy consumption caused by data movement.

[0126] Unlike memory system 310, host memory 306 can be used for in-memory processing of the host CPU 304. In-memory processing allows as much data as possible to be stored in host memory 306 and reduces latency caused by disk I / O (e.g., memory system I / O). In this configuration, host memory 306 can provide excellent performance for database work, real-time analytics, and other applications. However, host memory 306 is expensive and has limited capacity, which can limit its ability to process very large datasets. Therefore, a third data processing device can overcome some of the operational and performance limitations of host memory 306 by using memory system 310, which includes controller 312 for near-data processing (NDP).

[0127] As described above, the memory system according to embodiments of this disclosure can improve data input / output (I / O) performance by efficiently allocating or using internal resources and improving the utilization of limited internal resources.

[0128] In addition, the memory system according to the embodiments of this disclosure can reduce the storage capacity overhead of the volatile memory included in the memory system because there is no need to set up or establish a buffer dedicated to post-packaging repair (PPR).

[0129] The methods, processes, and / or operations described herein can be performed by code or instructions executable by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the apparatus described herein or an apparatus other than the elements described herein. Because the algorithms that form the basis of the methods or operations of the computer, processor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0130] In addition, another embodiment may include a computer-readable medium, such as a non-transient computer-readable medium, for storing the above-described code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device that may be movably or permanently coupled to a computer, processor, controller, or other signal processing device to execute code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0131] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features disclosed herein can be implemented, for example, in non-transient logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features can be, for example, any of a variety of integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0132] When implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be the device described herein or a device other than the elements described herein. Because the algorithms that form the basis of the methods or operations of the computer, processor, microprocessor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0133] While embodiments of the present disclosure have been described and illustrated with reference to specific examples, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the appended claims. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A memory system, comprising: At least one memory device; as well as The controller includes an input path and an output path. The input path is used to transmit data input / output requests, i.e., data I / O requests, from an external device to the at least one memory device. The output path is used to transmit responses corresponding to the data I / O requests. The controller selectively connects the output path to the input path to perform a post-packaging repair (PPR) operation.

2. The memory system according to claim 1, wherein, The controller further includes: A request buffer, included in the input path, stores the data I / O request; A response buffer, included in the output path, stores the response; A first multiplexer transmits the output of the response buffer to the external device, or activates a loopback to route the output of the response buffer to the request buffer; and The second multiplexer transmits the data I / O request and one of the outputs of the first multiplexer to the request buffer.

3. The memory system according to claim 2, wherein, The controller further includes a hierarchical structure, the hierarchical structure comprising: The first interface layer performs data communication with the external device; A second interface layer performs data communication with the at least one memory device; and A control logic layer is positioned between the first interface layer and the second interface layer, and controls or manages the operations to be performed through the first interface layer and the second interface layer.

4. The memory system according to claim 3, wherein, The control logic layer includes: Data input / output circuitry, for handling or processing the data input / output requests; After encapsulation, the control circuit is repaired to perform the PPR operation; and Memory management circuitry that checks, tracks, or manages the operating status of the memory system.

5. The memory system according to claim 4, wherein, The post-encapsulation repair control circuit: Determine whether to perform the post-encapsulation repair operation in an idle state; as well as The first multiplexer is controlled to loop back the output of the response buffer to the second multiplexer, and the second multiplexer is controlled to transmit the output of the first multiplexer to the request buffer to initiate the PPR operation.

6. The memory system according to claim 4, wherein, The memory management circuit: Check whether the memory system is in an idle state in order to transmit the state of the memory system to the packaged repair control circuit; as well as A read request for data stored at a first location that needs to be repaired is transmitted to the at least one memory device to perform the PPR operation.

7. The memory system according to claim 6, wherein, The controller: The data is stored in a second location different from the first location in the at least one memory device; and Replace the address of the first position with the address of the second position.

8. The memory system according to claim 3, wherein, The controller further includes volatile memory that stores the input / output results of tasks processed or transmitted in the first interface layer, the second interface layer, and the control logic layer. Each of the request buffer and the response buffer is stored in the volatile memory.

9. The memory system according to claim 3, wherein, The controller further includes a third multiplexer that transmits one of the output of the request buffer and a meaningless signal to the at least one memory device.

10. The memory system according to claim 1, wherein, The controller performs error correction operations on data output from the at least one memory device based on read requests generated by or sent from the memory management circuitry. The controller does not have a dedicated buffer for the PPR operation only.

11. A controller, comprising: At least one processor; as well as At least one memory, The controller performs a post-packaging repair (PPR) operation on at least one memory device, and activates a loopback during the PPR operation to connect the output path to the input path. The input path is used to transmit data input / output requests, i.e., data I / O requests, from external devices to the at least one memory device, and the output path is used to transmit a response corresponding to the data I / O request to the external device.

12. The controller of claim 11, further comprising: A request buffer, included in the input path, stores the data I / O request; A response buffer, included in the output path, stores the response; The first multiplexer transmits the output of the response buffer to the external device, or activates a loopback to route the output of the response buffer to the request buffer; as well as The second multiplexer transmits the data I / O request and one of the outputs of the first multiplexer to the request buffer.

13. The controller of claim 12, further comprising a hierarchical structure, the hierarchical structure comprising: The first interface layer performs data communication with the external device; The second interface layer performs data communication with the at least one memory device; as well as A control logic layer is positioned between the first interface layer and the second interface layer, and controls the operations to be performed through the first interface layer and the second interface layer.

14. The controller according to claim 13, wherein, The control logic layer includes: Data input / output circuitry, for handling or processing the data input / output requests; After encapsulation, the control circuit is repaired to perform the PPR operation; and A memory management circuit that checks, tracks, or manages the operational status of the at least one memory and the at least one processor.

15. The controller according to claim 14, wherein, The post-encapsulation repair control circuit: Determine whether to perform the post-encapsulation repair operation in an idle state; as well as The first multiplexer is controlled to loop back the output of the response buffer to the second multiplexer, and the second multiplexer is controlled to transmit the output of the first multiplexer to the request buffer to initiate the PPR operation.

16. The controller according to claim 14, wherein, The memory management circuit: Check whether the data input / output request has been input from the external device to transmit the check status to the packaged repair control circuit; as well as A read request for data stored at a first location that needs to be repaired is transmitted to the at least one memory device to perform the PPR operation.

17. The controller of claim 13, further comprising volatile memory, the volatile memory storing input / output results of tasks processed or transmitted in the first interface layer, the second interface layer, and the control logic layer, and Each of the request buffer and the response buffer is stored in the volatile memory.

18. The controller of claim 13, further comprising a third multiplexer that transmits one of the output of the request buffer and a meaningless signal to the at least one memory device.

19. A method of operating a memory system, the method comprising, during a post-packaging repair operation (PPR) of at least one memory device included in the memory system, activating a loopback for connecting an output path to an input path. in, The input path is used to transmit data input / output requests, i.e., data I / O requests, from external devices to the at least one memory device, and the output path is used to transmit a response corresponding to the data I / O request to the external device.

20. The method of claim 19, further comprising: Check whether the at least one memory device is in an idle state; Perform a read operation on data stored at a first location in the at least one memory device, wherein the PPR operation is performed at the first location; The data returned through the output path and the input path is stored in a second location of the at least one memory device; as well as Replace the address of the first position with the address of the second position.

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