Multi-protection self-locking circuit

Abstract

The invention relates to the technical field of power supply circuits, in particular to a multi-protection self-locking circuit which comprises a power supply management chip U3, a controllable precision voltage stabilization source U1, an optocoupler U2, a triode Q1, a triode Q2, a triode Q3, a triode Q5, an MOS tube Q4 and a temperature protection switch T1. The voltage detection interface, the current detection interface and the temperature protection switch T1 are used for detecting overvoltage, overcurrent and over-temperature abnormal signals respectively, a positive feedback self-locking loop composed of the triode Q1 and the MOS tube Q4 is triggered, the voltage of the LINE pin of the power management chip U3 is lowered, and a power driving signal is closed to achieve self-locking. According to the invention, accurate detection and reliable locking of three abnormal states are realized, the vicious cycle of repeated restart is prevented, and the circuit has the characteristics of strong anti-interference capability, rapid protection response, low device cost and wide compatibility, can be widely applied to various switching power supply scenes, and ensures long-term reliable operation of a power supply and load equipment.

Description

Technical Field

[0001] This invention relates to the field of power supply circuit technology, and specifically to a multi-protection self-locking circuit. Background Technology

[0002] As a core power supply device in the field of power electronics, AC-DC switching power supplies are widely used in various scenarios such as server racks, industrial control cabinets, and consumer electronics. Their operational stability directly determines the operational reliability of the entire power supply system and the load equipment. In practical applications, AC-DC switching power supplies inevitably encounter abnormal operating states such as overvoltage, overcurrent, and overtemperature. To ensure equipment safety, existing switching power supplies are usually equipped with corresponding protection mechanisms to deal with these abnormal situations.

[0003] However, the protection mechanisms of existing AC-DC switching power supplies have significant flaws. When the power supply enters abnormal states such as overvoltage, overcurrent, or overtemperature, the protection circuit cannot quickly lock the power supply, causing it to fall into a vicious cycle of "protection-restart-re-protection-restart." This vicious cycle not only fails to fundamentally solve the power supply abnormality problem but also causes secondary damage to the power supply itself and the load equipment it powers, and may even exacerbate the fault.

[0004] Specifically, regarding damage to the power supply itself, taking over-temperature abnormalities as an example, a minor over-temperature fault that could originally be recovered simply by shutting down and cooling can, due to the frequent thermal shocks generated during repeated restarts, lead to damage to the core components inside the power supply. In the most severe cases, this can result in the power supply completely burning out, such as the switching transistor exploding, causing irreversible damage to the power supply. Regarding damage to the load equipment, under the voltage and current surges caused by repeated power supply restarts, the load equipment can gradually develop from an initial minor abnormal state of "being able to work but generating a lot of heat" to a complete failure with multiple electronic components damaged and unable to work properly, significantly increasing equipment maintenance costs and downtime losses.

[0005] The hazards of repeated restarts of a single AC-DC switching power supply are particularly prominent in complex systems such as server racks and industrial control cabinets. Subsystems powered by this power supply may experience operational abnormalities due to unstable power supply, which in turn can interfere with other devices in the entire system through internal communication links or control signals, triggering a chain of failures and ultimately paralyzing the entire complex system, causing serious economic losses and production stoppages.

[0006] Therefore, it is evident that existing protection mechanisms for AC-DC switching power supplies under abnormal conditions suffer from insufficient reliability, susceptibility to secondary damage, and systemic failures due to their inability to promptly lock down the power supply and prevent repeated restarts. Consequently, addressing the issue of repeated restarts in AC-DC switching power supplies under abnormal conditions, achieving rapid lock-up after an anomaly, preventing damage to the power supply and load, and preventing systemic failure has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to address the aforementioned shortcomings in the prior art by providing a multi-protection self-locking circuit.

[0008] The objective of this invention is achieved through the following technical solution: a multi-protection self-locking circuit, comprising a power management chip U3, a first input interface, a second input interface, a current detection interface, and a voltage detection interface; The multi-protection self-locking circuit also includes optocoupler U2, transistor Q1, transistor Q2, transistor Q3, MOSFET Q4, transistor Q5, temperature protection switch T1, and controllable precision voltage regulator U1; The power management chip U3 includes a DELAY pin, an ISEN pin, and a LINE pin; the first input interface is connected to the LINE pin; the LINE pin is connected to the collector of transistor Q3; the emitter of transistor Q3 is grounded; one end of the optocoupler U2 switch is connected to the second input interface; the other end of the optocoupler U2 switch is connected to the base of transistor Q3, the collector of transistor Q1, the collector of transistor Q2, and the gate of MOSFET Q4; the source of MOSFET Q4 is grounded; the base of transistor Q1 is connected to the drain of MOSFET Q4 and the emitter of transistor Q1. The transistors are connected as follows: the emitter of transistor Q1 and the emitter of transistor Q2 are connected to the second input interface; the base of transistor Q2 is connected to the cathode of controllable precision voltage regulator U1 and the collector of transistor Q5; the emitter of transistor Q5 and the anode of controllable precision voltage regulator U1 are grounded; the base of transistor Q5 is grounded through temperature protection switch T1; the base of transistor Q5 is connected to the second input interface; the reference terminal of controllable precision voltage regulator U1 is connected to the DELAY pin; the control terminal of optocoupler U2 is connected to the voltage detection interface; and the current detection interface is connected to the ISEN pin.

[0009] The present invention is further configured such that transistors Q1 and Q2 are both PNP transistors; transistors Q3 and Q5 are both NPN transistors; and MOSFET Q4 is an N-type MOSFET.

[0010] The present invention is further configured such that the multi-protection self-locking circuit also includes resistors R1, R2, R3, R5, R7 and R8; The emitter of transistor Q1 is connected to the second input interface via resistor R1; the base of transistor Q1 is connected to the emitter of transistor Q1 via resistor R2; the gate of MOSFET Q4 is grounded via resistor R7; the emitter of transistor Q2 is connected to the second input interface via resistor R3; the emitter of transistor Q2 is connected to the base of transistor Q2 via resistor R5; the base of transistor Q5 is connected to the second input interface via resistors R8 and R3 in sequence; one end of the optocoupler U2 switch is connected to the second input interface via resistor R3.

[0011] The present invention is further configured such that the multi-protection self-locking circuit includes a resistor R9, a Zener diode ZD2, and a resistor R12; the voltage detection interface is connected to the cathode of the Zener diode ZD2 through the resistor R9; the anode of the Zener diode ZD2 is connected to one end of the control terminal of the optocoupler U2; the other end of the control terminal of the optocoupler U2 is grounded; and the anode of the Zener diode ZD2 is grounded through the resistor R12.

[0012] The present invention is further configured such that the multi-protection self-locking circuit also includes a Zener diode ZD1; one end of the resistor R8 is connected to the second input interface through a resistor R3; the other end of the resistor R8 is connected to the base of the transistor Q5; one end of the resistor R8 is connected to the cathode of the Zener diode ZD1; and the anode of the Zener diode ZD1 is grounded.

[0013] The present invention is further configured such that the multi-protection self-locking circuit also includes a capacitor C3; the other end of the resistor R8 is grounded through the capacitor C3.

[0014] The present invention is further configured such that the multi-protection self-locking circuit also includes a resistor R6 and a capacitor C2; the reference terminal of the controllable precision voltage regulator U1 is connected to the DELAY pin through the resistor R6; the reference terminal of the controllable precision voltage regulator U1 is grounded through the capacitor C2.

[0015] The present invention is further configured such that the multi-protection self-locking circuit also includes a resistor R4 and a capacitor C1; the DELAY pin is grounded through the resistor R4; the DELAY pin is grounded through the capacitor C1.

[0016] The present invention is further configured such that the multi-protection self-locking circuit also includes a resistor R15 and a capacitor C9; the current detection interface is connected to the ISEN pin through the resistor R15; the ISEN pin is grounded through the capacitor C9.

[0017] The present invention is further configured such that the multi-protection self-locking circuit includes resistors R10 and R11 and capacitor C4; the LINE pin is grounded through resistor R11; the LINE pin is grounded through capacitor C4; and the first input interface is connected to the LINE pin through resistor R10.

[0018] The beneficial effects of this invention are as follows: This invention uses a positive feedback self-locking circuit composed of transistor Q1 and MOSFET Q4. Once any abnormal state of overvoltage, overcurrent, or overtemperature is detected, it immediately triggers lock-up and maintains that state. Even if the abnormal signal disappears afterward, manual power-off troubleshooting is still required before reset. This completely prevents the vicious cycle of protection-restart-reprotection in existing technologies, avoids performance degradation or explosion of core power supply components due to repeated thermal shocks and stress shocks, and prevents complete failures such as burnt-out input filter circuits and chip breakdowns of downstream components due to continuous voltage or current surges in load equipment. This significantly reduces maintenance costs and downtime losses. Attached Figure Description

[0019] The invention will be further described with reference to the accompanying drawings, but the embodiments in the drawings do not constitute any limitation on the invention. For those skilled in the art, other drawings can be obtained based on the following drawings without creative effort.

[0020] Figure 1 This is the circuit schematic diagram of the present invention; Among them: 1. First input interface; 2. Second input interface; 3. Current detection interface; 4. Voltage detection interface. Detailed Implementation

[0021] The present invention will be further described in conjunction with the following embodiments.

[0022] Depend on Figure 1 As can be seen, the multi-protection self-locking circuit described in this embodiment includes a power management chip U3, a first input interface 1, a second input interface 2, a current detection interface 3, and a voltage detection interface 4; The multi-protection self-locking circuit also includes an optocoupler U2, transistors Q1, Q2, Q3, MOSFETs Q4 and Q5, a temperature protection switch T1, and a controllable precision voltage regulator U1; wherein the power management chip U3 can be model L6599; the controllable precision voltage regulator U1 can be model TL431; the first input interface 1 and the second input interface 2 can be connected to the back end of the rectifier module in the switching power supply; the current detection interface 3 can be connected to the primary side of the transformer in the switching power supply; and the voltage detection interface 4 can be connected to the secondary side of the transformer in the switching power supply.

[0023] The power management chip U3 includes a DELAY pin, an ISEN pin, and a LINE pin; the first input interface 1 is connected to the LINE pin; the LINE pin is connected to the collector of transistor Q3; the emitter of transistor Q3 is grounded; one end of the optocoupler U2 switch is connected to the second input interface 2; the other end of the optocoupler U2 switch is connected to the base of transistor Q3, the collector of transistor Q1, the collector of transistor Q2, and the gate of MOSFET Q4; the source of MOSFET Q4 is grounded; the base of transistor Q1 is connected to the drain of MOSFET Q4 and the emitter of transistor Q1. Connections are made as follows: the emitters of transistors Q1 and Q2 are connected to the second input interface 2; the base of transistor Q2 is connected to the cathode of the controllable precision voltage regulator U1 and the collector of transistor Q5; the emitter of transistor Q5 and the anode of the controllable precision voltage regulator U1 are grounded; the base of transistor Q5 is grounded through the temperature protection switch T1; the base of transistor Q5 is connected to the second input interface 2; the reference terminal of the controllable precision voltage regulator U1 is connected to the DELAY pin; the control terminal of the optocoupler U2 is connected to the voltage detection interface 4; and the current detection interface 3 is connected to the ISEN pin.

[0024] Specifically, the multi-protection self-locking circuit described in this embodiment ensures that when the switching power supply is working normally, all protection mechanisms of the circuit are not triggered, and the power supply outputs normally. At this time, voltage detection interface 4 did not detect overvoltage, Zener diode ZD2 was not broken down, there was no current at the control terminal of optocoupler U2, and the switch terminal of optocoupler U2 was cut off; current detection interface 3 did not detect overcurrent, there was no abnormal signal at the ISEN pin of power management chip U3, the internal 150uA current source of power management chip U3 was not activated, the voltage at the DELAY pin was lower than 2.5V, and the controllable precision voltage regulator U1 was cut off; the temperature did not reach the threshold, the temperature protection switch T1 remained normally closed, the base of transistor Q5 was grounded through the temperature protection switch T1, the base potential of transistor Q5 was low, and transistor Q5 was cut off.

[0025] At this time, the gate of MOSFET Q4 is grounded through resistor R7, and MOSFET Q4 is cut off; the base of transistor Q1 is at the same potential as the emitter of transistor Q1 through resistor R2, and transistor Q1 is cut off; the base of transistor Q2 is at the same potential as the emitter of transistor Q2 through resistor R5, and transistor Q2 is cut off; there is no high potential drive at the base of transistor Q3, and transistor Q3 is cut off; the LINE pin of power management chip U3 is powered through the first input interface 1, and the voltage after voltage division by resistors R10 and R11 is greater than 1.24V, power management chip U3 outputs drive signal normally, and the power supply works stably.

[0026] When voltage detection interface 4 detects that the secondary output voltage of the transformer in the switching power supply exceeds the limit, the Zener diode ZD2 breaks down in reverse. After the Zener diode ZD2 breaks down, the control terminal of the optocoupler U2 is energized, and the switching terminal of the optocoupler U2 is turned on. The voltage of the second input interface 2 is applied to the base of transistor Q3, the collector of transistor Q1, and the gate of MOSFET Q4 through the switching terminal of optocoupler U2. The gate of MOSFET Q4 is connected to a high potential, and after MOSFET Q4 is turned on, it pulls the base of transistor Q1 to ground. The base voltage of transistor Q1 is less than the emitter voltage of transistor Q1, causing transistor Q1 to turn on. After transistor Q1 is turned on, the second input interface 2 continuously applies power to the gate of MOSFET Q4 through transistor Q1, forming a positive feedback self-lock. Even if the Zener diode ZD2 recovers and the optocoupler U2 is turned off, MOSFET Q4 remains on. At the same time, the base of transistor Q3 is connected to a high potential. After transistor Q3 is turned on, it pulls the LINE pin of power management chip U3 to ground, making the voltage of the LINE pin of power management chip U3 less than 1.24V. When power management chip U3 detects that the LINE pin voltage is below the standard, it immediately shuts off the drive signal, and the power supply stops outputting, realizing overvoltage self-lock.

[0027] When the current detection interface 3 detects that the primary current of the transformer in the switching power supply exceeds the limit, the ISEN pin of the power management chip U3 receives an overcurrent signal; the power management chip U3 internally starts a 150uA current source to charge the external capacitor C1 connected to the DELAY pin; when the voltage at the DELAY pin is charged to 2.5V, the reference voltage of the controllable precision voltage regulator U1 reaches the standard, and the cathode of the controllable precision voltage regulator U1 is pulled low and turned on; after the cathode of the controllable precision voltage regulator U1 is pulled low, the base voltage of transistor Q2 is less than the emitter voltage of the transistor, and transistor Q2 turns on; after transistor Q2 turns on, the second input interface 2 is connected to the gate of MOSFET Q4 through transistor Q2, and MOSFET Q4 turns on; after MOSFET Q4 turns on, it will... The base of transistor Q1 is pulled to ground; the base voltage of transistor Q1 is less than the emitter voltage of transistor Q1, causing transistor Q1 to conduct; after transistor Q1 conducts, the second input interface 2 continuously applies power to the gate of MOSFET Q4 through transistor Q1, forming a positive feedback self-locking. Even if the Zener diode ZD2 recovers and the optocoupler U2 is turned off, MOSFET Q4 remains on; at the same time, the base of transistor Q3 is connected to a high potential, and after transistor Q3 conducts, it pulls the LINE pin of power management chip U3 to ground, making the voltage of the LINE pin of power management chip U3 less than 1.24V; when power management chip U3 detects that the LINE pin voltage is below the standard, it immediately shuts off the drive signal, and the power supply stops outputting, realizing overcurrent self-locking.

[0028] When the ambient temperature around temperature protection switch T1 reaches 100℃, the bimetallic reed of temperature protection switch T1 actuates, and temperature protection switch T1 is disconnected. Before temperature protection switch T1 is disconnected, the base of transistor Q5 is grounded through temperature protection switch T1, and transistor Q5 is cut off. After temperature protection switch T1 is disconnected, the base of transistor Q5 is connected to the second input interface 2 through resistors R8 and R3, and transistor Q5 is turned on. After transistor Q5 is turned on, the base of transistor Q2 is grounded through the collector of transistor Q5, and the base voltage of transistor Q2 is less than the emitter voltage of transistor Q2, and transistor Q2 is turned on. After transistor Q2 is turned on, the second input interface 2 is connected to the gate of MOSFET Q4 through transistor Q2, and MOSFET Q4 is turned on. After MOSFET Q4 is turned on, it pulls the base of transistor Q1 to ground. The base voltage of transistor Q1 is less than the emitter voltage of transistor Q1, causing transistor Q1 to conduct. After transistor Q1 is turned on, the second input interface 2 is continuously connected to the gate of MOSFET Q4 through transistor Q1, forming a positive feedback self-lock. Even if the Zener diode ZD2 recovers and the optocoupler U2 is turned off, MOSFET Q4 remains on. At the same time, the base of transistor Q3 is connected to a high potential. After transistor Q3 is turned on, it pulls the LINE pin of power management chip U3 to ground, making the voltage of the LINE pin of power management chip U3 less than 1.24V. When power management chip U3 detects that the LINE pin voltage is not up to standard, it immediately shuts off the drive signal, and the power supply stops outputting, achieving over-temperature self-lock.

[0029] In this embodiment, a multi-protection self-locking circuit is described, wherein transistors Q1 and Q2 are both PNP transistors; transistors Q3 and Q5 are both NPN transistors; and MOSFET Q4 is an N-type MOSFET.

[0030] The multi-protection self-locking circuit described in this embodiment further includes resistors R1, R2, R3, R5, R7, and R8. The emitter of transistor Q1 is connected to the second input interface 2 via resistor R1; the base of transistor Q1 is connected to the emitter of transistor Q1 via resistor R2; the gate of MOSFET Q4 is grounded via resistor R7; the emitter of transistor Q2 is connected to the second input interface 2 via resistor R3; the emitter of transistor Q2 is connected to the base of transistor Q2 via resistor R5; the base of transistor Q5 is connected to the second input interface 2 via resistors R8 and R3 in sequence; one end of the optocoupler U2 switch is connected to the second input interface 2 via resistor R3.

[0031] Specifically, resistor R1 acts as the emitter current limiting resistor for PNP transistor Q1, limiting the emitter current when Q1 is turned on to prevent excessive current from burning out Q1; resistor R2 provides a bias path for the base of transistor Q1, ensuring that the base and emitter are at the same potential when Q1 is in a static state, thus ensuring that Q1 is turned off, while also suppressing sudden changes in the base potential during dynamic processes; resistor R7 provides a ground discharge path for the gate of N-type MOSFET Q4, pulling the gate potential of MOSFET Q4 low to ground when in a static state, ensuring that MOSFET Q4 is turned off. To prevent false turn-on caused by a floating gate; resistor R3 serves as a common current-limiting resistor, providing a unified power supply path for the emitter of transistor Q2, the base of transistor Q5, and the switching terminal of optocoupler U2, limiting the current in each branch within a safe range; resistor R5 provides bias to the base of PNP transistor Q2, ensuring that the base and emitter of transistor Q2 are at the same potential when in static state, thus ensuring that transistor Q2 is cut off; resistor R8 provides current limiting to the base of NPN transistor Q5, limiting the current flowing into the base of transistor Q5 and preventing transistor Q5 from being damaged due to excessive base current.

[0032] The multi-protection self-locking circuit described in this embodiment further includes a resistor R9, a Zener diode ZD2, and a resistor R12; the voltage detection interface 4 is connected to the cathode of the Zener diode ZD2 through resistor R9; the anode of the Zener diode ZD2 is connected to one end of the control terminal of the optocoupler U2; the other end of the control terminal of the optocoupler U2 is grounded; and the anode of the Zener diode ZD2 is grounded through resistor R12.

[0033] Specifically, resistor R9 is connected in series between voltage detection interface 4 and the cathode of Zener diode ZD2 to limit the current flowing through Zener diode ZD2 and prevent it from being damaged by overcurrent breakdown. Zener diode ZD2 has a precise threshold for overvoltage detection. When the output voltage detected by voltage detection interface 4 exceeds the reverse breakdown voltage of Zener diode ZD2, Zener diode ZD2 conducts in reverse; otherwise, it remains cut off. Resistor R12 is connected in parallel between the control terminal of optocoupler U2 and ground to form a current discharge path. This ensures that there is no residual current at the control terminal of optocoupler U2 when Zener diode ZD2 has not broken down, and also limits the current flowing into the control terminal of optocoupler U2 when Zener diode ZD2 is conducting, thus protecting optocoupler U2.

[0034] The multi-protection self-locking circuit described in this embodiment further includes a Zener diode ZD1; one end of the resistor R8 is connected to the second input interface 2 via a resistor R3; the other end of the resistor R8 is connected to the base of the transistor Q5; one end of the resistor R8 is connected to the cathode of the Zener diode ZD1; and the anode of the Zener diode ZD1 is grounded.

[0035] Specifically, the cathode of Zener diode ZD1 is connected to the junction of resistor R8 and resistor R3, while the anode of Zener diode ZD1 is grounded. Their function is to clamp the potential of this node. When an abnormally high voltage (such as a surge or spike voltage) occurs in the voltage supplied by the second input interface 2, Zener diode ZD1 breaks down in reverse, clamping the node potential at the Zener diode ZD1's regulated voltage value, preventing the abnormally high voltage from being conducted to the base of transistor Q5 through resistor R8.

[0036] This embodiment describes a multi-protection self-locking circuit, which further includes a capacitor C3; the other end of the resistor R8 is grounded through capacitor C3. Specifically, capacitor C3 is connected in parallel between the base of transistor Q5 and ground, and is a high-frequency filter capacitor. The over-temperature detection circuit may contain high-frequency noise such as power supply ripple and electromagnetic interference. This noise can cause instantaneous fluctuations in the base potential of transistor Q5. Capacitor C3 rapidly absorbs the noise energy through charging and discharging, stabilizing the base potential of transistor Q5.

[0037] The multi-protection self-locking circuit described in this embodiment further includes a resistor R6 and a capacitor C2; the reference terminal of the controllable precision voltage regulator U1 is connected to the DELAY pin through the resistor R6; the reference terminal of the controllable precision voltage regulator U1 is grounded through the capacitor C2.

[0038] Specifically, resistor R6 is connected in series between the reference terminal of the controllable precision voltage regulator U1 and the DELAY pin of the power management chip U3 to limit the current between the DELAY pin and the reference terminal of the controllable precision voltage regulator U1, preventing excessive current from damaging the controllable precision voltage regulator U1 or the power management chip U3; capacitor C2 is connected in parallel between the reference terminal of the controllable precision voltage regulator U1 and ground to filter voltage noise transmitted from the DELAY pin to the reference terminal of the controllable precision voltage regulator U1, stabilize the input voltage of the reference terminal of the controllable precision voltage regulator U1, and prevent noise from causing the controllable precision voltage regulator U1 to make incorrect judgments.

[0039] The multi-protection self-locking circuit described in this embodiment further includes a resistor R4 and a capacitor C1; the DELAY pin is grounded through the resistor R4; the DELAY pin is grounded through the capacitor C1.

[0040] Specifically, resistor R4 is connected in parallel between the DELAY pin and ground, serving as the bleeder resistor for the external capacitor C1 connected to the DELAY pin. When the overcurrent signal disappears, capacitor C1 discharges rapidly through resistor R4, restoring the voltage of the DELAY pin to a low potential, preparing for the next overcurrent detection. Capacitor C1 is also a delay capacitor for the DELAY pin. The 150uA current source inside the power management chip U3 achieves overcurrent delay by charging capacitor C1. Subsequent protection will only be triggered when capacitor C1 is charged to 2.5V at the DELAY pin, thus avoiding false protection caused by instantaneous overcurrent.

[0041] The multi-protection self-locking circuit described in this embodiment further includes a resistor R15 and a capacitor C9; the current detection interface 3 is connected to the ISEN pin through the resistor R15; the ISEN pin is grounded through the capacitor C9.

[0042] Specifically, resistor R15 is connected in series between current detection interface 3 and ISEN pin to limit the current flowing into ISEN pin and prevent large current in the current detection signal from impacting the internal circuitry of power management chip U3; capacitor C9 is connected in parallel between ISEN pin and ground to filter high-frequency noise and ripple in the current detection signal, making the current signal received by ISEN pin smoother and more stable, and preventing noise from causing power management chip U3 to misjudge overcurrent.

[0043] The multi-protection self-locking circuit described in this embodiment further includes resistors R10 and R11 and capacitor C4; the LINE pin is grounded through resistor R11; the LINE pin is grounded through capacitor C4; the first input interface 1 is connected to the LINE pin through resistor R10.

[0044] Specifically, resistors R10 and R11 form a voltage divider circuit, connected in series between the first input interface 1 and ground. The LINE pin is connected to the voltage divider point of resistors R10 and R11. The static voltage of the LINE pin is set by the voltage divider to ensure that the LINE pin voltage is stable above 1.24V during normal operation, which meets the conditions for normal operation of the power management chip U3. Capacitor C4 is connected in parallel between the LINE pin and ground as a filter capacitor to filter out high-frequency noise and fluctuations in the LINE pin voltage, preventing noise from causing the LINE pin voltage to momentarily drop below 1.24V, which would cause the power management chip U3 to shut down erroneously.

[0045] This embodiment uses a positive feedback self-locking circuit composed of transistor Q1 and MOSFET Q4. Once any abnormal state of overvoltage, overcurrent, or overtemperature is detected, it immediately triggers lock-up and maintains that state. Even if the abnormal signal disappears afterward, manual power-off troubleshooting is still required before reset. This completely prevents the vicious cycle of protection-restart-reprotection in existing technologies, avoids performance degradation or explosion of core power supply components due to repeated thermal and stress shocks, and prevents complete failures such as input filter circuit burnout or downstream chip breakdown due to continuous voltage or current surges in load equipment. This significantly reduces maintenance costs and downtime losses.

[0046] This embodiment integrates three protection mechanisms: overvoltage, overcurrent, and overtemperature, covering core abnormal power supply operation scenarios. Overvoltage protection uses a Zener diode ZD2 to set a precise threshold (e.g., 12V) and optocoupler U2 to isolate the transmitted signal, avoiding high-voltage interference. Overcurrent protection utilizes the built-in 150uA current source of the power management chip U3 and the delayed charging design of capacitor C1 on the DELAY pin to accurately distinguish between instantaneous inrush current and continuous overcurrent, preventing false triggering. Overtemperature protection uses a mechanical temperature switch T1, which has a fast response speed, is more stable than electronic temperature measurement, and is unaffected by electromagnetic interference. The three protection mechanisms are independent of each other but share a self-locking circuit, achieving comprehensive protection by locking the entire device after an abnormality occurs in one area.

[0047] This embodiment of the circuit ensures the accuracy of the protection logic through multiple anti-interference designs: capacitors C2, C3, C4, and C9 filter signal noise to avoid false triggering caused by high-frequency interference; Zener diode ZD1 clamps abnormal high voltage to protect the over-temperature detection branch devices; current-limiting resistors R1, R3, R7, and R9 limit the operating current of the devices to prevent overcurrent damage; optocoupler U2 provides electrical isolation between the primary and secondary sides to prevent high-voltage conduction interference to the main control circuit. These multiple designs enable the circuit to operate stably even in complex environments such as power supply ripple, electromagnetic interference, and voltage surges, achieving a high accuracy rate in protection triggering.

[0048] This embodiment features a simple structure, low cost, strong compatibility and practicality. The circuit uses general-purpose components, which are low-cost and easy to procure, eliminating the need for dedicated protection chips. The core protection function is implemented through only three pins of the power management chip U3, without the need for additional chip pin expansion, simplifying chip packaging and circuit layout. The first input interface 1 and the second input interface 2 can be directly connected to the back end of the switching power supply rectifier module. The current detection interface 3 and the voltage detection interface 4 are adapted to the primary and secondary sides of the transformer, respectively, making it suitable for various AC-DC switching power supplies with wide compatibility, easy for mass production and technology implementation.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A multi-protection self-locking circuit, characterized in that: It includes a power management chip U3, a first input interface (1), a second input interface (2), a current detection interface (3), and a voltage detection interface (4); The multi-protection self-locking circuit also includes optocoupler U2, transistor Q1, transistor Q2, transistor Q3, MOSFET Q4, transistor Q5, temperature protection switch T1, and controllable precision voltage regulator U1; The power management chip U3 includes a DELAY pin, an ISEN pin, and a LINE pin; the first input interface (1) is connected to the LINE pin; the LINE pin is connected to the collector of transistor Q3; the emitter of transistor Q3 is grounded; one end of the optocoupler U2 switch is connected to the second input interface (2); the other end of the optocoupler U2 switch is connected to the base of transistor Q3, the collector of transistor Q1, the collector of transistor Q2, and the gate of MOSFET Q4; the source of MOSFET Q4 is grounded; the base of transistor Q1 is connected to the drain of MOSFET Q4 and the emitter of transistor Q1. The emitters of transistors Q1 and Q2 are connected to the second input interface (2); the base of transistor Q2 is connected to the cathode of the controllable precision voltage regulator U1 and the collector of transistor Q5; the emitter of transistor Q5 and the anode of the controllable precision voltage regulator U1 are grounded; the base of transistor Q5 is grounded through the temperature protection switch T1; the base of transistor Q5 is connected to the second input interface (2); the reference terminal of the controllable precision voltage regulator U1 is connected to the DELAY pin; the control terminal of the optocoupler U2 is connected to the voltage detection interface (4); and the current detection interface (3) is connected to the ISEN pin.

2. The multi-protection self-locking circuit according to claim 1, characterized in that: Transistors Q1 and Q2 are both PNP transistors; transistors Q3 and Q5 are both NPN transistors; and MOSFET Q4 is an N-type MOSFET.

3. The multi-protection self-locking circuit according to claim 1, characterized in that: The multi-protection self-locking circuit also includes resistors R1, R2, R3, R5, R7, and R8. The emitter of transistor Q1 is connected to the second input interface (2) through resistor R1; the base of transistor Q1 is connected to the emitter of transistor Q1 through resistor R2; the gate of MOSFET Q4 is grounded through resistor R7; the emitter of transistor Q2 is connected to the second input interface (2) through resistor R3; the emitter of transistor Q2 is connected to the base of transistor Q2 through resistor R5; the base of transistor Q5 is connected to the second input interface (2) through resistors R8 and R3 in sequence; one end of the optocoupler U2 switch is connected to the second input interface (2) through resistor R3.

4. The multi-protection self-locking circuit according to claim 3, characterized in that: The multi-protection self-locking circuit also includes resistor R9, Zener diode ZD2 and resistor R12; the voltage detection interface (4) is connected to the cathode of Zener diode ZD2 through resistor R9; the anode of Zener diode ZD2 is connected to one end of the control terminal of optocoupler U2; the other end of the control terminal of optocoupler U2 is grounded; the anode of Zener diode ZD2 is grounded through resistor R12.

5. The multi-protection self-locking circuit according to claim 3, characterized in that: The multi-protection self-locking circuit also includes a Zener diode ZD1; one end of the resistor R8 is connected to the second input interface (2) through a resistor R3; the other end of the resistor R8 is connected to the base of the transistor Q5; one end of the resistor R8 is connected to the cathode of the Zener diode ZD1; and the anode of the Zener diode ZD1 is grounded.

6. The multi-protection self-locking circuit according to claim 5, characterized in that: The multi-protection self-locking circuit also includes capacitor C3; the other end of resistor R8 is grounded through capacitor C3.

7. The multi-protection self-locking circuit according to claim 3, characterized in that: The multi-protection self-locking circuit also includes a resistor R6 and a capacitor C2; the reference terminal of the controllable precision voltage regulator U1 is connected to the DELAY pin through the resistor R6; the reference terminal of the controllable precision voltage regulator U1 is grounded through the capacitor C2.

8. A multi-protection self-locking circuit according to claim 7, characterized in that: The multi-protection self-locking circuit also includes a resistor R4 and a capacitor C1; the DELAY pin is grounded through resistor R4; the DELAY pin is grounded through capacitor C1.

9. A multi-protection self-locking circuit according to claim 3, characterized in that: The multi-protection self-locking circuit also includes a resistor R15 and a capacitor C9; the current detection interface (3) is connected to the ISEN pin through the resistor R15; the ISEN pin is grounded through the capacitor C9.

10. A multi-protection self-locking circuit according to claim 3, characterized in that: The multi-protection self-locking circuit also includes resistors R10 and R11 and capacitor C4; the LINE pin is grounded through resistor R11; the LINE pin is grounded through capacitor C4; the first input interface (1) is connected to the LINE pin through resistor R10.

Images