Household appliance communication fault positioning method and device, equipment and storage medium

Abstract

The invention relates to a household appliance communication fault positioning method and device, equipment and a storage medium. The method comprises the steps that after a main control board detects communication abnormity, communication fault detection is triggered and executed; detecting the time delay and packet loss rate of the current communication link section from the current communication link section of the main control board; based on the time delay and the packet loss rate, judging whether the current communication link section has a fault or not; if yes, outputting a fault detection result; and if not, based on the detection result and the topology table representing the connection logic relation of all levels of board cards of the communication link, fault detection is carried out on the next communication link section by taking the current link section as a relay until a final detection conclusion is obtained. Compared with a mode of troubleshooting through an external tool or manual short circuit in the prior art, the scheme of the application has the positive effects of realizing automatic diagnosis and remarkably improving the detection efficiency.

Description

Technical Field

[0001] This application relates to the field of household appliance technology, and in particular to a method, apparatus, device and storage medium for locating communication faults in household appliances. Background Technology

[0002] With the rapid development of smart home technology, smart refrigerators, air conditioners, and other home appliances are gradually evolving towards multi-module collaborative operation. To achieve orderly control and data interaction among various functional modules, the ABC cascaded motherboard architecture is widely used in these home appliances. This architecture splits the control functions of the home appliance into three independent motherboards: A, B, and C. Data transmission between the motherboards at each level is conducted via serial ports. In this data transmission mode, since data needs to be transmitted step by step through the ABC link, once a communication interruption or data transmission error occurs, the fault point may involve any level of the motherboard itself, the serial port line between two motherboards, or the relay abnormality of the intermediate node, which will make fault location difficult.

[0003] In the existing technology, troubleshooting serial communication faults is carried out by using external tools (such as logic analyzers) or by manually shorting the circuit. This method is cumbersome, time-consuming, and cannot be embedded in the system's self-test process. Summary of the Invention

[0004] This application provides a method, apparatus, device, and storage medium for locating communication faults in home appliances, in order to solve the problems of cumbersome operation and long time consumption in the prior art of troubleshooting serial communication faults by using external tools (such as logic analyzers) or manual short-circuiting.

[0005] In a first aspect, this application provides a method for locating communication faults in home appliances, the method being applied to a main control board in a communication link, the method comprising: After the main control board detects a communication anomaly, it triggers the execution of communication fault detection. Starting from the current communication link segment where the main control board is located, detect the latency and packet loss rate of the current communication link segment; Based on the aforementioned latency and packet loss rate, determine whether there is a fault in the current communication link segment; If so, output the fault detection result; If not, based on the detection results and the topology table characterizing the connection logic of each level of the communication link, the current link segment is used as a relay to perform fault detection on the next communication link segment until the final detection conclusion is obtained.

[0006] In one optional implementation, the step of detecting the latency and packet loss rate of the current communication link segment, starting from the current communication link segment where the main control board is located, includes: A state switching command is sent to the first target board on the current communication link to switch the first target board to loopback mode. In loopback mode, the first target board short-circuits the RX chip serial port and the TX chip serial port through an analog switch to disconnect the external link and enter a self-transmitting and self-receiving state. Send a probe frame to the first target board, wherein the probe frame carries a staining sequence and a sending timestamp. Receive the return frame sent by the first target board after receiving the probe frame in loopback mode; Based on the information carried in the returned frame, the latency and packet loss rate of the current communication link segment are calculated.

[0007] In one optional implementation, calculating the latency and packet loss rate of the current communication link segment based on the information carried by the returned frame includes: The main control board parses the returned frame, calculates the round-trip delay ΔT based on the sending timestamp and the current receiving timestamp, and verifies the integrity of the coloring sequence to obtain the packet loss rate L.

[0008] In one optional implementation, determining whether the current communication link segment is faulty based on the latency and packet loss rate includes: Determine whether the delay ΔT and packet loss rate L are both within the normal range. If so, determine that the serial port of the TX chip on the main control board, the communication link between the main control board and the first target board, and the serial port of the RX chip on the first target board are all without faults.

[0009] In one optional implementation, the topology table, based on the detection results and characterizing the logical connections between the various levels of the communication link boards, performs fault detection on the next communication link segment using the current link segment as a relay, thereby obtaining the final detection conclusion, including: If the current link segment is determined to be fault-free, the main control board will use the first target board on the current link as an intermediate board to relay the loopback command to the second target board of the next communication link segment, so that the second target board enters the loopback mode; at this time, the intermediate board is in normal transmit and receive mode. The main control board generates a probe frame for the second target board, which is then sent to the second target board via the intermediate board. Receive the return frame sent by the second target board, and calculate the latency and packet loss rate of the current communication link segment where the second target board is located; Based on the latency and packet loss rate, it is determined whether the current communication link segment where the second target board is located is faulty.

[0010] In one optional implementation, determining whether the current communication link segment is faulty based on the latency and packet loss rate includes: If the latency and / or packet loss rate are not within the normal range, it is determined that the serial port of the intermediate board TX chip is faulty, or the communication link is faulty.

[0011] In one optional implementation, the content structure of the probe frame includes: a frame header for characterizing the probe frame category identifier; a staining sequence field; a target board unique identifier ID; a transmission timestamp field; and a checksum field.

[0012] Secondly, this application provides a communication fault location device for home appliances, the device being applied to a main control board in a communication link, the device comprising: The first detection module is used to trigger communication fault detection after detecting a communication anomaly. The second detection module is used to detect the latency and packet loss rate of the current communication link segment, starting from the current communication link segment where the main control board is located. The judgment module is used to determine whether there is a fault in the current communication link segment based on the latency and packet loss rate; The output module is used to output the fault detection results; The third detection module is used to perform fault detection on the next communication link segment, using the current link segment as a relay, based on the detection results and the topology table characterizing the connection logic relationship of each level of the communication link, until the final detection conclusion is obtained.

[0013] Thirdly, this application provides a communication fault location device for home appliances, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, communication interface, and memory communicate with each other through the communication bus. Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the steps of the method as described in any embodiment of the first aspect.

[0014] Fourthly, this application also provides a computer-readable storage medium, characterized in that it stores a computer program thereon, which, when executed by a processor, implements the steps of the method described in any embodiment of the first aspect.

[0015] Compared with the prior art, the technical solution provided in this application has the following advantages: In the method provided in this application, after the main control board of the communication link detects a communication anomaly, it triggers communication fault detection. Then, the main control board begins to perform communication fault detection and localization, starting from the communication link segment where the main control board is currently located, detecting the latency and packet loss rate of the current communication link segment. Based on the detected latency and packet loss rate, the main control board determines whether the current communication link segment has a fault. If a fault is found, the fault detection result is directly output. If the detected current communication link segment has no fault, the main control board, based on the detection result and the topology table representing the logical connection relationship of each level of the communication link, uses the current link segment as a relay to perform fault detection on the next communication link segment, thereby obtaining the final detection and localization conclusion. In this application embodiment, the fault detection and localization of the communication link is embedded in the system self-test process, and the main control board controls the completion of fault localization for the entire communication link segment. Compared with the prior art method of troubleshooting through external tools or manual short-circuiting, this method has the positive effect of achieving automatic diagnosis and significantly improving detection efficiency. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 A flowchart illustrating a method for locating communication faults in home appliances, provided as an embodiment of this application; Figure 2 A schematic diagram of a communication link for a home appliance provided in an embodiment of this application; Figure 3 This is a schematic diagram of a process for detecting the latency and packet loss rate of the current communication link segment, provided in an embodiment of this application. Figure 4 A flowchart illustrating fault location of a BC communication link segment is provided for a specific embodiment of this application; Figure 5This is a schematic diagram of the structure of a communication fault location device for home appliances provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a communication fault location device for home appliances provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0022] Currently, home appliances (such as smart refrigerators, air conditioners, and other multi-module systems) often adopt an ABC cascaded motherboard architecture, exchanging data via serial ports. Troubleshooting communication faults in this type of architecture presents several challenges. First, existing technologies mostly employ end-to-end communication detection or single-level heartbeat mechanisms. When communication between the main control board and the terminal board is interrupted, it's impossible to determine whether the fault lies with an intermediate board or a broken link, lacking independent testing capabilities for intermediate nodes, leading to a "chain-like blind spot" in fault location. Second, traditional methods rely on packet capture with logic analyzers or manual short-circuit testing, which are cumbersome and cannot be integrated into the system's self-test process. Furthermore, complex algorithm solutions require additional hardware support, making them difficult to run in real-time on resource-constrained home appliance motherboards.

[0023] In summary, existing troubleshooting and handling solutions for serial communication faults in ABC cascaded motherboard architectures of home appliances cannot simultaneously meet the requirements of low cost, low complexity, and high adaptability, and are difficult to effectively solve the troubleshooting problems in practical applications. Based on this, this application provides a method, apparatus, device, and storage medium for locating communication faults in home appliances, which can embed the fault location and detection of communication links into an automatic detection system to improve detection efficiency.

[0024] The present application solution will be described in detail below through specific embodiments.

[0025] Figure 1A flowchart illustrating a method for locating communication faults in home appliances provided in this application embodiment; see reference. Figure 1 As shown, the method includes the following steps S10-S40: S10. After the main control board detects a communication abnormality, it triggers the execution of communication fault detection.

[0026] Figure 2 This is a schematic diagram of a communication link for a home appliance provided in an embodiment of this application; see reference. Figure 2 As shown, the communication link system in this embodiment includes at least three motherboards A, B, and C. The three motherboards are cascaded sequentially through the TX→RX chip serial port to form an ABC cascaded motherboard architecture. In the actual embodiment, board A serves as the main control board, board B serves as the intermediate board, and board C serves as the terminal board, exchanging data through the serial port.

[0027] The aforementioned main control board, as the core circuit board, is the control center of the system. It is used to coordinate the working status of various functional boards (such as the B board and other motherboards at various levels), issue various operation commands, receive and parse feedback data from each board, and execute result judgment and / or result output logic such as link detection and status diagnosis.

[0028] In this embodiment of the application, after the main control board (A board) detects an abnormality in the communication link ABC, it directly triggers the fault detection and location process, thereby directly embedding the fault detection and location process provided in this embodiment of the application into the entire automatic process of the system.

[0029] S20. Starting from the current communication link segment where the main control board is located, detect the latency and packet loss rate of the current communication link segment.

[0030] The main control board A first checks whether there is a fault in the communication link between the AB segment. The cause of the fault may be a serial port fault of the TX chip on board A, a fault in the AB link, or a serial port fault of the RX chip on board B.

[0031] S30. Based on the latency and packet loss rate, determine whether there is a fault in the current communication link segment.

[0032] If the packet loss rate and latency detected by the main control board are within the normal range, it indicates that there is no fault in the current communication link, that is, there is no fault in the serial port of the main control board TX chip, the link between the main control board and the target board, and the serial port of the target board RX chip.

[0033] S40. If there is a fault in the current communication link segment, output the fault detection result.

[0034] S50. If there is no fault in the current communication link segment, then based on the detection results and the topology table representing the connection logic relationship of each level of the communication link, the current link segment is used as a relay to perform fault detection on the next communication link segment, and then the final detection and location conclusion is obtained.

[0035] The main control board in this embodiment integrates a loopback control module, a probe frame generation module, a return frame verification module, and a fault location algorithm unit to implement the steps in the above method.

[0036] Figure 3 This application provides a schematic flowchart for detecting the latency and packet loss rate of the current communication link segment; see also... Figure 3 As shown, in one embodiment of this application, step S20 above, starting from the communication link segment where the main control board is currently located, detects the latency and packet loss rate of the current communication link segment, specifically including the following steps S201-S204: S201. The main control board sends a state switching command to the first target board on the current communication link, so that the first target board switches to loopback mode. In loopback mode, the first target board short-circuits the RX chip serial port and the TX chip serial port through an analog switch, disconnects the external link, and enters the self-transmitting and self-receiving state.

[0037] In this embodiment, a loop control module is set on the main control board. After the main control board starts the fault location process, it first sends a state switching command to the first target board. After receiving the command, the first target board switches to loop mode.

[0038] In one specific embodiment of this application, the loopback control module of the main control board triggers the first target board to enter the loopback mode by sending a state switching command 0xFE+board ID+0x01 (indicating loopback enable); or by sending a state switching command: 0x01+board ID+0x00 (indicating normal return) to trigger the first target board to enter the normal return mode.

[0039] In specific application examples, intermediate boards and terminal boards can be equipped with configurable loopback modules via analog circuits to receive state switching control from the main control board. For example, a low-cost analog switch (such as CD4066) can be added to the front end of the serial transceiver of each board, controlled by GPIO. In normal mode, the serial port of the board's RX chip is connected to the external TX terminal, and the serial port of the TX chip is connected to the external RX terminal. In loopback mode, the serial ports of the board's RX and TX chips are internally shorted, disconnecting the external link and achieving self-transmission and reception.

[0040] S202. Send a probe frame to the first target board, wherein the probe frame carries a staining sequence and a sending timestamp.

[0041] In one specific embodiment of this application, the content structure of the probe frame includes: a frame header, used to characterize the probe frame category identifier; a staining sequence field; a target board unique identifier ID; a transmission timestamp field; and a checksum field.

[0042] In one specific embodiment, the structure of the probe frame is shown in Table 1 below:

[0043] Table 1 S203. Receive the return frame sent by the first target board after receiving the probe frame in loopback mode.

[0044] The returned frame carries the aforementioned coloring sequence and a sending timestamp. In the event of packet loss, the coloring sequence may be incomplete.

[0045] S204. Based on the information carried in the returned frame, calculate the latency and packet loss rate of the current communication link segment.

[0046] In a specific embodiment of this application, step S204, calculating the latency and packet loss rate of the current communication link segment based on the information carried by the returned frame, specifically includes the following step A10: Step A10: The main control board parses the returned frame, calculates the round-trip delay ΔT based on the sending timestamp and the current receiving timestamp, verifies the integrity of the coloring sequence, and obtains the packet loss rate L.

[0047] After receiving the return frame, the main control board extracts the coloring sequence and timestamp Tr of the return frame, verifies the integrity of the coloring sequence, calculates the packet loss rate L, and calculates the round-trip delay of the communication link segment: ΔT = Tr Ts.

[0048] After obtaining the round-trip delay ΔT and packet loss rate L, a fault decision is made based on these parameters and the topology table. For example, the decision-making process includes: if the coloring sequence of board A is within the normal range and ΔT = 2.1ms is calculated (the theoretical value is set to 1.0ms), then the AB segment is judged to be abnormal, and the conclusion "AB link impedance is abnormal" is output.

[0049] In another embodiment of this application, step S30 above, determining whether the current communication link segment is faulty based on the latency and packet loss rate, specifically includes the following step B10: Step B10: Determine whether the delay ΔT and packet loss rate L are both within the normal range. If so, determine that the serial port of the main control board TX chip, the communication link between the main control board and the target board, and the serial port of the first target board RX chip are all without faults.

[0050] In one specific embodiment of this application, if the main control board determines that the current AB communication link segment is normal, it continues to detect the communication status of the BC communication link segment. During the detection of the BC communication link, since the initial assessment indicates that the internal condition of board B is normal, the main control board controls board B to be in normal forwarding mode, using board B as a relay node to detect the BC segment. In this case, because the AB communication link segment is already ensured to be normal, the end-to-end AC communication link segment is then tested. If the test fails, the fault can be located in the BC communication link segment.

[0051] Furthermore, in step S50 above, based on the detection results and the topology table characterizing the connection logic of each level of the communication link, the current link segment is used as a relay to perform fault detection on the next communication link segment, thereby obtaining the final detection conclusion. Specifically, this includes the following steps C10-C40: Step C10: If it is determined that there is no fault in the current link segment, the main control board will use the first target board on the current link as an intermediate board to relay the loopback command to the second target board of the next communication link segment, so that the current second target board enters the loopback mode; at this time, the intermediate board is in the normal transmit and receive mode.

[0052] In this embodiment, it should be noted that the above-mentioned limitations of "first" and "second" are only used to distinguish the description of the two target boards.

[0053] Step C20: The main control board generates a probe frame for the second target board and sends it to the second target board via the intermediate board.

[0054] The probe frame also carries staining sequence and timestamp information.

[0055] Step C30: Receive the return frame sent by the second target board and calculate the latency and packet loss rate of the current communication link segment.

[0056] Taking the second target board as board C as an example, in loopback mode, board C receives a probe frame and forwards it as a return frame to the main control board, which then receives the return frame.

[0057] Step C40: Based on the latency and packet loss rate, determine whether there is a fault in the current communication link segment where the second target board is located.

[0058] In this embodiment, the final delay ΔT includes four delay segments: A→B→C→B→A. When ΔT is abnormal, the main control board can further infer whether the fault is in the "sending path" or the "return path" by combining the topology table.

[0059] In this embodiment of the application, step C40 above, which determines whether the current communication link segment where the second target board is located is faulty based on the latency and packet loss rate, specifically includes the following step C401: Step C401: If the delay and / or the packet loss rate are not within the normal range, then it is determined that the serial port of the intermediate board TX chip is faulty, or the communication link where the second target board is located is faulty.

[0060] Based on the aforementioned latency and packet loss rate, if a fault is detected in the BC communication link segment, the main control board will output a detection conclusion prompting "Check the BC connection cable or the B board transmitting chip".

[0061] Figure 4 A flowchart illustrating fault location of a BC communication link segment is provided as a specific embodiment of this application; see reference. Figure 4 As shown, this embodiment, taking a specific application scenario and the ABC serial communication link of a smart refrigerator as an example, provides a detailed explanation of the above-mentioned application for BC communication link segment detection: Step S401: The main control board A detects a communication anomaly and first verifies that the AB communication link segment is normal. The main control board A sends a loopback command to the intermediate board B (i.e., the first target board mentioned above), and board B enters loopback mode. Board A sends probe frames to board B and receives return frames from board B, calculating ΔT and packet loss rate L; If the packet loss rate is low and ΔT is normal, that is, the AB segment is normal, then the AB communication link segment is confirmed to be normal: the TX chip on board A, the AB link, and the RX chip on board B are all without faults, and board B itself is working normally (because the loopback mode verifies its internal transmit and receive functions).

[0062] Step S402: After relaying through intermediate board B, test the AC communication link segment again. Board A sends a loopback command to Board C (the second target board mentioned above) according to the topology table, and Board C enters loopback mode; at this time, Board B is in normal mode. Board A generates a probe frame targeting board C, which is then sent to board C via the path A→B→C. After the probe frame loops back on board C, the return frame returns to the main control board A via the path C→B→A. Board A receives the returned frames and analyzes the latency and packet loss rate.

[0063] Step S403, Fault Conclusion Deduction and Output: If the A→C segment test fails (abnormal latency or packet loss rate >90%), since step 1 above confirmed that segment AB is normal, the following conclusion can be deduced: Since the internal functions of board B are normal (as verified in step 1), the problem must occur in the process of board B forwarding data to C. Therefore, it is determined to be either "board B TX chip serial port failure" or "BC link failure". At this time, the fault conclusion is output.

[0064] Furthermore, the main control board can display repair solutions on the screen or push repair solutions to the cloud for repair personnel to refer to.

[0065] In this embodiment, a relay mechanism is employed: during BC segment testing, board B does not enter loopback mode but operates in normal forwarding mode, acting only as a relay node. Furthermore, through indirect inference, board A cannot directly test the BC link; instead, an "elimination method" is used to first ensure the AB segment is functioning correctly, then test the end-to-end AC segment. If the test fails, the fault is located in the BC segment.

[0066] In a specific embodiment, if a fault has been detected in segment AB, a chip-level or segment-level fault conclusion is output, and a repair solution is pushed through the display screen or the cloud.

[0067] Therefore, in the above embodiments of this application, no additional communication lines are required. Millisecond-level automatic diagnosis can be achieved solely through software protocols and low-cost analog switches. This is compatible with existing home appliance hardware platforms and can significantly improve diagnostic efficiency and system reliability.

[0068] The actual technical effects of the solution in this application embodiment have been tested and shown that the solution can complete the fault location of the three-board cascaded link within 10ms, improve the repair efficiency by more than 50%, and the hardware cost is almost zero. It is especially suitable for high-reliability home appliances such as smart refrigerators and air conditioners.

[0069] Figure 5 A schematic diagram of a communication fault location device for home appliances provided in this application embodiment; see reference Figure 5 As shown, this device is used on the main control board in a communication link. The device includes: The first detection module 501 is used to trigger the execution of communication fault detection after detecting a communication abnormality; The second detection module 502 is used to detect the latency and packet loss rate of the current communication link segment, starting from the current communication link segment where the main control board is located. The judgment module 503 is used to determine whether there is a fault in the current communication link segment based on the delay and packet loss rate; Output module 504 is used to output fault detection results; The third detection module 505 is used to perform fault detection on the next communication link segment, using the current link segment as a relay, based on the detection results and the topology table characterizing the connection logic relationship of each level of the communication link, thereby obtaining the final detection conclusion. Figure 6A schematic diagram of the structure of a home appliance communication fault location device provided in this application embodiment; refer to Figure 6 As shown in the figure, this application provides an air conditioner control device, including a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114. Memory 113 is used to store computer programs; In one embodiment of this application, the processor 111, when executing a program stored in the memory 113, implements a method for locating communication faults in home appliances provided in any of the foregoing method embodiments, including: After the main control board detects a communication anomaly, it triggers the execution of communication fault detection. Starting from the current communication link segment where the main control board is located, detect the latency and packet loss rate of the current communication link segment; Based on the aforementioned latency and packet loss rate, determine whether there is a fault in the current communication link segment; If so, output the fault detection result; If not, based on the detection results and the topology table characterizing the connection logic of each level of the communication link, the current link segment is used as a relay to perform fault detection on the next communication link segment, thereby obtaining the final detection and location conclusion.

[0070] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of a home appliance communication fault location method as provided in any of the foregoing method embodiments.

[0071] In the above embodiment, after the main control board detects a communication anomaly, it triggers the execution of communication fault detection. Starting from the communication link segment where the main control board is currently located, it detects the latency and packet loss rate of the current communication link segment. Based on the latency and packet loss rate, it determines whether the current communication link segment has a fault. If it does, it outputs the fault detection result. If it does not, based on the detection result and the topology table representing the connection logic relationship of each level of the communication link, it uses the current link segment as a relay to perform fault detection on the next communication link segment, thereby obtaining the final detection and location conclusion.

[0072] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0073] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0074] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0075] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for locating communication faults in home appliances, characterized in that, The method is applied to the main control board in a communication link, and the method includes: After the main control board detects a communication anomaly, it triggers the execution of communication fault detection. Starting from the current communication link segment where the main control board is located, detect the latency and packet loss rate of the current communication link segment; Based on the aforementioned latency and packet loss rate, determine whether there is a fault in the current communication link segment; If so, output the fault detection result; If not, based on the detection results and the topology table characterizing the connection logic of each level of the communication link, the current link segment is used as a relay to perform fault detection on the next communication link segment until the final detection and location conclusion is obtained.

2. The method according to claim 1, characterized in that, The step of detecting the latency and packet loss rate of the current communication link segment, starting from the current communication link segment of the main control board, includes: A state switching command is sent to the first target board on the current communication link to switch the first target board to loopback mode. In loopback mode, the first target board short-circuits the RX chip serial port and the TX chip serial port through an analog switch, thereby disconnecting the external link and entering a self-transmitting and self-receiving state. Send a probe frame to the first target board, wherein the probe frame carries a staining sequence and a sending timestamp. Receive the return frame sent by the first target board after receiving the probe frame in loopback mode; Based on the information carried in the returned frame, the latency and packet loss rate of the current communication link segment are calculated.

3. The method according to claim 2, characterized in that, The calculation of the latency and packet loss rate of the current communication link segment based on the information carried in the returned frame includes: The main control board parses the returned frame, calculates the round-trip delay ΔT based on the sending timestamp and the current receiving timestamp, and verifies the integrity of the coloring sequence to obtain the packet loss rate L.

4. The method according to claim 3, characterized in that, The step of determining whether there is a fault in the current communication link segment based on the latency and packet loss rate includes: Determine whether the delay ΔT and packet loss rate L are both within the normal range. If so, determine that the serial port of the TX chip on the main control board, the communication link between the main control board and the first target board, and the serial port of the RX chip on the first target board are all without faults.

5. The method according to claim 1, characterized in that, The topology table, based on the detection results and characterizing the logical connections between the various levels of the communication link boards, uses the current link segment as a relay to perform fault detection on the next communication link segment, thereby obtaining the final detection conclusion, including: If the current link segment is determined to be fault-free, the main control board will use the first target board on the current link as an intermediate board to relay the loopback command to the second target board of the next communication link segment, so that the second target board enters the loopback mode; at this time, the intermediate board is in normal transmit and receive mode. The main control board generates a probe frame for the second target board, which is then sent to the second target board via the intermediate board. Receive the return frame sent by the second target board, and calculate the latency and packet loss rate of the current communication link segment where the second target board is located; Based on the latency and packet loss rate, it is determined whether the current communication link segment where the second target board is located is faulty.

6. The method according to claim 5, characterized in that, The step of determining whether the current communication link segment where the second target board is located is faulty based on the latency and packet loss rate includes: If the latency and / or the packet loss rate are not within the normal range, it is determined that the serial port of the intermediate board TX chip is faulty, or the communication link of the second target board is faulty.

7. The method according to claim 2, characterized in that, The content structure of the probe frame includes: a frame header, used to characterize the probe frame category identifier; a staining sequence field; a target board unique identifier ID; a transmission timestamp field; and a checksum field.

8. A device for locating communication faults in household appliances, characterized in that, The device is used on the main control board in a communication link, and the device includes: The first detection module is used to trigger communication fault detection after detecting a communication anomaly. The second detection module is used to detect the latency and packet loss rate of the current communication link segment, starting from the current communication link segment where the main control board is located. The judgment module is used to determine whether there is a fault in the current communication link segment based on the latency and packet loss rate; The output module is used to output the fault detection results; The third detection module is used to perform fault detection on the next communication link segment, using the current link segment as a relay, based on the detection results and the topology table characterizing the connection logic relationship of each level of the communication link, until the final detection conclusion is obtained.

9. A communication fault location device for home appliances, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other through the communication bus. Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1-7.

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