Device and method for preventing host from being hung up and switching chip

Abstract

The invention discloses a device and method for preventing a host from being hung up and a switch chip, and belongs to the technical field of computer buses and interfaces, and the device for preventing the host from being hung up comprises a message analysis and screening module, an address and resource control module, a cache module, a content addressable memory module, a message checking module and a response message generation module. The method comprises the following steps: analyzing, verifying and timestamp marking a message sent to endpoint equipment, and caching field information of the message; checking whether the response of the message is overtime or whether a destination port fails through a polling mechanism; when response timeout or fault is detected, a response message is automatically constructed and completed according to an original message field and returned to the host, resources occupied by the host are released in time, and system hanging is avoided.

Description

Technical Field

[0001] This application relates to the field of computer bus and interface technology, and in particular to a device, method and switching chip for preventing host computer from crashing. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial expansion bus standard. In a multi-layer cascaded network interconnection system built with PCIe switching chips, the host communicates with multiple endpoint devices (EPs) through the switching chip. PCIe transaction layer TLP (Transaction Layer Packet) messages include P (Posted) type messages, NP (Non-Posted) type messages, and CPL (Completion) type messages. P type messages are posting messages, NP type messages are non-posting messages, and CPL type messages are completion / response messages. NP type messages require a response; that is, after the switching chip sends an NP type message from the host to the endpoint device, it also needs to route the completion response message generated by the endpoint device back to the host.

[0003] According to the PCIe protocol, after a host sends a request-to-responder message, it must wait for a completion response from the target device. If the downstream port of the switching chip or its connected endpoint device fails, the request-to-responder message sent by the host to the failed port will not receive the corresponding completion message. This will cause the host's corresponding queue or cache resources to be continuously occupied and unable to be released, potentially leading to the host entering a waiting state or the system entering an unresponsive state, i.e., the host is stuck. Current solutions to this stuck state require resetting the switching chip or related equipment to recover. This process results in the loss of all messages sent to the switching chip but not yet processed, causing serious consequences such as data inconsistency and service interruption. Summary of the Invention

[0004] This application aims to provide a device, method, and switching chip for preventing host hang-up. By autonomously generating a completion response message based on the response request message received at the downstream destination port when the downstream destination port fails, the host hang-up is prevented, thereby ensuring the continued operation of the switching chip.

[0005] To achieve the above objectives, the first aspect of this application provides a device for preventing host hang-up, applied to a switching chip, the device comprising: The message analysis and filtering module is used to parse the messages sent to the endpoint device and filter out the messages that need to be responded to, perform a legality check on the messages that need to be responded to, and add a first timestamp to the messages that need to be responded to that pass the legality check to obtain the corresponding first message; wherein, the first timestamp is the current timestamp when the message that needs to be responded to passes the legality check; The address and resource control module is used to receive the first message, determine the first address in the cache module and the second address in the content-addressable memory module according to the bitmap, extract the first preset field set and the first timestamp from the first message as the second message and write them to the first address, and extract the second preset field set from the first message as the third message and write it to the second address; wherein, the bit width of the bitmap is the same as the depth of the cache module and corresponds one-to-one, and the bit width of the bitmap is also the same as the depth of the content-addressable memory module and corresponds one-to-one. A caching module is used to store the second message; Content-addressable memory module for storing the third message; Message inspection module; Response message generation module; The address and resource control module polls and checks the cache module to generate a corresponding first read address signal; The caching module sends the fourth message to the message checking module according to the first read address signal; wherein, the fourth message is the second message in the caching module that corresponds to the first read address signal; The message inspection module performs a message inspection based on the first preset field set and the corresponding first timestamp of the fourth message to determine whether the corresponding first message has timed out or the destination port is faulty. If so, the message inspection module sends the first preset field set of the fourth message to the response message generation module; the message inspection module also sends the first address corresponding to the fourth message to the address and resource control module. The response message generation module generates a corresponding first completion response message for routing back to the host based on the first preset field set of the fourth message; wherein, the first completion response message is a completion response message for request failure; The address and resource control module releases the address resources corresponding to the first address and the second address based on the first address corresponding to the fourth message; The content addressable memory module also receives a second completion response message sent by the endpoint device, and matches the second completion response message with all third messages in the content addressable memory module. If the match is successful, the second address corresponding to the fifth message is sent to the address and resource control module; wherein, the fifth message is a third message that is successfully matched with the second completion response message. The address and resource control module releases the address resources corresponding to the first and second addresses based on the second address corresponding to the fifth message.

[0006] Optionally, the message inspection module determines the difference between the second timestamp and the first timestamp, and determines whether the difference is greater than a preset timeout value. If so, it is considered that the response of the first message corresponding to the fourth message has timed out; wherein, the second timestamp is the current timestamp when the message inspection module performs message inspection on the fourth message.

[0007] Optionally, the message inspection module reads the link training state machine state of the switching chip and the isolation state register state of the downstream port of the switching chip to determine whether the switching chip link is faulty or whether the downstream port is in an isolated state. If the switching chip link is faulty or the downstream port is in an isolated state, the destination port of the first message corresponding to the fourth message is considered to be faulty.

[0008] Optionally, the first preset field set includes: traffic category field, attribute field, target identifier field, length field, first double character enable field, last double character enable field, requester segmentation information field, requester segmentation validity information field, and tag field; The response message generation module uses the traffic category field and attribute field of the fourth message as the traffic category field and attribute field of the first completed response message, uses the target identifier field of the fourth message as the completer identifier field of the first completed response message, determines the byte count field and low address field of the first completed response message based on the length field, first double-word enable field and last double-word enable field of the fourth message, and uses the tag field, requester segment validity information field and requester segment information field of the fourth message as the tag field, destination segment validity information field and destination segment information field of the first completed response message to obtain the first completed response message.

[0009] Optionally, the content-addressable memory module receives a response message sent by the endpoint device and adds a third timestamp to obtain a corresponding second completion response message. It then determines whether the second completion response message is the last completion response message. Based on the byte count field, low address field, and length field of the second completion response message, it determines whether the sum of the byte count field and low address field is less than or equal to four times the length field. If so, the second completion response message is considered the last completion response message, and it is matched with all third messages in the content-addressable memory module. If not, the second completion response message is not matched with any third messages in the content-addressable memory module. The third timestamp is the current timestamp when the content-addressable memory module receives the response message sent by the endpoint device.

[0010] Optionally, the second preset field set includes: a request identifier field, a tag field, a requester segmentation validity information field, and a requester segmentation information field; The content-addressable memory module extracts the third preset field set from the second completion response message, matches the third preset field set of the second completion response message with the second preset field set of all third messages, and if the match is successful, sends the second address corresponding to the fifth message and the third timestamp of the second completion response message to the address and resource control module; wherein, the third preset field set includes: request identifier field, tag field, destination segment validity information field and destination segment information field; the fifth message is the third message that successfully matches the second completion response message.

[0011] Optionally, the device for preventing host computer hang-up further includes: Delay statistics module; The content addressable memory module determines whether to perform transmission delay statistics on the fifth message based on the switching chip configuration. If yes, it sends a first signal to the address and resource control module. The first signal is a signal for the cache module to read the fifth message and perform transmission delay statistics. The address and resource control module generates a corresponding second read address signal, and the cache module sends the sixth message to the delay statistics module for delay statistics based on the second read address signal; wherein, the sixth message is the second message in the cache module that corresponds to the fifth message.

[0012] Optionally, the delay statistics module reads the first timestamp of the sixth message, determines the current message delay value of the destination port of the sixth message based on the first timestamp and the corresponding third timestamp, updates the current first average delay value of the destination port based on the current message delay value, obtains the second average delay value of the destination port, and performs delay statistics based on the second average delay value of the destination port, as follows: in, This indicates the current message delay value of the destination port of the sixth message; This indicates the current first average delay value of the destination port of the sixth message; This represents the second average delay value of the destination port of the sixth message; This indicates the preset weighting coefficients.

[0013] A second aspect of this application provides a switching chip including the host hang-prevention device described above.

[0014] A third aspect of this application provides a method for preventing host computer hang-up, applied to the aforementioned device for preventing host computer hang-up, comprising: The message sent to the endpoint device is parsed and the message requiring response is filtered out. The message requiring response is then checked for validity. The message requiring response that passes the validity check is stamped with a first timestamp to obtain the corresponding first message. The first address in the cache module and the second address in the content addressable memory module are determined according to the bitmap. The first preset field set and the first timestamp in the first message are extracted, recorded as the second message, and written to the first address. The second preset field set in the first message is extracted, recorded as the third message, and written to the second address. The cache module is polled and checked to generate a corresponding first read address signal. The cache module is then read to obtain the fourth packet. The packet is checked according to the first preset field set and the corresponding first timestamp of the fourth packet to determine whether the corresponding first packet has timed out or the destination port is faulty. If so, a first completion response packet for routing back to the host is generated according to the first preset field set of the fourth packet. The address resources of the corresponding first address and second address are released according to the first address corresponding to the fourth packet. The second completion response message sent by the receiving endpoint device is matched with all the third messages in the content addressable memory module. If the match is successful, the address resources of the corresponding first address and second address are released according to the second address corresponding to the fifth message.

[0015] This application provides a device, method, and switching chip for preventing host hang-up. By generating corresponding completion response messages with a request failure status for each of the response messages sent to the faulty destination port or those that have timed out, the host completes the response and releases the host's cache resources. This can effectively prevent the host from hanging up due to waiting for completion response messages for a long time when the downstream destination port fails. Attached Figure Description

[0016] Figure 1 This is a structural block diagram of a device for preventing host computer from freezing, provided in an embodiment of this application.

[0017] Figure 2 A flowchart illustrating the steps of a method for preventing host computer from freezing, as provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives and technical solutions of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0019] In related technologies, the upstream port of a switching chip receives a response request message from the host and forwards it to the target endpoint device through the corresponding downstream port of the switching chip. The downstream port of the switching chip also receives a completion response message from the target endpoint device and routes it to the host through the corresponding upstream port. If the downstream port of the switching chip fails, the host may hang due to prolonged waiting for a response from the target endpoint device. For example, if a port of a cascaded switching chip fails, the host may enter a prolonged waiting state and hang because it has not received a response message for the sent response request message for an extended period.

[0020] Based on the above analysis, please refer to Figure 1 , Figure 1This is a structural block diagram of a device for preventing host hang-up according to an embodiment of this application. This embodiment provides a device 11 for preventing host hang-up, applied to a switching chip. The device 11 copies and receives messages sent from the switching chip to endpoint devices. It parses, verifies, and timestamps the messages sent to the endpoint devices, and caches the field information of the response messages. A polling mechanism checks whether the response messages have timed out or the destination port is faulty. When a timeout or fault is detected, a completion response message (CPL message) is automatically constructed based on the original message fields and returned to the host, thereby releasing the host's occupied resources in a timely manner and preventing system hang-up. The device 11 also copies and receives completion response messages sent from endpoint devices to the switching chip, matches the completion response messages with the cached response messages, and if a match is found, releases the cached response message resources to cache subsequent response messages.

[0021] As an example, the anti-host hangup device 11 provided in this application can be applied to downstream port 1. The anti-host hangup device 11 provided in this application includes: The message analysis and filtering module 111 is used to parse the messages sent to the endpoint device and filter out the messages that need to be responded to, perform a legality check on the messages that need to be responded to, and add a first timestamp to the messages that pass the legality check to obtain the corresponding first message; wherein, the first timestamp is the current timestamp when the message that needs to be responded to passes the legality check, which is obtained according to the global time counter; Address and resource control module 112 is used to receive the first message, determine the first address in cache module 113 and the second address in content addressable memory module 114 according to the bitmap, extract the first preset field set and the first timestamp from the first message as the second message and write it to the first address, and extract the second preset field set from the first message as the third message and write it to the second address; wherein, the bit width of the bitmap is the same as the depth of the cache module 113 and corresponds one-to-one, and the bit width of the bitmap is also the same as the depth of the content addressable memory module 114 and corresponds one-to-one. Cache module 113 is used to store the second message; Content-addressable memory module 114 is used to store the third message; Message inspection module 115; Response message generation module 116; The address and resource control module 112 polls and checks the cache module 113 to generate a corresponding first read address signal; The cache module 113 sends the fourth message to the message inspection module 115 according to the first read address signal; wherein, the fourth message is the second message in the cache module 113 corresponding to the first read address signal; The message inspection module 115 performs a message inspection based on the first preset field set and the corresponding first timestamp of the fourth message to determine whether the corresponding first message has timed out or the destination port is faulty. If so, the message inspection module 115 sends the first preset field set of the fourth message to the response message generation module 116; the message inspection module 115 also sends the first address corresponding to the fourth message to the address and resource control module 112. The response message generation module 116 generates a corresponding first completion response message for routing back to the host based on the first preset field set of the fourth message; wherein, the first completion response message is a completion response message for request failure; The address and resource control module 112 releases the address resources corresponding to the first address and the second address according to the first address corresponding to the fourth message; The content addressable memory module 114 also receives a second completion response message sent by the endpoint device, and matches the second completion response message with all third messages in the content addressable memory module 114. If the match is successful, the second address corresponding to the fifth message is sent to the address and resource control module 112; wherein, the fifth message is a third message that is successfully matched with the second completion response message. The address and resource control module 112 releases the address resources corresponding to the first address and the second address based on the second address corresponding to the fifth message.

[0022] The anti-host hangup device 11 provided in this application copies the messages sent by the switching chip to the endpoint device, checks for message response timeouts or destination port failures, constructs a request failure completion response message based on the second message corresponding to the message response timeout or destination port failure, and routes it back to the host. This enables the generation of corresponding request failure status completion response messages for all messages sent to the faulty destination port or with timeouts, returning them to the host and completing the response, thereby releasing host cache resources. This effectively avoids the host hanging up due to prolonged waiting for completion response messages when the downstream destination port fails. The anti-host hangup device 11 also receives completion response messages sent by the endpoint device to the switching chip, matches the completion response message with the relevant fields corresponding to the request response messages in the content addressable memory module 114. If a match is found, the resources corresponding to the request response message in the cache module 113 and the content addressable memory module 114 are released to cache the relevant fields of subsequent request response messages.

[0023] Taking a PCIe Switch as an example, where the response message is of type NP, the following is a detailed explanation. In practical applications, the message analysis and filtering module 111 receives messages from PCIe Switch2EP (sent by the PCIe Switch to the EP), performs preliminary message parsing and filtering to identify NP type messages, and conducts a preliminary check on the NP type messages. If the NP type message does not conform to the protocol specification or contains errors, the message is discarded and an interrupt notification is generated to the system. If the NP type message conforms to the specification, it is transmitted to the subsequent address and resource control module 112 along with the current timestamp.

[0024] The address and resource control module 112 maintains a bitmap table to indicate the address validity of the cache module 113 (random access memory) and the content-addressable memory module 114. The cache module 113 and the content-addressable memory module 114 have the same depth and share the same bitmap. The bit width of this bitmap corresponds one-to-one with the depth of the cache module 113 and the content-addressable memory module 114. The bitmap can be a multi-bit register, with its bit width corresponding to the depth of the cache module 113 and the content-addressable memory module 114. Each bit indicates whether the corresponding address in the cache module 113 and the content-addressable memory module 114 is writable. In other words, each bit in this bitmap has a one-to-one mapping relationship with each address in the cache module 113, and also with each address in the content-addressable memory module 114. The bitmap is initially set to 1 upon power-on. When a certain NP type message is written, the bitmap is set to 0 at that address. Setting it to 0 indicates that the first address of the cache module 113 and the second address in the content-addressable memory module 114 associated with that bit are occupied, used, or unwritable.

[0025] The address and resource control module 112 receives an NP-type message from the message analysis and filtering module 111, finds an empty location through a bitmap, and outputs the first address in the cache module 113 and the second address in the content addressable memory module 114 corresponding to the empty location. It writes some fields of the NP-type message into the cache module 113 according to the first address, and writes some fields of the NP-type message (such as the Transaction ID in the PCIe message) into the content addressable memory module 114 according to the second address.

[0026] The message inspection module 115 checks whether NP type messages have timed out and whether the destination port of NP type messages has failed. When a problem is detected in an NP type message, it sends the NP type message to the response message generation module 116 to generate a completion response message with an unsupported request (UR) or completion abort (CA) status, and notifies the address and resource control module 112 to release the address resource corresponding to the NP type message. When a timeout or failure occurs, the bit in the bitmap is reset to 1, indicating that the first address in the cache module 113 and the second address in the content-addressable memory module 114 associated with the bit are free, available, and writable.

[0027] If the message inspection module 115 detects a message response timeout or a destination port failure, the response message generation module 116 constructs a completion response message indicating a failed request based on the second message corresponding to the timeout or destination port failure, and routes it back to the host, thereby preventing the host from hanging and ensuring the system continues to operate. In other words, when a PCIe Switch port fails, the PCIe Switch can autonomously generate a response message based on the required response messages received on that port (such as NP-type messages in PCIe), thereby preventing the host from hanging and ensuring the system continues to operate. After receiving the constructed completion response message indicating a failed request from the PCIe Switch, the host can retrain and re-establish the link for the failed port.

[0028] Furthermore, the content addressable memory module 114 receives the completion response message returned by the EP2Switch (sent by the EP to the PCIe Switch), matches the completion response message with the partial fields of the NP type message stored in the partial fields of the NP type message, and releases the relevant resources of the corresponding NP type message after a match, that is, sets the bit of the corresponding bitmap to 1, so that the relevant fields of the subsequent NP type message can be stored.

[0029] As an example, the device 11 for preventing host hang-up at the downstream port 1 further includes: The sending module 118 is used to send messages to the endpoint device, copy the messages sent to the endpoint device and send them to the message analysis and filtering module 111; The receiving module 119 is used to receive the completion response message returned by the endpoint device, copy the completion response message returned by the endpoint device and send it to the content addressable memory module 114.

[0030] Specifically, the sending module 118 and the receiving module 119 are connected to the same endpoint device. The switching chip may include multiple downstream ports 1, which are connected to multiple endpoint devices of the same number. Each of the multiple downstream ports 1 can be connected to the host through the same upstream port 2. The sending module 118 copies the messages sent by the switching chip to the endpoint devices and sends them to the message analysis and filtering module 111. The receiving module 119 copies the completion response messages sent by the endpoint devices to the switching chip and sends them to the content-addressable memory module 114.

[0031] As an example, the message analysis and filtering module 111 parses and filters the messages sent to the endpoint device, wherein the message is the message sent to the endpoint device by the copy sending module 118.

[0032] Furthermore, the message analysis and filtering module 111 performs a legality check on the message to be responded to, and determines whether the message to be responded to conforms to the PCIe protocol specification and does not carry any errors. If so, the message to be responded to passes the legality check; if not, the obtained message to be responded to is discarded, and an interrupt signal is generated to notify the user that a message that does not conform to the PCIe protocol specification or carries errors has appeared.

[0033] As an example, the address and resource control module 112 includes a bitmap implemented by a register vector. The bitmap's bit width is the same as and corresponds one-to-one with the depth of the cache module 113. The bitmap's bit width is also the same as and corresponds one-to-one with the depth of the content-addressable memory module 114. Therefore, the bitmap's bit width corresponds to the depth of the cache module 113 and the depth of the content-addressable memory module 114. The cache module 113 and the content-addressable memory module 114 can share a single bitmap, thereby saving resources.

[0034] Specifically, each bit in the bitmap represents whether the corresponding first address in the cache module 113 and the corresponding second address in the content-addressable memory module 114 are writable. The free address of the bitmap is initially set to 1 upon power-on, indicating that the first address in the cache module 113 corresponding to the free address of the bitmap is writable for a second message, and the second address in the content-addressable memory module 114 corresponding to the free address of the bitmap is writable for a third message. When the first address in the cache module 113 corresponding to the free address of the bitmap is used to write a second message, and the second address in the content-addressable memory module 114 corresponding to the free address of the bitmap is used to write a third message, the free address of the bitmap is set to 0. Setting it to 0 indicates that the first address in the cache module 113 corresponding to the free address of the bitmap is not writable for a second message, and the second address in the content-addressable memory module 114 corresponding to the free address of the bitmap is not writable for a third message.

[0035] After the first message is sent to the address and resource control module 112, the address and resource control module 112 will find the position that is 1 according to the bitmap. This position being 1 indicates that the first address of the corresponding associated cache module 113 and the second address in the content-addressable memory module 114 are free, available, and writable. The address and resource control module 112 extracts the corresponding second message according to the first message and writes it into the first address in the cache module 113 corresponding to the position of 1 in the bitmap. The address and resource control module 112 also extracts the corresponding third message according to the first message and writes it into the second address in the content-addressable memory module 114 corresponding to the position of 1 in the bitmap.

[0036] Specifically, since the bitmap is implemented by a register vector, the bitmap can simultaneously set different bits in the bit width to 1 or 0.

[0037] As an example, the address and resource control module 112 also includes a depth counter, which is used to record the number of first packets written and to generate back pressure on the host based on the number of first packets written.

[0038] Specifically, when a new NP message needs to be written and a free address is found in the bitmap (i.e., a bit is set to 1 in the bitmap), and this bit is set to 0 after the message is written, the depth counter is incremented. When the message count of the depth counter reaches the preset back pressure line, a back pressure signal is generated on the upstream port 2 of the switching chip, stopping the upstream port 2 from sending messages to the endpoint device. The back pressure line is set according to the bit width of the bitmap.

[0039] As an example, the first preset field set includes: traffic category field tc, attribute field attr, target identifier field DST_ID, length field len, first double-word enable field first_dw_be, last double-word enable field last_dw_be, requester segment information field req_sgmt, requester segment validity information field rsv, and tag field; the second preset field set includes: request identifier field req_id, tag field tag, requester segment validity information field rsv, and requester segment information field req_sgmt.

[0040] As an example, cache module 113 includes a read-write dual-port (1 Read 1 Write RAM), which performs one read operation and one write operation simultaneously within the same clock cycle.

[0041] As an example, in the polling message inspection process, the message inspection module 115 determines whether the corresponding first message has timed out based on the first timestamp corresponding to the fourth message. Specifically, by determining the difference between the second timestamp and the first timestamp, it is judged whether the difference is greater than a preset timeout value. If so, the first message corresponding to the fourth message is considered to have timed out; if not, the first message corresponding to the fourth message is considered not to have timed out. The second timestamp is the current timestamp when the message inspection module 115 performs message inspection on the fourth message, obtained from a global time counter. The timeout value can be set according to the actual situation. For example, it can be set to be greater than the first time, where the first time can be the time from when the host sends an NP type message to the endpoint device through the switching chip to when the host receives the completion response message returned by the endpoint device through the switching chip. That is, the first time is the normal response time from the host through the switching chip to the endpoint device.

[0042] The message inspection module 115 can determine the corresponding destination port based on the first preset field set of the fourth message. By reading the Link Training and Status State Machine (LTSSM) status of the switching chip and the isolation status register (DPC Status Register) status of the downstream port of the switching chip, it can determine whether the switching chip link is faulty or whether the downstream port is in an isolated state. If the switching chip link is faulty or the downstream port is in an isolated state, the destination port of the first message corresponding to the fourth message is considered to be faulty. If the switching chip link is not faulty and the downstream port is not in an isolated state, the destination port of the first message corresponding to the fourth message is considered to be not faulty.

[0043] Furthermore, in the response message generation module 116, a first completion response message for routing back to the host is generated according to the first preset field set of the fourth message.

[0044] Specifically, the traffic category field tc and attribute field attr of the fourth message can be used as the traffic category field and attribute field of the first completion response message. The target identifier field DST_ID of the fourth message can be used as the completer identifier field of the first completion response message. The byte count field and low address field of the first completion response message can be determined according to the length field len, the first double-word enable field first_dw_be, and the last double-word enable field last_dw_be of the fourth message. The tag field tag, the requester segment validity information field rsv, and the requester segment information field req_sgmt of the fourth message can be used as the tag field, destination segment validity information field, and destination segment information field of the first completion response message. The message type field of the first completion response message is fixed as the completion response message type. In the A5 type orthogonal header content, the status field is set to the state of not supporting request or completion aborted. The remaining fields are set to the default values ​​of the PCIe protocol specification to obtain the first completion response message. In other words, the switching chip generates a completion response message that does not support the request or the completion abort status and replies to the host, notifying the host that the message sent to that port has failed, thus preventing the host from crashing.

[0045] Specifically, in the response message generation module 116, the completion response message for a failed request, i.e., the first completion response message, is a 4DW FLIT format message.

[0046] Furthermore, the address and resource control module 112 releases the address resources of the first address in the corresponding cache module 113 and the second address in the content addressable memory module 114 according to the first address corresponding to the fourth message.

[0047] As an example, when the device for preventing host hang-up in this application detects a response timeout or destination port failure in a message requiring a response, it will reset the corresponding bit in the bitmap to 1, thereby releasing the first address in the cache module and the second address in the content-addressable memory module that corresponds to the bit mapping.

[0048] Furthermore, the address and resource control module 112 releases the address resources of the first address in the corresponding cache module 113 and the second address in the content addressable memory module 114 according to the second address corresponding to the fifth message.

[0049] As an example, after the device for preventing host hang-up in this application matches and hits the content addressable memory module with the completion response message returned by the receiving endpoint device, it resets the corresponding bit in the bitmap to 1 according to the fifth message that hits, thereby releasing the first address in the cache module and the second address in the content addressable memory module mapped to the corresponding bit.

[0050] Furthermore, if it is determined that the response to the first message corresponding to the fourth message times out and the endpoint device returns a completion response message for the fourth message at this time, that is, the message that timed out and the completion response message returned by the endpoint device are the same message, then the generation of the first completion response message for the first message that timed out corresponding to the fourth message will be stopped. This avoids replying with two completion response messages for a message that needs a response, and prevents the host from receiving two completion response messages with different states for a message that needs a response. In practical applications, this situation can be avoided by configuring the timeout value.

[0051] Further, the content-addressable memory module receives a completion response message sent by the endpoint device and adds a third timestamp to obtain a corresponding second completion response message. It then determines whether the second completion response message is the last completion response message. Based on the byte count field, low address field, and length field of the second completion response message, it determines whether the sum of the byte count field and the low address field is less than or equal to four times the length field. If so, the second completion response message is considered the last completion response message, and it is matched against all third messages in the content-addressable memory module. If not, the second completion response message is not matched against any third messages in the content-addressable memory module. The third timestamp is the current timestamp when the content-addressable memory module receives the response message sent by the endpoint device.

[0052] As an example, in the message matching process, the content-addressable memory module 114 receives the response message sent by the endpoint device and adds a third timestamp to obtain the corresponding second completion response message. It then determines whether the second completion response message is the last completion response message. Based on the number of bytes in the byte count field (byte_count), the low address field (la), and the length field (len) of the second completion response message, it determines whether the sum of the byte count field (byte_count) and the low address field (la) is less than or equal to the length field (len). 4. If yes, then the second completion response message is considered to be the last completion response message, and the second completion response message is matched with all third messages in the content addressable memory module 114; if no, then the second completion response message is not matched with all third messages in the content addressable memory module 114; wherein, the third timestamp is the current timestamp when the content addressable memory module receives the response message sent by the endpoint device, which is obtained according to the global time counter.

[0053] Further, the content addressable memory module 114 extracts the third preset field set from the second completion response message, matches the third preset field set of the second completion response message with the second preset field set in all third messages, and if the match is successful, sends the second address corresponding to the fifth message and the third timestamp of the second completion response message to the address and resource control module 112; wherein, the third preset field set includes: request identifier field req_id, tag field tag, destination segment validity information field dsv, and destination segment information field deq_sgmt; the fifth message is a third message that successfully matches the second completion response message.

[0054] Specifically, the content-addressable memory module 114 includes a content-addressable memory. The content-addressable memory concatenates the second preset field set in the third message in the following order: request identifier field req_id, tag field, requester segment validity information field rsv, and request segment information field req_sgmt. The content-addressable memory concatenates the third preset field set in the second completion response message in the following order: request identifier field req_id, tag field, destination segment validity information field dsv, and destination segment information field deq_sgmt. The third preset field set of the second completion response message is matched with the second preset field sets in all third messages according to the concatenation order preset by the content-addressable memory. If all field information is consistent, the match is successful.

[0055] Furthermore, when the receiving queue or buffer of the switching chip is almost full, the response message generation module 116 receives the generated backpressure signal through the receiving module 119 and sends it to the address and resource control module 112, thereby stopping the address and resource control module 112 from polling and checking the cache module.

[0056] As an example, the device 11 for preventing host hang-up provided in this application also includes: a latency statistics module 117.

[0057] As an example, in the delay statistics process, the content addressable memory module 114 determines whether to perform transmission delay statistics on the fifth message according to the switching chip configuration. If yes, it sends a first signal to the address and resource control module 112. The first signal is a signal for the cache module 113 to read the fifth message and perform transmission delay statistics.

[0058] Furthermore, when the switching chip configuration determines to perform transmission delay statistics on the fifth message, the address and resource control module 112 generates a corresponding second read address signal, and the cache module 113 sends the sixth message to the delay statistics module 117 for delay statistics based on the second read address signal; wherein, the sixth message is the second message in the cache module 113 corresponding to the fifth message.

[0059] As an example, the delay statistics module 117 reads the first timestamp of the sixth message and determines the current message delay value of the destination port of the sixth message based on the first timestamp and the corresponding third timestamp of the sixth message. According to the current message delay value The current first average delay value for the destination port Perform an update to obtain the second average latency value for the destination port. Second average delay value based on destination port Delay statistics are performed, and the calculation method is as follows: in, This indicates the current message delay value of the destination port of the sixth message; This indicates the current first average delay value of the destination port of the sixth message; The second average delay value of the destination port of the sixth message is represented by the first average delay value. The update was performed to obtain the result; This indicates the preset weighting coefficients.

[0060] Specifically, the weighting coefficient It is configured as a globally programmable parameter, with a value range of 0 to 1, a configuration granularity of 1 / 8, and a default value that can be set to 1 / 8. When At that time, the second average delay value of the destination port of the sixth message Since it's the instantaneous delay, only one of the instantaneous delay and average delay can be selected globally. If the destination port is performing the first delay calculation, then... .

[0061] As an example, when the address and resource control module 112 generates a first read address signal and a second read address signal simultaneously based on the second and fifth messages corresponding to the same first message, the cache module 113 first sends the sixth message to the delay statistics module 117 for delay statistics based on the second read address signal, and then sends the fourth message to the message inspection module 115 for message inspection based on the first read address signal.

[0062] In another embodiment of this application, this application also provides a switching chip, including the anti-host hangup device 11 as described above.

[0063] In another embodiment of this application, a method for preventing host hang-up is also provided, applied to the host hang-up prevention device 11 as described above. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a flowchart of a method for preventing host hang-up according to an embodiment of this application. The method for preventing host hang-up includes the following steps: Steps S1 to S3: Step S1: Parse the messages sent to the endpoint device and filter out the messages that need to be responded to. Perform a validity check on the messages that need to be responded to. Add a first timestamp to the messages that pass the validity check to obtain the corresponding first message. Determine the first address in the cache module 113 and the second address in the content addressable memory module 114 according to the bitmap. Extract the first preset field set and the first timestamp from the first message, record them as the second message and write them to the first address. Extract the second preset field set from the first message, record it as the third message and write it to the second address. Step S2: Poll the cache module 113 to generate a corresponding first read address signal to read the address of the cache module 113 to obtain the fourth message. Check the message according to the first preset field set and the corresponding first timestamp of the fourth message to determine whether the corresponding first message has timed out or the destination port is faulty. If so, generate a corresponding first completion response message for routing back to the host according to the first preset field set of the fourth message. Release the address resources of the corresponding first address and second address according to the first address corresponding to the fourth message. Step S3: The second completion response message sent by the receiving endpoint device is matched with all the third messages in the content addressable memory module 114. If the match is successful, the address resources of the corresponding first address and second address are released according to the second address corresponding to the fifth message.

[0064] In step S1, please refer to Figure 2 Step S1: Parse the messages sent to the endpoint device and filter out the messages that need to be responded to. Perform a validity check on the messages that need to be responded to. Add a first timestamp to the messages that pass the validity check to obtain the corresponding first message. Determine the first address in the cache module 113 and the second address in the content addressable memory module 114 according to the bitmap. Extract the first preset field set and the first timestamp from the first message, record them as the second message and write them to the first address. Extract the second preset field set from the first message, record it as the third message and write it to the second address.

[0065] As an example, the legality check of the response message includes: the message analysis and filtering module 111 performs a legality check on the response message, determines whether the response message conforms to the PCIe protocol specification and does not carry any errors. If so, the response message passes the legality check; if not, the obtained response message is discarded, and an interrupt signal is generated to notify the user that a message that does not conform to the PCIe protocol specification or carries errors has appeared.

[0066] In step S2, please refer to Figure 2 In step S2: The cache module 113 is polled and checked to generate a corresponding first read address signal to read the address of the cache module 113 to obtain the fourth message. The message is checked according to the first preset field set of the fourth message and the corresponding first timestamp to determine whether the corresponding first message has responded with a timeout or the destination port is faulty. If so, a first completion response message for routing back to the host is generated according to the first preset field set of the fourth message. The address resources of the corresponding first address and second address are released according to the first address corresponding to the fourth message.

[0067] As an example, a message check is performed based on the first preset field set and the corresponding first timestamp of the fourth message to determine whether the corresponding first message has timed out. This includes: determining the difference between the second timestamp and the first timestamp, and judging whether the difference is greater than a preset timeout value. If so, the first message corresponding to the fourth message is considered to have timed out; if not, the first message corresponding to the fourth message is considered not to have timed out.

[0068] As an example, message checking is performed based on the first preset field set and the corresponding first timestamp of the fourth message to determine whether the destination port of the corresponding first message is faulty. This includes: determining whether the switching chip link is faulty or whether the downstream port is in an isolated state by reading the link training state machine state of the switching chip and the isolation state register state of the downstream port of the switching chip. If the switching chip link is faulty or the downstream port is in an isolated state, the destination port of the first message corresponding to the fourth message is considered to be faulty; if the switching chip link is not faulty and the downstream port is not in an isolated state, the destination port of the first message corresponding to the fourth message is considered not to be faulty.

[0069] As an example, generating a corresponding first completion response message for routing back to the host based on the first preset field set of the fourth message includes: generating a corresponding first completion response message for routing back to the host based on the first preset field set of the fourth message, wherein the first completion response message inherits the traffic category field tc and attribute field attr of the fourth message; using the target identifier field DST_ID of the fourth message as the completer identifier field of the first completion response message; calculating the byte count field and low address field of the first completion response message based on the length field len, the first double-word enable field first_dw_be, and the last double-word enable field last_dw_be of the fourth message; using the tag field tag, the requester segment validity information field rsv, and the requester segment information field req_sgmt of the fourth message as the tag field, destination segment validity information field, and destination segment information field of the first completion response message; setting the status field in the A5 type orthogonal header content to not support the request or completion aborted status, and setting the remaining fields to the default values ​​of the PCIe protocol specification to obtain the first completion response message.

[0070] In step S3, please refer to Figure 2 In step S3: The second completion response message sent by the receiving endpoint device is matched with all the third messages in the content addressable memory module 114. If the match is successful, the address resources of the corresponding first address and second address are released according to the second address corresponding to the fifth message.

[0071] As an example, before the second completion response message sent by the receiving endpoint device is matched with all the third messages in the content addressable memory module 114, the method further includes: determining whether the second completion response message is the last completion response message.

[0072] Specifically, determining whether the second completion response message is the last completion response message includes: based on the number of bytes in the byte count field byte_count, the low address field la, and the length field len of the second completion response message, determining whether the sum of the number of bytes in the byte count field byte_count and the low address field la is less than or equal to the number of bytes in the length field len. 4. If yes, then the second completion response message is considered to be the last completion response message, and the second completion response message is matched with all third messages in the content addressable memory module 114; if no, then the second completion response message is not matched with all third messages in the content addressable memory module 114.

[0073] As an example, matching the second completion response message sent by the receiving endpoint device with all the third messages in the content addressable memory module 114 includes: the content addressable memory module 114 extracting the third preset field set from the second completion response message and matching the third preset field set of the second completion response message with the second preset field sets in all the third messages in a preset order.

[0074] As an example, before releasing the address resources corresponding to the first and second addresses based on the second address corresponding to the fifth message, the method further includes: If it is determined whether the fifth message needs to be delayed, the address and resource control module 112 generates a corresponding second read address signal, and the cache module 113 reads the sixth message according to the second read address signal to perform delay statistics.

[0075] As an example, determining whether the fifth message needs to be subject to delay statistics includes: deciding whether to perform transmission delay statistics on the fifth message based on the switching chip configuration.

[0076] As an example, the step of reading the sixth message based on the second read address signal and performing delay statistics includes: determining the current message delay value of the destination port of the sixth message based on the first timestamp and the corresponding third timestamp of the sixth message. According to the current message delay value The current first average delay value for the destination port Perform an update to obtain the second average latency value for the destination port. Second average delay value based on destination port Perform delay statistics.

[0077] This application provides a device, method, and switching chip for preventing host hang-up. By generating corresponding completion response messages with a request failure status for each of the response messages sent to the faulty destination port or those that have timed out, the host completes the response and releases the host's cache resources. This can effectively prevent the host from hanging up due to waiting for completion response messages for a long time when the downstream destination port fails.

[0078] This application also includes a latency statistics function, which can count the latency from the switching chip to the endpoint device, and from the endpoint device generating a completion response message to the switching chip. It effectively observes the link status through the average latency value of the destination port, achieving the dual purpose of efficient resource reclamation and performance monitoring.

[0079] Although this application has been disclosed above with reference to embodiments, it is not intended to limit this application. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the appended claims.

Claims

1. A device for preventing host computer from freezing, characterized in that, The device, applied to a switching chip, includes: The message analysis and filtering module is used to parse the messages sent to the endpoint device and filter out the messages that need to be responded to, perform a legality check on the messages that need to be responded to, and add a first timestamp to the messages that need to be responded to that pass the legality check to obtain the corresponding first message; wherein, the first timestamp is the current timestamp when the message that needs to be responded to passes the legality check; The address and resource control module is used to receive the first message, determine the first address in the cache module and the second address in the content-addressable memory module according to the bitmap, extract the first preset field set and the first timestamp from the first message as the second message and write them to the first address, and extract the second preset field set from the first message as the third message and write it to the second address; wherein, the bit width of the bitmap is the same as the depth of the cache module and corresponds one-to-one, and the bit width of the bitmap is also the same as the depth of the content-addressable memory module and corresponds one-to-one. A caching module is used to store the second message; Content-addressable memory module for storing the third message; Message inspection module; Response message generation module; The address and resource control module polls and checks the cache module to generate a corresponding first read address signal; The caching module sends the fourth message to the message checking module according to the first read address signal; wherein, the fourth message is the second message in the caching module that corresponds to the first read address signal; The message inspection module performs a message inspection based on the first preset field set and the corresponding first timestamp of the fourth message to determine whether the corresponding first message has timed out or the destination port is faulty. If so, the message inspection module sends the first preset field set of the fourth message to the response message generation module; the message inspection module also sends the first address corresponding to the fourth message to the address and resource control module. The response message generation module generates a corresponding first completion response message for routing back to the host based on the first preset field set of the fourth message; wherein, the first completion response message is a completion response message for request failure; The address and resource control module releases the address resources corresponding to the first address and the second address based on the first address corresponding to the fourth message; The content addressable memory module also receives a second completion response message sent by the endpoint device, and matches the second completion response message with all third messages in the content addressable memory module. If the match is successful, the second address corresponding to the fifth message is sent to the address and resource control module; wherein, the fifth message is a third message that is successfully matched with the second completion response message. The address and resource control module releases the address resources corresponding to the first and second addresses based on the second address corresponding to the fifth message.

2. The device for preventing host computer from freezing as described in claim 1, characterized in that, The message inspection module determines the difference between the second timestamp and the first timestamp, and judges whether the difference is greater than a preset timeout value. If so, it is considered that the response of the first message corresponding to the fourth message has timed out; wherein, the second timestamp is the current timestamp when the message inspection module performs message inspection on the fourth message.

3. The device for preventing host computer from freezing as described in claim 1, characterized in that, The message inspection module reads the link training state machine state of the switching chip and the isolation state register state of the downstream port of the switching chip to determine whether the switching chip link is failed or whether the downstream port is in an isolated state. If the switching chip link is failed or the downstream port is in an isolated state, the destination port of the first message corresponding to the fourth message is considered to be faulty.

4. The device for preventing host computer from freezing as described in claim 1, characterized in that, The first preset field set includes: traffic category field, attribute field, target identifier field, length field, first double character enable field, last double character enable field, requester segment information field, requester segment validity information field, and tag field; The response message generation module uses the traffic category field and attribute field of the fourth message as the traffic category field and attribute field of the first completed response message, uses the target identifier field of the fourth message as the completer identifier field of the first completed response message, determines the byte count field and low address field of the first completed response message based on the length field, first double-word enable field and last double-word enable field of the fourth message, and uses the tag field, requester segment validity information field and requester segment information field of the fourth message as the tag field, destination segment validity information field and destination segment information field of the first completed response message to obtain the first completed response message.

5. The device for preventing host computer from freezing as described in claim 1, characterized in that, The content-addressable memory module receives a response message sent by the endpoint device and adds a third timestamp to obtain a corresponding second completion response message. It then determines whether the second completion response message is the last completion response message. Based on the byte count field, low address field, and length field of the second completion response message, it determines whether the sum of the byte count field and the low address field is less than or equal to four times the length field. If so, the second completion response message is considered the last completion response message, and it is matched against all third messages in the content-addressable memory module. If not, the second completion response message is not matched against any third messages in the content-addressable memory module. The third timestamp is the current timestamp when the content-addressable memory module receives the response message sent by the endpoint device.

6. The device for preventing host computer from freezing as described in claim 5, characterized in that, The second preset field set includes: request identifier field, tag field, requester segmentation validity information field, and requester segmentation information field; The content-addressable memory module extracts the third preset field set from the second completion response message, matches the third preset field set of the second completion response message with the second preset field set of all third messages, and if the match is successful, sends the second address corresponding to the fifth message and the third timestamp of the second completion response message to the address and resource control module; wherein, the third preset field set includes: request identifier field, tag field, destination segment validity information field and destination segment information field; the fifth message is the third message that successfully matches the second completion response message.

7. The device for preventing host computer from freezing as described in claim 6, characterized in that, Also includes: Delay statistics module; The content addressable memory module determines whether to perform transmission delay statistics on the fifth message based on the switching chip configuration. If yes, it sends a first signal to the address and resource control module. The first signal is a signal for the cache module to read the fifth message and perform transmission delay statistics. The address and resource control module generates a corresponding second read address signal, and the cache module sends the sixth message to the delay statistics module for delay statistics based on the second read address signal; wherein, the sixth message is the second message in the cache module that corresponds to the fifth message.

8. The device for preventing host computer from freezing as described in claim 7, characterized in that, The delay statistics module reads the first timestamp of the sixth message, determines the current message delay value of the destination port of the sixth message based on the first timestamp and the corresponding third timestamp, updates the current first average delay value of the destination port based on the current message delay value, obtains the second average delay value of the destination port, and performs delay statistics based on the second average delay value of the destination port, as follows: in, This indicates the current message delay value of the destination port of the sixth message; This indicates the current first average delay value of the destination port of the sixth message; This represents the second average delay value of the destination port of the sixth message; This indicates the preset weighting coefficients.

9. A switching chip, characterized in that, Includes the device for preventing host computer from freezing as described in any one of claims 1 to 8.

10. A method for preventing host computer from freezing, characterized in that, The device for preventing host computer hang-up as described in any one of claims 1 to 8 comprises: The message sent to the endpoint device is parsed and the message requiring response is filtered out. The message requiring response is then checked for validity. The message requiring response that passes the validity check is stamped with a first timestamp to obtain the corresponding first message. The first address in the cache module and the second address in the content addressable memory module are determined according to the bitmap. The first preset field set and the first timestamp in the first message are extracted, recorded as the second message, and written to the first address. The second preset field set in the first message is extracted, recorded as the third message, and written to the second address. The cache module is polled and checked to generate a corresponding first read address signal. The cache module is then read to obtain the fourth packet. The packet is checked according to the first preset field set and the corresponding first timestamp of the fourth packet to determine whether the corresponding first packet has timed out or the destination port is faulty. If so, a first completion response packet for routing back to the host is generated according to the first preset field set of the fourth packet. The address resources of the corresponding first address and second address are released according to the first address corresponding to the fourth packet. The second completion response message sent by the receiving endpoint device is matched with all the third messages in the content addressable memory module. If the match is successful, the address resources of the corresponding first address and second address are released according to the second address corresponding to the fifth message.

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