Pixel-level high-linearity PFM ADC and control method
By adding a detection compensation stage to the PFM ADC, and using the reference voltage adjustment and comparator circuit to detect the delay time to compensate for the reference voltage, the problem of uneven voltage variation under different photocurrent inputs is solved, and a pixel-level PFM ADC with high linearity and low power consumption is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN UNIV OF TECH
- Filing Date
- 2026-03-30
- Publication Date
- 2026-05-19
AI Technical Summary
Existing PFM ADCs exhibit varying voltage changes due to delay time under different photocurrent inputs, leading to input-output nonlinearity and affecting image quality.
A detection compensation stage is added to the PFM ADC. The delay time is detected by the reference voltage adjustment circuit and the comparator circuit, and the reference voltage is compensated to ensure that the voltage change on the integrating capacitor is the same under different photocurrent inputs. A small capacitor and a multiplexed comparator are used as a unity-gain amplifier.
A high linearity PFM ADC was achieved, reducing circuit power consumption while maintaining a suitable area, solving the nonlinearity problem, and improving imaging quality.
Smart Images
Figure CN122069443A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit image sensor technology, specifically relating to pixel-level high linearity PFM ADC, and also to a control method for pixel-level high linearity PFM ADC. Background Technology
[0002] Infrared image sensors have important applications in security monitoring, military equipment, meteorological monitoring and industrial production. Their main development directions include higher spatial resolution, greater dynamic range and faster response speed and frame rate.
[0003] Pixel-level pulse frequency modulation analog-to-digital converters (PFM ADCs) are commonly used readout circuit solutions in infrared image sensor research. They employ current-pulse modulation technology, which means that the integrated charge no longer depends on the power supply voltage and integrating capacitor, as is the case with traditional readout circuits, but rather on the number of digital pulse accumulations. This breaks through the limitations of integrated charge and dynamic range in traditional readout circuits, meeting the dynamic range requirements of infrared image sensors. However, the charge loss due to delay time varies under different photocurrent inputs. Especially under high light intensity conditions, the amount of charge lost per integration increases, leading to a significant increase in the voltage change per integration on the integrating capacitor, resulting in severe input-output nonlinearity. A pixel-level PFM ADC structure with high linearity can ensure accurate signal conversion and improve image quality. Summary of the Invention
[0004] The purpose of this invention is to provide a pixel-level high linearity PFM ADC, which solves the problem in the prior art where the voltage change is different under different photocurrent inputs due to the delay time, and greatly improves the linearity of the pixel-level PFM ADC.
[0005] Another objective of this invention is to provide a control method for a pixel-level high linearity PFM ADC.
[0006] The first technical solution adopted in this invention is a pixel-level high linearity PFM ADC, including an input stage circuit. The input stage circuit is connected to the positive input terminal of a comparator COMP. The negative input terminal of the comparator COMP is connected to a reference voltage adjustment circuit. The output terminal of the comparator COMP is connected to an output shaping circuit. The output of the output shaping circuit is connected to a counter. The output of the counter is used as the output digital code value of the PFM ADC.
[0007] The first technical solution of the present invention is further characterized in that,
[0008] The input stage circuit consists of a photodiode PD and a transmission transistor M1. The anode of the photodiode PD is connected to GND, and the cathode of the photodiode PD is connected to the source of the transmission transistor M1. The drain of the transmission transistor M1 is connected to the upper plate of the integrating capacitor Cint, and the lower plate of the integrating capacitor Cint is connected to GND. The drain of the transmission transistor M1 is also connected to the output terminal of the switch K1. The input terminal of the switch K1 is connected to the source of the reset transistor M2. The drain of the reset transistor M2 is connected to the power supply voltage VDD, and the gate of the reset transistor M2 is connected to the output terminal of the output shaping circuit.
[0009] The positive input terminal of comparator COMP is connected to the upper plate of the integrating capacitor. The output terminal of comparator COMP is connected to the output shaping circuit. The output terminal of comparator COMP is also connected to the input terminal of switch K7. The output terminal of switch K7 is connected to the negative input terminal of the comparator. The negative input terminal of comparator COMP is also connected to the reference voltage adjustment circuit.
[0010] The reference voltage adjustment circuit includes five switches K2~K6 and a small capacitor C1. The output of switch K2 is connected to the upper plate of capacitor C1. The input of switch K2 is connected to the fixed reference voltage Vref. The input of switch K6 is connected to the fixed reference voltage Vref. The output of switch K6 is connected to the upper plate of the small capacitor C1. The output of switch K6 is also connected to the input of switch K3. The output of switch K3 is connected to the negative input of comparator COMP. The fixed reference voltage Vref is also connected to the input of switch K4. The output of switch K4 is connected to the lower plate of small capacitor C1. The output of switch K4 is also connected to the input of switch K5. The output of switch K5 is connected to the negative input of the comparator.
[0011] The output shaping circuit includes three cascaded inverters INV1, INV2, and INV3. The input of inverter INV1 is connected to the output of comparator COMP. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the gate of reset transistor M2. The output of inverter INV3 is also connected to a counter. The output of the counter is the digital code value Dout of the entire PFM ADC.
[0012] The second technical solution adopted in this invention is a pixel-level high linearity PFM ADC control method, which adds a detection compensation stage before the PFM ADC integration and counting stage, and makes the voltage change on the integration capacitor Cint the same under different photocurrent inputs by compensating the reference voltage.
[0013] The second technical solution of the present invention is further characterized in that, The specific steps are as follows: Step 1: When starting work, the pixel first begins exposure. The input stage circuit generates a photocurrent signal to integrate the integrating capacitor Cint. The circuit enters the detection compensation stage t1. At this time, switch K1 is off, and the negative input terminal of the comparator is a fixed reference voltage Vref. When the voltage on the integrating capacitor Cint drops to the reference voltage, the comparator output flips to a low level. At this time, the integrating capacitor Cint is not reset through the reset transistor M2, but is reset to the reference voltage Vref through the on switch K2. At the same time, the comparator is reset, and the photocurrent continues to integrate the integrating capacitor Cint until the comparator flips for the second time. The interval between the two flips of the comparator is the detected delay time Td. Step 2: After the comparator flips for the second time, the integrating capacitor Cint is reset to the reference voltage Vref. The photocurrent is integrated over the integrating capacitor Cint. The integration time is the same as the delay time Td. The charge loss caused by the delay time is stored in the integrating capacitor Cint and converted into the corresponding voltage change. Step 3: Adjust the reference voltage by adjusting switches K3~K6; Step 4: After adjusting the reference voltage, the PFM ADC enters the integration and counting stage t2. First, switch K1 is turned on, and the integrating capacitor is reset to a high level through reset transistor M2. At this time, the comparator output is high, the pixel begins exposure, and the photocurrent integrates with the integrating capacitor. When the voltage on the integrating capacitor drops to the new reference voltage Vref1, the comparator flips to a low level, and the shaping circuit outputs a high level. This high level turns on reset transistor M2 to reset the integrating capacitor to a high level, thereby causing the comparator output to flip to a high level. The shaping circuit outputs a low level and turns off the reset transistor. The integrating current continues to integrate with the integrating capacitor Cint until the comparator flips again. The above integration-reset process is repeated. The shaping circuit outputs multiple pulse signals, and the counter counts the pulse signals. The counting result is the output digital code value Dout of the PFM ADC.
[0014] Step 3 is implemented in the following steps: In the reference voltage adjustment circuit, switch K6 is turned off, and switch K4 is turned on to connect the small capacitor C1 between the negative input terminal of the comparator and the reference voltage. Then, switch K7 is turned on to connect the output terminal of the comparator to the negative input terminal of the comparator, and the comparator is multiplexed as a unity-gain amplifier so that the voltage at the negative input terminal of the comparator is the same as the voltage of the upper plate of the integrating capacitor Cint. K3, K4, and K7 are turned off. At this time, the voltage of the upper plate of the small capacitor C1 is the fixed reference voltage Vref minus the corresponding voltage change converted in step 2. The voltage of the lower plate of the small capacitor C1 is floating, and the voltage value is the fixed reference voltage Vref. Then, switch K6 is turned on so that the voltage of the upper plate of the small capacitor C1 is the fixed reference voltage Vref, and the voltage of the lower plate of the small capacitor C1 becomes the fixed reference voltage Vref plus the corresponding voltage change converted in step 2. Then, the lower plate of the small capacitor C1 is connected to the negative input terminal of the comparator, and the voltage of the lower plate of the small capacitor C1 is used as the new reference voltage Vref1 in the normal integration counting stage, thus achieving the purpose of adjusting the reference voltage.
[0015] The beneficial effects of this invention are that the pixel-level high linearity PFM ADC circuit compensates for the reference voltage by detecting the delay time through a reference voltage adjustment circuit and a comparator circuit. This ensures that the single voltage change on the integrating capacitor is the same when different photocurrents are input during the integration counting stage, solving the nonlinearity problem caused by the delay time when different currents are input, and guaranteeing high linearity of input and output. Simultaneously, the use of a small capacitor C1 and a multiplexed comparator circuit to implement a unity-gain amplifier does not occupy excessive pixel area. Compensating for the reference voltage by detecting the delay reduces the requirement for comparator delay, thereby reducing circuit power consumption. Therefore, high linearity is achieved while also considering area and power consumption. Attached Figure Description
[0016] Figure 1 A schematic diagram of a pixel-level high linearity PFM ADC structure; Figure 2 This is the timing diagram of the high linearity PFM ADC of the present invention; Figure 3 This is the equivalent circuit diagram of the PFM ADC in the integration and counting stage of the present invention. Detailed Implementation
[0017] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0018] The present invention provides a pixel-level high linearity PFM ADC, the structure of which is as follows: Figure 1As shown, it includes an input stage circuit, which is connected to the positive input terminal of comparator COMP. The negative input terminal of comparator COMP is connected to a reference voltage adjustment circuit. The output terminal of comparator COMP is connected to an output shaping circuit. The output of the output shaping circuit is connected to a counter. The output of the counter is used as the output digital code value of the PFM ADC.
[0019] The input stage circuit consists of a photodiode PD and a transmission transistor M1. The anode of the photodiode PD is connected to GND, and the cathode of the photodiode PD is connected to the source of the transmission transistor M1. The drain of the transmission transistor M1 is connected to the upper plate of the integrating capacitor Cint, and the lower plate of the integrating capacitor Cint is connected to GND. The drain of the transmission transistor M1 is also connected to the output terminal of the switch K1. The input terminal of the switch K1 is connected to the source of the reset transistor M2. The drain of the reset transistor M2 is connected to the power supply voltage VDD, and the gate of the reset transistor M2 is connected to the output terminal of the output shaping circuit.
[0020] The positive input terminal of comparator COMP is connected to the upper plate of the integrating capacitor. The output terminal of comparator COMP is connected to the output shaping circuit. The output terminal of comparator COMP is also connected to the input terminal of switch K7. The output terminal of switch K7 is connected to the negative input terminal of the comparator. The negative input terminal of comparator COMP is also connected to the reference voltage adjustment circuit.
[0021] The reference voltage adjustment circuit includes five switches K2~K6 and a small capacitor C1. The output of switch K2 is connected to the upper plate of capacitor C1. The input of switch K2 is connected to the fixed reference voltage Vref. The input of switch K6 is connected to the fixed reference voltage Vref. The output of switch K6 is connected to the upper plate of the small capacitor C1. The output of switch K6 is also connected to the input of switch K3. The output of switch K3 is connected to the negative input of comparator COMP. The fixed reference voltage Vref is also connected to the input of switch K4. The output of switch K4 is connected to the lower plate of small capacitor C1. The output of switch K4 is also connected to the input of switch K5. The output of switch K5 is connected to the negative input of the comparator.
[0022] The output shaping circuit includes three cascaded inverters INV1, INV2, and INV3. The input of inverter INV1 is connected to the output of comparator COMP. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the gate of reset transistor M2. The output of inverter INV3 is also connected to a counter. The output of the counter is the digital code value Dout of the entire PFM ADC.
[0023] The pixel-level high linearity PFM ADC control method of the present invention adds a detection compensation stage before the integration and counting stage of the PFM ADC, and makes the voltage change on the integration capacitor Cint the same under different photocurrent inputs by compensating the reference voltage.
[0024] The specific steps are as follows: Step 1: When starting work, the pixel first begins exposure. The input stage circuit generates a photocurrent signal to integrate the integrating capacitor Cint. The circuit enters the detection compensation stage t1. At this time, switch K1 is off, and the negative input terminal of the comparator is a fixed reference voltage Vref. When the voltage on the integrating capacitor Cint drops to the reference voltage, the comparator output flips to a low level. At this time, the integrating capacitor Cint is not reset through the reset transistor M2, but is reset to the reference voltage Vref through the on switch K2. At the same time, the comparator is reset, and the photocurrent continues to integrate the integrating capacitor Cint until the comparator flips for the second time. The interval between the two flips of the comparator is the detected delay time Td. Step 2: After the comparator flips for the second time, the integrating capacitor Cint is reset to the reference voltage Vref. The photocurrent is integrated over the integrating capacitor Cint. The integration time is the same as the delay time Td. The charge loss caused by the delay time is stored in the integrating capacitor Cint and converted into the corresponding voltage change. Step 3: Adjust the reference voltage by adjusting switches K3~K6; Step 4: After adjusting the reference voltage, the PFM ADC enters the integration and counting stage t2. First, switch K1 is turned on, and the integrating capacitor is reset to a high level through reset transistor M2. At this time, the comparator output is high, the pixel begins exposure, and the photocurrent integrates with the integrating capacitor. When the voltage on the integrating capacitor drops to the new reference voltage Vref1, the comparator flips to a low level, and the shaping circuit outputs a high level. This high level turns on reset transistor M2 to reset the integrating capacitor to a high level, thereby causing the comparator output to flip to a high level. The shaping circuit outputs a low level and turns off the reset transistor. The integrating current continues to integrate with the integrating capacitor Cint until the comparator flips again. The above integration-reset process is repeated. The shaping circuit outputs multiple pulse signals, and the counter counts the pulse signals. The counting result is the output digital code value Dout of the PFM ADC.
[0025] Step 3 is implemented in the following steps: In the reference voltage adjustment circuit, switch K6 is turned off, and switch K4 is turned on to connect the small capacitor C1 between the negative input terminal of the comparator and the reference voltage. Then, switch K7 is turned on to connect the output terminal of the comparator to the negative input terminal of the comparator, and the comparator is multiplexed as a unity-gain amplifier so that the voltage at the negative input terminal of the comparator is the same as the voltage of the upper plate of the integrating capacitor Cint. K3, K4, and K7 are turned off. At this time, the voltage of the upper plate of the small capacitor C1 is the fixed reference voltage Vref minus the corresponding voltage change converted in step 2. The voltage of the lower plate of the small capacitor C1 is floating, and the voltage value is the fixed reference voltage Vref. Then, switch K6 is turned on so that the voltage of the upper plate of the small capacitor C1 is the fixed reference voltage Vref, and the voltage of the lower plate of the small capacitor C1 becomes the fixed reference voltage Vref plus the corresponding voltage change converted in step 2. Then, the lower plate of the small capacitor C1 is connected to the negative input terminal of the comparator, and the voltage of the lower plate of the small capacitor C1 is used as the new reference voltage Vref1 in the normal integration counting stage, thus achieving the purpose of adjusting the reference voltage.
[0026] Example 1 The pixel-level high linearity PFM ADC circuit of this invention, such as... Figure 1 As shown, it includes an input stage circuit, which is connected to the positive input terminal of a comparator. The negative input terminal of the comparator is connected to a reference voltage adjustment circuit. The output terminal of the comparator is connected to an output shaping circuit. The output of the output shaping circuit is connected to a counter. The output of the counter is used as the output digital code value Dout of the PFM ADC.
[0027] Example 2 The present invention provides a pixel-level high linearity PFM ADC, the structure of which is as follows: Figure 1 As shown, it includes an input stage circuit, which is connected to the positive input terminal of comparator COMP. The negative input terminal of comparator COMP is connected to a reference voltage adjustment circuit. The output terminal of comparator COMP is connected to an output shaping circuit. The output of the output shaping circuit is connected to a counter. The output of the counter is used as the output digital code value of the PFM ADC.
[0028] The input stage circuit consists of a photodiode PD and a transmission transistor M1. The anode of the photodiode PD is connected to GND, and the cathode of the photodiode PD is connected to the source of the transmission transistor M1. The drain of the transmission transistor M1 is connected to the upper plate of the integrating capacitor Cint, and the lower plate of the integrating capacitor Cint is connected to GND. The drain of the transmission transistor M1 is also connected to the output terminal of the switch K1. The input terminal of the switch K1 is connected to the source of the reset transistor M2. The drain of the reset transistor M2 is connected to the power supply voltage VDD, and the gate of the reset transistor M2 is connected to the output terminal of the output shaping circuit.
[0029] Example 3 The present invention provides a pixel-level high linearity PFM ADC, the structure of which is as follows: Figure 1As shown, it includes an input stage circuit, which is connected to the positive input terminal of comparator COMP. The negative input terminal of comparator COMP is connected to a reference voltage adjustment circuit. The output terminal of comparator COMP is connected to an output shaping circuit. The output of the output shaping circuit is connected to a counter. The output of the counter is used as the output digital code value of the PFM ADC.
[0030] The input stage circuit consists of a photodiode PD and a transmission transistor M1. The anode of the photodiode PD is connected to GND, and the cathode of the photodiode PD is connected to the source of the transmission transistor M1. The drain of the transmission transistor M1 is connected to the upper plate of the integrating capacitor Cint, and the lower plate of the integrating capacitor Cint is connected to GND. The drain of the transmission transistor M1 is also connected to the output terminal of the switch K1. The input terminal of the switch K1 is connected to the source of the reset transistor M2. The drain of the reset transistor M2 is connected to the power supply voltage VDD, and the gate of the reset transistor M2 is connected to the output terminal of the output shaping circuit.
[0031] The positive input terminal of comparator COMP is connected to the upper plate of the integrating capacitor. The output terminal of comparator COMP is connected to the output shaping circuit. The output terminal of comparator COMP is also connected to the input terminal of switch K7. The output terminal of switch K7 is connected to the negative input terminal of the comparator. The negative input terminal of comparator COMP is also connected to the reference voltage adjustment circuit.
[0032] The reference voltage adjustment circuit includes five switches K2~K6 and a small capacitor C1. The output of switch K2 is connected to the upper plate of capacitor C1. The input of switch K2 is connected to the fixed reference voltage Vref. The input of switch K6 is connected to the fixed reference voltage Vref. The output of switch K6 is connected to the upper plate of the small capacitor C1. The output of switch K6 is also connected to the input of switch K3. The output of switch K3 is connected to the negative input of comparator COMP. The fixed reference voltage Vref is also connected to the input of switch K4. The output of switch K4 is connected to the lower plate of small capacitor C1. The output of switch K4 is also connected to the input of switch K5. The output of switch K5 is connected to the negative input of the comparator.
[0033] Example 4 The pixel-level high linearity PFM ADC circuit includes a detection compensation stage t1 and an integration counting stage t2. In the detection compensation stage t1, the reference voltage adjustment circuit and comparator circuit detect the delay time and compensate the reference voltage accordingly, ensuring that the single voltage change on the integrating capacitor is the same under different photocurrent inputs during the integration counting stage. The operating timing is as follows: Figure 2As shown. The input stage circuit generates a photocurrent signal that integrates the integrating capacitor Cint. The circuit then enters the detection and compensation stage t1. At this time, the negative input of the comparator is a fixed reference voltage Vref. When the voltage on the integrating capacitor drops to the reference voltage Vref, the comparator output flips to a low level. Instead of resetting the integrating capacitor Cint through the reset transistor M2, the integrating capacitor Cint is reset to the reference voltage Vref through the on-switch K2. Simultaneously, the comparator is reset, and the photocurrent continues to integrate the integrating capacitor Cint until the comparator flips for the second time. The interval between the two flips of the comparator is used as the detected delay time Td. After the comparator flips for the second time, the voltage on the upper plate of the integrating capacitor is reset to the reference voltage Vref again. The photocurrent integrates the integrating capacitor Cint for the same delay time Td, storing the charge loss caused by the delay time on the integrating capacitor Cint and converting it into a corresponding voltage change.
[0034] Next, in the reference voltage adjustment circuit, switch K6 is turned off, and switch K4 is turned on, connecting the small capacitor C1 between the comparator's negative input and the fixed reference voltage Vref. Then, through switch K7, the comparator's output is connected to the comparator's negative input, using the comparator as a unity-gain amplifier, making the voltage at the comparator's negative input the same as the voltage on the upper plate of the integrating capacitor Cint. Switches K3, K4, and K7 are then turned off. At this point, the voltage on the upper plate of the small capacitor C1 is the fixed reference voltage Vref minus the voltage change due to the delay time. The lower plate of the small capacitor C1 is floating, and its voltage is the fixed reference voltage Vref. Then, switch K6 is turned on, making the voltage on the upper plate of the small capacitor C1 the voltage connected to the fixed reference voltage Vref. The voltage on the lower plate of the small capacitor C1 becomes the fixed reference voltage Vref plus the voltage change due to the delay time. This voltage on the lower plate of the small capacitor C1 is then used as the new reference voltage Vref1 for the normal integration counting phase through switch K5.
[0035] Example 5 During the integration counting phase t2, the integration-reset process is repeated on the integrating capacitor. The number of integration-reset cycles is used as the output code value of the PFM ADC. The equivalent circuit for the integration counting phase is as follows: Figure 3As shown, switches K1, K5, and K6 are on, while switches K2, K3, K4, and K7 are off, and Vtg is at a high level. During operation, the integrating capacitor is first reset to a high level via reset transistor M2. At this point, the comparator output is high, and pixel exposure begins. The photocurrent integrates with the integrating capacitor. When the voltage across the integrating capacitor drops to the new reference voltage Vref1, the comparator flips to a low level, and the shaping circuit outputs a high level. This high level activates reset transistor M2, resetting the integrating capacitor to a high level, causing the comparator output to flip back to a high level. The shaping circuit outputs a low level, the reset transistor turns off, and the integrating current continues to integrate with the integrating capacitor Cint until the comparator flips again. This integration-reset process is repeated during exposure. The shaping circuit output Vpulse consists of multiple pulse signals, which are counted by a counter. The count result is the digital code value Dout of the PFM ADC.
[0036] Example 6 The pixel-level high linearity PFM ADC control method of the present invention adds a detection compensation stage before the integration and counting stage of the PFM ADC, and makes the voltage change on the integration capacitor Cint the same under different photocurrent inputs by compensating the reference voltage.
[0037] The specific steps are as follows: Step 1: When starting work, the pixel first begins exposure. The input stage circuit generates a photocurrent signal to integrate the integrating capacitor Cint. The circuit enters the detection compensation stage t1. At this time, switch K1 is off, and the negative input terminal of the comparator is a fixed reference voltage Vref. When the voltage on the integrating capacitor Cint drops to the reference voltage, the comparator output flips to a low level. At this time, the integrating capacitor Cint is not reset through the reset transistor M2, but is reset to the reference voltage Vref through the on switch K2. At the same time, the comparator is reset, and the photocurrent continues to integrate the integrating capacitor Cint until the comparator flips for the second time. The interval between the two flips of the comparator is the detected delay time Td. Step 2: After the comparator flips for the second time, the integrating capacitor Cint is reset to the reference voltage Vref. The photocurrent is integrated over the integrating capacitor Cint. The integration time is the same as the delay time Td. The charge loss caused by the delay time is stored in the integrating capacitor Cint and converted into the corresponding voltage change. Step 3: Adjust the reference voltage by adjusting switches K3~K6; Step 4: After adjusting the reference voltage, the PFM ADC enters the integration and counting stage t2. First, switch K1 is turned on, and the integrating capacitor is reset to a high level through reset transistor M2. At this time, the comparator output is high, the pixel begins exposure, and the photocurrent integrates with the integrating capacitor. When the voltage on the integrating capacitor drops to the new reference voltage Vref1, the comparator flips to a low level, and the shaping circuit outputs a high level. This high level turns on reset transistor M2 to reset the integrating capacitor to a high level, thereby causing the comparator output to flip to a high level. The shaping circuit outputs a low level and turns off the reset transistor. The integrating current continues to integrate with the integrating capacitor Cint until the comparator flips again. The above integration-reset process is repeated. The shaping circuit outputs multiple pulse signals, and the counter counts the pulse signals. The counting result is the output digital code value Dout of the PFM ADC.
[0038] This invention presents a pixel-level high-linearity PFM ADC circuit. Based on a detection delay time compensation reference voltage strategy, it ensures that the single-time voltage change on the integrating capacitor remains the same under different photocurrent inputs during the integration and counting phase. This solves the nonlinearity problem caused by the delay time under different photocurrent inputs, guaranteeing high linearity of input and output. Furthermore, the use of a small capacitor C1 and a multiplexed comparator circuit to implement a unity-gain amplifier avoids occupying excessive pixel area. Compensating the reference voltage through detection delay reduces the requirements for comparator delay, thereby reducing circuit power consumption. Therefore, it achieves high linearity while balancing area and power consumption.
Claims
1. A pixel-level high linearity PFM ADC, characterized in that, It includes an input stage circuit, which is connected to the positive input terminal of comparator COMP. The negative input terminal of comparator COMP is connected to a reference voltage adjustment circuit. The output terminal of comparator COMP is connected to an output shaping circuit. The output of the output shaping circuit is connected to a counter. The output of the counter is used as the output digital code value of the PFM ADC.
2. The pixel-level high linearity PFM ADC according to claim 1, characterized in that, The input stage circuit consists of a photodiode PD and a transmission transistor M1. The anode of the photodiode PD is connected to GND, and the cathode of the photodiode PD is connected to the source of the transmission transistor M1. The drain of the transmission transistor M1 is connected to the upper plate of the integrating capacitor Cint, and the lower plate of the integrating capacitor Cint is connected to GND. The drain of the transmission transistor M1 is also connected to the output terminal of the switch K1. The input terminal of the switch K1 is connected to the source of the reset transistor M2. The drain of the reset transistor M2 is connected to the power supply voltage VDD, and the gate of the reset transistor M2 is connected to the output terminal of the output shaping circuit.
3. The pixel-level high linearity PFM ADC according to claim 2, characterized in that, The positive input terminal of the comparator COMP is connected to the upper plate of the integrating capacitor. The output terminal of the comparator COMP is connected to the output shaping circuit. The output terminal of the comparator COMP is also connected to the input terminal of switch K7. The output terminal of switch K7 is connected to the negative input terminal of the comparator. The negative input terminal of the comparator COMP is also connected to the reference voltage adjustment circuit.
4. The pixel-level high linearity PFM ADC according to claim 3, characterized in that, The reference voltage adjustment circuit includes five switches K2~K6 and a small capacitor C1. The output of switch K2 is connected to the upper plate of capacitor C1. The input of switch K2 is connected to the fixed reference voltage Vref. The input of switch K6 is connected to the fixed reference voltage Vref. The output of switch K6 is connected to the upper plate of the small capacitor C1. The output of switch K6 is also connected to the input of switch K3. The output of switch K3 is connected to the negative input of comparator COMP. The fixed reference voltage Vref is also connected to the input of switch K4. The output of switch K4 is connected to the lower plate of the small capacitor C1. The output of switch K4 is also connected to the input of switch K5. The output of switch K5 is connected to the negative input of the comparator.
5. The pixel-level high linearity PFM ADC according to claim 4, characterized in that, The output shaping circuit includes three cascaded inverters INV1, INV2, and INV3. The input of inverter INV1 is connected to the output of comparator COMP. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the gate of reset transistor M2. The output of inverter INV3 is also connected to a counter. The output of the counter is the digital code value Dout of the entire PFM ADC.
6. A control method for a pixel-level high linearity PFM ADC, characterized in that, A detection compensation stage is added before the PFM ADC integration and counting stage. The voltage change on the integration capacitor Cint is made the same under different photocurrent inputs by compensating the reference voltage.
7. The control method for a pixel-level high linearity PFM ADC according to claim 6, characterized in that, The specific steps are as follows: Step 1: When starting work, the pixel first begins exposure. The input stage circuit generates a photocurrent signal to integrate the integrating capacitor Cint. The circuit enters the detection compensation stage t1. At this time, switch K1 is off, and the negative input terminal of the comparator is a fixed reference voltage Vref. When the voltage on the integrating capacitor Cint drops to the reference voltage, the comparator output flips to a low level. At this time, the integrating capacitor Cint is not reset through the reset transistor M2, but is reset to the reference voltage Vref through the on switch K2. At the same time, the comparator is reset, and the photocurrent continues to integrate the integrating capacitor Cint until the comparator flips for the second time. The interval between the two flips of the comparator is the detected delay time Td. Step 2: After the comparator flips for the second time, the integrating capacitor Cint is reset to the reference voltage Vref. The photocurrent is integrated over the integrating capacitor Cint. The integration time is the same as the delay time Td. The charge loss caused by the delay time is stored in the integrating capacitor Cint and converted into the corresponding voltage change. Step 3: Adjust the reference voltage by adjusting switches K3~K6; Step 4: After adjusting the reference voltage, the PFM ADC enters the integration and counting stage t2. First, switch K1 is turned on, and the integrating capacitor is reset to a high level through reset transistor M2. At this time, the comparator output is high, the pixel begins exposure, and the photocurrent integrates with the integrating capacitor. When the voltage on the integrating capacitor drops to the new reference voltage Vref1, the comparator flips to a low level, and the shaping circuit outputs a high level. This high level turns on reset transistor M2 to reset the integrating capacitor to a high level, thereby causing the comparator output to flip to a high level. The shaping circuit outputs a low level and turns off the reset transistor. The integrating current continues to integrate with the integrating capacitor Cint until the comparator flips again. The above integration-reset process is repeated. The shaping circuit outputs multiple pulse signals, and the counter counts the pulse signals. The counting result is the output digital code value Dout of the PFM ADC.
8. The control method for a pixel-level high linearity PFM ADC according to claim 7, characterized in that, Step 3 is implemented in the following steps: In the reference voltage adjustment circuit, switch K6 is turned off, and switch K4 is turned on to connect the small capacitor C1 between the negative input terminal of the comparator and the reference voltage. Then, switch K7 is turned on to connect the output terminal of the comparator to the negative input terminal of the comparator, and the comparator is multiplexed as a unity-gain amplifier so that the voltage at the negative input terminal of the comparator is the same as the voltage of the upper plate of the integrating capacitor Cint. K3, K4, and K7 are turned off. At this time, the voltage of the upper plate of the small capacitor C1 is the fixed reference voltage Vref minus the corresponding voltage change converted in step 2. The voltage of the lower plate of the small capacitor C1 is floating, and the voltage value is the fixed reference voltage Vref. Then, switch K6 is turned on so that the voltage of the upper plate of the small capacitor C1 is the fixed reference voltage Vref, and the voltage of the lower plate of the small capacitor C1 becomes the fixed reference voltage Vref plus the corresponding voltage change converted in step 2. Then, the lower plate of the small capacitor C1 is connected to the negative input terminal of the comparator, and the voltage of the lower plate of the small capacitor C1 is used as the new reference voltage Vref1 in the normal integration counting stage, thus achieving the purpose of adjusting the reference voltage.