Multi-valued memory forming method and multi-valued memory
By designing a multi-value memory with a ring-shaped vertical transfer transistor structure, the problems of existing memory in terms of area, speed, leakage current and power consumption are solved, achieving higher storage density and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GALAXYCORE SHANGHAI
- Filing Date
- 2024-11-18
- Publication Date
- 2026-05-19
AI Technical Summary
Existing SRAM and DRAM memories have shortcomings in terms of area, speed, leakage current and power consumption, and also suffer from reset noise issues.
Design a multi-value memory that adopts a ring vertical transfer transistor structure. The floating diffusion region is surrounded by the ring vertical transfer transistor. The distance between the channel region and the gate dielectric layer is less than a preset threshold. It is formed by etching process to reduce electric field strength and improve gate control capability.
It reduces memory leakage current, increases storage density and reduces power consumption, while simplifying the manufacturing process and reducing refresh cycles.
Smart Images
Figure CN122069705A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a multi-value memory and a multi-value memory. Background Technology
[0002] Random access memory (RAM) allows data to be read from or written on demand, and the read / write speed is independent of the data's storage location. This type of memory has the fastest read / write speeds among memory types, but it loses its stored data when power is off, so it is mainly used to store data needed for short periods. Based on the type of information stored, RAM can be further divided into static random access memory (SRAM) and dynamic random access memory (DRAM).
[0003] An existing SRAM structure is as follows: Figure 1 As shown, its storage cell is a flip-flop composed of six MOS transistors. It has two stable states and is also called a bistable flip-flop. SRAM has a faster storage speed and lower power consumption. However, compared to DRAM, SRAM occupies a larger area for the same storage capacity.
[0004] An existing DRAM structure is as follows Figure 2 As shown, its memory cell is a memory circuit composed of a MOSFET M1 and a capacitor C1, where the MOSFET M1 acts as a switch and the capacitor C1 acts as a storage medium. The capacitor C1 in DRAM is generally formed using a stacked or trench configuration. The advantages are a small footprint and the ability to achieve large capacities. The disadvantages are that the manufacturing process is much more complex than logic circuits, and the access speed is slower than SRAM. Furthermore, DRAM memory cells store information based on the charge on the capacitor C1, which decreases over time and with temperature, thus requiring periodic refreshes to maintain the correct information stored. Simultaneously, since the capacitor C1 and MOSFET M1 are electrically interconnected, a contact hole exists for this interconnection. This contact hole needs to contact the silicon surface when interconnecting with the MOSFET. This interface between the contact hole and the silicon contains electron-active interface states. Due to the presence of these interface states, the surface has numerous defect centers, making it easy for charge carriers to be captured and released, potentially leading to difficult-to-control leakage current problems. Increased leakage current leads to shorter refresh times and increased power consumption. Additionally, both DRAM and SRAM exhibit reset noise during read and write operations. Summary of the Invention
[0005] The purpose of this invention is to provide a method for forming a multi-value memory, comprising: A charge storage region is formed in a semiconductor substrate, and a floating diffusion region is formed at the upper position of the charge storage region; A ring-shaped vertical transfer transistor is formed around the floating diffusion region. The spatial distance between any point in the channel region of the ring-shaped vertical transfer transistor and the gate dielectric layer of the ring-shaped vertical transfer transistor is less than a preset threshold, so that all silicon in the channel region of the floating diffusion region is depleted, thereby improving the gate control capability.
[0006] Furthermore, the floating diffusion region, the annular vertical transfer transistor channel, and the charge storage region all employ the same doping type and are formed in the same process.
[0007] Furthermore, the aspect ratio of the floating diffusion zone is not less than 1.2:1.
[0008] Furthermore, it also includes: using an etching process to maintain a preset height difference between the gate of the annular vertical transfer transistor and the floating diffusion region, so as to reduce the electric field strength between the floating diffusion region and the channel of the annular vertical transfer transistor.
[0009] Furthermore, the semiconductor substrate includes a first substrate and a second substrate, the second substrate being formed above the first substrate and having a doping type opposite to that of the first substrate, the first substrate being used to form the charge storage region, and the second substrate being used to form the annular vertical transfer transistor.
[0010] Further, forming a charge storage region in the semiconductor substrate includes: According to the first photolithography pattern, the semiconductor substrate is etched to form a first trench; A first dielectric layer is formed on the surface of the first trench; A first polycrystalline silicon layer is formed by filling the surface of the first dielectric layer with polycrystalline silicon material to form the storage capacitor of the charge storage region.
[0011] Furthermore, after forming the charge storage region, the method further includes: According to the second photolithography pattern, the surface of the charge storage region is etched to the interface between the first substrate and the second substrate to form an annular second trench, and the floating diffusion region is formed on the upper part of the charge storage region; The second trench is filled with a medium to form a second medium layer; A second polycrystalline silicon layer is formed by filling the surface of the second dielectric layer with polycrystalline silicon material. According to the third photolithography pattern, a portion of the second polysilicon layer is etched, such that the second polysilicon layer near the floating diffusion region is etched below the surface of the second substrate, and the second polysilicon layer above the adjacent charge storage region is disconnected, forming the gate of the annular vertical transfer transistor.
[0012] Furthermore, after forming the gate of the annular vertical transfer transistor, the method further includes: Ion implantation of the same type as the first substrate doping is performed in the floating diffusion region; Dopant ion implantation of the opposite type to that of the charge storage region is performed at the bottom of the second trench to form a dark current blocking structure and a channel barrier structure. The gate access voltage of the ring vertical transfer transistor causes the second substrate surrounded by the ring vertical transfer transistor to conduct, forming an electron transport channel.
[0013] The present invention also provides a multi-value memory, which is formed using the multi-value memory formation method described above.
[0014] Furthermore, the storage area of the multi-value memory includes multiple storage sub-columns, each storage sub-column including several storage cells and the floating diffusion region, and the storage cell including at least the charge storage region and the ring vertical transfer transistor.
[0015] This invention proposes a novel multi-value memory using the aforementioned scheme. It designs a ring-shaped vertical transistor structure, where the gate surrounds the entire floating diffusion region. The spatial distance between any point in the ring-shaped vertical transfer transistor channel region and the gate dielectric layer of the ring-shaped vertical transfer transistor is less than a preset threshold. This allows for complete channel exhaustion in the small-size direction, resulting in better channel control and further reducing transistor leakage current. The reduction in overall memory leakage current brings several benefits: Firstly, with the capacitance value remaining constant, lower leakage current results in a smaller least significant bit voltage, allowing the full-scale level to be divided into more parts, thus storing more information and increasing storage density. Secondly, while maintaining the same number of storage bits, a smaller capacitor is required, allowing for a thicker capacitor dielectric layer to reduce capacitor leakage and further lower the overall leakage level. Thirdly, a thicker dielectric layer also reduces manufacturing complexity and improves product yield. Furthermore, reduced leakage current also reduces refresh cycles and lowers memory power consumption. Attached Figure Description
[0016] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.
[0017] Figures 1-8This is a schematic diagram of a method for forming a multi-value memory in one embodiment of the present invention.
[0018] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation
[0019] This invention provides a method for forming a multi-value memory. Specifically, it includes the following steps: Step S100: A charge storage region 110 is formed in the semiconductor substrate 100, and a floating diffusion region (FD) is formed at the upper position of the charge storage region 110. Step S200: A ring-shaped vertical transfer transistor (VTG) is formed around the floating diffusion region (FD). The spatial distance between any point in the channel region of the ring-shaped vertical transfer transistor and the gate dielectric layer 141 of the ring-shaped vertical transfer transistor is less than a preset threshold, so that all silicon in the channel region of the floating diffusion region (FD) is depleted, thereby improving the gate control capability.
[0020] In an optional implementation, the floating diffusion region (FD), the annular vertical transfer transistor channel, and the storage region of the charge storage region 110 are all doped with the same type of doping, such as all P-type doping or all N-type doping, and are formed in the same process.
[0021] Preferably, the aspect ratio of the floating diffusion region (FD) is not less than 1.2:1. The elongated floating diffusion region (FD) ensures that the spatial distance between any point in the surrounding annular vertical transfer transistor channel region and the gate dielectric layer 141 of the annular vertical transfer transistor is less than a preset threshold. This allows the channel to be completely exhausted in a small-dimensional direction, resulting in better channel control and further reducing transistor leakage current. In an optional embodiment based on this, when forming the annular vertical transfer transistor (VTG) in step S200, an etching process can be used to maintain a preset height difference between the gate of the annular vertical transfer transistor (VTG) and the floating diffusion region (FD) to reduce the electric field strength between the floating diffusion region and the channel of the annular vertical transfer transistor.
[0022] In optional implementations, such as Figure 3 As shown, the semiconductor substrate 100 includes a first substrate 100a and a second substrate 100b, the second substrate 100b being formed above the first substrate 100a and having a doping type opposite to that of the first substrate 100a. The first substrate 100a is used to form the charge storage region 110, and the second substrate 100b is used to form the ring vertical transfer transistor (VTG).
[0023] Optionally, in step S100, forming the charge storage region 110 in the semiconductor substrate 100 includes: Step S110: Etch the semiconductor substrate 100 according to the first photolithography pattern to form the first trench 120; Step S120: A first dielectric layer 121 is formed on the surface of the first trench 120, such as... Figure 4 As shown; Step S130: Fill the surface of the first dielectric layer 121 with polycrystalline silicon material to form a first polycrystalline silicon layer 130, thereby forming the storage capacitor of the charge storage region 110, such as... Figure 5 As shown.
[0024] Preferably, after forming the charge storage region 110 in step S100, the method further includes: Step S141: According to the second photolithography pattern, etch the surface of the charge storage region 110 to the interface between the first substrate 100a and the second substrate 100b to form an annular second trench 140, and form the floating diffusion region (FD) region on the upper part of the charge storage region 110; Step S142: Fill the second trench 140 with a medium to form a second medium layer 141, such as... Figure 6 As shown; Step S143: Fill the surface of the second dielectric layer 141 with polycrystalline silicon material to form a second polycrystalline silicon layer 150, such as... Figure 7 As shown; Step S144: According to the third photolithography pattern, a portion of the second polysilicon layer 150 is etched, such that the second polysilicon layer 150 near the floating diffusion region (FD) is etched below the surface of the second substrate 100b, and the second polysilicon layer 150 above the adjacent charge storage region 110 is disconnected, forming the gate 151 of the ring vertical transfer transistor (VTG), as shown. Figure 8 As shown.
[0025] Optionally, after forming the gate of the annular vertical transfer transistor (VTG) in step S144, the method further includes: Step S151: Perform ion implantation in the floating diffusion region (FD) with the same doping type as the first substrate 100a, such as... Figure 8 Central 160 area; Step S152: Perform dopant ion implantation at the bottom of the second trench with a doping type opposite to that of the charge storage region 110 to form a dark current blocking structure and a channel barrier structure. Step S153: Apply a gate voltage to the ring vertical transfer transistor (VTG) to turn on the second substrate 100b surrounded by the ring vertical transfer transistor (VTG), thereby forming an electron transport channel.
[0026] Regarding the step function diagram after ADC conversion, assuming the memory has N bits, the full-scale input voltage range is the full range (FRS). The width of each step represents the minimum effective level (LSB), and 2N represents the total number of ADC codes. The LSB equals the FRS divided by 2N, but this requires the LSB to be larger than the leakage current level in the entire circuit; otherwise, the input voltage cannot be quantized. Therefore, reducing leakage current helps to reduce the LSB voltage level range, allowing the input voltage to be divided into more parts, enabling the storage of more bits and increasing storage density. Furthermore, assuming the same number of bits is maintained, smaller capacitors are required, allowing for a thicker capacitor dielectric layer. This reduces capacitor leakage current, thus lowering the overall leakage level. A thicker dielectric layer also reduces manufacturing complexity and improves product yield. Simultaneously, reduced leakage current decreases refresh cycles and lowers memory power consumption.
[0027] The present invention also provides a multi-value memory, which is formed using the multi-value memory formation method described above.
[0028] In an optional implementation, the storage area of the multi-value memory includes multiple storage sub-columns, each storage sub-column including several storage cells and the floating diffusion region, wherein the storage cells include at least the charge storage region and the annular vertical transfer transistor.
[0029] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.
Claims
1. A method for forming a multi-value memory, characterized in that, include: A charge storage region is formed in a semiconductor substrate, and a floating diffusion region is formed at the upper position of the charge storage region; A ring-shaped vertical transfer transistor is formed around the floating diffusion region. The spatial distance between any point in the channel region of the ring-shaped vertical transfer transistor and the gate dielectric layer of the ring-shaped vertical transfer transistor is less than a preset threshold, so that all silicon in the channel region of the floating diffusion region is depleted, thereby improving the gate control capability.
2. The method for forming a multi-value memory as described in claim 1, characterized in that, The floating diffusion region, the annular vertical transfer transistor channel, and the charge storage region all use the same doping type and are formed in the same process.
3. The method for forming a multi-value memory as described in claim 1, characterized in that, The aspect ratio of the floating diffusion zone is not less than 1.2:
1.
4. The method for forming a multi-value memory as described in claim 1, characterized in that, Also includes: By using an etching process, a preset height difference is maintained between the gate of the annular vertical transfer transistor and the floating diffusion region, thereby reducing the electric field strength between the floating diffusion region and the channel of the annular vertical transfer transistor.
5. The method for forming a multi-value memory as described in claim 1, characterized in that, The semiconductor substrate includes a first substrate and a second substrate, the second substrate being formed above the first substrate and having a doping type opposite to that of the first substrate. The first substrate is used to form the charge storage region, and the second substrate is used to form the annular vertical transfer transistor.
6. The method for forming a multi-value memory as described in claim 5, characterized in that, The formation of the charge storage region in the semiconductor substrate includes: According to the first photolithography pattern, the semiconductor substrate is etched to form a first trench; A first dielectric layer is formed on the surface of the first trench; A first polycrystalline silicon layer is formed by filling the surface of the first dielectric layer with polycrystalline silicon material to form the storage capacitor of the charge storage region.
7. The method for forming a multi-value memory as described in claim 6, characterized in that, After forming the charge storage region, the method further includes: According to the second photolithography pattern, the surface of the charge storage region is etched to the interface between the first substrate and the second substrate to form an annular second trench, and the floating diffusion region is formed on the upper part of the charge storage region; The second trench is filled with a medium to form a second medium layer; A second polycrystalline silicon layer is formed by filling the surface of the second dielectric layer with polycrystalline silicon material. According to the third photolithography pattern, a portion of the second polysilicon layer is etched, such that the second polysilicon layer near the floating diffusion region is etched below the surface of the second substrate, and the second polysilicon layer above the adjacent charge storage region is disconnected, forming the gate of the annular vertical transfer transistor.
8. The method for forming a multi-value memory as described in claim 7, characterized in that, After forming the gate of the annular vertical transfer transistor, the method further includes: Ion implantation of the same type as the first substrate doping is performed in the floating diffusion region; Dopant ion implantation of the opposite type to that of the charge storage region is performed at the bottom of the second trench to form a dark current blocking structure and a channel barrier structure. The gate access voltage of the ring vertical transfer transistor causes the second substrate surrounded by the ring vertical transfer transistor to conduct, forming an electron transport channel.
9. A multi-value memory, characterized in that, It is formed using the multi-value memory formation method as described in any one of claims 1-8.
10. The multi-value memory as described in claim 9, characterized in that, The storage area of the multi-value memory includes multiple storage sub-columns, each storage sub-column including several storage cells and the floating diffusion region, and the storage cells including at least the charge storage region and the ring vertical transfer transistor.