Semiconductor structure and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure and a storage system. The semiconductor structure comprises gate structures, first isolation structures located between the adjacent gate structures and first doping layers extending in the first direction. The plurality of gate structures are positioned on one side of the first doping layer along the second direction and are arranged at intervals in the first direction, and each gate structure comprises a gate layer and a first gap which is positioned between the gate layer and the first doping layer along the second direction and extends into the first doping layer along the second direction; the gate structure is provided with a first surface deviating from one side of the first doping layer in the second direction; a second surface, facing one side of the first surface along the second direction, of the first doping layer between the gate structure and the first isolation structure has a first junction position with the side wall of the gate structure and has a second junction position with the side wall of the first isolation structure, and the second junction position is located between the first junction position and the first surface in the second direction; the second direction intersects the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Memory can include Random Access Memory (RAM), Read Only Memory (ROM), and cache. RAM can be further divided into Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Therefore, compared to SRAM, a single bit of data in DRAM requires only one capacitor and one transistor to process, resulting in a relatively simpler structure. Transistors in semiconductor structures such as DRAM include vertical transistors.

[0003] However, the performance of semiconductor structures, taking memory as an example, needs to be improved. Summary of the Invention

[0004] This application provides a semiconductor structure, a method for fabricating the semiconductor structure, and a storage system that can at least partially solve the above-mentioned problems or other problems in the art.

[0005] This application provides a semiconductor structure, including a first doped layer, a gate structure, and a first isolation structure. The first doped layer extends along a first direction. A plurality of gate structures are located on one side of the first doped layer along a second direction and are spaced apart in the first direction. Each gate structure includes a gate layer and a first gap located between the gate layer and the first doped layer along the second direction. The gate structure has a first surface on the side facing away from the first doped layer in the second direction. The first isolation structure is located between adjacent gate structures. The first gap extends into the first doped layer along the second direction. The second surface of the first doped layer between the gate structure and the first isolation structure has a first boundary position with the sidewall of the gate structure and a second boundary position with the sidewall of the first isolation structure in the second direction. The second boundary position is located between the first boundary position and the first surface in the second direction. The second direction intersects the first direction.

[0006] In some embodiments, the spacing between the second surface and the first surface in the second direction increases from the first isolation structure to the gate structure.

[0007] In some embodiments, the distance between the first boundary position and the second boundary position along the second direction is 12nm to 30nm.

[0008] In some embodiments, the semiconductor structure further includes a semiconductor pillar located on one side of the first doped layer along the second direction and between the gate structure and the first isolation structure.

[0009] In some embodiments, the gate structure further includes a gate dielectric layer and an insulating layer; the gate dielectric layer is located between the gate layer and the semiconductor pillar; the insulating layer is located on the side of the gate layer away from the semiconductor pillar; wherein the first gap is also located along a second direction between the gate dielectric layer and the first doped layer and between the insulating layer and the first doped layer.

[0010] In some implementations, a portion of the first gap is located between the insulating layer and the gate dielectric layer in a first direction.

[0011] In some embodiments, the first doped layer also extends to a portion of the gate dielectric layer on the side surface opposite to the gate layer along a first direction.

[0012] In some embodiments, the first isolation structure includes a first isolation portion, a second gap, and a second isolation portion. The first isolation portion is located between adjacent semiconductor pillars along a first direction; the second gap is located between the first isolation portion and the first doped layer along a second direction; and the second isolation portion is located between the second gap and the semiconductor pillars and is located between a portion of the first isolation portion and the first doped layer in the second direction.

[0013] In some embodiments, the first doped layer also extends to a portion of the second isolation portion on the side surface opposite to the second void along the first direction.

[0014] In some embodiments, the semiconductor structure further includes bit lines located on the side of the first doped layer away from the semiconductor pillar and extending along a first direction.

[0015] This application also provides a method for fabricating a semiconductor structure, comprising: forming a first doped layer extending along a first direction; forming a gate structure, wherein a plurality of gate structures are spaced apart in the first direction; forming a first isolation structure; wherein the gate structure is located on one side of the first doped layer along a second direction, the gate structure includes a gate layer and a first gap located between the gate layer and the first doped layer along the second direction, the gate structure has a first surface on the side of the second direction away from the first doped layer, and the first isolation structure is located between adjacent gate structures; wherein the first gap extends into the first doped layer along the second direction; the second surface of the first doped layer between the gate structure and the first isolation structure on the side of the first surface along the second direction has a first boundary position with the sidewall of the gate structure and a second boundary position with the sidewall of the first isolation structure, the second boundary position being located between the first boundary position and the first surface in the second direction; wherein the second direction intersects the first direction.

[0016] In some embodiments, forming a gate structure includes: forming a first trench extending along a third direction in a semiconductor layer, wherein a plurality of first trenches are arranged along a first direction; and forming a gate structure in the first trench; wherein the third direction intersects the first direction and the second direction.

[0017] In some embodiments, forming the first isolation structure includes: forming a second trench extending in a third direction in a semiconductor layer, wherein the size of the second trench is smaller than the size of the first trench in a second direction; and forming the first isolation structure in the second trench; wherein a portion of the semiconductor layer located between the first trench and the second trench and located on one side of the first doped layer along the second direction forms a semiconductor pillar.

[0018] In some embodiments, forming a first doped layer extending along a first direction includes: forming a first doped portion in a semiconductor layer on the side of the first trench opposite to the second direction, the first doped portion further extending to the side of the first trench in the first direction; and forming a second doped portion in a semiconductor layer on the side of the second trench opposite to the second direction, the second doped portion further extending to the side of the second trench in the first direction; wherein the second doped portion is connected to the first doped portion and constitutes the first doped layer.

[0019] In some embodiments, the preparation method further includes: forming a first protective layer on the inner wall of the first groove; wherein forming the first doped portion includes: performing ion implantation on the semiconductor layer on the side of the first groove opposite to the second direction through the first protective layer to form a first initial doped portion; and annealing the first initial doped portion to form the first doped portion; wherein the preparation method further includes: removing the first protective layer.

[0020] In some embodiments, forming a first isolation structure in a second slot includes: forming a first initial isolation structure and a first sacrificial layer in the second slot, the first initial isolation structure surrounding the sidewalls of the first sacrificial layer and the surfaces of the first sacrificial layer on both sides along a second direction; removing a portion of the first initial isolation structure located between the first sacrificial layer and the first doped layer along the second direction; and removing the first sacrificial layer to form a second void; wherein the remaining portion of the first initial isolation structure and the second void form the first isolation structure.

[0021] In some embodiments, forming a gate structure in a first slot includes: forming an initial gate dielectric layer on the sidewall of the first slot and on the inner wall of the first slot along the side opposite to the second direction; forming an initial gate layer in the first slot, the initial gate layer being located on the side of the initial gate dielectric layer away from the semiconductor pillar and the first doped layer; removing a portion of the initial gate dielectric layer located on the inner wall of the first slot along the side opposite to the second direction, the portion of the initial gate dielectric layer located on the sidewall of the first slot forming a gate dielectric layer; and removing a portion of the initial gate layer located between the gate dielectric layer and the first doped layer, the portion of the initial gate layer located on the side of the gate dielectric layer away from the semiconductor pillar forming a gate layer; wherein a first gap is also located between the gate dielectric layer and the first doped layer along the second direction.

[0022] In some embodiments, removing the portion of the initial gate dielectric layer located on the side of the first slot opposite to the second direction includes: removing the portion of the initial gate dielectric layer located on the side of the first slot opposite to the second direction from the side of the first doped layer; wherein, removing the portion of the initial gate layer located between the gate dielectric layer and the first doped layer includes: removing the portion of the initial gate layer located between the gate dielectric layer and the first doped layer from the side of the first doped layer opposite to the second direction.

[0023] In some embodiments, forming the gate structure in the first slot further includes: forming an insulating layer in the first slot; wherein the insulating layer is located on the side of the gate layer away from the gate dielectric layer; wherein the first void is also located between the insulating layer and the first doped layer along a second direction.

[0024] In another aspect, this application provides a storage system including a controller and a semiconductor structure as described in any of the embodiments above, wherein the controller is coupled to the semiconductor structure and is used to control the semiconductor structure to store data. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0026] Figure 1This is a schematic diagram of a semiconductor structure according to an embodiment of this application;

[0027] Figure 2 For along Figure 1 A schematic diagram of the first doped layer, the semiconductor pillar, and the depletion region formed by the first doped layer and the semiconductor pillar;

[0028] Figure 3 This is a schematic diagram of a semiconductor structure according to another embodiment of this application;

[0029] Figure 4 for Figure 3 A schematic diagram of the first doped layer, the semiconductor pillar, and the depletion region formed by the first doped layer and the semiconductor pillar;

[0030] Figure 5 for Figure 3 A top view of the semiconductor structure;

[0031] Figure 6 This is a schematic diagram of a semiconductor structure according to another embodiment of this application;

[0032] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0033] Figures 8 to 33 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application;

[0034] Figure 34 This is a block diagram of a system having a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0035] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0038] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0039] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0041] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0042] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] This application provides a semiconductor structure in some embodiments. Figure 1 This is a schematic diagram of a semiconductor structure according to one embodiment of this application. Figure 2 For along Figure 1 A schematic diagram of the first doped layer, the semiconductor pillar, and the depletion region formed by the first doped layer and the semiconductor pillar.

[0044] refer to Figure 1 The semiconductor structure includes a first doped layer 110, a gate structure 120, a first isolation structure 130, and a semiconductor pillar F. Multiple gate structures 120 are spaced apart in a first direction X and located on one side of the first doped layer 110 along a second direction Z. Each gate structure 120 includes a gate layer 121, a gate dielectric layer 122, an insulating layer 123, and a first gap 124. The first gap 124 is located along the second direction Z between the gate layer 121 and the first doped layer 110, between the gate dielectric layer 122 and the first doped layer 110, and between the insulating layer 123 and the first doped layer 110. The first gap 124 extends along the second direction Z into the first doped layer 110. The first isolation structure 130 is located between adjacent gate structures 120. The first isolation structures 130 are spaced apart from the first doped layers 110 on both sides of the second direction Z. The semiconductor pillar F is located between the gate structure 120 and the first isolation structure 130. The gate structure 120 has a first surface on the side opposite to the first doped layer 110 in the second direction Z, and the first doped layer 110 has a second surface on the side facing the first surface in the second direction Z. The spacing between the second surface and the first surface in the second direction Z decreases from the first isolation structure 130 to the gate structure 120.

[0045] refer to Figure 2 L11 indicates that the sidewall of the first gap 124 will not induce a leakage current channel defect, while L21 indicates that the sidewall of the first gap 124 will induce a leakage current channel defect. It can be seen that the number of defects L21 needs to be reduced and the leakage current of the semiconductor structure needs to be reduced.

[0046] Other embodiments of this application provide a semiconductor structure. Figure 3 This is a schematic diagram of the semiconductor structure 10000 according to other embodiments of this application. Figure 4 for Figure 3 A schematic diagram of the first doped layer 210, the semiconductor pillar F, and the depletion region H formed by the first doped layer 210 and the semiconductor pillar F. Figure 5 for Figure 3 A top view of the semiconductor structure 10000. Figure 6 This is a schematic diagram of the semiconductor structure 10000 according to other embodiments of this application. Figure 6 for Figure 5 A cross-sectional view along the cutting line N1-M2.

[0047] refer to Figure 3 and Figure 6 The semiconductor structure 10000 includes a first doped layer 210, a gate structure 220, and a first isolation structure 230. The first doped layer 210 extends along a first direction X.

[0048] refer to Figure 3 and Figure 6Multiple gate structures 220 are located on one side of the first doped layer 210 along the second direction Z and spaced apart in the first direction X. Each gate structure 220 includes a gate layer 221 and a first gap 224 located between the gate layer 221 and the first doped layer 210 along the second direction Z. The gate structure 220 has a first surface T1 on the side of the second direction Z away from the first doped layer 210. A first isolation structure 230 is located between adjacent gate structures 220.

[0049] refer to Figure 3 and Figure 6 The first gap 224 extends along the second direction Z into the first doped layer 210. The second surface T2 of the first doped layer 210 between the gate structure 220 and the first isolation structure 230 has a first boundary position T21 with the sidewall of the gate structure 220 and a second boundary position T22 with the sidewall of the first isolation structure 230. The second boundary position T22 is located between the first boundary position T21 and the first surface T1 in the second direction Z.

[0050] The second direction Z intersects the first direction X. For example, the second direction Z is perpendicular to the first direction X.

[0051] In this embodiment of the semiconductor structure 10000, the first gap 224 is used to reduce the parasitic capacitance between the gate structure 220 and the surrounding structures. Since the second boundary position T22 is located between the first boundary position T21 and the first surface T1 in the second direction Z, the first doped layer 210 can extend to a larger area of ​​the sidewall of the gate structure 220. This results in the interface between the first doped layer 210 and the semiconductor pillar F facing the first surface T1 being further away from the side surface of the first gap 224 facing away from the gate layer 221 in the second direction Z. The depletion region H formed by the first doped layer 210 and the semiconductor pillar F (reference) Figure 4 The side surface of the gate layer 221 that is further away from the first gap 224 along the second direction Z reduces the number of defects from the sidewall surface of the first gap 224 that come into contact with the depletion region H, reduces the degree of leakage current induction of the depletion region H by the defects, reduces the leakage current path of the depletion region H, and reduces leakage current.

[0052] refer to Figure 4 In the semiconductor structure 10000 in this application embodiment, L1 indicates that the sidewall of the first gap 224 will not induce a leakage channel defect, and L2 indicates that the sidewall of the first gap 224 will induce a leakage channel defect. It can be seen that the number of defects L2 is reduced, the degree of leakage induction of defects L2 in the depletion region H is reduced, and the leakage is reduced.

[0053] In some embodiments, the spacing between the second surface T2 and the first surface T1 in the second direction Z increases from the first isolation structure 230 to the gate structure 220, further reducing the number of defects from the sidewall surface of the first gap 224 that are in contact with the depletion region H, and further reducing the leakage path of the depletion region H.

[0054] In some embodiments, the distance between the first boundary position T21 and the second boundary position T22 along the second direction Z is 12nm to 30nm, for example, 12nm, 15nm, 18nm, 20nm, 25nm, or 30nm. A distance greater than or equal to 12nm between the first boundary position T21 and the second boundary position T22 along the second direction Z effectively reduces the induction of defects on the depletion region H formed by the first doped layer 210 and the semiconductor pillar F, effectively reduces the leakage current path in the depletion region H, and effectively reduces leakage current. A distance less than or equal to 30nm between the first boundary position T21 and the second boundary position T22 along the second direction Z makes the process easier to implement.

[0055] In some implementations, reference Figure 3 , Figure 5 and Figure 6 The semiconductor structure 10000 also includes a semiconductor pillar F, which is located on one side of the first doped layer 210 along the second direction Z and between the gate structure 220 and the first isolation structure 230.

[0056] In some embodiments, the material of the semiconductor pillar F includes any one of single-crystal silicon, single-crystal germanium, germanium silicon, silicon carbon, and group III-V compound semiconductor materials and group II-VI compound semiconductor materials. The material of the semiconductor pillar F may also be at least one of other semiconductor materials known in the art.

[0057] In some embodiments, the portion of the semiconductor pillar F located on the side of the first doped layer 210 facing the first surface T1 is spaced apart from the first gap 224. In other words, the first gap 224 does not contact the portion of the semiconductor pillar F located on the side of the first doped layer 210 facing the first surface T1, so that the portion of the semiconductor pillar F located on the side of the first doped layer 210 facing the first surface T1 can be kept away from defects on the sidewall of the first gap 224, effectively reducing leakage current.

[0058] In other embodiments, the sidewalls of the first gap 224 may expose a portion of the semiconductor pillar F.

[0059] In some implementations, reference Figure 3 , Figure 5 and Figure 6The gate structure 220 also includes a gate dielectric layer 222 and an insulating layer 223. The gate dielectric layer 222 is located between the gate layer 221 and the semiconductor pillar F, and the insulating layer 223 is located on the side of the gate layer 221 away from the semiconductor pillar F. The first gap 224 is also located along the second direction Z between the gate dielectric layer 222 and the first doped layer 210 and between the insulating layer 223 and the first doped layer 210.

[0060] In some embodiments, the gate dielectric layer 222 may be made of a high-k (dielectric constant) dielectric material, where the dielectric constant K may be greater than 3.9, for example. The material of the gate dielectric layer 222 may include any one of alumina, hafnium dioxide, zirconium dioxide, lanthanum oxide, and titanium oxide. In other embodiments, the material of the gate dielectric layer 222 is silicon oxide.

[0061] In some embodiments, the insulating layer 223 is made of materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0062] In some embodiments, the material of the gate layer 221 includes any one of a metal gate material and a polysilicon gate material. For example, the material of the gate layer 221 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, or silicides.

[0063] In some embodiments, a portion of the first gap 224 is located between the insulating layer 223 and the gate dielectric layer 222 in the first direction X. This increases the space of the first gap 224, which is more helpful in reducing the parasitic capacitance between the gate structure 220 and the surrounding structures.

[0064] In some embodiments, the first doped layer 210 further extends to a portion of the gate dielectric layer 222 on the side surface opposite to the gate layer 221 along the first direction X. In other words, the first boundary location T21 is located on the sidewall surface of the gate dielectric layer 222 opposite to the gate layer 221.

[0065] In other embodiments, the first boundary position T21 is located on the sidewall surface of the first gap 224.

[0066] The first isolation structure 230 is used to reduce electrical interference between adjacent gate structures 220.

[0067] In some implementations, reference Figure 3 and Figure 6The first isolation structure 230 includes a first isolation portion 231, a second isolation portion 232, and a second gap 233. The first isolation portion 231 is located between adjacent semiconductor pillars F along a first direction X. The second gap 233 is located between the first isolation portion 231 and the first doped layer 210 along a second direction Z. The second isolation portion 232 is located between the second gap 233 and the semiconductor pillars F, and also partially between the first isolation portion 231 and the first doped layer 210 in the second direction Z. The second gap 233 is used to reduce the parasitic capacitance of the semiconductor structure 10000.

[0068] In some embodiments, the material of the first isolation portion 231 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the second isolation portion 232 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0069] In other embodiments, the first isolation structure may not include the second gap.

[0070] In some embodiments, the portion of the semiconductor pillar F located on the side of the first doped layer 210 facing the first surface T1 is spaced apart from the second gap 233. In other words, the second gap 233 does not contact the portion of the semiconductor pillar F located on the side of the first doped layer 210 facing the first surface T1, so that the portion of the semiconductor pillar F located on the side of the first doped layer 210 facing the first surface T1 can be kept away from defects on the sidewall of the second gap 233, further reducing leakage current.

[0071] In other embodiments, the sidewalls of the second gap 233 may expose a portion of the semiconductor pillar F.

[0072] In some embodiments, the first doped layer 210 also extends to a portion of the second isolation portion 232 on the side surface opposite to the second void 233 along the first direction X.

[0073] In some implementations, reference Figure 3 and Figure 6 The semiconductor structure 10000 also includes a bit line 200, which is located on the side of the first doped layer 210 away from the semiconductor pillar F and extends along the first direction X.

[0074] In some implementations, reference Figure 5 The semiconductor structure 10000 further includes a second isolation structure 2001a, which is located between adjacent semiconductor pillars F along the third direction Y and between the gate structure 220 and the first isolation structure 230; wherein the third direction Y intersects the first direction X and the second direction Z. For example, the third direction Y is perpendicular to the first direction X and perpendicular to the second direction Z.

[0075] In some embodiments, the material of the second isolation structure 2001a is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0076] In some implementations, reference Figure 6 The semiconductor structure 10000 further includes a second doped layer 300, which is located in the semiconductor pillar F and on the side of the gate layer 221 away from the first doped layer 210 in the second direction Z; wherein the second doped layer 300 is the source region and the first doped layer 210 is the drain region; or, the second doped layer 300 is the drain region and the first doped layer 210 is the source region.

[0077] In some implementations, reference Figure 6 The semiconductor structure 10000 also includes a memory cell 302, which is located on the side of the second doped layer 300 away from the first doped layer 210 and is connected to the second doped layer 300.

[0078] In some embodiments, the storage unit 302 includes at least one of a dynamic random access memory (DRAM), a phase change memory (PCM) unit, and a ferroelectric memory unit.

[0079] In some embodiments, storage unit 302 is a capacitor for storing charge as binary information stored by the corresponding storage unit 302. In some embodiments, storage unit 302 is a phase change memory (PCM) element (e.g., including chalcogenide alloys) for storing binary information based on the different resistivities in amorphous and crystalline phases. In other embodiments, storage unit 302 is a ferroelectric capacitor for storing binary information based on the switching between two polarization states of a ferroelectric material under an external electric field.

[0080] In some embodiments, the storage unit 302 is a capacitor, which includes a first electrode layer, a second electrode layer, and a dielectric layer. The dielectric layer is located between the first electrode layer and the second electrode layer. For example, the dielectric layer can store and release charge by changing the voltage state between the first and second electrode layers, thereby enabling the storage and retrieval of information in the storage unit 302. The dielectric layer can be made of insulating materials such as silicon dioxide or silicon nitride, or other suitable materials. The material of the first electrode layer includes, but is not limited to, monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium. The material of the second electrode layer includes, but is not limited to, monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium. One of the first and second electrode layers is connected to the second doped layer 300.

[0081] In some implementations, reference Figure 6The semiconductor structure 10000 also includes a contact layer 301 located between the memory cell 302 and the second doped layer 300. The contact layer 301 is used to reduce the contact resistance between the memory cell 302 and the second doped layer 300. The material of the contact layer 301 includes metal silicide.

[0082] Another embodiment of this application provides a method for fabricating a semiconductor structure, see reference. Figure 7 ,include:

[0083] Step S1: Form a first doped layer extending along a first direction;

[0084] Step S2: Form a gate structure, wherein multiple gate structures are arranged at intervals in the first direction;

[0085] Step S3: Form the first isolation structure;

[0086] The gate structure is located on one side of the first doped layer along the second direction. The gate structure includes a gate layer and a first gap located between the gate layer and the first doped layer along the second direction. The gate structure has a first surface on the side opposite to the first doped layer in the second direction. The first isolation structure is located between adjacent gate structures.

[0087] Wherein, the first gap extends into the first doped layer along the second direction; the second surface of the first doped layer between the gate structure and the first isolation structure has a first boundary position with the sidewall of the gate structure and a second boundary position with the sidewall of the first isolation structure along the second direction, and the second boundary position is located between the first boundary position and the first surface in the second direction; wherein, the second direction intersects with the first direction.

[0088] In some embodiments, forming a first doped layer extending along a first direction includes: forming a first doped portion in a semiconductor layer on the side of the first trench opposite to the second direction, the first doped portion further extending to the side of the first trench in the first direction; and forming a second doped portion in a semiconductor layer on the side of the second trench opposite to the second direction, the second doped portion further extending to the side of the second trench in the first direction; wherein the second doped portion is connected to the first doped portion and constitutes the first doped layer.

[0089] In some embodiments, forming a gate structure includes: forming a first trench extending along a third direction in a semiconductor layer, wherein a plurality of first trenches are arranged along a first direction; and forming a gate structure in the first trench; wherein the third direction intersects the first direction and the second direction.

[0090] In some embodiments, forming the first isolation structure includes: forming a second trench extending in a third direction in a semiconductor layer, wherein the size of the second trench is smaller than the size of the first trench in a second direction; and forming the first isolation structure in the second trench; wherein a portion of the semiconductor layer located between the first trench and the second trench and located on one side of the first doped layer along the second direction forms a semiconductor pillar.

[0091] In some embodiments, forming a first isolation structure in a second slot includes: forming a first initial isolation structure and a first sacrificial layer in the second slot, the first initial isolation structure surrounding the sidewalls of the first sacrificial layer and the surfaces of the first sacrificial layer on both sides along a second direction; removing a portion of the first initial isolation structure located between the first sacrificial layer and the first doped layer along the second direction; and removing the first sacrificial layer to form a second void, wherein the remaining portion of the first initial isolation structure and the second void form the first isolation structure.

[0092] In some embodiments, forming the first initial isolation structure includes: forming a second protective layer on the inner wall of the second slot before forming the first sacrificial layer; and forming a third protective layer in the second slot, the third protective layer being located on the side of the first sacrificial layer opposite to the first doped layer along a second direction; wherein the third protective layer and the second protective layer constitute the first initial isolation structure.

[0093] In some embodiments, the method for fabricating the semiconductor structure further includes: forming a second isolation structure, the second isolation structure being located between adjacent semiconductor pillars along a third direction and between the gate structure and the first isolation structure; wherein the third direction intersects with the first direction and the second direction.

[0094] In some embodiments, forming the second isolation structure includes: forming a second initial isolation structure extending along a first direction in a semiconductor layer; wherein a first slot penetrates the second initial isolation structure along a third direction, a second slot penetrates the second initial isolation structure along a third direction, and the portion of the initial isolation structure located between the first slot and the second slot forms the second isolation structure.

[0095] The following is combined Figures 8 to 33 This section provides a detailed introduction to the fabrication process of semiconductor structures.

[0096] Reference Figure 8 , Figure 9 and Figure 10 , Figure 10 For along Figure 9 Cross-sectional view of the dicing lines M1-M2, at semiconductor layer 2000 (reference). Figure 8 A second initial isolation structure 2001 extending along the first direction X is formed in the middle.

[0097] In some embodiments, forming a second initial isolation structure 2001 extending along a first direction X in the semiconductor layer 2000 includes: forming an isolation trench (not shown) extending along the first direction X in the semiconductor layer 2000; and forming the second initial isolation structure 2001 in the isolation trench. A plurality of second initial isolation structures 2001 are arranged at intervals along a third direction Y.

[0098] In some embodiments, the process for forming the isolation trench is an etching process, which includes one or a combination of dry etching and wet etching processes. The process for forming the second initial isolation structure 2001 in the isolation trench includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0099] The material of the second initial isolation structure 2001 is the same as the material of the second isolation structure in the aforementioned embodiment.

[0100] Reference Figure 11 and Figure 12 , Figure 11 In order to be in Figure 9 A basic diagram. Figure 12 For along Figure 11 A cross-sectional view of the dicing line N1-N2 shows that a first slot 2002 extending along the third direction Y is formed in the semiconductor layer 2000, and a plurality of first slots 2002 are arranged along the first direction X.

[0101] It should be noted that, Figure 11 The mask layer D is omitted.

[0102] The first slot 2002 penetrates the second initial isolation structure 2001 along the third direction Y. The dimension of the first slot 2002 along the second direction Z is smaller than the dimension of the second initial isolation structure 2001 along the second direction Z.

[0103] In some embodiments, forming a first trench 2002 in the semiconductor layer 2000 includes forming a mask layer D (reference) on one side of the semiconductor layer 2000 along the second direction Z. Figure 12 ); and using the mask layer D as a mask to etch the semiconductor layer 2000 to form the first groove 2002.

[0104] In some embodiments, the process of etching semiconductor layer 2000 using mask layer D as a mask is an etching process, which includes one or a combination of dry etching process and wet etching process.

[0105] In some embodiments, the material of the mask layer D is different from the material of the semiconductor layer 2000. For example, the material of the mask layer D includes silicon nitride.

[0106] refer to Figure 13, Figure 13 In order to be in Figure 12 Based on the schematic diagram, a first protective layer 2003 is formed on the inner wall of the first slot 2002. For example, the first protective layer 2003 is formed on the side wall of the first slot 2002 and on the side surface of the first slot 2002 opposite to the second direction Z.

[0107] In some embodiments, the material of the first protective layer 2003 is different from the material of the semiconductor layer 2000, and the material of the first protective layer 2003 is different from the material of the mask layer D. For example, the material of the first protective layer 2003 includes silicon oxide.

[0108] In some embodiments, the process of forming the first protective layer 2003 includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0109] refer to Figure 14 A first doped portion 2004 is formed in the semiconductor layer 2000 on the side of the first slot 2002 opposite to the second direction Z. The first doped portion 2004 also extends to the side of the first slot 2002 in the first direction X.

[0110] In some embodiments, forming the first doped portion 2004 includes: performing ion implantation on the semiconductor layer 2000 of the first trench 2002 along the side opposite to the second direction Z through a first protective layer 2003 to form a first initial doped portion; and annealing the first initial doped portion to form the first doped portion 2004. The first protective layer 2003 can reduce implantation damage to the inner wall surface of the first trench 2002 during the formation of the first doped portion 2004.

[0111] refer to Figure 15 Remove the first protective layer 2003.

[0112] In some embodiments, the process for removing the first protective layer 2003 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0113] It should be noted that in other embodiments, the first protective layer may not be formed, and correspondingly, the step of removing the first protective layer is not performed.

[0114] Continue to refer to Figure 15 After forming the first doped portion 2004, the size of the mask layer D along the first direction X is reduced.

[0115] For example, after removing the first protective layer 2003, the size of the mask layer D along the first direction X is reduced.

[0116] In some embodiments, the process of reducing the size of the mask layer D along the first direction X is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0117] refer to Figure 16 After the first doped portion 2004 is formed, the second sacrificial layer 2005 is formed in the first groove 2002.

[0118] For example, after reducing the size of the mask layer D along the first direction X, a second sacrificial layer 2005 is formed in the first slot 2002.

[0119] In some embodiments, the process of forming the second sacrificial layer 2005 includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0120] In some embodiments, the material of the second sacrificial layer 2005 is different from the material of the semiconductor layer 2000, and the material of the mask layer D is different. For example, the material of the second sacrificial layer 2005 may include a metallic material, such as tungsten.

[0121] A reduced mask layer D along the first direction X is used to define the location of the second sacrificial layer 2005. The second sacrificial layer 2005 also extends to a portion of the surface of the semiconductor layer 2000 along the second direction Z.

[0122] refer to Figure 17 and Figure 18 , Figure 17 for Figure 16 A basic diagram. Figure 17 for Figure 18 A cross-sectional view along the cutting line N1-N2, showing the removal of the mask layer D.

[0123] In some embodiments, the process for removing the mask layer D is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0124] The second sacrificial layer 2005 is used to define the location of the subsequent second slot.

[0125] refer to Figure 19 , Figure 19 In order to be in Figure 17 The schematic diagram shows that a second slot 2006 extending in the third direction Y is formed in the semiconductor layer 2000, and the size of the second slot 2006 is smaller than the size of the first slot 2002 in the second direction Z.

[0126] The second slot 2006 penetrates the second initial isolation structure 2001 along the third direction Y. The dimension of the second slot 2006 along the second direction Z is smaller than the dimension of the second initial isolation structure 2001 along the second direction Z. The portion of the semiconductor layer 2000 located between the first slot 2002 and the second slot 2006 and located on the side of the first doped layer 210 along the second direction Z forms a semiconductor pillar F. The second initial isolation structure 2001 between the second slot 2006 and the first slot 2002 constitutes the second isolation structure 2001a (reference). Figure 5 ).

[0127] In some embodiments, forming a second trench 2006 in the semiconductor layer 2000 includes etching the semiconductor layer 2000 using a second sacrificial layer 2005 as a mask to form the second trench 2006. For example, the second trench 2006 is formed in the semiconductor layer 2000 after the mask layer D is removed.

[0128] In some embodiments, the process of etching the semiconductor layer 2000 using the second sacrificial layer 2005 as a mask is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0129] refer to Figure 20 A second protective layer 2008a is formed on the inner wall of the second slot 2006. For example, the second protective layer 2008a is formed on the side wall of the second slot 2006 and on the surface of the second slot 2006 along the side opposite to the second direction Z.

[0130] In some embodiments, the process of forming the second protective layer 2008a includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0131] In some embodiments, the material of the second protective layer 2008a includes silicon oxide.

[0132] refer to Figure 21 A second doped portion 2007 is formed in the semiconductor layer 2000 on the side opposite to the second direction Z of the second slot 2006. The second doped portion 2007 also extends to the side of the second slot 2006 in the first direction X. The second doped portion 2007 is connected to the first doped portion 2004 and forms the first doped layer 210.

[0133] In some embodiments, after the second protective layer 2008a is formed, the second doped portion 2007 is formed.

[0134] In some embodiments, forming a second doped portion 2007 in the semiconductor layer 2000 on the side of the second trench 2006 opposite to the second direction Z includes: performing ion implantation on the semiconductor layer 2000 on the side of the second trench 2006 opposite to the second direction Z through a second protective layer 2008a to form a second initial doped portion; and annealing the second initial doped portion to form the second doped portion 2007. The second protective layer 2008a can reduce implantation damage to the inner wall surface of the second trench 2006 during the formation of the second doped portion 2007.

[0135] The second doped section 2007 is connected to the first doped section 2004 and forms the first doped layer 210. Since the first doped layer 210 between the first slot 2002 and the second slot 2006 has undergone two ion implantations, the doping concentration of the first doped layer 210 between the first slot 2002 and the second slot 2006 is increased, and the volume of the first doped layer 210 is increased, which can reduce the contact resistance between the first doped layer 210 and the subsequently formed bit line.

[0136] refer to Figure 22 A first sacrificial layer 2009 is formed in the second slot 2006. For example, the first sacrificial layer 2009 is formed after a second protective layer 2008a is formed on the inner wall of the second slot 2006. A third protective layer 2008b is formed in the second slot 2006, located on the side of the first sacrificial layer 2009 facing away from the first doped layer 210 along the second direction Z. The third protective layer 2008b and the second protective layer 2008a constitute a first initial isolation structure 2300. The first initial isolation structure 2300 surrounds the sidewalls of the first sacrificial layer 2009 and the surfaces of the first sacrificial layer 2009 on both sides along the second direction Z.

[0137] In some embodiments, after the second doped portion 2007 is formed, the first sacrificial layer 2009 is formed.

[0138] It should be noted that, in this embodiment, the second protective layer 2008a is formed on the inner wall of the second groove 2006 before the second doped portion 2007 is formed, as an example. In other embodiments, the second protective layer 2008a may be formed on the inner wall of the second groove 2006 after the second doped portion 2007 is formed.

[0139] In some embodiments, the process of forming the first sacrificial layer 2009 includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0140] In some embodiments, the process of forming the third protective layer 2008b includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0141] In some embodiments, the material of the first sacrificial layer 2009 is different from the material of the third protective layer 2008b, the material of the first sacrificial layer 2009 is different from the material of the second protective layer 2008a, and the material of the first sacrificial layer 2009 is different from the material of the semiconductor layer 2000.

[0142] For example, the first sacrificial layer 2009 is made of titanium nitride. The third protective layer 2008b is made of silicon oxide. The second protective layer 2008a is made of silicon oxide.

[0143] refer to Figure 23 After forming the first initial isolation structure 2300 and the first sacrificial layer 2009, the second sacrificial layer 2005 is removed (see reference). Figure 22 ), revealing the first slot 2002.

[0144] In some embodiments, the process for removing the second sacrificial layer 2005 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0145] In some embodiments, the method further includes: removing a portion of the first initial isolation structure 2300 located on the side of the second sacrificial layer 2005 opposite to the first doped layer 210 until the second sacrificial layer 2005 is exposed; thereafter, removing the second sacrificial layer 2005 to expose the first slot 2002.

[0146] refer to Figures 24 to 33 Forming a gate structure 220 in a first slot 2002 includes: forming an initial gate dielectric layer 222b on the sidewall of the first slot 2002 and on the inner wall of the first slot 2002 along the side opposite to the second direction Z; forming an initial gate layer 221b in the first slot 2002, the initial gate layer 221b being located on the side of the initial gate dielectric layer 222b away from the semiconductor pillar F and the first doped layer 210; removing a portion of the initial gate dielectric layer 222b located on the inner wall of the first slot 2002 along the side opposite to the second direction Z, the portion of the initial gate dielectric layer 222b located on the sidewall of the first slot 2002 forming a gate dielectric layer 222; and removing a portion of the initial gate layer 221b located between the gate dielectric layer 222 and the first doped layer 210, the portion of the initial gate layer 221b located on the side of the initial gate dielectric layer 222 away from the semiconductor pillar F forming a gate layer 221.

[0147] refer to Figure 24An initial gate dielectric material film 222a is formed on the side wall of the first slot 2002, the inner wall of the first slot 2002 on the side opposite to the second direction Z, and the surface of the first initial isolation structure 2300 on the side away from the first doped layer 210.

[0148] In some embodiments, the process of forming the initial gate dielectric material film 222a includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0149] In some embodiments, the material of the initial gate dielectric material film 222a is the same as the material of the gate dielectric layer 222 in the aforementioned embodiments.

[0150] refer to Figure 25 An initial gate material film 221a is formed on the surface of the initial gate dielectric material film 222a.

[0151] In some embodiments, the process of forming the initial gate material film 221a includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0152] In some embodiments, the material of the initial gate material film 221a is the same as the material of the gate layer 221 in the aforementioned embodiments.

[0153] Continue to refer to Figure 25 A first insulating material film 223a is formed in the first slot 2002, and the first insulating material film 223a also extends to the surface of the initial gate material film 221a outside the first slot 2002.

[0154] In some embodiments, the process of forming the first insulating material film 223a includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0155] In some embodiments, the material of the first insulating material film 223a is the same as the material of the insulating layer 223 in the aforementioned embodiments.

[0156] refer to Figure 26 The portion of the first insulating material film 223a extending to the surface of the initial gate material film 221a outside the first slot 2002 and the portion of the first insulating material film 223a located within the first slot 2002 are removed, and the remaining first insulating material film 223a forms the first insulating film 223b.

[0157] In some embodiments, the process used to remove the portion of the first insulating material film 223a extending to the surface of the initial gate material film 221a outside the first slot 2002 and the portion of the first insulating material film 223a located within the first slot 2002 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0158] refer to Figure 27 The portion of the initial gate material film 221a located outside the first slot 2002 and the portion of the initial gate material film 221a located inside the first slot 2002 are removed, and the remaining initial gate material film 221a forms the initial gate layer 221b.

[0159] In some embodiments, the process used to remove the portion of the initial gate material film 221a located outside the first slot 2002 and the portion of the initial gate material film 221a located inside the first slot 2002 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0160] In some embodiments, the surface of the first insulating film 223b facing away from the first doped layer 210 has a different height in the second direction Z than the surface of the initial gate layer 221b facing away from the first doped layer 210. Figure 27 In this embodiment, relative to the first doped layer 210, the height of the surface of the first insulating film 223b facing away from the first doped layer 210 in the second direction Z is greater than the height of the surface of the initial gate layer 221b facing away from the first doped layer 210 in the second direction Z. In other embodiments, the height of the surface of the first insulating film facing away from the first doped layer in the second direction may be less than the height of the surface of the initial gate layer facing away from the first doped layer in the second direction.

[0161] In other embodiments, the surface of the first insulating film facing away from the first doped layer is at the same height in the second direction as the surface of the initial gate layer facing away from the first doped layer.

[0162] refer to Figure 28 A second insulating film 223c is formed in the first slot 2002 on the side of the first insulating film 223b and the initial gate layer 221b away from the first doped layer 210. The second insulating film 223c and the first insulating film 223b constitute the insulating layer 223.

[0163] In some embodiments, the process of forming the second insulating film 223c includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0164] In some embodiments, the material of the second insulating film 223c is the same as the material of the insulating layer 223 in the aforementioned embodiments.

[0165] In some embodiments, the method further includes removing the portion of the initial gate dielectric material film 222a outside the first slot 2002, and forming an initial gate dielectric layer 222b from the portion of the initial gate dielectric material film 222a inside the first slot 2002. The initial gate layer 221b is located on the side of the initial gate dielectric layer 222b opposite to the semiconductor pillar F and the first doped layer 210.

[0166] refer to Figure 29 and Figure 30 , Figure 30 for Figure 29 In an inverted view, a second doped layer 300 is formed, which is located in the semiconductor pillar F and on the side of the initial gate layer 221b away from the first doped layer 210 in the second direction Z; wherein the second doped layer 300 is the source region and the first doped layer 210 is the drain region; or, the second doped layer 300 is the drain region and the first doped layer 210 is the source region.

[0167] In some embodiments, the process of forming the second doped layer 300 includes an ion implantation process.

[0168] Continue to refer to Figure 29 and Figure 30 A storage cell 302 is formed, which is located on the side of the second doped layer 300 away from the first doped layer 210 and is connected to the second doped layer 300.

[0169] The storage unit 302 is described in the foregoing embodiments and will not be described in detail again.

[0170] In some embodiments, the method for fabricating the semiconductor structure further includes forming a contact layer 301 on the side of the second doped layer 300 opposite to the first doped layer 210. Forming the memory cell 302 includes forming the memory cell 302 on the side of the contact layer 301 opposite to the second doped layer 300. The material of the contact layer 301 is as described in the foregoing embodiments.

[0171] refer to Figure 31 , Figure 31 In order to be in Figure 30 Based on the schematic diagram, the portion of the initial gate dielectric layer 222b located on the inner wall of the first slot 2002 along the side opposite to the second direction Z is removed, and the portion of the initial gate dielectric layer 222b located on the side wall of the first slot 2002 forms the gate dielectric layer 222.

[0172] In some embodiments, removing the portion of the inner wall of the initial gate dielectric layer 222b located on the side of the first slot 2002 opposite to the second direction Z includes: removing the portion of the inner wall of the initial gate dielectric layer 222b located on the side of the first slot 2002 opposite to the second direction Z from the side of the first doped layer 210 opposite to the second direction Z.

[0173] In some embodiments, the process used to remove the portion of the initial gate dielectric layer 222b located on the inner wall of the first slot 2002 along the side opposite to the second direction Z is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0174] In some embodiments, the method for fabricating the semiconductor structure further includes removing a portion of the first initial isolation structure 2300 located between the first sacrificial layer 2009 and the first doped layer 210 along the second direction Z.

[0175] In some embodiments, the process used to remove the portion of the first initial isolation structure 2300 located between the first sacrificial layer 2009 and the first doped layer 210 along the second direction Z is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0176] In some embodiments, during the removal of the portion of the inner wall of the initial gate dielectric layer 222b located on the side of the first slot 2002 opposite to the second direction Z, the portion of the first initial isolation structure 2300 located between the first sacrificial layer 2009 and the first doped layer 210 along the second direction Z is also removed, simplifying the process.

[0177] It should be noted that, since the dimension of the first trench along the second direction Z is smaller than the dimension of the second initial isolation structure 2001 along the second direction Z, a second initial isolation structure 2001 is also present between adjacent first doped layers 210 along the third direction Y and on the side of the initial gate layer 221b in the opposite direction to the second direction Z. Since the dimension of the second trench along the second direction Z is smaller than the dimension of the second initial isolation structure 2001 along the second direction Z, a second initial isolation structure 2001 is also present between adjacent first doped layers 210 along the third direction Y and on the side of the first sacrificial layer 2009 in the opposite direction to the second direction Z. By etching the remaining second initial isolation structure 2001, the initial gate dielectric layer 222b and the first initial isolation structure 2300 are exposed. The initial gate dielectric layer 222b and the first initial isolation structure 2300 located between adjacent first doped layers 210 along the third direction Y are removed, thereby revealing a portion of the initial gate dielectric layer 222b and a portion of the first initial isolation structure 2300 along the third direction Y on the side of the first doped layer 210 in the second direction Z.

[0178] refer to Figure 32 The portion of the initial gate layer 221b located between the gate dielectric layer 222 and the first doped layer 210 is removed, and the portion of the initial gate layer 221b located on the side of the gate dielectric layer 222 away from the semiconductor pillar F forms the gate layer 221.

[0179] The insulating layer 223 is located on the side of the gate layer 221 away from the gate dielectric layer 222; wherein, the first gap 224 is located along the second direction Z between the gate dielectric layer 222 and the first doped layer 210, between the gate layer 221 and the first doped layer 210, and between the insulating layer 223 and the first doped layer 210.

[0180] In some embodiments, removing the portion of the initial gate layer 221b located between the gate dielectric layer 222 and the first doped layer 210 includes removing the portion of the initial gate layer 221b located between the gate dielectric layer 222 and the first doped layer 210 from the side of the first doped layer 210 along the direction opposite to the second direction Z.

[0181] In some embodiments, the process used to remove the portion of the initial gate layer 221b located between the gate dielectric layer 222 and the first doped layer 210 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0182] In some embodiments, the method for fabricating the semiconductor structure further includes: removing the first sacrificial layer 2009 to form a second gap 233, wherein the remaining portion of the first initial isolation structure 2300 and the second gap 233 form a first isolation structure 230. The description of the first isolation structure 230 is the same as that of the foregoing embodiments and will not be repeated in detail.

[0183] In some embodiments, the process for removing the first sacrificial layer 2009 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0184] In some embodiments, the first sacrificial layer 2009 is removed during the process of removing the portion of the initial gate layer 221b located between the gate dielectric layer 222 and the first doped layer 210.

[0185] refer to Figure 33 Bit line 200 is formed, which is located on the side of the first doped layer 210 away from the semiconductor pillar F and extends along the first direction X.

[0186] Another embodiment of this application also provides a system 30000 having a storage system 32000. (See reference...) Figure 34 , Figure 34 This is a block diagram of a system 30000 having a storage system 32000 according to one embodiment of this application.

[0187] like Figure 34 As shown, system 30000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 32000 located therein). Figure 34 As shown, system 30000 may include host 31000 and storage system 32000. Storage system 32000 may have one or more semiconductor structures 32100 and controller 32200. Host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 31000 may be configured to send or receive data to and from semiconductor structure 32100.

[0188] In some implementations, controller 32200 may be coupled to semiconductor structure 32100 and host 31000, and is configured to control semiconductor structure 32100. For example, controller 32200 may be configured to control semiconductor structure 32100 to perform operations such as read, erase, and program. Controller 32200 may also manage data stored in semiconductor structure 32100 and communicate with host 31000. For example, controller 32200 may communicate with external devices (e.g., host 31000) according to a specific communication protocol.

[0189] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0190] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: The first doped layer extends along a first direction; A gate structure, wherein a plurality of gate structures are located on one side of the first doped layer along a second direction and are spaced apart in the first direction, the gate structure including a gate layer and a first gap located between the gate layer and the first doped layer along the second direction, the gate structure having a first surface on the side opposite to the first doped layer in the second direction; as well as A first isolation structure is located between adjacent gate structures; Wherein, the first gap extends into the first doped layer along the second direction, and the second surface of the first doped layer between the gate structure and the first isolation structure has a first boundary position with the sidewall of the gate structure and a second boundary position with the sidewall of the first isolation structure along the second direction, and the second boundary position is located between the first boundary position and the first surface in the second direction; The second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, wherein, The distance between the second surface and the first surface in the second direction increases from the first isolation structure to the gate structure.

3. The semiconductor structure according to claim 1, wherein, The distance between the first boundary position and the second boundary position along the second direction is 12nm to 30nm.

4. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A semiconductor pillar is located on one side of the first doped layer along the second direction and between the gate structure and the first isolation structure.

5. The semiconductor structure according to claim 4, wherein, The gate structure further includes: A gate dielectric layer is located between the gate layer and the semiconductor pillar; and An insulating layer is located on the side of the gate layer opposite to the semiconductor pillar; The first gap is also located along the second direction between the gate dielectric layer and the first doped layer, and between the insulating layer and the first doped layer.

6. The semiconductor structure according to claim 5, wherein, A portion of the first gap is located between the insulating layer and the gate dielectric layer in the first direction.

7. The semiconductor structure according to claim 5, wherein, The first doped layer also extends to a portion of the gate dielectric layer on a side surface opposite to the gate layer along the first direction.

8. The semiconductor structure according to claim 4, wherein, The first isolation structure includes: A first isolation portion is located between adjacent semiconductor pillars along the first direction; The second gap is located between the first isolation portion and the first doped layer along the second direction; and The second isolation portion is located between the second gap and the semiconductor pillar and is located in the second direction between a portion of the first isolation portion and the first doped layer.

9. The semiconductor structure according to claim 8, wherein, The first doped layer also extends to a portion of the second isolation portion on the side surface opposite to the second void along the first direction.

10. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: Bit lines are located on the side of the first doped layer away from the semiconductor pillar and extend along the first direction.

11. A method for fabricating a semiconductor structure, comprising: A first doped layer extending along a first direction is formed; A gate structure is formed, and a plurality of the gate structures are arranged at intervals in the first direction; Forming the first isolation structure; The gate structure is located on one side of the first doped layer along the second direction. The gate structure includes a gate layer and a first gap located between the gate layer and the first doped layer along the second direction. The gate structure has a first surface on the side opposite to the first doped layer in the second direction. The first isolation structure is located between adjacent gate structures. Wherein, the first gap extends into the first doped layer along the second direction; the second surface of the first doped layer between the gate structure and the first isolation structure has a first boundary position with the sidewall of the gate structure and a second boundary position with the sidewall of the first isolation structure along the second direction, and the second boundary position is located between the first boundary position and the first surface in the second direction; The second direction intersects with the first direction.

12. The preparation method according to claim 11, wherein, Forming the gate structure includes: A first trench extending along a third direction is formed in a semiconductor layer, and a plurality of the first trenches are arranged along the first direction; and The gate structure is formed in the first slot; Wherein, the third direction intersects with the first direction and also intersects with the second direction.

13. The preparation method according to claim 12, wherein, Forming the first isolation structure includes: A second trench extending along the third direction is formed in the semiconductor layer, wherein the size of the second trench is smaller than the size of the first trench in the second direction; and The first isolation structure is formed in the second slot; Wherein, the portion of the semiconductor layer located between the first slot and the second slot and located on one side of the first doped layer along the second direction forms a semiconductor pillar.

14. The preparation method according to claim 13, wherein forming the first doped layer extending along the first direction comprises: A first doped portion is formed in the semiconductor layer on the side of the first slot opposite to the second direction, and the first doped portion further extends to the side of the first slot in the first direction; and A second doped portion is formed in the semiconductor layer on the side of the second slot opposite to the second direction, and the second doped portion further extends to the side of the second slot in the first direction; wherein the second doped portion is connected to the first doped portion and constitutes the first doped layer.

15. The preparation method according to claim 14, wherein, The preparation method further includes: A first protective layer is formed on the inner wall of the first slot; The formation of the first doped portion includes: Ion implantation is performed on the semiconductor layer along the side opposite to the second direction of the first trench through the first protective layer to form a first initial doped portion; and The first initial doped portion is annealed to form the first doped portion; The preparation method further includes: Remove the first protective layer.

16. The preparation method according to claim 14, wherein, Forming the first isolation structure in the second slot includes: A first initial isolation structure and a first sacrificial layer are formed in the second slot, wherein the first initial isolation structure surrounds the sidewalls of the first sacrificial layer and the surfaces of the first sacrificial layer on both sides along the second direction; Remove the portion of the first initial isolation structure located between the first sacrificial layer and the first doped layer along the second direction; and Remove the first sacrificial layer to form a second void; The remaining portion of the first initial isolation structure and the second gap form the first isolation structure.

17. The preparation method according to claim 13, wherein, Forming the gate structure in the first slot includes: An initial gate dielectric layer is formed on the sidewall of the first slot and on the inner wall of the first slot on the side opposite to the second direction. An initial gate layer is formed in the first slot, the initial gate layer being located on the side of the initial gate dielectric layer opposite to the semiconductor pillar and the first doped layer; The portion of the initial gate dielectric layer located on the inner wall of the first slot along the side opposite to the second direction is removed, and the portion of the initial gate dielectric layer located on the side wall of the first slot forms the gate dielectric layer; and The portion of the initial gate layer located between the gate dielectric layer and the first doped layer is removed, and the portion of the initial gate layer located on the side of the gate dielectric layer opposite to the semiconductor pillar is used to form the gate layer; The first gap is located between the gate dielectric layer and the first doped layer along the second direction.

18. The preparation method according to claim 17, wherein, Removing the portion of the initial gate dielectric layer located on the inner wall of the first slot along the side opposite to the second direction includes: Remove the portion of the inner wall of the initial gate dielectric layer located on the side opposite to the second direction from the first doped layer. The removal of the portion of the initial gate layer located between the gate dielectric layer and the first doped layer includes: Remove the portion of the initial gate layer located between the gate dielectric layer and the first doped layer from the side of the first doped layer along the direction opposite to the second direction.

19. The preparation method according to claim 17, wherein, Forming the gate structure in the first slot further includes: An insulating layer is formed in the first slot; The insulating layer is located on the side of the gate layer opposite to the gate dielectric layer; The first gap is located between the insulating layer and the first doped layer along the second direction.

20. A storage system, comprising: The semiconductor structure as described in any one of claims 1 to 10; as well as A controller, coupled to the semiconductor structure, is used to control the semiconductor structure to store data.

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