Semiconductor structure, preparation method thereof and electronic equipment
By forming a protective layer on the sidewall of the reference filling hole, the void defect problem caused by poor word line via morphology is solved, thereby improving the performance of the semiconductor structure and optimizing the process flow.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-19
AI Technical Summary
In semiconductor structures, poor morphology of word line vias can easily lead to void defects, affecting device performance.
By forming a protective layer on the sidewall of the reference filling hole to maintain its morphology and avoid the influence of the virtual structure removal process on the structural filling hole, an atomic layer deposition process is used to form the protective layer and protect the sidewall of the reference filling hole during the etching process.
It improves the performance of semiconductor structures, avoids the occurrence of void defects, optimizes the process flow, and ensures the morphological integrity of the structure filling holes.
Smart Images
Figure CN122069708A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are gradually increasing. Any tiny differences and defects in the manufacturing process may affect the performance of the devices. Summary of the Invention
[0003] This disclosure provides a semiconductor structure, its fabrication method, and an electronic device, which can optimize the morphology of word line vias, reduce the probability of void defects in the word line structure, and improve the performance of the semiconductor structure.
[0004] A method for fabricating a semiconductor structure, comprising:
[0005] A substrate is provided on which a stacked structure is formed, the stacked structure including an insulating layer and a sacrificial layer alternately stacked along a first direction perpendicular to the substrate, and an initial through-hole is provided in the stacked structure along the first direction;
[0006] A virtual structure is formed in the initial through hole;
[0007] A mask layer is formed on the top surface of the virtual structure and the stacked structure away from the substrate;
[0008] A reference filling hole is formed on the virtual structure, penetrating the mask layer along the first direction;
[0009] A protective layer is formed on the sidewall of the reference filling hole;
[0010] The virtual structure is removed based on the reference filling hole to form a structural filling hole.
[0011] In one embodiment, forming a virtual structure in the initial through-hole includes:
[0012] A first filling layer is formed on the inner wall of the initial through hole;
[0013] A second filling layer is formed by filling the initial through-hole, and the second filling layer is adjacent to the first filling layer;
[0014] The virtual structure includes the first filling layer and the second filling layer.
[0015] In one embodiment, forming a reference filling hole in the virtual structure that penetrates the mask layer along the first direction includes:
[0016] The mask layer is removed from the top surface of the second filler layer and at least the portion of the top surface of the first filler layer near the second filler layer to form the reference filler hole;
[0017] The sidewall of the reference filling hole is located on the top surface of the first filling layer.
[0018] In one embodiment, the protective layer is formed using an atomic layer deposition process;
[0019] The etching selectivity ratio between the protective layer and the first filling layer is less than 1.
[0020] In one embodiment, the mask layer is formed using a plasma-enhanced chemical vapor deposition process in which the process gas includes tetraethyl orthosilicate.
[0021] The mask layer and the first filling layer are both made of silicon dioxide, and the etching selectivity ratio of the mask layer and the first filling layer is greater than 1.
[0022] In one embodiment, the top layer of the stacked structure is the sacrificial layer, and after forming the virtual structure in the initial via, the method for fabricating the semiconductor structure further includes:
[0023] A cover layer is formed on the top surface of the virtual structure and the stacked structure away from the substrate;
[0024] The surface of the cover layer near the stacked structure is adjacent to the sacrificial layer at the top of the stacked structure, and the reference filling hole penetrates the cover layer.
[0025] In one embodiment, the structure filling via includes a signal line filling via, and the method for fabricating the semiconductor structure further includes:
[0026] Signal lines are formed in the holes filled in the structure;
[0027] The signal lines are spaced apart from the sacrificial layer.
[0028] In one embodiment, the signal line includes a word line, and the method for fabricating the semiconductor structure prior to forming the signal line in the structure-filled via further includes:
[0029] A semiconductor material layer and a dielectric layer are sequentially formed on the inner wall of the filling hole of the structure;
[0030] The signal line is adjacent to the dielectric layer.
[0031] In one embodiment, before forming a mask layer on the top surface of the virtual structure and the stacked structure away from the substrate, the method for fabricating the semiconductor structure further includes:
[0032] A mask material layer is formed on the surface of the stacked structure, and the mask material layer extends to cover the virtual structure;
[0033] An isolation groove is formed in the stacked structure, extending in a second direction parallel to the substrate. The isolation groove is located on one side of the virtual structure and penetrates the mask material layer and the stacked structure in the first direction.
[0034] Based on the isolation groove, the sacrificial layer in the stacked structure is replaced with a conductive layer;
[0035] An isolation structure is formed in the isolation groove;
[0036] The mask layer extends to cover the top surface of the isolation structure away from the substrate; in a third direction parallel to the substrate, the isolation groove is spaced apart from the initial through hole, and the third direction intersects the second direction.
[0037] A semiconductor structure, comprising:
[0038] Base;
[0039] The storage stack structure includes conductive layers and insulating layers alternately stacked along a first direction perpendicular to the substrate;
[0040] A structural filling hole penetrates the storage stack structure along the first direction;
[0041] A protective layer covers the sidewalls of the opening portion of the structure that fills the hole away from the substrate.
[0042] An electronic device includes the semiconductor structure described above, or includes a semiconductor structure made by the method described above for preparing the semiconductor structure.
[0043] In the above semiconductor structure fabrication method, the protective layer formed on the sidewall of the reference filling hole can maintain the sidewall morphology of the reference filling hole, so that the process of removing the virtual structure does not affect the opening morphology of the formed structure filling hole, avoids the problem of voids in the filling structure formed in the structure filling hole, and improves the performance of the semiconductor structure. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in some embodiments;
[0046] Figure 2 This is a schematic cross-sectional view of the semiconductor structure after the initial via is formed in some embodiments;
[0047] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the virtual structure is formed in some embodiments;
[0048] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the isolation trench is formed in some embodiments;
[0049] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the filling trench is formed in some embodiments;
[0050] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure after the isolation structure is formed in some embodiments;
[0051] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after the reference fill hole is formed in some embodiments;
[0052] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the protective layer has been formed in some embodiments;
[0053] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the formation of structural filling holes in some embodiments;
[0054] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after word lines are formed in some embodiments.
[0055] Explanation of reference numerals in the attached figures:
[0056] Substrate 102, stacked structure 104, virtual structure 106, mask material layer 108, conductive layer 110, isolation structure 112, mask layer 114, hard mask layer 116, protective layer 118, word line 120, semiconductor material layer 122, dielectric layer 124, insulating layer 202, sacrificial layer 204, initial via 206, first fill layer 208, second fill layer 210, isolation trench 212, fill trench 214, first isolation layer 216, second isolation layer 218, reference fill hole 220, structural fill hole 222. Detailed Implementation
[0057] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0059] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.
[0060] It is understood that the terms "first," "second," etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first filler layer may be referred to as a second filler layer, and similarly, a second filler layer may be referred to as a first filler layer. Both the first filler layer and the second filler layer are filler layers, but they are not the same filler layer.
[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "several" means at least one, such as one, two, etc., unless otherwise expressly specified.
[0062] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in some embodiments, such as... Figure 1 As shown, a method for fabricating a semiconductor structure is provided, comprising:
[0063] S102 provides a substrate having a laminated structure.
[0064] Specifically, a substrate is provided on which a stacked structure is formed. The stacked structure includes an insulating layer and a sacrificial layer alternately stacked along a first direction perpendicular to the substrate. An initial via is provided in the stacked structure, penetrating the structure along the first direction. It is understood that the initial via includes at least one of an initial word line via, an initial bit line via, and an initial capacitor via. The initial word line via can define the shape and position of subsequently formed word lines extending along the first direction; the initial bit line via can define the shape and position of subsequently formed bit lines extending along the first direction; and the initial capacitor via can define the shape and position of subsequently formed capacitors. As an example, the insulating layer is made of silicon dioxide, and the sacrificial layer is made of silicon nitride.
[0065] In some embodiments, the substrate material includes undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the substrate material is selected as single-crystal silicon.
[0066] S104 forms a virtual structure in the initial through hole.
[0067] Specifically, a deposition process, such as chemical vapor deposition or atomic layer deposition, is used to form a virtual structure within the initial via. Furthermore, the virtual structure fills the initial via.
[0068] S106, a mask layer is formed on the top surface of the virtual structure and the stacked structure away from the substrate.
[0069] Specifically, a mask layer is formed on the top surface of the virtual structure away from the substrate, and the mask layer extends along the top surface of the virtual structure away from the substrate to cover the top surface of the stacked structure away from the substrate.
[0070] S108, a reference filling hole is formed on the virtual structure.
[0071] A reference filling hole is formed on the virtual structure, penetrating the mask layer along a first direction. The orthographic projection of the virtual structure onto the substrate covers the orthographic projection of the reference filling hole onto the substrate. Furthermore, the bottom of the reference filling hole exposes the virtual structure.
[0072] S110, a protective layer is formed on the sidewall of the reference filling hole.
[0073] A conformal protective layer is formed on the sidewall of the reference filling hole. The protective layer can protect the mask layer exposed on the sidewall of the reference filling hole, resulting in a reference filling hole with smooth sidewalls, maintaining the morphology of the reference filling hole, and avoiding the influence of the virtual structure removal process on the sidewall morphology of the reference filling hole.
[0074] S112, remove virtual structures based on reference filling holes to form structural filling holes.
[0075] Based on the reference filling hole, the virtual structure in the initial through hole is etched away to form the structure filling hole, which includes the connected initial through hole and the reference filling hole.
[0076] In the above semiconductor structure fabrication method, the protective layer formed on the sidewall of the reference filling hole can maintain the sidewall morphology of the reference filling hole, so that the process of removing the virtual structure does not affect the opening morphology of the formed structure filling hole, avoids the problem of voids in the filling structure formed in the structure filling hole, and improves the performance of the semiconductor structure.
[0077] Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure after the initial via is formed in some embodiments. For example, the X direction can be... Figure 2 The first direction shown is perpendicular to the base 102, and the Y direction can be... Figure 2 The second direction parallel to the base 102, the Z direction can be Figure 2 The middle parallel to the third direction of the base 102, the second direction intersects with the third direction, such as Figure 2As shown, firstly, a substrate 102 is provided. Secondly, using a deposition process, such as chemical vapor deposition or atomic layer deposition, an insulating layer 202 and a sacrificial layer 204 are alternately stacked along a first direction X on the substrate 102 to obtain a stacked structure 104 located on the substrate 102. Thirdly, the stacked structure 104 is patterned to form initial vias 206, which penetrate the stacked structure 104 along the first direction X. The initial vias 206 define the morphology and location of signal lines (word lines and / or bit lines) extending along the first direction in the semiconductor structure, or the morphology and location of capacitors in the semiconductor structure. Further, the initial vias 206 are arranged in an array along a plane parallel to the substrate 102 (the plane containing the second direction Y and the third direction Z).
[0078] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the virtual structure is formed in some embodiments, such as... Figure 3 As shown, in one embodiment, forming a virtual structure 106 in the initial through-hole 206 includes steps S202-S204.
[0079] S202, a first filling layer 208 is formed on the inner wall of the initial through hole 206.
[0080] S204, a second filling layer 210 is formed by filling the initial through hole 206, and the second filling layer 210 is adjacent to the first filling layer 208.
[0081] Specifically, steps S202-S204 are as follows: First, a first filling layer 208 is formed on the inner wall of the initial through hole 206. The first filling layer 208 covers the sidewall and bottom of the initial through hole 206 and can protect the morphology of the initial through hole 206. There is a gap between the initial through hole 206 and the first filling layer 208 on the sidewall. Second, a second filling layer 210 is formed in the initial through hole 206. The second filling layer 210 fills the initial through hole 206 and is adjacent to the first filling layer 208. The virtual structure 106 includes the first filling layer 208 and the second filling layer 210. For example, the material of the first filling layer 208 includes silicon dioxide, and the material of the second filling layer 210 includes polycrystalline silicon.
[0082] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the isolation trench is formed in some embodiments. Figure 5 This is a schematic cross-sectional view of the semiconductor structure after the filling trench is formed in some embodiments. Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure after the isolation structure is formed in some embodiments, such as... Figure 4 , Figure 5 , Figure 6As shown, in one embodiment, before forming a mask layer on the top surface of the virtual structure 106 and the stacked structure 104 away from the substrate 102, the method for fabricating the semiconductor structure further includes steps S302-S308.
[0083] S302, a mask material layer is formed on the surface of the stacked structure, the mask material layer extending to cover the virtual structure.
[0084] like Figure 4 As shown, a mask material layer 108 is formed on the top surface of the stacked structure 104 away from the substrate 102 using a deposition process, such as atomic layer deposition or chemical vapor deposition. The mask material layer 108 extends to cover the top surface of the virtual structure 106 away from the substrate 102. Exemplarily, the material of the mask material layer 108 includes oxides (e.g., silicon dioxide) or nitrides (e.g., silicon nitride). As an example, the mask material layer 108 includes silicon dioxide.
[0085] S304, forming an isolation groove in the laminated structure that extends in a second direction parallel to the substrate.
[0086] like Figure 4 As shown, an isolation groove 212 extending along a second direction Y parallel to the substrate 102 is formed in the stacked structure 104. The isolation groove 212 is located on one side of the virtual structure 106. On a third direction Z parallel to the substrate 102, the isolation groove 212 is spaced apart from the initial through hole 206 (virtual structure 106). The third direction Z intersects the second direction Y. Furthermore, the third direction Z is perpendicular to the second direction Y. In the first direction X, the isolation groove 212 penetrates the mask material layer 108 and the stacked structure 104.
[0087] S306, based on the isolation groove, the sacrificial layer in the stacked structure is replaced with a conductive layer.
[0088] like Figure 5 , Figure 6 As shown, firstly, based on the isolation trench 212, lateral etching is performed to remove the sacrificial layer 204 in the stacked structure 104, forming a filling trench 214 communicating with the isolation trench 212, wherein the bottom of the filling trench 214 exposes the virtual structure 106. Then, a conductive layer 110 is formed in the filling trench 214, the conductive layer 110 including transmission lines extending along the second direction Y. Further, the conductive layer 110 fills the filling trench 214. As an example, one of the structure filling hole and the filling trench 214 is a word line filling hole, and the other is a bit line filling hole. In the case where the structure filling hole is a word line filling hole, the filling trench 214 is a bit line filling hole, and the transmission lines in the conductive layer 110 are bit lines.
[0089] For example, the material of the conductive layer 110 includes one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). As an example, the constituent material of the conductive layer 110 is titanium nitride (TiN).
[0090] S308, an isolation structure is formed in the isolation groove.
[0091] like Figure 6 As shown, an isolation structure 112 is formed in the isolation groove 212, filling the isolation groove 212. Exemplarily, the isolation structure 112 includes a first isolation layer 216 and a second isolation layer 218. The first isolation layer 216 covers the inner wall of the isolation groove 212, and the second isolation layer 218 is located in the isolation groove 212 and adjacent to the first isolation layer 216. The isolation structure 112 separates two adjacent transmission lines. Exemplarily, after forming the isolation structure 112, a mask layer 114 is formed on the side of the isolation structure 112 and the stacked structure 104 away from the substrate, such as... Figure 7 As shown, the mask layer 114 extends to cover the top surface of the isolation structure 112 away from the substrate 102. Exemplarily, the first isolation layer 216 is made of silicon nitride, and the second isolation layer 218 is made of polysilicon.
[0092] like Figure 2 As shown, in one embodiment, the top layer of the stacked structure 104 is the sacrificial layer 204. After forming the virtual structure 106 in the initial via 206, the method for fabricating the semiconductor structure further includes: forming a capping layer on the top surface of the virtual structure 106 and the stacked structure 104 away from the substrate 102; wherein the surface of the capping layer near the stacked structure 104 is adjacent to the sacrificial layer 204 on the top layer of the stacked structure 104, the reference filling via penetrates the capping layer, and a memory structure, such as a storage capacitor, located on the top layer of the semiconductor structure can subsequently be formed in the capping layer. When the top layer of the stacked structure 104 is an insulating layer 202 and a capping layer is present, the memory structure located on the top layer of the semiconductor structure is formed in the capping layer and the top insulating layer 202.
[0093] Understandably, when both a capping layer and a masking material layer 108 are present, the masking material layer 108 is located on the top surface of the capping layer away from the substrate 102, and the bottom surface of the masking material layer 108 is adjacent to the top surface of the capping layer away from the substrate 102. Further, the masking material layer 108 formed on the surface of the stacked structure 104 in step S302 can serve as a capping layer. In this case, the bottom surface of the masking material layer 108 near the substrate 102 is in contact with the surface of the stacked structure 104 away from the substrate 102. As an example, the masking material layer 108 on the surface of the stacked structure 104 in the attached figure also serves as a capping layer.
[0094] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after the reference fill hole is formed in some embodiments. Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the protective layer has been formed in some embodiments, such as... Figure 7 , Figure 8 As shown, a mask layer 114 is formed on the virtual structure 106, extending to cover the top surface of the stacked structure 104 away from the substrate 102. When a mask material layer 108 is formed on the stacked structure 104, the mask layer 114 is adjacent to the top surface of the mask material layer 108 away from the substrate 102. In one embodiment, the mask layer 114 is formed using a plasma-enhanced chemical vapor deposition process with a process gas including tetraethyl orthosilicate; wherein both the mask layer 114 and the first filler layer 208 are made of silicon dioxide, and the etching selectivity ratio of the mask layer 114 and the first filler layer 208 is greater than 1.
[0095] After the mask layer 114 is formed, a reference filling hole 220 is formed on the virtual structure 106. The reference filling hole 220 penetrates the mask layer 114 and the mask material layer 108 along the first direction X. The orthographic projection of the virtual structure 106 on the substrate 102 covers the orthographic projection of the reference filling hole 220 on the substrate 102. Furthermore, the bottom of the reference filling hole 220 is exposed on the virtual structure 106.
[0096] It is understandable that although both the mask layer 114 and the first fill layer 208 are made of silicon dioxide, the first fill layer 208, formed first, undergoes a multi-step furnace tube hot process. Under the same etching conditions, such as wet etching, the etching rate of the first fill layer 208 is lower than that of the mask layer 114. When the process conditions remain unchanged, and the protective layer 118 is absent from the sidewall of the reference fill hole 220, the sidewall of the reference fill hole 220 exposes the mask layer 114. During the removal of the virtual structure 106 based on the reference fill hole 220, the removal amount of the mask layer 114 is greater than that of the first fill layer 208 along the direction parallel to the substrate 102. This results in a groove in the mask layer 114 communicating with the reference fill hole 220, making the opening of the structural fill hole have a pot-shaped morphology. This is not conducive to forming filling structures (such as word lines, bit lines, or electrodes of storage capacitors) in the structural fill hole, and the subsequently formed filling structure... Void defects can easily occur in the filling structure, affecting its performance. However, the reference filling hole 220 in this disclosure has a protective layer 118 formed on its sidewall. The sidewall of the reference filling hole 220 exposes the protective layer 118 located between the reference filling hole 220 and the mask layer 114. During the removal of the virtual structure 106 based on the reference filling hole 220, the mask layer 114 is not etched, so that the sidewall morphology of the reference filling hole 220 remains unchanged. A filling structure without voids can be formed in the structural filling hole 222 including the reference filling hole 220 and the initial via 206, which optimizes the process flow and improves the performance of the semiconductor structure.
[0097] For example, the method for fabricating a semiconductor structure further includes forming a hard mask layer 116 on the surface of the mask layer 114 away from the substrate 102. For example, the material of the hard mask layer 116 includes silicon nitride. At this time, after forming a reference filling hole 220 on the virtual structure 106, the reference filling hole 220 penetrates the mask layer 114, the hard mask layer 116, and the mask material layer 108 in the first direction X. Furthermore, the bottom of the reference filling hole 220 exposes the virtual structure 106. This arrangement avoids the problem that the etching rate of the mask material layer 108 or the cover layer is greater than the etching rate of the virtual structure 106 under the same process conditions, which would affect the morphology of the filling hole and reduce the performance of the filling structure.
[0098] In one embodiment, forming a reference filling hole 220 penetrating the mask layer 114 on the virtual structure 106 includes: removing the mask layer 114 from the top surface of the second filling layer 210 and at least a portion of the top surface of the first filling layer 208 near the second filling layer 210 to form the reference filling hole 220; wherein the sidewall of the reference filling hole 220 is located on the top surface of the first filling layer 208. This arrangement can reduce the impact of the addition of the protective layer 118 on the sidewall morphology of the structural filling hole 222 obtained after removing the virtual structure 106. For example, the sidewall of the reference filling hole 220 is aligned with the sidewall of the initial via 206 (virtual structure 106), that is, the orthographic projection of the reference filling hole 220 on the substrate 102 coincides with the orthographic projection of the initial via 206 on the substrate 102; at this time, the minimum size of the structural filling hole obtained after removing the virtual structure 106 is closest to the size of the initial via 206, and the attenuation of the semiconductor structure performance by the protective layer 118 is minimized.
[0099] like Figure 8 As shown, in one embodiment, the protective layer 118 is formed using an atomic layer deposition process; wherein the etching selectivity ratio of the protective layer 118 to the first filling layer 208 is less than 1.
[0100] Specifically, an atomic layer deposition process is used to form a protective layer material on the inner wall of the reference filling hole 220. Then, the protective layer material at the bottom of the reference filling hole 220 is removed to form a protective layer 118 composed of the protective layer material on the sidewalls of the reference filling hole 220. For example, the material of the protective layer 118 includes silicon nitride.
[0101] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the formation of structural filling holes in some embodiments, such as... Figure 9 As shown, based on the reference filling hole 220, firstly, based on the reference filling hole 220 with a protective layer 118 formed on its sidewall, an etching process, such as wet etching or dry etching, is used to remove the second filling layer 210 in the initial via 206; secondly, the first filling layer 208 on the inner wall of the initial via 206 is etched away to form a structural filling hole 222. The sidewall of the structural filling hole 222 exposes the conductive layer 110. The structural filling hole 222 penetrates the hard mask layer 116, the mask layer 114, the mask material layer 108, and the stacked structure 104, including the initial via 206 and the reference filling hole 220.
[0102] In one embodiment, the structure filling hole 222 includes a signal line filling hole, and the method for fabricating the semiconductor structure further includes: forming a signal line in the structure filling hole 222; the signal line is spaced apart from the conductive layer 110 (the sacrificial layer 204 in the stacked structure on one side of the structure filling hole 222 has been replaced with the conductive layer 110), so that the signal line in the semiconductor structure is separated from the transmission line.
[0103] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after word lines are formed in some embodiments, such as... Figure 10 As shown, the signal line includes a word line 120, which is spaced apart from the conductive layer 110 (the sacrificial layer 204 in the stacked structure on one side of the structural filling hole 222 has been replaced by the conductive layer 110), so that the word line 120 in the semiconductor structure is separated from the bit line.
[0104] For example, the signal line material includes one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2), indium tin oxide (ITO), and indium zinc oxide (IZO); and the metal silicide includes titanium silicide (TiSi). As an example, the signal line is constructed of indium tin oxide (ITO) and / or indium zinc oxide (IZO).
[0105] like Figure 10 As shown, in one embodiment, before forming the signal line (word line 120) in the structure filling hole 222, the method for fabricating the semiconductor structure further includes: sequentially forming a semiconductor material layer 122 and a dielectric layer 124 on the inner wall of the structure filling hole 222; wherein, the signal line (word line 120) is adjacent to the dielectric layer 124, and the semiconductor material layer 122 and the dielectric layer 124 subsequently form the semiconductor layer and gate dielectric layer of the transistor in the semiconductor structure, forming part of the transistor structure during the formation of the word line 120, thus simplifying the process flow.
[0106] For example, the material of the semiconductor material layer 122 includes one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO, IWO). Materials such as titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.
[0107] These materials have a wide bandgap and low leakage current. For example, when the semiconductor material layer 122 is IGZO, the transistor leakage current is small, which can improve the performance of dynamic memory.
[0108] The material of the semiconductor material layer 122 mentioned above only emphasizes the element type of the material, and does not emphasize the atomic ratio of the material or the film quality of the material.
[0109] For example, the material of dielectric layer 124 includes silicon oxide (SiO2) or silicon oxynitride (SiNO). Because the feature size of the gate is very small, dielectric layer 124 is preferably made of a high dielectric constant (high k) material to reduce parasitic capacitance. High k materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. In ideal embodiments, hafnium oxide, zirconium oxide, and aluminum oxide are preferred. The formation process of dielectric layer 124 can employ any existing technology well known to those skilled in the art, such as chemical vapor deposition.
[0110] In one embodiment, the method for fabricating the semiconductor structure further includes: removing the semiconductor material layer 122 corresponding to the insulating layer 202 to form semiconductor layers spaced apart along the first direction X; forming a memory structure in the stacked structure 104, the memory structure being adjacent to the semiconductor layer and spaced apart from the conductive layer 110 (bit line); wherein the semiconductor layer includes a first source / drain adjacent to the conductive layer 110 (bit line), a second source / drain adjacent to the memory structure, and a channel region connecting the first source / drain and the second source / drain, the semiconductor structure including a transistor and a memory structure, the transistor including a semiconductor layer and a dielectric layer 124. Further, the method for fabricating the semiconductor structure further includes: removing the dielectric layer 124 corresponding to the insulating layer 202.
[0111] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0112] This disclosure also provides a semiconductor structure that can be fabricated using the above-described semiconductor structure fabrication method. The parts that are the same as or corresponding to those in the above-described semiconductor structure fabrication method will not be described again below.
[0113] like Figure 9 , Figure 10 As shown, in one embodiment, the semiconductor structure includes: a substrate 102, a memory stack structure, a structure filling via 222, and a protective layer 118; the memory stack structure includes conductive layers and insulating layers alternately stacked along a first direction perpendicular to the substrate 102, the difference from the stack structure in the semiconductor structure fabrication method is that the sacrificial layer in the stack structure is replaced with a conductive layer; the structure filling via 222 penetrates the memory stack structure along the first direction X; the protective layer 118 covers the sidewall of the structure filling via 222 away from the opening portion of the substrate 102.
[0114] like Figure 10 As shown, the semiconductor structure also includes signal lines located in the structure filling vias 222 and spaced apart from the conductive layer 110. As an example, the signal lines include word lines 120 and / or bit lines.
[0115] This disclosure also provides an electronic device including the semiconductor structure described above. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the described electronic device.
[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0117] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure embodiments, and these modifications and improvements all fall within the protection scope of the present disclosure embodiments.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a stacked structure is formed, the stacked structure including an insulating layer and a sacrificial layer alternately stacked along a first direction perpendicular to the substrate, and an initial through-hole is provided in the stacked structure along the first direction; A virtual structure is formed in the initial through hole; A mask layer is formed on the top surface of the virtual structure and the stacked structure away from the substrate; A reference filling hole is formed on the virtual structure, penetrating the mask layer along the first direction; A protective layer is formed on the sidewall of the reference filling hole; The virtual structure is removed based on the reference filling hole to form a structural filling hole.
2. The preparation method according to claim 1, characterized in that, The process of forming a virtual structure in the initial through-hole includes: A first filling layer is formed on the inner wall of the initial through hole; A second filling layer is formed by filling the initial through-hole, and the second filling layer is adjacent to the first filling layer; The virtual structure includes the first filling layer and the second filling layer.
3. The preparation method according to claim 2, characterized in that, The process of forming a reference filling hole in the virtual structure that penetrates the mask layer along the first direction includes: The mask layer is removed from the top surface of the second filler layer and at least the portion of the top surface of the first filler layer near the second filler layer to form the reference filler hole; The sidewall of the reference filling hole is located on the top surface of the first filling layer.
4. The preparation method according to claim 2, characterized in that, The protective layer is formed using atomic layer deposition (ALD) technology. The etching selectivity ratio between the protective layer and the first filling layer is less than 1.
5. The preparation method according to claim 1, characterized in that, The top layer of the stacked structure is the sacrificial layer, and the method for fabricating the semiconductor structure after forming a virtual structure in the initial via further includes: A cover layer is formed on the top surface of the virtual structure and the stacked structure away from the substrate; The surface of the cover layer near the stacked structure is adjacent to the sacrificial layer at the top of the stacked structure, and the reference filling hole penetrates the cover layer.
6. The preparation method according to claim 1, characterized in that, The structure filling vias include signal line filling vias, and the method for fabricating the semiconductor structure further includes: Signal lines are formed in the holes filled in the structure; The signal lines are spaced apart from the sacrificial layer.
7. The preparation method according to claim 6, characterized in that, The signal line includes a word line, and the method for fabricating the semiconductor structure before forming the signal line in the structure filling hole further includes: A semiconductor material layer and a dielectric layer are sequentially formed on the inner wall of the filling hole of the structure; The signal line is adjacent to the dielectric layer.
8. The preparation method according to claim 1, characterized in that, Before forming a mask layer on the top surface of the virtual structure and the stacked structure away from the substrate, the method for fabricating the semiconductor structure further includes: A mask material layer is formed on the surface of the stacked structure, and the mask material layer extends to cover the virtual structure; An isolation groove is formed in the stacked structure, extending in a second direction parallel to the substrate. The isolation groove is located on one side of the virtual structure and penetrates the mask material layer and the stacked structure in the first direction. Based on the isolation groove, the sacrificial layer in the stacked structure is replaced with a conductive layer; An isolation structure is formed in the isolation groove; The mask layer extends to cover the top surface of the isolation structure away from the substrate; in a third direction parallel to the substrate, the isolation groove is spaced apart from the initial through hole, and the third direction intersects the second direction.
9. A semiconductor structure, characterized in that, include: Base; The storage stack structure includes conductive layers and insulating layers alternately stacked along a first direction perpendicular to the substrate; A structural filling hole penetrates the storage stack structure along the first direction; A protective layer covers the sidewalls of the opening portion of the structure that fills the hole away from the substrate.
10. An electronic device, characterized in that, The semiconductor structure includes the semiconductor structure described in claim 9, or the semiconductor structure prepared by the method described in any one of claims 1 to 8.