Semiconductor device with capacitor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device with a capacitor structure and a forming method thereof. The semiconductor device with the capacitor structures comprises a substrate, a plurality of inner supporting layers, an outer supporting structure and a plurality of capacitor structures. The substrate has an array region and a peripheral region. The inner support layer is disposed in the array region on the substrate. The first support portion of the outer support structure is disposed in the peripheral region on the substrate. The second supporting part of the outer supporting structure comprises a connecting part connected with the inner supporting layers and a top extending part arranged on the first supporting part. A thickness of the top extension is different from a thickness of one of the inner support layers farthest from the substrate. Each capacitor structure passes through the inner support layers.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods of forming the same, and more particularly to semiconductor devices with capacitor structures for improving support strength and methods of forming the same. Background Technology

[0002] With advancements in semiconductor technology, and to meet consumer demand for miniaturized electronic devices, manufacturing processes are striving to reduce component sizes. However, this process presents numerous challenges. Take the traditional columnar capacitor structure as an example: capacitor holes are typically formed within alternating sacrificial oxide and nitride layers. The sacrificial oxide layers are then completely removed, leaving the nitride layer as a support structure to support the columnar capacitors subsequently formed within the holes. This increases the capacitance of the columnar capacitor. However, as dimensions shrink and the aspect ratio of the capacitor holes increases, the strength of the traditional support structure needs improvement. For instance, support structures located at the edges of the array region are prone to breakage or collapse, which in turn makes the columnar capacitors at the edges susceptible to collapse. Furthermore, the dielectric layer thickness on the sidewalls of columnar capacitors at the array region edges may be significantly greater than that on the sidewalls of columnar capacitors at the center of the array region, leading to uneven capacitance values. These issues have a greater impact on test bonds formed using the same process, reducing testing and production efficiency. Summary of the Invention

[0003] The capacitor structure and its formation method proposed in this application can solve or improve the problems that traditional columnar capacitor structures are prone to, such as insufficient strength of the supporting structure, breakage of the outer supporting structure, uneven capacitance value, and / or reduced testing and production efficiency.

[0004] Embodiments of this application provide a semiconductor device with a capacitor structure, comprising: a substrate having an array region and a peripheral region other than the array region; a plurality of inner support layers disposed in the array region on the substrate and having a plurality of outer sidewalls adjacent to the peripheral region; an outer support structure including: a first support portion disposed in the peripheral region on the substrate; and a second support portion including: a connecting portion connecting to the outer sidewalls of the inner support layers; and a top extension portion disposed on the first support portion, wherein the thickness of the top extension portion is different from the thickness of the inner support layer furthest from the substrate; and a plurality of capacitor structures located in the array region on the substrate, each capacitor structure passing through the inner support layer and including a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

[0005] Some embodiments of this application provide a method for forming a semiconductor device with a capacitor structure, including: forming a plurality of inner support layers in an array region on a substrate; forming an outer support structure, including: a first support portion formed in a peripheral region on the substrate; and a second support portion, including: a connecting portion connected to an outer sidewall of the inner support layers; and a top extension portion formed on the first support portion, wherein the thickness of the top extension portion is different from the thickness of the inner support layer furthest from the substrate; and forming a plurality of capacitor structures in an array region on the substrate, each capacitor structure passing through the inner support layer and including a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

[0006] This application embodiment first defines stacked islands containing alternating sacrificial and support materials in the array region, and then covers the outside of the stacked islands with a dielectric layer to reinforce the support material. This makes it less likely for these inner support layers to break during the sacrificial material removal process, thereby improving the yield of the high aspect ratio capacitor structure. Attached Figure Description

[0007] Figure 1A , Figure 2A , Figure 3A Until Figure 17A This is a partial top view of a semiconductor device including a capacitor structure at different intermediate manufacturing stages in the array region and the peripheral region according to some embodiments of this application.

[0008] Figure 1B , Figure 2B , Figure 3B Until Figure 17B The following are shown respectively along Figure 1A , Figure 2A , Figure 3A Until Figure 17A The diagram shows a cross-section taken by line B-B'.

[0009] Figure 18 A schematic diagram illustrating a wafer at an intermediate manufacturing stage according to some embodiments of this application is shown.

[0010] [Symbol Explanation]

[0011] 10: Semiconductor devices

[0012] 100: Substrate

[0013] 1: Chip

[0014] A1: Array area

[0015] A2: Surrounding Area

[0016] 102: Contact plug

[0017] BL: Bitline

[0018] 108: Bottom isolation layer

[0019] 1100: Sacrificial Materials

[0020] 1110: First Sacrificial Material Layer

[0021] 1120: Second Sacrificial Material Layer

[0022] 111: First Sacrifice Layer

[0023] 112: Second Sacrificial Layer

[0024] 111C: Lower cavity

[0025] 112C: Upper cavity

[0026] 120M, 120T: Inner support layer

[0027] 120Tb: Bottom surface

[0028] 1200: Supporting material

[0029] 1210: First support material layer

[0030] 1220: Second support material layer

[0031] 121: First Support Layer

[0032] 122: Second support layer

[0033] S: Stacked islands

[0034] 130, 170, 223: Mask

[0035] 132,172,224: Opening

[0036] 151: First dielectric layer

[0037] 1511: The first part of the first dielectric layer

[0038] 1512: The second part of the first dielectric layer

[0039] 1513: The third part of the first dielectric layer

[0040] 152: Second dielectric layer

[0041] 1521: The first part of the second dielectric layer

[0042] 1522: The second part of the second dielectric layer

[0043] 100-E: Sidewall

[0044] Sw, 111s, 112s, 121s, 122s, 1611s, 250s: outer wall

[0045] 151s: Vertical sidewall

[0046] Sa, 108a, 111a, 122a, 151a, 152a, 160a: Top surface

[0047] 160: First Support Section

[0048] 161: Second Support Section

[0049] 160b: Bottom surface

[0050] 1600: Insulating material layer

[0051] 1611: Connecting part

[0052] 1611w: Inner wall

[0053] 1612: Top extension

[0054] 1613: Bottom extension

[0055] 180: External support structure

[0056] 182: Capacitor port

[0057] 2100: Bottom electrode material layer

[0058] 210: Bottom electrode

[0059] 210a: Top surface of the bottom electrode

[0060] 221: Oxide layer

[0061] 222: Mask material layer

[0062] 225: Groove

[0063] 2300: Dielectric material layer

[0064] 230: Dielectric layer

[0065] 230s: Surface

[0066] 2500: Top electrode material layer

[0067] 250: Top electrode

[0068] 2700: Conductive material layer

[0069] 2700U: Upper part of the conductive material layer

[0070] 270: Conductive filler layer

[0071] 2800: Metallic material layer

[0072] 280: Metal layer

[0073] SC: Capacitor Structure

[0074] 160PA, 280PA: Vertical projection range

[0075] T1, T2, T3: Thickness

[0076] B-B': line

[0077] D1: First Direction

[0078] D2: Second Direction

[0079] D3: Third direction

[0080] X: Direction

[0081] Y: direction

[0082] Z: Direction Detailed Implementation

[0083] Embodiments of this application provide a semiconductor device with a capacitor structure and a method for forming the same. In some of the following embodiments, the semiconductor device may include, for example, Dynamic Random Access Memory (DRAM), but this application is not limited to this. The semiconductor device may also be any other semiconductor device with a capacitor structure, such as an integrated circuit including silicon capacitors or other electronic devices. Some embodiments of this application will now be described in more detail with reference to the accompanying drawings.

[0084] Reference Figure 17A , Figure 17B A semiconductor device 10 with a capacitor structure SC according to an embodiment of this application includes a substrate 100, a plurality of inner support layers 120M and 120T, an outer support structure 180, and a plurality of capacitor structures SC. The inner support layers 120M and 120T are disposed in an array region A1 on the substrate 100. A first support portion 160 of the outer support structure 180 is disposed in a peripheral region A2 on the substrate 100. A second support portion 161 of the outer support structure 180 includes a plurality of outer sidewalls 121s and 122s (denoted as...) connecting the inner support layers 120M and 120T. Figure 4B The connecting portion 1611 (in the middle) and the top extension portion 1612 provided on the first support portion 160. Each capacitor structure SC passes through these inner support layers 120M and 120T.

[0085] The following describes a method for forming a semiconductor device having a capacitor structure according to an embodiment of this application. (Refer to...) Figure 1A , Figure 1BA sacrificial material 1100 and a support material 1200 are alternately formed over a substrate 100. Specifically, the substrate 100 has an array region A1 and a peripheral region A2 outside the array region A1. The material of the substrate 100 may include semiconductor materials, such as silicon, gallium arsenide, gallium nitride, germanium silicide, or combinations thereof. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate. For simplicity, existing components within the substrate 100, such as isolation structures and buried word lines used to define the active region, are omitted in this example diagram.

[0086] In some embodiments, multiple bit lines BL and multiple contact plugs 102 located in array region A1 may be formed in an interlayer dielectric layer (not shown) above substrate 100. In some embodiments, before alternately forming sacrificial material 1100 and support material 1200, a bottom isolation layer 108 may be formed on the interlayer dielectric layer (not shown) and covering the contact plugs 102 and bit lines BL to protect components below the bottom isolation layer 108 from damage or defects in subsequent processes for fabricating capacitor structures (e.g., wet and dry etching). The bottom isolation layer 108 may be located in array region A1 and peripheral region A2. The interlayer dielectric layer is, for example, one or more oxide layers. The bottom isolation layer 108 may be a nitride layer, such as a silicon nitride layer.

[0087] In this embodiment, the sacrificial material 1100 includes a first sacrificial material layer 1110 and a second sacrificial material layer 1120, and the support material 1200 includes a first support material layer 1210 and a second support material layer 1220. The sacrificial material 1100 includes a dielectric material, such as an oxide, that has etch selectivity between itself and the support material 1200. The support material 1200 includes a dielectric material, such as a nitride, that provides support strength. This application does not limit the number of layers of the sacrificial material 1100 and the support material 1200.

[0088] like Figure 1B As shown, a first sacrificial material layer 1110, a first support material layer 1210, a second sacrificial material layer 1120, and a second support material layer 1220 are alternately formed above the substrate 100, for example, along a first direction D1 (e.g., the Z direction). These bit lines BL may be spaced apart along a second direction D2 (e.g., the X direction), and the bit lines BL may extend along a third direction D3 (e.g., the Y direction). Contact plugs 102 may be formed between adjacent bit lines BL for electrically connecting subsequently formed capacitor structures to the substrate 100.

[0089] Reference Figure 2A , Figures 2B to 3A , Figure 3B A stacked island S can be formed by patterning the sacrificial material 1100 and the support material 1200, such that the coverage area of ​​the stacked island S does not exceed the array region A1. For example... Figure 2A , Figure 2B As shown, a mask 130 can be formed on the second support material layer 1220, and the coverage area of ​​the mask 130 does not exceed the array region A1. The bit line BL and the contact plug 102 are also within the coverage area of ​​the mask 130.

[0090] Then, refer to Figure 3A , Figure 3B The sacrificial material 1100 and support material 1200 exposed by the opening 132 of the mask 130 are removed to form a stacked island S located in the array region A1. The stacked island S may include a first sacrificial layer 111, a first support layer 121, a second sacrificial layer 112, and a second support layer 122, which are sequentially located on the substrate 100 from bottom to top along the first direction D1. Furthermore, the width of the stacked island S (e.g., in the second direction D2) does not exceed the width of the array region A1.

[0091] It is worth noting that etching the sacrificial material 1100 and the support material 1200 may not substantially affect the bottom isolation layer 108, meaning the coverage area of ​​the stacked islands S is smaller than that of the bottom isolation layer 108. Furthermore, although only a single array region A1 and peripheral region A2 are shown in the figures, in some embodiments, multiple array regions A1 on the wafer can form their own independent stacked islands S. After the stacked islands S are formed, the mask 130 can be removed by ashing or wet etching. A cleaning process can then be selectively performed to remove residues.

[0092] Then, refer to Figure 4A , Figure 4B The first dielectric layer 151 can be compliantly and blanket-formed on the substrate 100 using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). In this document, when blanket formation is mentioned, it means that the element is formed in both the array region A1 and the peripheral region A2.

[0093] In this example, the outer sidewalls 111s of the first sacrificial layer 111, the outer sidewalls 121s of the first support layer 121, the outer sidewalls 112s of the second sacrificial layer 112, and the outer sidewalls 122s of the second support layer 122 constitute the outer sidewalls Sw of the stacked island S. The top surface 122a of the second support layer 122 provides the top surface Sa of the stacked island S. A first portion 1511 of the first dielectric layer 151 may cover the outer sidewalls Sw of the stacked island S to form the connection portion 1611 of the second support portion 161, and a second portion 1512 of the first dielectric layer 151 may cover the top surface Sa of the stacked island S. In some embodiments, a third portion 1513 of the first dielectric layer 151 may cover the bottom isolation layer 108 located in the peripheral region A2 to form the bottom extension 1613 of the second support portion 161.

[0094] Furthermore, the first dielectric layer 151 may include, for example, nitrides, oxides, other suitable dielectric materials, or combinations thereof. In some embodiments, the first dielectric layer 151, the bottom isolation layer 108, the first support layer 121, and the second support layer 122 may have the same material, such as a silicon nitride layer, and the first dielectric layer 151 is in direct contact with the bottom isolation layer 108, the first support layer 121, and the second support layer 122 without having an interface.

[0095] Then, refer to Figure 5A , Figure 5B An insulating material layer 1600 can be formed on the first dielectric layer 151 by deposition processes such as PVD or CVD. The insulating material layer 1600 may include, for example, oxides, oxynitrides, other suitable dielectric materials, or combinations thereof. In some embodiments, the insulating material layer 1600 and the first dielectric layer 151 may comprise different materials. In this example, the insulating material layer 1600 may be an oxide layer, while the first dielectric layer 151 may be a nitride layer.

[0096] Then, refer to Figure 6A , Figure 6B According to some embodiments, the insulating material layer 1600 located in the array region A1 is removed by a planarization process such as chemical mechanical polishing (CMP), etching, or a combination thereof to expose the first dielectric layer 151. In this example, an excess portion of the insulating material layer 1600 is removed by a CMP process until the top surface 151a of the second portion 1512 of the first dielectric layer 151 is exposed. The remaining portion of the insulating material layer 1600 forms a first support portion 160 located in the peripheral region A2. The first support portion 160 may surround the vertical sidewall 151s of the first dielectric layer 151. The top surface 160a of the first support portion 160 may be flush with the top surface 151a of the second portion 1512 of the first dielectric layer 151.

[0097] Next, a second dielectric layer 152 can be formed on the first support portion 160 and the second portion 1512 of the first dielectric layer 151 using processes such as PVD, CVD, and ALD. This completes the fabrication of the outer support structure 180 of this embodiment. In this embodiment, the first portion 1521 of the second dielectric layer 152 is formed on the first support portion 160, forming the top extension 1612 of the second support portion 161. The second portion 1522 of the second dielectric layer 152 is formed on the second portion 1512 of the first dielectric layer 151. The thickness of the second dielectric layer 152 may be different from the thickness of the first dielectric layer 151. For example, the thickness of the second dielectric layer 152 is less than the thickness of the first dielectric layer 151.

[0098] The second dielectric layer 152 may have a flat top surface 152a. The second dielectric layer 152 may include nitrides, oxides, other suitable dielectric materials, or combinations thereof. The material of the second dielectric layer 152 may be the same as that of the first dielectric layer 151, for example, both being silicon nitride layers. The material of the second dielectric layer 152 may be different from the material of the first support 160; for example, the second dielectric layer 152 may be a silicon nitride layer and the first support 160 may be a silicon oxide layer. (Refer to...) Figure 7A , Figure 7B A mask 170 can be formed on the second dielectric layer 152 using a patterning process. This mask 170 has a plurality of openings 172 located in the array region A1 to expose a portion of the top surface 152a of the second dielectric layer 152. In some embodiments, these openings 172 may correspond to the locations of contact plugs 102.

[0099] Then, refer to Figure 8A , Figure 8B Capacitor vias 182 can be formed, for example, through an etching process via the opening 172 of the mask 170, penetrating the second dielectric layer 152, the first dielectric layer 151, the stacked islands S, and the bottom isolation layer 108. Each capacitor via 182 extends, for example, in a first direction D1, and these capacitor vias 182 are spaced apart in a second direction D2. After forming the capacitor vias 182, the mask 170 is removed.

[0100] Then, refer to Figure 9A , Figure 9B A bottom electrode material layer 2100 can be formed on the second dielectric layer 152 by CVD, ALD, PVD, or a combination thereof, and the bottom electrode material layer 2100 is deposited along the sidewalls and bottom of the capacitor holes 182, having a U-shaped profile in the capacitor holes 182. In some embodiments, the bottom electrode material layer 2100 in the capacitor holes 182 contacts and is electrically connected to the contact plug 102. The bottom electrode material layer 2100 includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable conductive materials.

[0101] Subsequently, according to some embodiments, a process for removing the sacrificial material is performed, as shown in Figures 10A / 10B to 14A / 14B.

[0102] Reference Figure 10A , Figure 10BAccording to some embodiments, an excess oxide layer 221 is deposited above the bottom electrode material layer 2100, and the oxide layer 221 fills the remaining space in the capacitor aperture 182 outside the bottom electrode material layer 2100. Next, a mask material layer 222 is deposited above the oxide layer 221, the top surface of the mask material layer 222 being a flat surface. Then, a mask 223 is formed above the mask material layer 222 by a patterning process. This mask 223 has a plurality of openings 224 to expose portions of the top surface of the mask material layer 222. The mask 223 is, for example, a patterned photoresist. In this embodiment, the size of the openings 224 may cover portions of multiple adjacent capacitor apertures 182.

[0103] Then, refer to Figure 11A , Figure 11B According to some embodiments, portions of the underlying material layers, including portions of the oxide layer 221, the second dielectric layer 152, the first dielectric layer 151, the bottom electrode material layer 2100, and the second support layer 122, can be removed via openings 224 in the mask 223 to form a plurality of grooves 225 exposing the second sacrificial layer 112. The mask 223 and mask material layers 222 can then be removed, and a cleaning process can be selectively performed to remove residues.

[0104] Then, refer to Figure 12A , Figure 12B The second sacrificial layer 112 can be removed via the groove 225 to form an upper cavity 112C located in the array region A1. Furthermore, the remaining portion of the oxide layer 221 can be removed. In an example where the second sacrificial layer 112 contains oxide, both the oxide layer 221 and the second sacrificial layer 112 can be removed simultaneously.

[0105] According to this embodiment, since the first support portion 160 is covered by the second dielectric layer 152 and the bottom electrode material layer 2100 when the second sacrificial layer 112 is removed, the first support portion 160 can be protected from damage. Therefore, after the second sacrificial layer 112 is removed, the second support layer 122 floating on the upper cavity 112C in the array region A1 can be reinforced by the outer support structure 180, making the second support layer 122 less prone to breakage or collapse.

[0106] Then, refer to Figure 13A , Figure 13BAccording to some embodiments, a back-etching process can be performed to remove a portion of the bottom electrode material layer 2100 beyond the top surface 152a of the second dielectric layer 152, and the remaining portion of the bottom electrode material layer 2100 forms the bottom electrode 210. In this embodiment, the second portion 1512 of the first dielectric layer 151, the second portion 1522 of the second dielectric layer 152, and the support material furthest from the substrate 100 (in this embodiment, the second support layer 122) form the inner support layer 120T furthest from the substrate 100. The flat top surface of the second dielectric layer 152 can serve as the top extension 1612 and the top surface of the inner support layer 120T furthest from the substrate 100, and can be flush with the top surface 210a of the bottom electrode 210. The thickness T1 of the top extension 1612 can be different from the thickness T2 in the inner support layer 120T furthest from the substrate 100. To improve the support strength of the inner support layer 120T, the thickness T1 of the top extension 1612 may be less than the thickness T2 of the inner support layer 120T furthest from the substrate 100. To improve the support strength of the outer support structure 180, the top surface 160a of the first support portion 160 may be higher than the bottom surface 120Tb of the inner support layer 120T.

[0107] Furthermore, according to some embodiments, after the bottom electrode 210 is formed, the exposed portion of the first support layer 121 in the upper cavity 112C is removed to expose a portion of the top surface 111a of the lower first sacrificial layer 111, and an inner support layer 120M is formed.

[0108] Then, refer to Figure 14A , Figure 14B The first sacrificial layer 111 can be removed by a suitable process (e.g., wet etching) via the exposed portion of the first sacrificial layer 111 to form a lower cavity 111C located in the array region A1.

[0109] In embodiments where the second dielectric layer 152, the first dielectric layer 151, and the support material 1200 comprise nitrides, and the sacrificial material 1100 comprises oxides, an etching method with a high removal rate for oxides can be selected to remove the first sacrificial layer 111 and the second sacrificial layer 112. Furthermore, since the first support portion 160 is covered by the second dielectric layer 152 during the removal of the first sacrificial layer 111, the first support portion 160 is protected from damage. Therefore, after removing the first sacrificial layer 111, the outer support structure 180 can reinforce the second support layer 122 floating on the upper cavity 112C and the first support layer 121 floating on the lower cavity 111C in the array region A1, thereby strengthening these inner support layers 120M and 120T (indicated by...). Figure 13B The inner support layers 120M and 120T are not easily broken or collapsed. In this way, these inner support layers can effectively support the bottom electrode 210, thereby improving the yield of the semiconductor device 10 and facilitating miniaturization.

[0110] Furthermore, for capacitor structures (SC) with high aspect ratios, the top of the SC is more prone to collapse than the bottom. Therefore, as... Figure 13B As shown, the thickness T2 of the inner support layer 120T furthest from the substrate 100 can be greater than the thickness T3 of the inner support layer 120M closest to the substrate 100, so as to improve the support strength of the inner support layer 120T furthest from the substrate 100, which in turn helps to improve the yield of the capacitor structure SC with a high aspect ratio.

[0111] Semiconductor devices formed near the edge of a wafer are particularly susceptible to damage from processing conditions, which can easily cause structural collapse. This is especially true for miniaturized semiconductor devices with capacitor structures. Please refer to [link to relevant documentation]. Figure 18 According to some embodiments of this application, wafer 1 includes a plurality of semiconductor devices 10 with capacitor structures. For semiconductor devices 10 adjacent to the sidewalls 100-E of the substrate 100 of wafer 1, their second dielectric layer 152 (top extension 1612 of the second support portion 161) covers the top surface of the first support portion 160 and the outer sidewalls and the sidewalls 100-E of the substrate 100. In this way, the outer support structure 180 according to this embodiment can improve the support strength of the plurality of inner support layers in the semiconductor devices 10 adjacent to the sidewalls 100-E of the substrate 100 of wafer 1, thereby improving the yield of the semiconductor devices 10 and facilitating miniaturization.

[0112] Reference Figure 15A , Figure 15B According to some embodiments, after forming the upper cavity 112C, the lower cavity 111C, and the bottom electrode 210, a dielectric material layer 2300 is formed on the bottom electrode 210 and the walls of the lower cavity 111C and the upper cavity 112C. For example, a dielectric material layer 2300 with a high dielectric constant (e.g., greater than or equal to 3.9) is compliantly deposited on the inner and outer surfaces of the bottom electrode 210. The dielectric material layer 2300 is, for example, a two-layer structure of silicon oxide / silicon nitride, but this application is not limited to this.

[0113] Then, a top electrode material layer 2500 is compliantly formed on the dielectric material layer 2300. The dielectric material layer 2300 and the top electrode material layer 2500 may also be formed on the second dielectric layer 152 and extend in the array region A1 and the peripheral region A2. In some embodiments, the top electrode material layer 2500 includes titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable electrode materials. The top electrode material layer 2500 and the bottom electrode 210 may include the same material, for example, both being titanium nitride layers, and may be formed by CVD, ALD, PVD, or a combination thereof.

[0114] Then, refer to Figure 16A , Figure 16B According to some embodiments, a conductive material layer 2700 is formed on the top electrode material layer 2500. The conductive material layer 2700 may be over-deposited and fill the spaces left after the formation of the dielectric material layer 2300 and the top electrode material layer 2500 in the lower cavity 111C and the upper cavity 112C. The upper portion 2700U of the conductive material layer 2700 is located above the top surface of the second dielectric layer 152. The conductive material layer 2700 comprises a conductive material with good conductivity, such as silicon-containing conductive materials including boron-doped polycrystalline silicon, silicon-germanium, highly boron-doped silicon-germanium, or other suitable conductive materials to reduce resistance, and may be formed by CVD, ALD, PVD, or a combination thereof. In some embodiments, the conductive material layer 2700 is a silicon-germanium layer deposited by CVD.

[0115] Next, a metal material layer 2800 may be formed above the upper portion 2700U of the conductive material layer 2700, the metal material layer 2800 including, for example (but not limited to), tungsten.

[0116] Then, refer to Figure 17A , Figure 17B According to some embodiments, portions of the metal material layer 2800, conductive material layer 2700, top electrode material layer 2500, and dielectric material layer 2300 in the peripheral region A2 are removed, leaving portions that form a metal layer 280, a conductive filling layer 270, a top electrode 250, and a dielectric layer 230 in the array region A1, respectively. The top electrode 250, dielectric layer 230, and bottom electrode 210 form a capacitor structure SC. In this embodiment, the top electrode 250 may cover the inner support layer 120T, and the outer wall 1611s of the connection portion 1611 may be further away from the center of the array region A1 than the outer wall 250s of the top electrode 250. The dielectric layer 230 may cover the inner wall 1611w of the connection portion 1611, and the outer wall 1611s of the connection portion 1611 may be further away from the center of the array region A1 than the surface 230s of the dielectric layer 230 closest to the peripheral region A2. The dielectric layer 230 can cover the inner support layer 120T, and the outer wall 1611s of the connection portion 1611 can be further away from the center of the array region A1 than the surface 230s of the dielectric layer 230 that is closest to the peripheral region A2.

[0117] Furthermore, it is worth noting that in conventional capacitor structure manufacturing methods, the conductive filling layer and metal layer covering the capacitor structure form a protruding tail structure on the peripheral region of the substrate, affecting the yield of the capacitor structure. In contrast, the capacitor structure SC according to an embodiment of this application does not have this tail structure. In this embodiment, the capacitor structure SC may further include a metal layer 280 and a conductive filling layer 270. The metal layer 280 located in the array region A1 is formed on the top surface of the conductive filling layer 270. For example... Figure 17BAs shown, the vertical projection range 280PA of the metal layer 280 on the substrate 100 does not exceed the vertical projection range 160PA of the first support portion 160 on the substrate 100. In other words, the vertical projection range 280PA of the metal layer 280 on the substrate 100 does not overlap with the vertical projection range 160PA of the first support portion 160 on the substrate 100. The metal layer 280 can serve as the electrode connection layer of the capacitor structure SC.

[0118] According to the semiconductor device with a capacitor structure and the method for forming the same, since it does not have a conventional tail structure, the size of the array region A1 can be reduced, the distance between the contact element subsequently formed in the peripheral region A2 and the array region A1 can be shortened, thereby reducing the overall size of the semiconductor device 10.

[0119] In this embodiment, the bottom isolation layer 108 may include a first portion located between the dielectric layer 230 and the substrate 100, and a second portion located between the bottom extension and the substrate 100. To improve the strength of the outer support structure, the bottom surface 160b of the first support portion 160 may be higher than the top surface 108a of the first portion of the bottom isolation layer 108.

[0120] The method proposed in the above embodiment defines the stacked islands S in the array region A1 before forming the capacitor structure SC. Figure 2B , Figure 3B ), and using a two-stage dielectric layer deposition process ( Figure 4B , Figure 6B The sacrificial material is removed from the array region A1 to cover the entire wafer, thereby reinforcing the inner support layer 120T furthest from the substrate 100 in the array region A1 and forming the outer support structure 180. Furthermore, the outer support structure 180 is not affected when the sacrificial material in the array region A1 is removed. In the semiconductor device 10 with a capacitor structure SC according to the embodiment, these inner support layers 121 and 120T are reinforced by the outer support structure 180, thereby making them less prone to breakage and effectively supporting the capacitor structure SC with a high aspect ratio, thus improving the yield of the semiconductor device 10.

[0121] Furthermore, test keys are typically fabricated on the wafer dicing ridges during the wafer design phase to check whether the electrical performance of the manufactured components meets their specifications. In some embodiments, the semiconductor device 10 of this embodiment can be used to fabricate the test keys, and the top extension 1612 of the second support portion 161 can serve as the contact point of the test key for testing the wafer to detect the component's electrical properties. According to the embodiment, the semiconductor device 10 of this embodiment can be used in both the wafer area and the test keys. Furthermore, due to the support of the first support portion 160 below, the top extension 1612 of the second support portion 161 is less prone to cracking or breakage during the process (e.g., during the removal of sacrificial material), which also improves the yield of the WAT test keys, thereby improving testing efficiency and accuracy.

[0122] Furthermore, according to the method of this application, since the dielectric material layer 2300 is deposited, the substrate 100 of the peripheral region A2 is covered by the first dielectric layer 151, the second dielectric layer 152, and the first support portion 160 (e.g., when the dielectric material layer 2300 is deposited, the substrate 100 of the peripheral region A2 is covered by the first dielectric layer 151, the second dielectric layer 152, and the first support portion 160). Figure 14B Therefore, the precursor of the dielectric material layer 2300 will not enter the array region A1 from the peripheral region A2, which can better control the thickness of the dielectric material layer 2300. The dielectric material layer 2300 has the same and uniform thickness whether it is near or far from the edge of the array region A1, thereby improving the operation performance of the capacitor structure SC and improving power consumption.

[0123] Therefore, the semiconductor device with a capacitor structure and its formation method of this application can improve product yield, facilitate miniaturization and improve power consumption, thereby achieving energy saving and carbon reduction, reducing greenhouse gas emissions, and thus implementing green processes.

Claims

1. A semiconductor device having a capacitor structure, characterized in that, include: A substrate having an array region and a peripheral region outside the array region; Multiple inner support layers are disposed in the array region on the substrate and have multiple outer sidewalls adjacent to the peripheral region; An external support structure, including: A first support portion is disposed in the peripheral region on the substrate; and A second support section includes: A connecting portion, connecting the outer sidewall of the inner support layer; and A top extension is disposed on the first support portion, wherein the thickness of the top extension is different from the thickness of the inner support layer furthest from the substrate; and Multiple capacitor structures are located in the array region on the substrate. Each capacitor structure passes through the inner support layer and includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

2. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The thickness of the top extension is less than the thickness of the inner support layer furthest from the substrate.

3. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The thickness of the inner support layer furthest from the substrate is greater than the thickness of the inner support layer closest to the substrate.

4. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The top extension is flush with the top surface of the inner support layer furthest from the substrate, and also flush with the top surface of the bottom electrode.

5. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The top surface of the first support portion is higher than the bottom surface of the inner support layer that is furthest from the substrate.

6. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The top extension covers the top surface and outer wall of the first support and the side wall of the substrate.

7. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The second support portion further includes: A bottom extension is located between the substrate and the first support portion.

8. The semiconductor device with a capacitor structure according to claim 7, characterized in that, Including: A bottom isolation layer is disposed on the substrate, and includes a first portion located between the dielectric layer and the substrate, and a second portion located between the bottom extension and the substrate. The bottom surface of the first support is higher than the top surface of the first part of the bottom isolation layer.

9. The semiconductor device having a capacitor structure according to claim 8, characterized in that, The second support portion is made of a different material than the first support portion, and the bottom isolation layer and the inner support layer are made of the same material as the second support portion.

10. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The top electrode covers the inner support layer furthest from the substrate, and the outer wall of the connection is further away from the center of the array region than the outer wall of the top electrode.

11. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The dielectric layer covers the inner sidewall of the connection portion, and the outer sidewall of the connection portion is further away from the center of the array region than the surface of the dielectric layer closest to the peripheral region.

12. The semiconductor device with a capacitor structure according to claim 1, characterized in that, The dielectric layer covers the inner support layer furthest from the substrate, and the outer wall of the connection is further away from the center of the array region than the surface of the dielectric layer closest to the peripheral region.

13. The semiconductor device with a capacitor structure according to claim 1, characterized in that, Including: A conductive filling layer is formed on the top electrode and fills the space between the capacitor structures and the space surrounded by the inner support layer, the connection portion, and the capacitor structure closest to the peripheral region; and A metal layer is formed on the conductive filler layer, wherein the vertical projection range of the metal layer on the substrate does not exceed the vertical projection range of the inner sidewall of the first support portion on the substrate.

14. The semiconductor device with a capacitor structure according to claim 1, characterized in that, It further includes multiple contact plugs above the substrate, wherein the capacitor structure is located above the contact plugs and is electrically connected to the contact plugs.

15. A method for forming a semiconductor device having a capacitor structure, characterized in that, include: Multiple inner support layers are formed in an array region on a substrate; Forming an external support structure, including: A first support portion is formed in a peripheral region on the substrate; and A second support section includes: A connecting portion, connecting to the outer wall of the inner support layer; and A top extension is formed on the first support portion, wherein the thickness of the top extension is different from the thickness of the inner support layer furthest from the substrate; and Multiple capacitor structures are formed in the array region on the substrate. Each capacitor structure passes through the inner support layer and includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

16. The method for forming a semiconductor device having a capacitor structure according to claim 15, characterized in that, The thickness of the top extension is less than the thickness of the inner support layer furthest from the substrate.

17. The method for forming a semiconductor device having a capacitor structure according to claim 15, characterized in that, The steps of forming the inner support layer and the outer support structure include: A sacrificial material and a support material are alternately formed above the substrate; The sacrificial material and the support material are patterned to form a stacked island such that the coverage of the stacked island does not exceed the array area; A first dielectric layer is formed, wherein a first portion of the first dielectric layer covers the sidewall of the stacked island to form the connection portion of the second support, and a second portion of the first dielectric layer covers the top surface of the stacked island; and A second dielectric layer is formed on the first support portion and the second portion of the first dielectric layer, wherein the second dielectric layer formed on the first support portion forms the top extension of the second support portion, and the second portion of the first dielectric layer, the second dielectric layer formed on the second portion of the first dielectric layer, and the support material furthest from the substrate form the inner support layer furthest from the substrate.

18. The method for forming a semiconductor device having a capacitor structure according to claim 17, characterized in that, Including: Before the sacrificial material and the support material are alternately formed, a bottom isolation layer is formed over the substrate in the array region and the peripheral region; A third portion forming the first dielectric layer covers the bottom insulating layer located in the peripheral region to form a bottom extension of the second support portion; and The first support portion is formed on the third portion of the first dielectric layer.

19. The method for forming a semiconductor device having a capacitor structure according to claim 17, characterized in that, The steps for forming the first support portion include: An insulating material layer is formed on the first dielectric layer in the array region and the peripheral region; and Remove the insulating material layer located in the array region, so that the remaining portion of the insulating material layer forms the first support portion, and the top surface of the first support portion is flush with the top surface of the second portion of the first dielectric layer.

20. The method for forming a semiconductor device having a capacitor structure according to claim 15, characterized in that, The dielectric layer covers the inner sidewall of the connection portion, and the outer sidewall of the connection portion is further away from the center of the array region than the surface of the dielectric layer closest to the peripheral region.

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