Memory cell with fill region separating two IO functional circuits

Abstract

The invention discloses a memory cell having a fill region separating two IO functional circuits. The memory cell includes a first IO functional circuit and a second IO functional circuit separated by a fill region. Each of the first IO functional circuit and the second IO functional circuit is associated with an array of bit cells. The first IO functional circuit has transistors in a first set of first type active region structures and a first set of second type active region structures. The second IO functional circuit has transistors in a second set of first type active region structures and a second set of second type active region structures. The fill region includes a third set of first type active region structures adjacent to the first set of first type active region structures and adjacent to the second set of first type active region structures.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to memory cells having a fill area that separates two I / O functional circuits. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but offer more functionality at higher speeds. Miniaturization processes have also led to more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs, while ensuring that standard cell layout design and manufacturing specifications are met. Summary of the Invention

[0003] According to a first aspect of this disclosure, an integrated circuit is provided, comprising: a first group of first-type active region structures, each of the first-type active region structures extending in a first direction; a first group of second-type active region structures, each of the second-type active region structures extending in the first direction; a second group of first-type active region structures, each of the first-type active region structures extending in the first direction; a second group of second-type active region structures, each of the second-type active region structures extending in the first direction; and a third group of first-type active region structures, each of the first-type active region structures extending in the first direction, wherein the first group of first-type active region structures and the first group of second-type active region structures are connected to the third group of first-type active region structures along a second direction. Two groups of first-type active region structures and a second group of second-type active region structures are separated, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structure in the first group of first-type active region structures and to the first-type active region structure in the second group of first-type active region structures; a first IO functional circuit having a first-type transistor in the first group of first-type active region structures and a second-type transistor in the first group of second-type active region structures; and a second IO functional circuit having a first-type transistor in the second group of first-type active region structures and a second-type transistor in the second group of second-type active region structures.

[0004] According to a second aspect of this disclosure, an integrated circuit is provided, comprising: a first group of first-type active region structures, each of the first-type active region structures extending in a first direction; a first group of second-type active region structures, each of the second-type active region structures extending in the first direction; a first I / O functional circuit having first-type transistors in the first group of first-type active region structures and second-type transistors in the first group of second-type active region structures; a second group of first-type active region structures, each of the first-type active region structures extending in the first direction; a second group of second-type active region structures, each of the second-type active region structures extending in the first direction; and a second I / O functional circuit having... The second group of first-type active region structures includes a first-type transistor and a second-type transistor in the second group of second-type active region structures; and a third group of first-type active region structures, each extending in the first direction, wherein the first I / O functional circuit is separated from the second I / O functional circuit by the third group of first-type active region structures along a second direction, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures and is adjacent to the first-type active region structures in the second group of first-type active region structures.

[0005] According to a third aspect of this disclosure, a method for forming an integrated circuit is provided, comprising: forming a first group of first-type active region structures, a second group of first-type active region structures, and a third group of first-type active region structures, wherein the third group of first-type active region structures is adjacent to a first-type active region structure in the first group of first-type active region structures and to a second-type active region structure in the second group of first-type active region structures; and forming a first group of second-type active region structures and a second group of second-type active region structures, wherein the second group of first-type active region structures and the second group of second-type active region structures are adjacent to a first-type active region structure in the first group of first-type active region structures. The active region structure is separated from the first group of first-type active region structures and the first group of second-type active region structures by a filling region in which the third group of first-type active region structures are located; gate-conductors and terminal-conductors extending in a second direction are fabricated, wherein each active region structure extends in a first direction perpendicular to the second direction; a first IO functional circuit having transistors in the first group of first-type active region structures and the first group of second-type active region structures is formed; and a second IO functional circuit having transistors in the second group of first-type active region structures and the second group of second-type active region structures is formed. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of this disclosure can be best understood from the specific implementations described below. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1B This is a schematic diagram of a memory cell according to some embodiments.

[0008] Figures 2A to 2B According to some embodiments Figures 1A to 1B A schematic diagram of the I / O function circuit in a memory cell.

[0009] Figures 3A to 3F According to some embodiments Figure 2A A cross-sectional view of the device in the diagram.

[0010] Figures 4A to 4B According to some embodiments Figure 2A A cross-sectional view of the NMOS active region structure in the padding area of ​​the device.

[0011] Figures 5A to 5F According to some embodiments Figure 2B A cross-sectional view of the device in the diagram.

[0012] Figures 6A to 6B According to some embodiments Figure 2B A cross-sectional view of the NMOS active region structure in the filled region of the device.

[0013] Figures 7A to 7B as well as Figures 8A to 8B This is a schematic diagram of a memory storage device having three memory cells according to some embodiments.

[0014] Figures 9A to 9B These are schematic diagrams of memory storage devices, each having an integer number of memory cells, according to some embodiments.

[0015] Figures 10A to 10B This is a schematic diagram of a memory cell according to some embodiments.

[0016] Figures 11A to 11B This is a schematic diagram of a memory cell having wires connecting I / O function circuitry to a bit cell array, according to some embodiments.

[0017] Figure 12 This is a flowchart of a method 1200 for manufacturing an integrated circuit according to some embodiments.

[0018] Figure 13 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0019] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to some embodiments. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components, values, operations, materials, arrangements, etc., are described below. These are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., may also be considered. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0022] In some embodiments, the memory storage device includes a plurality of memory cells. Each memory cell includes a plurality of bit cell arrays and a plurality of I / O functional circuits. Each bit cell array forms a row of bit cells aligned with the I / O functional circuits along the X direction. Each bit cell in the bit cell array is connected to the I / O functional circuits via one or more wires extending along the X direction. The bit cell array has a height along the Y direction. The height of each of the plurality of I / O functional circuits is less than the height of the bit cell array.

[0023] In each memory cell, a fill region separates a first I / O functional circuit and a second I / O functional circuit along the Y direction. The first I / O functional circuit is implemented using first-type transistors (e.g., NMOS transistors) in a first group of first-type active region structures and second-type transistors (e.g., PMOS transistors) in a first group of second-type active region structures. The second I / O functional circuit is implemented using first-type transistors (e.g., NMOS transistors) in a second group of first-type active region structures and second-type transistors (e.g., PMOS transistors) in a second group of second-type active region structures. The fill region is implemented using a third group of first-type active region structures (in some specific embodiments, where no NMOS transistors are present). Furthermore, the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures and to the first-type active region structures in the second group of first-type active region structures.

[0024] Figures 1A to 1B This is a schematic diagram of a memory cell according to some embodiments. Memory cell U A and U B Each of them occupies a rectangular area in the integrated circuit. Figure 1A Memory unit U in A The associated rectangular region has a height H extending in the Y direction. UA and the length L extending in the X direction UA .and Figure 1B Memory unit U in B The associated rectangular region has a height H extending in the Y direction. UB and the length L extending in the X direction UB The X and Y directions are perpendicular to each other.

[0025] exist Figures 1A to 1B In the memory unit U A and U B Each of them includes a plurality of I / O functional circuits arranged along the Y direction in the first circuit region (e.g., Figure 1A 110A to 140A or Figure 1B (110B to 140B in the diagram) and multiple bit cell arrays (e.g., four bit cell arrays 180 in the diagram) arranged along the Y direction in the second circuit region. Each of the multiple I / O function circuits has the same layout. Memory cell (U A or U B The number of I / O function circuits in a memory cell is equal to the number of bit cell arrays in the memory cell, because each of the I / O function circuits is associated with a corresponding bit cell array and is configured to transmit or receive signals from the corresponding bit cell array.

[0026] Each of the multiple I / O function circuits has a width W extending in the X direction. io and the height H extending in the Y direction io Memory unit (i.e., U A or U B Each of the bit cell arrays in the array comprises a bit cell array arranged along the X direction. Each bit cell (e.g., 80) has a width W extending in the X direction. bc and the height H extending in the Y direction bc In the memory cell (i.e., U...) A or U B In the diagram, the height H of the I / O function circuit is... io Less than the height H of the bit cell array bc .

[0027] The length L of the first circuit region containing multiple I / O function circuits io The width W of the circuit unit containing I / O functional circuitry io Determined. The length L of the second circuit region containing multiple bit cell arrays. bca The number of bit cells in the array and the width W of bit cell 80 bc Related. In Figures 1A to 1B In the example, the length L bca Equals 6*W bc This is because there are six bit cells in each bit cell array of the memory cell.

[0028] In this disclosure, a bit cell in a bit cell array is broadly defined. In some embodiments, a bit cell is a static random access memory cell (e.g., an SRAM cell). In some embodiments, a bit cell comprises two SRAM cells arranged along the Y direction; therefore, the width W of the bit cell is... bc It is equal to the width of an SRAM cell, while the height H of the bit cell is... bc It is twice the height of an SRAM cell. In some embodiments, a bit cell comprises two SRAM cells arranged along the X direction; therefore, the width W of the bit cell is twice the height of an SRAM cell. bc The width of a bit cell is twice the width of an SRAM cell, while the height of a bit cell, Hbc, is equal to the height of an SRAM cell. In some embodiments, a bit cell comprises four SRAM cells arranged in a 2x2 matrix; therefore, the width W of the bit cell is twice the width of an SRAM cell. bc It is twice the width of an SRAM cell, while the height H of a bit cell is... bcIt is twice the height of an SRAM cell. Example implementations of SRAM cells classified by transistor count include four-transistor, six-transistor, eight-transistor, and ten-transistor SRAM cells. Example implementations of SRAM cells classified by port count include single-port and dual-port SRAM cells. In the examples above, depending on the specific implementation, a bit cell is operable to store one or more bits of information because a particular implementation of a bit cell includes one or more SRAM cells. Furthermore, while SRAM cells are provided as example implementations of bit cells, other implementations of bit cells with other types of memory cells are within the scope of this disclosure.

[0029] exist Figures 1A to 1B In the memory cell, the height (e.g., height H) UA or height H UB The number of bit cell arrays and the height H of the bit cells in the memory cell. bc Related. In Figures 1A to 1B In the example, there are four bit cell arrays in the memory cell, therefore the height of the memory cell (H) UA or H UB ) is the height H of the bit cell. bc Four times that.

[0030] exist Figures 1A to 1B In the middle, because of the height H of the IO function circuit io Less than the height H of the bit cell array bc Furthermore, the number of I / O function circuits is equal to the number of bit cell arrays in the memory cell, so a fill area (150A or 150B) is added to the first circuit area. Specifically, in Figure 1A In this circuit, filler region 150A is added in the first circuit region between I / O function circuit 110A and I / O function circuit 120A. Figure 1B In this circuit, fill region 150B is added in the first circuit region between I / O function circuit 110B and I / O function circuit 120B. Figure 1A memory unit U A The filling area and I / O function circuits in Figure 2A It is depicted in more detail in the diagram. Figure 1B memory unit U B The filling area and I / O function circuits in Figure 2B It is depicted in more detail in the diagram.

[0031] exist Figure 2AIn the I / O functional circuits 110A to 140A, each includes two PMOS active region structures 52p and 54p extending in the X direction and two NMOS active region structures 52n and 54n extending in the X direction. The two PMOS active region structures 52p and 54p are arranged between the two NMOS active region structures 52n and 54n. The fill region 150A includes two NMOS active region structures 55n1 and 55n2 extending in the X direction. NMOS active region structure 55n1 is adjacent to NMOS active region structure 52n of I / O functional circuit 110A, while NMOS active region structure 55n2 is adjacent to NMOS active region structure 54n of I / O functional circuit 120A. As an example, cross-sectional views of each of the NMOS active region structures (i.e., 52n and 54n) and PMOS active region structures (i.e., 52p and 54p) in I / O functional circuit 110A are shown. Figures 3A to 3D A cross-sectional view of each of the NMOS active region structures (i.e., 55n1 and 55n2) in one of the figures and in the filled region 150A is shown in [the figures]. Figures 3E to 3F In one of the attached figures. Figures 3A to 3F Each of the cross-sectional diagrams in the diagram is individually Figure 2A One of the cutting planes AA', BB', CC', DD', PP', and QQ' shown.

[0032] exist Figure 2A In each of the I / O functional circuits 110A to 140A, the NMOS transistor is either implemented in the NMOS active region structure 52n or in the NMOS active region structure 54n. The PMOS transistor in each of the I / O functional circuits 110A to 140A is either implemented in the PMOS active region structure 52p or in the PMOS active region structure 54p. In some embodiments, each of the two NMOS active region structures 55n1 and 55n2 within the fill region 150A is a dummy active region structure that does not contain functional transistors. In some embodiments, a method is used to support any of the I / O functional circuits 110A to 140A and the memory cell U. A The NMOS transistors operating in any of the bit cells in the filling region 150 implement one or more of the two NMOS active region structures 55n1 and 55n2. In some embodiments, NMOS transistors are used to implement one or more of the two NMOS active region structures 55n1 and 55n2 in the filling region 150, and at least one of the NMOS transistors in the filling region 150 serves as some of the I / O function circuits 110A to 140A or memory cells U. A Some bit units have head switches or tail switches.

[0033] The head switch of the I / O function circuit is a FET switch connected between the upper power supply (e.g., VDD) and the I / O function circuit. When the head switch is set to the connected state, the upper power supply is applied to the I / O function circuit. When the head switch is set to the open state, the I / O function circuit is decoupled from the upper power supply. The tail switch of the I / O function circuit is a FET switch connected between the lower power supply (e.g., VSS) and the I / O function circuit. When the tail switch is set to the connected state, the lower power supply is applied to the I / O function circuit. When the tail switch is set to the open state, the I / O function circuit is decoupled from the lower power supply.

[0034] exist Figure 2B In the I / O functional circuits 110B to 140B, each includes two PMOS active region structures 52p and 54p extending in the X direction and two NMOS active region structures 52n and 54n extending in the X direction. The two NMOS active region structures 52n and 54n are arranged between the two PMOS active region structures 52p and 54p. The fill region 150B includes two PMOS active region structures 55p1 and 55p2 extending in the X direction. PMOS active region structure 55p1 is adjacent to PMOS active region structure 52p of I / O functional circuit 110B, while PMOS active region structure 55p2 is adjacent to PMOS active region structure 54p of I / O functional circuit 120B. As an example, cross-sectional views of each of the NMOS active region structures (i.e., 52n and 54n) and PMOS active region structures (i.e., 52p and 54p) in I / O functional circuit 110B are shown. Figures 5A to 5D A cross-sectional view of each of the PMOS active region structures (i.e., 55p1 and 55p2) in one of the figures and in the filled region 150B is shown in [the figures]. Figure 5E Of Figure 5F One of the attached figures. Figures 5A to 5F Each of the cross-sectional diagrams in the diagram is individually Figure 2B One of the cutting planes AA', BB', CC', DD', PP', and QQ' shown.

[0035] exist Figure 2BIn each of the I / O functional circuits 110B to 140B, the NMOS transistor is either implemented in the NMOS active region structure 52n or in the NMOS active region structure 54n. The PMOS transistor in each of the I / O functional circuits 110B to 140B is either implemented in the PMOS active region structure 52p or in the PMOS active region structure 54p. In some embodiments, each of the two PMOS active region structures 55p1 and 55p2 within the fill region 150B is a dummy active region structure that does not contain functional transistors. In some embodiments, a method is used to support any of the I / O functional circuits 110B to 140B and the memory cell U. B The PMOS transistors operating in any of the bit cells in the PMOS region 150B implement one or more of the two PMOS active region structures 55p1 and 55p2. In some embodiments, one or more of the two PMOS active region structures 55p1 and 55p2 are implemented using PMOS transistors, and at least one of the PMOS transistors in the fill region 150B serves as some of the I / O function circuits 110B to 140B or memory cell U. B Some bit units have head switches or tail switches.

[0036] exist Figures 1A to 1B as well as Figures 2A to 2B Various implementations of the active region structure in the memory cell and various implementations of the transistor are within the scope of this disclosure. In some embodiments, each of the NMOS active region structure (i.e., 52n and 54n) and the PMOS active region structure (i.e., 52p and 54p) includes one or more fin structures; therefore, the NMOS transistor and PMOS transistor implemented with the active region structure are finFET transistors. In some embodiments, each of the NMOS active region structure (i.e., 52n and 54n) and the PMOS active region structure (i.e., 52p and 54p) includes one or more nanosheets; therefore, the NMOS transistor and PMOS transistor implemented with the active region structure are nanosheet transistors. In some embodiments, each of the NMOS active region structure (i.e., 52n and 54n) and the PMOS active region structure (i.e., 52p and 54p) includes one or more nanowires; therefore, the NMOS transistor and PMOS transistor implemented with the active region structure are nanowire transistors.

[0037] In this memory cell U, NMOS transistors are implemented in the filled region 150A. AIn some embodiments, the type of NMOS transistor implemented depends on the type of NMOS active region structure supporting the NMOS transistor. Examples of NMOS transistors implemented in the NMOS active region structures 55n1 and 55n2 of fill region 150A include finFET transistors, nanosheet transistors, and nanowire transistors. In this embodiment, a PMOS transistor is implemented in memory cell U in fill region 150B. B In some embodiments, the type of PMOS transistor implemented depends on the type of PMOS active region structure supporting the PMOS transistor. Examples of PMOS transistors implemented in the PMOS active region structures 55p1 and 55p2 of the filled region 150B include finFET transistors, nanosheet transistors, and nanowire transistors.

[0038] Figures 3A to 3F According to some embodiments Figure 2A The cross-sectional views of the device along various cutting planes, the device is Figure 1A memory unit U A Part of it. Figure 3A (It is along) Figure 2A In the cross-sectional view of the cut plane AA', the NMOS active region structure 54n is on the substrate 30. Each gate conductor (e.g., g54n) intersects the NMOS active region structure 54n, and at least one of the gate conductors forms the gate terminal of the NMOS transistor. Each terminal conductor (e.g., t54n) intersects the NMOS active region structure 54n, and at least one of the terminal conductors forms the source or drain terminal of the NMOS transistor. In some embodiments, the active regions in the NMOS active region structure 54n (e.g., the channel region below the gate terminal, and the source or drain region below the source terminal) are isolated from the active regions in adjacent circuit cells by boundary isolation regions i301A below the dummy gate conductor 301A and i309A below the dummy gate conductor 309A.

[0039] exist Figure 3B (It is along) Figure 2AIn the cross-sectional view of the cut plane BB', the PMOS active region structure 54p is on the substrate 30. Each gate conductor (e.g., g54p) intersects the PMOS active region structure 54p, and at least one of the gate conductors forms the gate terminal of the PMOS transistor. Each terminal conductor (e.g., t54p) intersects the PMOS active region structure 54p, and at least one of the terminal conductors forms the source or drain terminal of the PMOS transistor. In some embodiments, the active regions (e.g., channel regions, source regions, or drain regions) in the PMOS active region structure 54p are isolated from the active regions in adjacent circuit cells by boundary isolation regions i301B below the dummy gate conductor 301B and i309B below the dummy gate conductor 309B.

[0040] exist Figure 3C (It is along) Figure 2A In the cross-sectional view of the cut plane CC', the PMOS active region structure 52p is on the substrate 30. Each gate conductor (e.g., g52p) intersects the PMOS active region structure 52p, and at least one of the gate conductors forms the gate terminal of the PMOS transistor. Each terminal conductor (e.g., t52p) intersects the PMOS active region structure 52p, and at least one of the terminal conductors forms the source or drain terminal of the PMOS transistor. In some embodiments, the active regions (e.g., channel regions, source regions, or drain regions) in the PMOS active region structure 52p are isolated from the active regions in adjacent circuit cells by boundary isolation regions i301C below the dummy gate conductor 301C and i309C below the dummy gate conductor 309C.

[0041] exist Figure 3D (It is along) Figure 2A In the cross-sectional view of the cut plane DD', the NMOS active region structure 52n is on the substrate 30. Each gate conductor (e.g., g52n) intersects the NMOS active region structure 52n, and at least one of the gate conductors forms the gate terminal of the NMOS transistor. Each terminal conductor (e.g., t52n) intersects the NMOS active region structure 52n, and at least one of the terminal conductors forms the source or drain terminal of the NMOS transistor. In some embodiments, the active regions (e.g., channel regions, source regions, or drain regions) in the NMOS active region structure 52n are isolated from the active regions in adjacent circuit cells by boundary isolation regions i301D below the dummy gate conductor 301D and i309D below the dummy gate conductor 309D.

[0042] exist Figure 3E (It is along) Figure 2AIn the cross-sectional view of the cut plane PP', the NMOS active region structure 55n1 is on the substrate 30. Transistors are not implemented in the NMOS active region structure 55n1 between the boundary isolation regions i301E and i309E. The boundary isolation region i301E is below the dummy gate-conductor 301E, and the boundary isolation region i309E is below the dummy gate-conductor 309E. In some embodiments, the boundary isolation regions i301E and i309E are not implemented in the NMOS active region structure 55n1 at the boundary of the first circuit region containing the I / O functional circuitry. Additionally, in some embodiments, the dummy gate-conductor 301E and dummy gate-conductor 309E are also not implemented at the boundary.

[0043] exist Figure 3F (It is along) Figure 2A In the cross-sectional view of the cut plane QQ', the NMOS active region structure 55n2 is on the substrate 30. Transistors are not implemented in the NMOS active region structure 55n2 between the boundary isolation regions i301F and i309F. The boundary isolation region i301F is below the dummy gate-conductor 301F, and the boundary isolation region i309F is below the dummy gate-conductor 309F. In some embodiments, the boundary isolation regions i301F and i309F are not implemented in the NMOS active region structure 55n2 at the boundary of the first circuit region containing the I / O functional circuitry. Additionally, in some embodiments, the dummy gate-conductor 301F and dummy gate-conductor 309F are also not implemented at the boundary.

[0044] exist Figures 3E to 3F In the illustrated embodiment, the transistors are not implemented in the NMOS active region structures 55n1 and 55n2 within the first circuit region containing the I / O functional circuitry. In some alternative embodiments, such as Figures 4A to 4B As shown, NMOS transistors are implemented in NMOS active region structures 55n1 and 55n2 within the first circuit region. In some embodiments, at least some of the NMOS transistors in NMOS active region structures 55n1 and 55n2 serve as head switches or tail switches for some of the I / O function circuits in I / O function circuits 110A to 140A. In some embodiments, at least some of the NMOS transistors in NMOS active region structures 55n1 and 55n2 serve as memory cell U. A Some bit units have head switches or tail switches.

[0045] exist Figure 4A (It is along) Figure 2AIn the cross-sectional view of the cut plane PP', the NMOS active region structure 55n1 is on the substrate 30. Each gate conductor (e.g., g55n1) intersects the NMOS active region structure 55n1, and at least one of the gate conductors forms the gate terminal of the NMOS transistor. Each terminal conductor (e.g., t55n1) intersects the NMOS active region structure 55n1, and at least one of the terminal conductors forms the source or drain terminal of the NMOS transistor. In some embodiments, the active regions in the NMOS active region structure 55n1 are isolated from the active regions in adjacent circuit cells by boundary isolation regions i301E below the dummy gate conductor 301E and i309E below the dummy gate conductor 309E.

[0046] exist Figure 4B (It is along) Figure 2A In the cross-sectional view of the cut plane QQ', the NMOS active region structure 55n2 is on the substrate 30. Each gate conductor (e.g., g55n2) intersects the NMOS active region structure 55n2, and at least one of the gate conductors forms the gate terminal of the NMOS transistor. Each terminal conductor (e.g., t55n2) intersects the NMOS active region structure 55n2, and at least one of the terminal conductors forms the source or drain terminal of the NMOS transistor. In some embodiments, the active regions in the NMOS active region structure 55n2 are isolated from the active regions in adjacent circuit cells by boundary isolation regions i301F below the dummy gate conductor 301F and i309F below the dummy gate conductor 309F.

[0047] Figures 5A to 5F According to some embodiments Figure 2B The cross-sectional views of the device along various cutting planes, the device is Figure 1B It is part of the memory unit UB. Figure 5A (It is along) Figure 2B In the cross-sectional view of the cut plane AA', the PMOS active region structure 54p is on the substrate 30. Each gate conductor (e.g., g54p) intersects the PMOS active region structure 54p, and at least one of the gate conductors forms the gate terminal of the PMOS transistor. Each terminal conductor (e.g., t54p) intersects the PMOS active region structure 54p, and at least one of the terminal conductors forms the source or drain terminal of the PMOS transistor. In some embodiments, the active regions in the PMOS active region structure 54p are isolated from the active regions in adjacent circuit cells by boundary isolation regions i501B below the dummy gate conductor 501B and i509B below the dummy gate conductor 509B.

[0048] exist Figure 5B (It is along) Figure 2B In the cross-sectional view of the cut plane BB', the NMOS active region structure 54n is on the substrate 30. Each gate conductor (e.g., g54n) intersects the NMOS active region structure 54n, and at least one of the gate conductors forms the gate terminal of the NMOS transistor. Each terminal conductor (e.g., t54n) intersects the NMOS active region structure 54n, and at least one of the terminal conductors forms the source or drain terminal of the NMOS transistor. In some embodiments, the active regions in the NMOS active region structure 54n are isolated from the active regions in adjacent circuit cells by boundary isolation regions i501B below the dummy gate conductor 501B and i509B below the dummy gate conductor 509B.

[0049] exist Figure 5C (It is along) Figure 2B In the cross-sectional view of the cut plane CC', the NMOS active region structure 52n is on the substrate 30. Each gate conductor (e.g., g52n) intersects the NMOS active region structure 52n, and at least one of the gate conductors forms the gate terminal of the NMOS transistor. Each terminal conductor (e.g., t52n) intersects the NMOS active region structure 52n, and at least one of the terminal conductors forms the source or drain terminal of the NMOS transistor. In some embodiments, the active regions in the NMOS active region structure 52n are isolated from the active regions in adjacent circuit cells by boundary isolation regions i501C below the dummy gate conductor 501C and i509C below the dummy gate conductor 509C.

[0050] exist Figure 5D (It is along) Figure 2B In the cross-sectional view of the cut plane DD', the PMOS active region structure 52p is on the substrate 30. Each gate conductor (e.g., g52p) intersects the PMOS active region structure 52p, and at least one of the gate conductors forms the gate terminal of the PMOS transistor. Each terminal conductor (e.g., t52p) intersects the PMOS active region structure 52p, and at least one of the terminal conductors forms the source or drain terminal of the PMOS transistor. In some embodiments, the active regions in the PMOS active region structure 52p are isolated from the active regions in adjacent circuit cells by boundary isolation regions i501D below the dummy gate conductor 501D and i509D below the dummy gate conductor 509D.

[0051] exist Figure 5E (It is along) Figure 2BIn the cross-sectional view of the cut plane PP', the PMOS active region structure 55p1 is on the substrate 30. A transistor is not implemented in the PMOS active region structure 55p1 between the boundary isolation region i501E and the boundary isolation region i509E. The boundary isolation region i501E is below the dummy gate-conductor 501E, and the boundary isolation region i509E is below the dummy gate-conductor 509E. In some embodiments, the boundary isolation regions i501E and i509E are not implemented in the PMOS active region structure 55p1 at the boundary of the first circuit region containing the I / O functional circuitry. Additionally, in some embodiments, the dummy gate-conductor 501E and dummy gate-conductor 509E are also not implemented at the boundary.

[0052] exist Figure 5F (It is along) Figure 2B In the cross-sectional view of the cut plane QQ', the PMOS active region structure 55p2 is on the substrate 30. A transistor is not implemented in the PMOS active region structure 55p2 between the boundary isolation regions i501F and i509F. The boundary isolation region i501F is below the dummy gate-conductor 501F, and the boundary isolation region i509F is below the dummy gate-conductor 509F. In some embodiments, the boundary isolation regions i501F and i509F are not implemented in the PMOS active region structure 55p2 at the boundary of the first circuit region containing the I / O functional circuitry. Additionally, in some embodiments, the dummy gate-conductor 501F and dummy gate-conductor 509F are also not implemented at the boundary.

[0053] exist Figures 5E to 5F In the illustrated embodiment, the transistor is not implemented in the PMOS active region structures 55p1 and 55p2 within the first circuit region containing the I / O functional circuitry. In some alternative embodiments, such as Figures 6A to 6B As shown, PMOS transistors are implemented in PMOS active region structures 55p1 and 55p2 within the first circuit region. In some embodiments, at least some PMOS transistors in PMOS active region structures 55p1 and 55p2 serve as head switches or tail switches for some I / O function circuits in I / O function circuits 110B to 140B. In some embodiments, at least some PMOS transistors in PMOS active region structures 55p1 and 55p2 serve as memory cell U. B Some bit units have head switches or tail switches.

[0054] exist Figure 6A (It is along) Figure 2BIn the cross-sectional view of the cut plane PP', the PMOS active region structure 55p1 is on the substrate 30. Each gate conductor (e.g., g55p1) intersects the PMOS active region structure 55p1, and at least one of the gate conductors forms the gate terminal of the PMOS transistor. Each terminal conductor (e.g., t55p1) intersects the PMOS active region structure 55p1, and at least one of the terminal conductors forms the source or drain terminal of the PMOS transistor. In some embodiments, the active regions in the PMOS active region structure 55p1 are isolated from the active regions in adjacent circuit cells by boundary isolation regions i501E below the dummy gate conductor 501E and i509E below the dummy gate conductor 509E.

[0055] exist Figure 6B (It is along) Figure 2B In the cross-sectional view of the cut plane QQ', the PMOS active region structure 55p2 is on the substrate 30. Each gate conductor (e.g., g55p2) intersects the PMOS active region structure 55p2, and at least one of the gate conductors forms the gate terminal of the PMOS transistor. Each terminal conductor (e.g., t55p2) intersects the PMOS active region structure 55p2, and at least one of the terminal conductors forms the source or drain terminal of the PMOS transistor. In some embodiments, the active regions in the PMOS active region structure 55p2 are isolated from the active regions in adjacent circuit cells by boundary isolation regions i501F below the dummy gate conductor 501F and i509F below the dummy gate conductor 509F.

[0056] In some embodiments, such as Figures 7A to 7B as well as Figures 8A to 8B As shown, the memory storage device includes Figure 1A Multiple memory units U A or Figure 1B Multiple memory units U B . Figure 7A The memory storage device includes three memory cells 100A1, 100A2, and 100A3 arranged along the Y direction. Each of the three memory cells 100A1, 100A2, and 100A3 has a... Figure 1A memory unit U A The same schematic circuit design and has the same Figure 1A memory unit U A Same layout. In Figure 8A More details are shown in the middle. Figure 7A The memory storage device in the memory. Similar to... Figure 1A memory unit U A ,like Figure 8AAs shown, each of the three memory cells 100A1, 100A2, and 100A3 includes a four-bit cell array and four I / O function circuits. Each bit cell array is associated with a corresponding I / O function circuit.

[0057] In each memory cell (i.e., 100A1, 100A2, or 100A3), four I / O functional circuits are aligned with each other in a first circuit region, and four bit cell arrays are aligned with each other in a second circuit region. In each of the three memory cells, a fill region in the first circuit region is implemented using two NMOS active region structures. Two of the I / O functional circuits are located on a first side of the fill region with the two NMOS active region structures, while the other two I / O functional circuits are located on a second side of the fill region with the two NMOS active region structures. In some embodiments, NMOS transistors are implemented as head switches or tail switches of the memory cell in the two NMOS active region structures of the fill region. In some embodiments, the two NMOS active region structures of the fill region are not implemented using functional transistors.

[0058] Figure 7B The memory storage device includes three memory cells 100B1, 100B2, and 100B3 arranged along the Y direction. Each of the three memory cells 100B1, 100B2, and 100B3 has a... Figure 1B memory unit U B The same schematic circuit design and has the same Figure 1B memory unit U B Same layout. In Figure 8B More details are shown in the middle. Figure 7B The memory storage device in the memory. Similar to... Figure 1B memory unit U B ,like Figure 8B As shown, each of the three memory cells 100B1, 100B2, and 100B3 includes a four-bit cell array and four I / O function circuits. Each bit cell array is associated with a corresponding I / O function circuit.

[0059] In each memory cell (i.e., 100B1, 100B2, or 100B3), four I / O functional circuits are aligned with each other in a first circuit region, and four bit cell arrays are aligned with each other in a second circuit region. In each of the three memory cells, a fill region in the first circuit region is implemented using two PMOS active region structures. Two of the I / O functional circuits are located on a first side of the fill region with the two PMOS active region structures, while the other two I / O functional circuits are located on a second side of the fill region with the two PMOS active region structures. In some embodiments, PMOS transistors are implemented as head switches or tail switches of the memory cell in the two PMOS active region structures of the fill region. In some embodiments, the two PMOS active region structures of the fill region are not implemented using functional transistors.

[0060] Figures 7A to 7B as well as Figures 8A to 8B The memory storage device is provided as an example. In some embodiments, the memory storage device includes more than three memory cells. For example, in Figure 9A In this context, memory storage devices include... Figure 1A Multiple memory units U A And memory unit U A The quantity is an integer n (greater than 3). Figure 9B In this context, memory storage devices include... Figure 1B Multiple memory units U B And memory unit U B The quantity is an integer n (greater than 3).

[0061] Figure 1A memory unit U in A and Figure 1B Memory unit U in B Provided as an example. Figures 1A to 1B Memory unit U in A and U B Each of them has a four-cell array arranged in four rows. The height H of the cell array is... bc Greater than the height H of the I / O function circuit io Height H bc and height H io The ratio between them is 9 / 8, which corresponds to equation 4H. bc =4.5H io And the height of the filled area (e.g., 150A or 150B) is 0.5H. io In some alternative embodiments, Figures 10A to 10B Memory unit U in A and U BEach of them comprises a six-bit cell array 180A to 180F arranged in six rows. Figures 10A to 10B Memory unit U in A and U B Each includes six I / O function circuits (e.g., 110A to 160A or 110B to 160B). The height of the fill area (e.g., 150A or 150B) remains 0.5H. io .exist Figures 10A to 10B In the middle, height H bc and height H io The ratio between them is 13 / 12, which corresponds to equation 6H. bc =6.5H io Memory cells with four-bit cell arrays or six-bit cell arrays are provided as examples. Memory cells with other integer-number bit cell arrays are within the scope of this disclosure.

[0062] In memory cells (e.g., Figure 1A U in A , Figure 1B U in B , Figure 10A U in A or Figure 10B U in B In this architecture, each bit cell array is associated with a corresponding I / O function circuit, or equivalently, each I / O function circuit is associated with a corresponding bit cell array. Each I / O function circuit is coupled to a bit cell in the corresponding bit cell array via one or more wires. An I / O function circuit is a circuit connected to the bit cell array and configured to transmit signals to and / or receive signals from the bit cell array via one or more wires connected to the bit cells in the bit cell array. Examples of I / O function circuits include word line drivers, precharge drivers, sense amplifiers, and read / write select drivers.

[0063] Figures 11A to 11B This is a schematic diagram of a memory cell having wires connecting I / O function circuitry to a bit cell array, according to some embodiments. Figures 11A to 11B In the memory unit U A It includes four I / O function circuits 110A to 140A and four bit cell arrays 180A to 180D. Bit cell array 180A includes six bit cells 80AA to 80AF, bit cell array 180B includes six bit cells 80BA to 80BF, bit cell array 180C includes six bit cells 80CA to 80CF, and bit cell array 180D includes six bit cells 80DA to 80DF. Figures 11A to 11B Each bit cell in the example is implemented as a single-port six-transistor SRAM cell. More details are shown below. Figure 11AThe two bit cells in the diagram (i.e., 80BC and 80DB) are shown in more detail. Figure 11B One of the bit units in the (i.e., 80dB). Figures 11A to 11B Other implementations of bit units in this disclosure are within the scope of this disclosure.

[0064] exist Figure 11A In the memory unit U A This includes four wires 185A to 185D extending in the X direction. Each of the six bit cells 80AA to 80AF in bit cell array 180A is connected to wire 185A, which is further connected to I / O function circuit 130A. Each of the six bit cells 80BA to 80BF in bit cell array 180B is connected to wire 185B, which is further connected to I / O function circuit 110A. Each of the six bit cells 80CA to 80CF in bit cell array 180C is connected to wire 185C, which is further connected to I / O function circuit 120A. Each of the six bit cells 80AD to 80DF in bit cell array 180D is connected to wire 185D, which is further connected to I / O function circuit 140A.

[0065] exist Figure 11A In this configuration, each of the four conductors 185A to 185D extending in the X direction is a word line, and each of the four I / O function circuits 110A to 140A is a word line driver. Each column bit cell is connected to a corresponding pair of bit lines BL and BLb. The voltage transmitted from the word line driver to the word line is applied to the corresponding row of bit cells (which are connected to the word line), and the voltage on the word line determines whether each bit cell in the corresponding row is in read / write mode or memory mode. In read mode, the latch state of the bit cell is detected based on the voltage / current appearing on the corresponding pair of bit lines BL and BLb coupled to the bit cell. In write mode, the latch state of the bit cell is set by applying the voltage / current to the corresponding pair of bit lines BL and BLb coupled to the bit cell. In memory mode, the latch state of the bit cell is maintained because the internal latch circuitry in the bit cell is electrically isolated from the corresponding pair of bit lines BL and BLb connected to the bit cell.

[0066] exist Figure 11B In the memory unit U AThis includes four pairs of wires 186A1 to 186A2, 186B1 to 186B2, 186C1 to 186C2, and 186D1 to 186D2. Each wire extends in the X direction. Each of the six bit cells 80AA to 80AF in the bit cell array 180A is connected to a pair of wires 186A1 to 186A2, which are further connected to the IO function circuit 130A. Each of the six bit cells 80BA to 80BF in the bit cell array 180B is connected to a pair of wires 186B1 to 186B2, which are further connected to the IO function circuit 110A. Each of the six bit cells 80CA to 80CF in the bit cell array 180C is connected to a pair of wires 186C1 to 186C2, which are further connected to the IO function circuit 120A. Each of the six bit cells 80AD to 80DF in the bit cell array 180D is connected to a pair of wires 186D1 to 186D2, which are further connected to the IO function circuit 140A.

[0067] exist Figure 11B In this configuration, each of the four pairs of wires extending in the X direction is a pair of bit lines BL and BLb. A pair of wires 186A1 to 186A2 are a pair of bit lines for bit cell array 180A, a pair of wires 186B1 to 186B2 are a pair of bit lines for bit cell array 180B, a pair of wires 186C1 to 186C2 are a pair of bit lines for bit cell array 180C, and a pair of wires 186D1 to 186D2 are a pair of bit lines for bit cell array 180D. Each of the IO function circuits 110A to 140A (which is connected to the corresponding pair of bit lines) includes a sense amplifier and / or a precharge driver.

[0068] In such Figure 11AIn the illustrated embodiment, each of the four bit cell arrays (i.e., 180A, 180B, 180C, or 180D) is connected to a conductor used as a word line, and the corresponding I / O function circuit connected to the conductor includes a word line driver. In some alternative embodiments, each of the four bit cell arrays (i.e., 180A, 180B, 180C, or 180D) is connected to two conductors extending in the X direction. The two conductors connected to each bit cell array are also connected to the corresponding I / O function circuit (i.e., one of the four I / O function circuits 110A to 140A). One of the two conductors serves as a word line, and the other serves as a read / write select line. The corresponding I / O function circuit connected to the two conductors includes a word line driver and / or a read / write select driver. Each bit cell in the bit cell array has a port connected to the word line and a port connected to the read / write select line. The voltage transmitted from the read / write select driver to the read / write select line determines whether each bit cell in the corresponding row is in read-to-write mode or write-to-write mode. The voltage transmitted from the word line driver to the word line determines whether each bit cell in the corresponding row is enabled for read / write mode.

[0069] Figure 12 This is a flowchart of a method 1200 for manufacturing an integrated circuit according to some embodiments. Figure 12 The order of operations shown in method 1200 is for illustrative purposes only; it can be performed in a different manner. Figure 12 The sequential execution of method 1200 is shown. It should be understood that... Figure 12 Additional operations are performed before, during, and / or after the method 1200 shown, and this document may only briefly describe some other processes.

[0070] In operation 1210 of method 1200, a first group of first-type active region structures, a second group of first-type active region structures, and a third group of first-type active region structures are formed on a substrate. Each first-type active region structure extends in the X direction. The third group of first-type active region structures is adjacent to a first first-type active region structure in the first group of first-type active region structures and to a second first-type active region structure in the second group of first-type active region structures. Figure 2A as well as Figures 3A to 3F In the illustrated embodiment, the first group of first-type active region structures includes NMOS active region structures 52n and 54n in the IO functional circuit 110A, the second group of first-type active region structures includes NMOS active region structures 52n and 54n in the IO functional circuit 120A, and the third group of first-type active region structures includes NMOS active region structures 55n1 and 55n2 in the filled region 150A. Figure 2B as well as Figures 5A to 5FIn the illustrated embodiment, the first group of first-type active region structures includes PMOS active region structures 52p and 54p in the IO function circuit 110B, the second group of first-type active region structures includes PMOS active region structures 52p and 54p in the IO function circuit 120B, and the third group of first-type active region structures includes PMOS active region structures 55p1 and 55p2 in the filling region 150B.

[0071] In operation 1220 of method 1200, a first group of second-type active region structures and a second group of second-type active region structures are formed on a substrate. Each second-type active region structure extends in the X direction. The second group of first-type active region structures and the second group of second-type active region structures are separated from the first group of first-type active region structures and the first group of second-type active region structures by a filling region in which a third group of first-type active region structures are located. Figure 2A In the illustrated embodiment, the first group of second-type active region structures includes PMOS active region structures 52p and 54p in the IO function circuit 110A, while the second group of second-type active region structures includes PMOS active region structures 52p and 54p in the IO function circuit 120A. In such... Figure 2B In the illustrated embodiment, the first group of second-type active region structures includes NMOS active region structures 52n and 54n in the IO function circuit 110B, while the second group of second-type active region structures includes NMOS active region structures 52n and 54n in the IO function circuit 120B.

[0072] In operation 1230 of method 1200, gate-conductors and terminal-conductors are manufactured. Some gate-conductors intersect with one or more active region structures and form the gate terminals of various transistors. Some terminal-conductors intersect with one or more active region structures and form the source or drain terminals of various transistors. Figures 3A to 3F or Figures 5A to 5F In the illustrated embodiment, cross-sections of the various gate-conductors and terminal-conductors intersecting with the active region structure are depicted.

[0073] In operation 1240 of method 1200, a first I / O functional circuit is formed using transistors in the first group of first-type active region structures, and a first group of second-type active region structures is formed. Figure 2A In the embodiment shown, the NMOS transistors in the NMOS active region structures 52n and 54n and the PMOS transistors in the PMOS active region structures 52p and 54p form the IO function circuit 110A.

[0074] In operation 1250 of method 1200, a second IO functional circuit is formed using transistors in the second group of first-type active region structures and the second group of second-type active region structures. Figure 2A In the embodiment shown, the NMOS transistors in the NMOS active region structures 52n and 54n and the PMOS transistors in the PMOS active region structures 52p and 54p form the IO function circuit 120A.

[0075] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0076] In some embodiments, the EDA system 1300 includes an Automatic Placement and Routing (APR) system. The design layout view method described herein represents wire routing arrangements according to one or more embodiments, and according to some embodiments, can be implemented, for example, using the EDA system 1300.

[0077] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. The computer-readable storage medium 1304 is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions) and others. The instructions 1306, executed by the hardware processor 1302, represent (at least partially) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter referred to as the described process and / or method).

[0078] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to I / O interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1004 to make system 1300 available for performing some or all of the described processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0079] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes compact disc read-only memory (CD-ROM), rewritable recordable compact disc (CD-R / W), and / or digital video optical disc (DVD).

[0080] In one or more embodiments, computer-readable storage medium 1304 stores computer program code 1306 configured to enable EDA system 1300 (where such execution (at least partially) represents an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, computer-readable storage medium 1304 also stores information facilitating the execution of some or all of the described processes and / or methods. In one or more embodiments, computer-readable storage medium 1304 stores a standard cell library 1307 comprising standard cells as disclosed herein. In one or more embodiments, computer-readable storage medium 1304 stores one or more layout views 1309 corresponding to one or more layouts disclosed herein.

[0081] EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0082] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows EDA system 1300 to communicate with a network 1314 to which one or more other computer systems are connected. Network interface 1312 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more EDA systems 1300.

[0083] EDA system 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. The information is transmitted to processor 1302 via bus 1308. EDA system 1300 is also configured to receive information related to the user interface (UI) via I / O interface 1310. This information is stored in computer-readable storage medium 1304 as UI 1342.

[0084] In some embodiments, some or all of the described processes and / or methods are implemented as a standalone software application for processor execution. In some embodiments, some or all of the described processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the described processes and / or methods are implemented as a software application used by EDA system 1300. In some embodiments, software such as those available from CADENCE DESIGN SYSTEMS is used. Use tools like these or another suitable layout generation tool to generate a layout view that includes standard cells.

[0085] In some embodiments, these processes are implemented as the functionality of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory cells, such as one or more of the following: optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0086] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system 1400 according to some embodiments and the associated IC manufacturing process. In some embodiments, based on a layout view, the IC manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0087] exist Figure 14In this IC manufacturing system 1400, entities interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1460, such as design room 1420, mask room 1430, and IC manufacturer / fab (“fab”) 1450. The entities in the IC manufacturing system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1420, mask room 1430, and IC fab 1450 are owned by a single, larger company. In some embodiments, two or more of the design room 1420, mask room 1430, and IC fab 1450 coexist in a shared facility and use shared resources.

[0088] Design studio (or design team) 1420 generates an IC design layout view 1422. The IC design layout view 1422 includes various geometric patterns designed for an IC device 1460. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the integrated circuit device 1460 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout view 1422 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design studio 1420 implements appropriate design procedures to form the IC design layout view 1422. These design procedures include one or more of logic design, physical design, or placement and routing. The IC design layout view 1422 is presented in one or more data files containing geometric pattern information. For example, the IC design layout view 1422 may be represented in GDSII or DFII file format.

[0089] Mask chamber 1430 includes mask data preparation 1432 and mask fabrication 1444. Mask chamber 1430 uses an IC design layout view 1422 to fabricate one or more masks 1445 for use in fabricating various layers of an IC device 1460 based on the IC design layout view 1422. Mask chamber 1430 performs mask data preparation 1432, in which the IC design layout view 1422 is converted into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 1445 or a semiconductor wafer 1453). The design layout view 1422 is manipulated by mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of ICfab 1450. Figure 14 In this design, mask data preparation 1432 and mask manufacturing 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask manufacturing 1444 may be collectively referred to as mask data preparation.

[0090] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout view 1422. In some embodiments, mask data preparation 1432 also includes resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0091] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that uses a set of mask creation standard rules to check the IC design layout view 1422, which has already been processed in the OPC. This set of mask creation standard rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout view 1422 to compensate for lithographic effects during mask fabrication 1444, and can undo some modifications performed by the OPC to meet the mask creation standard rules.

[0092] In some embodiments, mask data preparation 1432 includes a lithography process inspection (LPC) simulating a process that will be implemented by IC fab 1450 to manufacture IC device 1460. The LPC simulates this process based on IC design layout view 1422 to create a simulated manufactured device, such as IC device 1460. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the shape of the simulated device is insufficient to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0093] It should be understood that the above description of mask data preparation 1432 has been simplified for clarity. In some embodiments, mask data preparation 1432 includes additional features such as logic operations (LOPs) to modify the IC design layout view 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout view 1422 during mask data preparation 1432 can be performed in various different sequences.

[0094] Following mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 is fabricated based on a modified IC design layout view 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the IC design layout view 1422. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or scribe line) 1445 based on the modified IC design layout view 1422. The mask 1445 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1445. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1445, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The mask(s) generated by mask fabrication 1444 are used in various processes. For example, such masks(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0095] IC fab 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, there may be a manufacturing facility (front-end process (FEOL) manufacturing) for front-end manufacturing of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging of IC products, and a third manufacturing facility may provide other services to the foundry enterprise.

[0096] IC fab 1450 includes manufacturing tool 1452 configured to perform various manufacturing operations on semiconductor wafer 1453 to manufacture IC device 1460 according to one or more masks (e.g., mask 1445). In various embodiments, manufacturing tool 1452 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment as discussed herein capable of performing one or more suitable manufacturing processes.

[0097] IC fab 1450 manufactures IC device 1460 using one or more masks 1445 manufactured by mask chamber 1430. Therefore, IC fab 1450 manufactures IC device 1460 at least indirectly using IC design layout view 1422. In some embodiments, semiconductor wafer 1453 is manufactured by IC fab 1450 using one or more masks 1445 to form IC device 1460. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout view 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1453 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0098] One aspect of this disclosure relates to an integrated circuit. The circuit includes: a first group of first-type active region structures, each of the first-type active region structures extending in a first direction; a first group of second-type active region structures, each of the second-type active region structures extending in a first direction; a second group of first-type active region structures, each of the first-type active region structures extending in a first direction; and a second group of second-type active region structures, each of the second-type active region structures extending in a first direction. The circuit further includes: a third group of first-type active region structures, each of which extends in a first direction, wherein the first group of first-type active region structures and the first group of second-type active region structures are separated from the second group of first-type active region structures and the second group of second-type active region structures by the third group of first-type active region structures along a second direction, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures and is adjacent to the first-type active region structures in the second group of first-type active region structures; a first IO function circuit having first-type transistors in the first group of first-type active region structures and second-type transistors in the first group of second-type active region structures; and a second IO function circuit having first-type transistors in the second group of first-type active region structures and second-type transistors in the second group of second-type active region structures.

[0099] Another aspect of this disclosure relates to an integrated circuit. The integrated circuit includes: a first group of first-type active region structures, each of the first-type active region structures extending in a first direction; a first group of second-type active region structures, each of the second-type active region structures extending in the first direction; a first I / O functional circuit having first-type transistors in the first group of first-type active region structures and second-type transistors in the first group of second-type active region structures; and a second I / O functional circuit having first-type transistors in the second group of first-type active region structures and second-type transistors in the second group of second-type active region structures. The circuit further includes: a third group of first-type active region structures, each of the first-type active region structures extending in the first direction, wherein the first I / O functional circuit is separated from the second I / O functional circuit by the third group of first-type active region structures along a second direction, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures and is adjacent to the first-type active region structures in the second group of first-type active region structures.

[0100] Another aspect of this disclosure relates to a method of manufacturing an integrated circuit. The method includes: forming a first group of first-type active region structures, a second group of first-type active region structures, and a third group of first-type active region structures, wherein the third group of first-type active region structures is adjacent to a first first-type active region structure in the first group of first-type active region structures and adjacent to a second first-type active region structure in the second group of first-type active region structures. The method further includes: forming a first group of second-type active region structures and a second group of second-type active region structures, wherein the second group of first-type active region structures and the second group of second-type active region structures are separated from the first group of first-type active region structures and the first group of second-type active region structures by a filling region having the third group of first-type active region structures therein. The method further includes: fabricating gate-conductors and terminal-conductors extending in a second direction, wherein each active region structure extends in a first direction perpendicular to the second direction; the method further includes: forming a first I / O functional circuit having transistors in the first group of first-type active region structures and the first group of second-type active region structures. The method further includes: forming a second IO functional circuit having transistors in a second set of first-type active region structures and a second set of second-type active region structures.

[0101] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0102] Example

[0103] Example 1. An integrated circuit, comprising: a first group of first-type active region structures, each of the first-type active region structures extending in a first direction; a first group of second-type active region structures, each of the second-type active region structures extending in the first direction; a second group of first-type active region structures, each of the first-type active region structures extending in the first direction; a second group of second-type active region structures, each of the second-type active region structures extending in the first direction; and a third group of first-type active region structures, each of the first-type active region structures extending in the first direction, wherein the first group of first-type active region structures and the first group of second-type active region structures are connected to the second group of first-type active region structures along a second direction via the third group of first-type active region structures. The first group of active region structures is separated from the second group of second-type active region structures, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures and is adjacent to the first-type active region structures in the second group of first-type active region structures; a first IO functional circuit having a first-type transistor in the first group of first-type active region structures and a second-type transistor in the first group of second-type active region structures; and a second IO functional circuit having a first-type transistor in the second group of first-type active region structures and a second-type transistor in the second group of second-type active region structures.

[0104] Example 2. An integrated circuit according to Example 1, wherein: each transistor in the first IO functional circuit is either in the first group of first type active region structures or in the first group of second type active region structures; and each transistor in the second IO functional circuit is either in the second group of first type active region structures or in the second group of second type active region structures.

[0105] Example 3. The integrated circuit according to Example 1 further includes: a first cell array connected to a first wire extending in the first direction, wherein the first wire is directly connected to the first I / O functional circuit; and a second cell array connected to a second wire extending in the first direction, wherein the second wire is directly connected to the second I / O functional circuit.

[0106] Example 4. The integrated circuit according to Example 3, wherein: each of the first IO function circuit and the second IO function circuit is in a circuit cell whose height along the second direction is less than the height of a bit cell in the first bit cell array or the second bit cell array.

[0107] Example 5. The integrated circuit according to Example 1, wherein the first IO functional circuit and the second IO functional circuit in the first circuit region further include: a first bit cell array and a second bit cell array located in a second circuit region that does not overlap with the first circuit region; a first wire extending in the first direction, directly connecting each bit cell in the first bit cell array to the first IO functional circuit; and a second wire extending in the first direction, directly connecting each bit cell in the second bit cell array to the second IO functional circuit.

[0108] Example 6. The integrated circuit according to Example 1, wherein: the third group of first type active region structures has first type transistors therein, the first type transistors being configured as head switches or tail switches coupled between a power supply and the first IO function circuit.

[0109] Example 7. The integrated circuit according to Example 1, wherein: the third group of first type active region structures has first type transistors therein, the first type transistors being configured as head switches or foot switches coupled between a power supply and the second IO functional circuit.

[0110] Example 8. An integrated circuit according to Example 1, wherein: each first type transistor is an NMOS transistor; and each second type transistor is a PMOS transistor.

[0111] Example 9. An integrated circuit according to Example 1, wherein: each first type transistor is a PMOS transistor; and each second type transistor is an NMOS transistor.

[0112] Example 10. The integrated circuit according to Example 1, wherein: the first IO function circuit includes a first word line driver; and the second IO function circuit includes a second word line driver.

[0113] Example 11. The integrated circuit according to Example 1, wherein: the first IO function circuit includes a first sense amplifier; and the second IO function circuit includes a second sense amplifier.

[0114] Example 12. An integrated circuit, comprising: a first group of first-type active region structures, each of the first-type active region structures extending in a first direction; a first group of second-type active region structures, each of the second-type active region structures extending in the first direction; a first I / O functional circuit having a first-type transistor in the first group of first-type active region structures and having a second-type transistor in the first group of second-type active region structures; a second group of first-type active region structures, each of the first-type active region structures extending in the first direction; a second group of second-type active region structures, each of the second-type active region structures extending in the first direction; and a second I / O functional circuit having a second-type active region structure extending in the first direction. The first group of active region structures includes a first type of transistor in a first type of active region structure and a second type of transistor in a second group of active region structures; and a third group of first type of active region structures, each of which extends in a first direction, wherein the first I / O functional circuit is separated from the second I / O functional circuit by the third group of first type of active region structures along a second direction, wherein the second direction is perpendicular to the first direction, and wherein the third group of first type of active region structures is adjacent to the first type of active region structures in the first group of first type of active region structures and is adjacent to the first type of active region structures in the second group of first type of active region structures.

[0115] Example 13. An integrated circuit according to Example 12, wherein: each transistor in the first IO functional circuit is either in the first group of first type active region structures or in the first group of second type active region structures; and each transistor in the second IO functional circuit is either in the second group of first type active region structures or in the second group of second type active region structures.

[0116] Example 14. The integrated circuit according to Example 12, wherein each first type of active region structure is an NMOS active region structure.

[0117] Example 15. The integrated circuit according to Example 12, wherein each first type of active region structure is a PMOS active region structure.

[0118] Example 16. A method comprising: forming a first group of first-type active region structures, a second group of first-type active region structures, and a third group of first-type active region structures, wherein the third group of first-type active region structures is adjacent to a first first-type active region structure in the first group of first-type active region structures and adjacent to a second first-type active region structure in the second group of first-type active region structures; forming a first group of second-type active region structures and a second group of second-type active region structures, wherein the second group of first-type active region structures and the second group of second-type active region structures are separated from the first group of first-type active region structures and the first group of second-type active region structures by a filling region having the third group of first-type active region structures therein; fabricating gate-conductors and terminal-conductors extending in a second direction, wherein each active region structure extends in a first direction perpendicular to the second direction; forming a first I / O functional circuit having transistors in the first group of first-type active region structures and the first group of second-type active region structures; and forming a second I / O functional circuit having transistors in the second group of first-type active region structures and the second group of second-type active region structures.

[0119] Example 17. The method according to Example 16 further includes: forming a first bit array, wherein each bit cell in the first bit array is connected to a first wire, the first wire being directly connected to the first I / O function circuit; and forming a second bit array, wherein each bit cell in the second bit array is connected to a second wire, the second wire being directly connected to the first I / O function circuit.

[0120] Example 18. The method according to Example 16 further includes: forming a first bit array, wherein each bit cell in the first bit array is connected to a first wire extending in the first direction, and wherein the first wire is configured to receive a signal from the first I / O function circuit; and forming a second bit array, wherein each bit cell in the second bit array is connected to a second wire extending in the first direction, and wherein the second wire is configured to receive a signal from the second I / O function circuit.

[0121] Example 19. The method according to Example 16 further includes: forming a first bit array, wherein each bit cell in the first bit array is connected to a first wire extending in the first direction, and wherein the first wire is configured to transmit a signal to the first I / O function circuit; and forming a second bit array, wherein each bit cell in the second bit array is connected to a second wire extending in the first direction, and wherein the second wire is configured to transmit a signal to the second I / O function circuit.

[0122] Example 20. The method according to Example 16 further includes: forming each of the first type active region structures in the third group of first type active region structures as a dummy active region structure in a filling region in which there are no transistors.

Claims

1. An integrated circuit, comprising: The first group of first-type active region structures, each of which extends in the first direction; The first group of second-type active region structures, each of which extends in the first direction; The second group of first-type active region structures, each of which extends in the first direction; The second group of second-type active region structures, each of which extends in the first direction; The third group of first-type active region structures, each of which extends in the first direction, wherein the first group of first-type active region structures and the first group of second-type active region structures are separated from the second group of first-type active region structures and the second group of second-type active region structures by the third group of first-type active region structures along the second direction, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures and is adjacent to the first-type active region structures in the second group of first-type active region structures; A first I / O functional circuit, having a first type of transistor in the first group of first type active region structures, and having a second type of transistor in the first group of second type active region structures; and The second IO function circuit has a first type transistor in the second group of first type active region structures and a second type transistor in the second group of second type active region structures.

2. The integrated circuit according to claim 1, wherein: Each transistor in the first IO functional circuit is either in the first group of first type active region structures or in the first group of second type active region structures; as well as Each transistor in the second IO functional circuit is either in the second group of first type active region structures or in the second group of second type active region structures.

3. The integrated circuit according to claim 1, further comprising: The first unit array is connected to a first wire extending in the first direction, wherein the first wire is directly connected to the first IO function circuit; and The second bit cell array is connected to a second wire extending in the first direction, wherein the second wire is directly connected to the second IO function circuit.

4. The integrated circuit according to claim 3, wherein: Each of the first IO function circuit and the second IO function circuit is located in a circuit cell whose height along the second direction is less than the height of a bit cell in the first bit cell array or the second bit cell array.

5. The integrated circuit according to claim 1, wherein, The first I / O function circuit and the second I / O function circuit in the first circuit region further include: The first unit array and the second unit array are located in the second circuit region that does not overlap with the first circuit region; A first wire extending in the first direction directly connects each bit cell in the first bit cell array to the first I / O functional circuit; and A second wire extending in the first direction directly connects each bit cell in the second bit cell array to the second IO function circuit.

6. The integrated circuit according to claim 1, wherein: The third group of first-type active region structures has first-type transistors therein, the first-type transistors being configured as head switches or tail switches coupled between the power supply and the first IO function circuit.

7. The integrated circuit according to claim 1, wherein: The third group of first-type active region structures has first-type transistors configured as head switches or foot switches coupled between a power supply and the second IO function circuit.

8. The integrated circuit according to claim 1, wherein: Each type-1 transistor is an NMOS transistor; and Each type II transistor is a PMOS transistor.

9. An integrated circuit, comprising: The first group of first-type active region structures, each of which extends in the first direction; The first group of second-type active region structures, each of which extends in the first direction; The first IO functional circuit has a first type of transistor in the first group of first type active region structures and a second type of transistor in the first group of second type active region structures. The second group of first-type active region structures, each of which extends in the first direction; The second group of second-type active region structures, each of which extends in the first direction; The second IO functional circuit has a first type transistor in the second group of first type active region structures and a second type transistor in the second group of second type active region structures. as well as The third group of first-type active region structures, each of which extends in the first direction, wherein the first IO functional circuit is separated from the second IO functional circuit by the third group of first-type active region structures along the second direction, wherein the second direction is perpendicular to the first direction, and wherein the third group of first-type active region structures is adjacent to the first-type active region structures in the first group of first-type active region structures, and is also adjacent to the first-type active region structures in the second group of first-type active region structures.

10. A method for forming an integrated circuit, comprising: A first group of first-type active region structures, a second group of first-type active region structures, and a third group of first-type active region structures are formed. The third group of first-type active region structures is adjacent to a first first-type active region structure in the first group of first-type active region structures and is also adjacent to a second first-type active region structure in the second group of first-type active region structures. A first group of second-type active region structures and a second group of second-type active region structures are formed, wherein the second group of first-type active region structures and the second group of second-type active region structures are separated from the first group of first-type active region structures and the first group of second-type active region structures by a filling region having the third group of first-type active region structures therein; A gate-conductor and a terminal-conductor extending in a second direction are fabricated, wherein each active region structure extends in a first direction perpendicular to the second direction; Forming a first I / O functional circuit having transistors in the first group of first type active region structures and the first group of second type active region structures; and A second IO functional circuit is formed having transistors in the second group of first type active region structures and the second group of second type active region structures.

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