Semiconductor device

Abstract

A semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate; a bit line in contact with a first end portion of each semiconductor pattern in the first direction and extending in a third direction perpendicular to an upper surface of the substrate; a plurality of word lines overlapping the plurality of semiconductor patterns in the third direction, respectively, and extending in a second direction intersecting the first direction; and a plurality of capacitors in contact with a second end portion of a corresponding semiconductor pattern of the plurality of semiconductor patterns along the first direction. Each word line includes a first conductive liner layer, a second conductive liner layer, and a conductive layer sequentially located on a corresponding semiconductor pattern of the plurality of semiconductor patterns, and the first conductive liner layer and the second conductive liner layer include materials different from each other or include the same material having a composition ratio different from each other.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] The goal is to increase the integration density of semiconductor devices. For two-dimensional semiconductor devices, the integration density is mainly determined by the area occupied by a unit memory cell, and this aspect of integration density may be affected by the level of fine patterning technology.

[0003] However, fine patterning techniques use expensive equipment and still limit the integration of two-dimensional semiconductor devices. Three-dimensional semiconductor memory devices, including memory cells arranged in three dimensions, have been proposed. Summary of the Invention

[0004] The embodiments attempt to provide semiconductor devices capable of controlling the threshold voltage of word lines and improving defects caused by bending.

[0005] Some embodiments of this disclosure provide a semiconductor device, including: a substrate; a plurality of semiconductor patterns located on the substrate; a bit line contacting a first end of each of the plurality of semiconductor patterns in a first direction and extending upward in a third direction perpendicular to the upper surface of the substrate; a plurality of word lines overlapping the plurality of semiconductor patterns in the third direction and extending in a second direction intersecting the first direction; and a plurality of capacitors contacting a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns along the first direction, wherein each of the plurality of word lines includes a first conductive substrate, a second conductive substrate, and a conductive layer sequentially located on a corresponding semiconductor pattern in the plurality of semiconductor patterns, wherein the first conductive substrate and the second conductive substrate comprise different materials from each other or comprise the same material having different compositional ratios from each other.

[0006] Some embodiments of this disclosure provide a semiconductor device, including: a substrate; a plurality of semiconductor patterns located on the substrate; a bit line contacting a first end of each of the plurality of semiconductor patterns in a first direction and extending upward in a third direction perpendicular to an upper surface of the substrate; a plurality of word lines overlapping the plurality of semiconductor patterns in the third direction and extending in a second direction intersecting the first direction; and a plurality of capacitors contacting a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns along the first direction, wherein each of the plurality of word lines includes: a first conductive liner located on a corresponding semiconductor pattern in the plurality of semiconductor patterns; a second conductive liner located on the first conductive liner; and a conductive layer located on the second conductive liner, wherein the conductive layer is thicker than each of the first conductive liner and the second conductive liner.

[0007] Some embodiments of this disclosure provide a semiconductor device, including: a substrate; a plurality of semiconductor patterns and a plurality of interlayer insulating layers, the plurality of semiconductor patterns and the plurality of interlayer insulating layers being alternately located on the substrate; a bit line, the bit line contacting a first end of each of the plurality of semiconductor patterns in a first direction and extending upward in a third direction perpendicular to the upper surface of the substrate; a plurality of word lines, the plurality of word lines respectively overlapping the plurality of semiconductor patterns in the third direction and extending in a second direction intersecting the first direction; and a plurality of capacitors, the plurality of capacitors contacting a second end of a corresponding semiconductor pattern of the plurality of semiconductor patterns along the first direction, wherein each of the plurality of word lines includes a first conductive liner, a second conductive liner, and a conductive layer, wherein each of the plurality of word lines is located between adjacent semiconductor patterns and interlayer insulating layers in the order of the first conductive liner, the second conductive liner, the conductive layer, the second conductive liner, and the first conductive liner, and wherein the first conductive liner and the second conductive liner comprise different materials or comprise the same material having different composition ratios.

[0008] According to some embodiments, the electrical characteristics of semiconductor devices can be improved, and defects caused by bending can be reduced. Attached Figure Description

[0009] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0010] Figure 2The following is illustrated according to some embodiments. Figure 1 A cross-sectional view of a semiconductor device taken by the A-A' line.

[0011] Figure 3 The following is illustrated according to some embodiments. Figure 1 A cross-sectional view of a semiconductor device taken by the A-A' line.

[0012] Figure 4 The following is illustrated according to some embodiments. Figure 1 A cross-sectional view of a semiconductor device taken by the A-A' line. Detailed Implementation

[0013] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0014] For clarity of description, irrelevant parts have been omitted, and the same reference numerals refer to the same or similar parts throughout the specification.

[0015] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of certain layers and regions are exaggerated for better understanding and ease of description.

[0016] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in the specification, "on" or "above" means located on or below the object portion, and does not necessarily mean located on the upper side of the object portion based on the direction of gravity.

[0017] Furthermore, unless explicitly stated otherwise, the word “comprise” and its variations such as “comprises” or “comprising” will be understood to mean including the stated element but excluding any other element.

[0018] Furthermore, throughout the specification, the phrase "in a plan view" refers to the view of a portion of the object from above, and the phrase "in a cross-sectional view" refers to the view of a section taken by cutting the portion of the object vertically from the side.

[0019] The following text will refer to Figure 1 and Figure 2 Describes a semiconductor device according to some embodiments.

[0020] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments is shown. Figure 2 The following is illustrated according to some embodiments. Figure 1 A cross-sectional view of a semiconductor device taken by the A-A' line.

[0021] refer to Figure 1 and Figure 2 According to some embodiments, a semiconductor device may include a substrate 110, a plurality of semiconductor patterns 140 stacked on the substrate 110, a bit line BL contacting a first end of each of the plurality of semiconductor patterns 140 along a first direction DR1 and extending along a third direction DR3 perpendicular to the upper surface of the substrate 110, a plurality of word lines WL overlapping each of the plurality of semiconductor patterns 140 along the third direction DR3 and extending along a second direction DR2 intersecting the first direction DR1, and a plurality of capacitors 170 contacting a second end of each of the plurality of semiconductor patterns 140 along the first direction DR1. The first direction DR1 and the second direction DR2 may be directions parallel to the upper surface of the substrate 110. The second direction DR2 may, for example, be a direction orthogonal to the first direction DR1.

[0022] Substrate 110 may include semiconductor materials. For example, substrate 110 may include group IV semiconductors, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, substrate 110 may include semiconductors such as Si or Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, or InP. For example, substrate 110 may be a single-crystal epitaxial layer grown on a single-crystal silicon substrate. However, the materials included in substrate 110 are not limited to these and can be varied.

[0023] Multiple semiconductor patterns 140 and multiple interlayer insulating layers 130 can be alternately stacked on the substrate 110. The interlayer insulating layers 130, semiconductor patterns 140, and semiconductor patterns 140 can be repeatedly stacked on the substrate 110 in this order. The multiple semiconductor patterns 140 and multiple interlayer insulating layers 130 can be arranged along a third direction DR3. Figure 1 The diagram shows four semiconductor patterns 140 and five interlayer insulating layers 130 stacked, but this disclosure is not limited thereto, and more semiconductor patterns 140 and more interlayer insulating layers 130 may be stacked on the third-party DR3.

[0024] Semiconductor pattern 140 may include a semiconductor material. For example, semiconductor pattern 140 may include silicon, germanium, or silicon-germanium. For example, semiconductor pattern 140 may include monocrystalline silicon or polycrystalline silicon.

[0025] Semiconductor pattern 140 may extend along a first direction DR1. Semiconductor pattern 140 may include a first end and a second end along the first direction DR1. The first end of semiconductor pattern 140 along the first direction DR1 may contact a bit line BL. The second end of semiconductor pattern 140 along the first direction DR1 may contact a capacitor 170. Both the first end and the second end of semiconductor pattern 140 along the first direction DR1 that contact the bit line BL and the capacitor 170 may include impurity regions. Semiconductor pattern 140 may include channel regions between the impurity regions.

[0026] Semiconductor patterns 140 may be spaced apart on a second direction DR2. Semiconductor patterns 140 may also be spaced apart and arranged on a first direction DR1. Bit lines BL or capacitors 170 may be located between the semiconductor patterns 140 spaced apart and arranged on the first direction DR1.

[0027] Interlayer insulating layer 130 may be located between semiconductor patterns 140. Interlayer insulating layer 130 may be located between semiconductor patterns 140 spaced apart on third-direction DR3.

[0028] The interlayer insulating layer 130 may include an insulating material. For example, the interlayer insulating layer 130 may include silicon oxide, silicon nitride, or silicon oxynitride, but this disclosure is not limited thereto.

[0029] The bit line BL extending on the third-direction DR3 can be located on the substrate 110. The semiconductor pattern 140 stacked on the third-direction DR3 can be connected to the same bit line BL. Although in Figure 1 A single bit line BL is shown, but this disclosure is not limited thereto, and a semiconductor device according to some embodiments may include multiple bit lines BL. The bit lines BL may be arranged at intervals along a first direction DR1 and a second direction DR2.

[0030] In some embodiments, the bit line BL may be cylindrical, but this disclosure is not limited thereto. For example, the bit line BL may be cylindrical. The bit line BL may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or a combination thereof. In some embodiments, the bit line BL may include doped polysilicon. However, this disclosure is not limited thereto, and the shape, material, etc., of the bit line BL may be varied in various ways.

[0031] The first insulating pattern 120 may be located between the substrate 110 and the bit line BL. The bit line BL can be separated from and insulated from the substrate 110 by the first insulating pattern 120. The first insulating pattern 120 may be embedded in the upper surface of the substrate 110. The upper surface of the first insulating pattern 120 may be at substantially the same height as the upper surface of the substrate 110, but this disclosure is not limited thereto. In some cases, the upper surface of the first insulating pattern 120 may be at a higher height than the upper surface of the substrate 110.

[0032] The first insulating pattern 120 may include an insulating material. For example, the first insulating pattern 120 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but this disclosure is not limited thereto, and the material of the first insulating pattern 120 may vary. The first insulating pattern 120 may be formed as a single layer or multiple layers.

[0033] In some embodiments, the word line WL may be located on opposite sides of the semiconductor pattern 140. The word line WL may be located on opposite sides of the semiconductor pattern 140 along a third direction DR3. The word line WL may overlap with the semiconductor pattern 140 on the third direction DR3. In some embodiments, the word line WL may surround the semiconductor pattern 140. The word line WL may have a full-around gate (GAA) structure surrounding the channel region of the semiconductor pattern 140. The word line WL may surround the outer surface of the semiconductor pattern 140 with the first direction DR1 as its central axis. In this case, the word line WL may not completely surround the outer surface of the semiconductor pattern 140 with the first direction DR1 as its central axis. For example, the word line WL may not surround opposite ends and adjacent portions of the outer surface of the semiconductor pattern 140 with the first direction DR1 as its central axis. The word line WL may surround the middle portion between the two ends of the outer peripheral surface of the semiconductor pattern 140 with the first direction DR1 as its central axis. In some embodiments, the semiconductor pattern 140 is in the shape of a quadrangular prism extending in a first direction DR1, and the word line WL may surround the four sides of the semiconductor pattern 140. In some embodiments, the word line WL may surround the surface of the semiconductor pattern 140 facing in a third direction DR3 and the surface facing in a second direction DR2.

[0034] In some embodiments, word lines WL may extend along the second direction DR2. Word lines WL may cover surfaces of semiconductor patterns 140 arranged along the second direction DR2 that face each other along the third direction DR3. In some embodiments, word lines WL may be located between semiconductor patterns 140 arranged along the second direction DR2. Word lines WL may be electrically connected to each semiconductor pattern 140 arranged along the second direction DR2.

[0035] The semiconductor device according to some embodiments may include a plurality of word lines WL corresponding to various semiconductor patterns 140 arranged on a third-direction DR3. The word lines WL may be arranged on the third-direction DR3. Among the word lines WL, the lowermost word line WL adjacent to the upper surface of the substrate 110 and the uppermost word line WL farthest from the upper surface of the substrate 110 may not be electrically connected to the semiconductor patterns 140. An interlayer insulating layer 130 may be located between the word lines WL arranged on the third-direction DR3.

[0036] In some embodiments, each word line WL may include a first conductive substrate 151, a second conductive substrate 153, and a conductive layer 155. The first conductive substrate 151, the second conductive substrate 153, and the conductive layer 155 may be stacked sequentially on a semiconductor pattern 140. The first conductive substrate 151 may be located on the semiconductor pattern 140, the second conductive substrate 153 may be located on the first conductive substrate 151, and the conductive layer 155 may be located on the second conductive substrate 153. The first conductive substrate 151 may be located outside the semiconductor pattern 140 to surround the semiconductor pattern 140. The second conductive substrate 153 may be located outside the first conductive substrate 151 to surround the first conductive substrate 151. The conductive layer 155 may be located outside the second conductive substrate 153 to surround the second conductive substrate 153. The first conductive substrate 151 located inside the conductive layer 155 and the first conductive substrate 155 located outside the conductive layer 155 may be connected between the conductive layer 155 and the capacitor 170. The second conductive liner 153 located inside the conductive layer 155 and the second conductive liner 153 located outside the conductive layer 155 can be connected between the conductive layer 155 and the capacitor 170.

[0037] In some embodiments, Figure 1 In a cross-section along the first direction DR1 and the third direction DR3, the first conductive liner 151, the second conductive liner 153, and the conductive layer 155 can be sequentially located between adjacent semiconductor patterns 140 and interlayer insulating layers 130 on the third direction DR3. In a cross-section along the first direction DR1 and the third direction DR3, the first conductive liner 151 can surround the second conductive liner 153, and the second conductive liner 153 can surround the conductive layer 155. In a cross-section along the first direction DR1 and the third direction DR3, the conductive layer 155 can be surrounded by the first conductive liner 151 and the second conductive liner 153. In a cross-section along the first direction DR1 and the third direction DR3, the conductive layer 155 can fill the space surrounded by the first conductive liner 151 and the second conductive liner 153.

[0038] In some embodiments, the semiconductor pattern 140 may be located approximately at the center between adjacent interlayer insulating layers 130 on the third-direction DR3. A gate insulating pattern Gox may surround the semiconductor pattern 140. The gate insulating pattern Gox may also cover the adjacent semiconductor pattern 140 and interlayer insulating layer 130 on the third-direction DR3. The gate insulating patterns Gox surrounding the semiconductor pattern 140 arranged on the second-direction DR2 may be interconnected on the second-direction DR2. A first conductive liner 151 may surround the semiconductor pattern 140 and the gate insulating pattern Gox surrounding the semiconductor pattern 140. The first conductive liner 151 may also cover the gate insulating pattern Gox covering the interlayer insulating layer 130. The first conductive liner 151 surrounding the semiconductor pattern 140 arranged on the second-direction DR2 may be interconnected on the second-direction DR2. A second conductive liner 153 may surround the semiconductor pattern 140, the gate insulating pattern Gox surrounding the semiconductor pattern 140, and the first conductive liner 151. The second conductive liner 153 may further cover the gate insulating pattern Gox covering the interlayer insulating layer 130 and the first conductive liner 151. The second conductive liner 153 surrounding the semiconductor pattern 140 arranged in the second direction DR2 may be interconnected with each other in the second direction DR2. The conductive layer 155 may surround the semiconductor pattern 140, the gate insulating pattern Gox surrounding the semiconductor pattern 140, the first conductive liner 151, and the second conductive liner 153. The conductive layer 155 may further cover the first conductive liner 151, the second conductive liner 153, and the gate insulating pattern Gox covering the interlayer insulating layer 130. The conductive layers 155 surrounding the semiconductor pattern 140 arranged in the second direction DR2 may be interconnected with each other in the second direction DR2. In some embodiments, the conductive layer 155 may be located between the semiconductor patterns 140 arranged in the second direction DR2.

[0039] In some embodiments, the conductive layer 155 may be thicker than the first conductive substrate 151 and the second conductive substrate 153. Here, the thickness of the conductive layer 155 may represent the width (or length) of its overlap with the semiconductor pattern 140 along the third direction DR3, and the thicknesses of the first conductive substrate 151 and the second conductive substrate 153 may represent the width (or length) along the third direction DR3 between the semiconductor pattern 140 and the conductive layer 155. In some embodiments, the thicknesses of the first conductive substrate 151 and the second conductive substrate 153 may both be greater than or equal to about 3 Å and less than or equal to about 100 Å.

[0040] Each of the first conductive liner 151, the second conductive liner 153, and the conductive layer 155 may include a conductive material. In some embodiments, the first conductive liner 151 and the second conductive liner 153 may include different materials, or may include the same material with different composition ratios. The first conductive liner 151 and the second conductive liner 153 may include different materials, or may include the same material with different composition ratios, thereby playing different roles within the word line WL.

[0041] In some embodiments, the first conductive liner 151 and the second conductive liner 153 may comprise different materials. For example, the first conductive liner 151 may comprise at least one of TiSiN, MoSiN, TaSiN, LaSiN, TiAlN, TiAlC, TiWN, TaN, and LaN, and the second conductive liner 153 may comprise at least one of MoN, TiN, W, Mo, Ta, Al, Cu, and Ru.

[0042] In some embodiments, the first conductive liner 151 and the second conductive liner 153 may comprise the same material with different composition ratios. For example, the first conductive liner 151 and the second conductive liner 153 may comprise at least one of TiSiN, MoSiN, TaSiN, LaSiN, TiAlN, TiAlC, and TiWN. The mass ratio of Si, Al, and W included in the first conductive liner 151 may be greater than 12%, and the mass ratio of Si, Al, and W included in the second conductive liner 153 may be less than 12%.

[0043] The first conductive substrate 151 can control the work function of the word line WL. That is, the first conductive substrate 151 can control the threshold voltage V of the word line WL. th Peaceful voltage V fb Furthermore, the first conductive liner 151 can reduce the amount (or density) of charge trapped at the interface between the semiconductor pattern 140 and the gate insulating pattern Gox.

[0044] The second conductive substrate 153 can increase the grain size of the conductive layer 155 located on the second conductive substrate 153. As the grain size of the conductive layer 155 increases, the resistance of the conductive layer 155 can decrease. In addition, the phenomenon of fine particles (agglomeration) in the conductive layer 155 can be prevented. Therefore, the phenomenon of bending of the conductive layer 155 and the formation of voids inside the conductive layer 155 can be prevented. Furthermore, the second conductive substrate 153 can prevent impurities generated during the deposition of the conductive layer 155 from penetrating into the semiconductor pattern 140 and causing defects.

[0045] In some embodiments, each of the first conductive liner 151 and the second conductive liner 153 may comprise a material different from that of the conductive layer 155. For example, the conductive layer 155 may comprise at least one of TiN, W, Mo, Ta, Al, Cu, and Ru, but this disclosure is not limited thereto. For example, when the conductive layer 155 comprises TiN, each of the first conductive liner 151 and the second conductive liner 153 may comprise at least one of the materials other than TiN in the above material examples. Since the conductive layers 155 and 153, which are in contact with each other, comprise different materials, an oxide film may not be formed between the conductive layer 155 and the second conductive liner 153.

[0046] Word line capping patterns (WLCs) may be located on the side surfaces of word lines (WL). The word line capping patterns (WLCs) may cover the side surfaces of word lines (WL) facing bit lines (BL) on semiconductor patterns 140. A semiconductor device according to some embodiments may include multiple word line capping patterns (WLCs) covering the side surfaces of each word line (WL). The word line capping patterns (WLCs) may be spaced apart on a third-direction DR3 by semiconductor patterns 140 located therebetween. The word line capping patterns (WLCs) may be spaced apart on a third-direction DR3 by interlayer insulating layers 130 located therebetween.

[0047] The word line cover pattern WLC may include an insulating material. The word line cover pattern WLC may include silicon nitride, but this disclosure is not limited thereto. The word line cover pattern WLC may be used to protect the word line WL. The word line WL may be surrounded by the word line cover pattern WLC and the gate insulating pattern Gox, described later.

[0048] The gate insulating pattern Gox can be located between the word line WL and the semiconductor pattern 140. The word line WL can be separated from the semiconductor pattern 140 by the gate insulating pattern Gox. The gate insulating pattern Gox can surround the word line WL. Figure 1 In the diagram, the gate insulating pattern Gox is shown to be located between the word line capping pattern WLC and the semiconductor pattern 140, and between the word line capping pattern WLC and the interlayer insulating layer 130, but this disclosure is not limited thereto. The structure and shape of the word line capping pattern WLC and the gate insulating pattern Gox can vary.

[0049] The gate insulating pattern Gox may include at least one of a high-k material, silicon oxide, silicon nitride, or silicon oxynitride. The high-dielectric-constant material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0050] Word lines (WL), word line capping patterns (WLC), and gate insulating patterns (Gox) can form word line structures (WLS). A semiconductor device according to some embodiments may include multiple word line structures (WLS). The word line structures (WLS) may be spaced apart on a third-direction DR3. Each word line structure (WLS) arranged along the third-direction DR3 may surround each semiconductor pattern 140 arranged along the third-direction DR3. An interlayer insulating layer 130 may be located between the word line structures (WLS) arranged on the third-direction DR3.

[0051] The second insulating pattern 160 may be located between the semiconductor patterns 140 disposed on the third-direction DR3. The second insulating pattern 160 may cover the side surfaces of the interlayer insulating layer 130 between the semiconductor patterns 140. The second insulating pattern 160 may cover the side surfaces of the gate insulating pattern Gox and the word line capping pattern WLC between the semiconductor patterns 140. The second insulating pattern 160 may also cover the upper and lower surfaces of the word line capping pattern WLC between the semiconductor patterns 140, but this disclosure is not limited thereto. For example, when the upper and lower surfaces of the word line capping pattern WLC are covered by the gate insulating pattern Gox, the second insulating pattern 160 may cover the side surfaces of the word line capping pattern WLC.

[0052] The second insulating pattern 160 may include an insulating material. For example, the second insulating pattern 160 may include at least one of silicon oxide or silicon nitride. Figure 1 In this embodiment, the second insulating pattern 160 is shown as a single layer, but this disclosure is not limited thereto. According to some embodiments, the second insulating pattern 160 can be formed as a multilayer. For example, the second insulating pattern 160 can be in the form of alternating stacks of silicon oxide films, silicon nitride films, and silicon oxide films on the side surfaces of the word line structure WLS and the side surfaces of the interlayer insulating layer 130.

[0053] As described above, a first end of the semiconductor pattern 140 along the first direction DR1 can contact the bit line BL, and a second end of the semiconductor pattern 140 along the first direction DR1 can contact the capacitor 170. The capacitor 170 may include a first electrode 171, a dielectric layer 173, a second electrode 175, and a plate electrode 177. The second end of the semiconductor pattern 140 along the first direction DR1 can contact the first electrode 171 of the capacitor 170. The first electrode 171 may be arranged parallel to the semiconductor pattern 140 along the first direction DR1.

[0054] A semiconductor device according to some embodiments may include a plurality of capacitors 170. Each capacitor 170 may include a first electrode 171. A semiconductor device according to some embodiments may include a plurality of first electrodes 171. The first electrodes 171 may be stacked on a third direction DR3. A first end of each first electrode 171 along a first direction DR1 may contact a corresponding semiconductor pattern in each semiconductor pattern 140 stacked on the third direction DR3.

[0055] The dielectric layer 173 may surround the first electrode 171. The dielectric layer 173 may conformally cover the surface of the first electrode 171 except for the surface in contact with the semiconductor pattern 140. The dielectric layer 173 may cover a plurality of first electrodes 171 stacked on the third-direction DR3. The dielectric layer 173 may cover the side surface of the interlayer insulating layer 130 disposed between adjacent first electrodes 171 on the third-direction DR3. The dielectric layer 173 may cover the upper surface of the substrate 110.

[0056] The second electrode 175 may cover the dielectric layer 173. The second electrode 175 may be separated from the first electrode 171 by the dielectric layer 173. The second electrode 175 may conformally cover the surface of the dielectric layer 173. The second electrode 175 may have a shape similar to that of the dielectric layer 173.

[0057] The plate electrode 177 may cover the second electrode 175. The plate electrode 177 may include a vertical portion extending in the third direction DR3 and a horizontal portion extending from the vertical portion to the opposite side in the first direction DR1. The lower portion of the vertical portion of the plate electrode 177 may be surrounded by the substrate 110. The vertical portion of the plate electrode 177 may extend in the third direction DR3, spanning the first electrodes 171 stacked in the third direction DR3. The horizontal portion of the plate electrode 177 may be located between the first electrodes 171 stacked in the third direction DR3, and between the lowermost first electrode 171 and the substrate 110.

[0058] In some embodiments, the dielectric layer 173 of each capacitor 170 may be integrally formed. For example, a first electrode 171 stacked on the third-direction DR3 may be covered by a single dielectric layer 173. In some embodiments, the second electrode 175 of each capacitor 170 may be integrally formed. For example, a first electrode 171 stacked on the third-direction DR3 may be covered by a single second electrode 175. In some embodiments, the plate electrode 177 of each capacitor 170 may be integrally formed. For example, a first electrode 171 stacked on the third-direction DR3 may be covered by a single plate electrode 177.

[0059] According to some embodiments, the semiconductor device may also include a component on the first direction DR1 and... Figure 1The first electrodes 171 shown are spaced apart and stacked on a third direction DR3. The first electrodes 171 spaced apart on a first direction DR1 can be covered by a single dielectric layer 173, a single second electrode 175, and a single plate electrode 177. The capacitor 170, including the same dielectric layer 173, the same second electrode 175, and the same plate electrode 177, can have a mirror-symmetric structure with respect to the plate electrode 177.

[0060] A semiconductor device according to some embodiments may include a plurality of first electrodes 171 spaced apart and arranged on the same layer in a second direction DR2. The first electrodes 171 spaced apart and positioned in the second direction DR2 may be covered by a single dielectric layer 173, a single second electrode 175, and a single plate electrode 177. The dielectric layer 173 and the second electrode 175 may cover the surface of the first electrode 171 facing the second direction DR2. The plate electrode 177 may extend in the second direction DR2. In some embodiments, the dielectric layer 173 and the second electrode 175 may be located between the spaced-apart first electrodes 171 in the second direction DR2, and the plate electrode 177 may not be located between the spaced-apart first electrodes 171 in the second direction DR2. The first electrodes 171 may be arranged and spaced apart in the second direction DR2, and the plate electrode 177 may extend from one side of the first electrode 171 along the first direction DR1 in the second direction DR2.

[0061] Each of the first electrode 171, the second electrode 175, and the plate electrode 177 may include a conductive material. Each of the first electrode 171, the second electrode 175, and the plate electrode 177 may include at least one of a metallic material, a conductive metal nitride, or a doped semiconductor material. In some embodiments, the first electrode 171 and the second electrode 175 may include the same material, and the plate electrode 177 may include a material different from the materials of the first electrode 171 and the second electrode 175. For example, the first electrode 171 and the second electrode 175 may include titanium nitride, and the plate electrode 177 may include doped silicon germanium.

[0062] The dielectric layer 173 may include at least one of a dielectric, a ferromagnetic material, or a semi-ferromagnetic material. The dielectric may include a high-k material. For example, the dielectric may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0063] A semiconductor device according to some embodiments may include a plurality of memory cells MC stacked on a third-direction DR3 perpendicular to the upper surface of a substrate 110. In some embodiments, each memory cell MC may include at least one transistor and at least one capacitor. In some embodiments, each memory cell MC may include a semiconductor pattern 140, a word line WL surrounding the semiconductor pattern 140 and electrically connected to the semiconductor pattern 140, a bit line BL connected to a first end of the semiconductor pattern 140, and a capacitor 170 connected to a second end of the semiconductor pattern 140.

[0064] According to some embodiments, a semiconductor device may include a first conductive liner 151 and a second conductive liner 153 between the gate insulating pattern Gox and the conductive layer 155. The first conductive liner 151 and the second conductive liner 153 may comprise different materials, or may comprise the same material but with different composition ratios. According to some embodiments, the threshold voltage of the word line WL can be controlled by the first conductive liner 151, which can reduce the amount (or density) of charge trapped at the interface between the semiconductor pattern 140 and the gate insulating pattern Gox, and the grain size of the conductive layer 155 can be increased by the second conductive liner 153. Therefore, the electrical characteristics of the semiconductor device can be improved, and defects caused by bending can be mitigated.

[0065] The following text will refer to Figure 3 describe Figure 1 and Figure 2 The example of a modified semiconductor device is shown.

[0066] Figure 3 The following is illustrated according to some embodiments. Figure 1 A cross-sectional view of a semiconductor device taken by the A-A' line. Figure 3 The embodiments shown can be compared with Figure 1 and Figure 2 The embodiments shown are essentially the same. Figure 3 In some embodiments shown, with Figure 1 and Figure 2 The same components shown in the embodiments can be represented by the same symbols. Hereinafter, focus will be placed on those... Figure 1 and Figure 2 The differences between the embodiments shown are described. Figure 3 The comparative embodiments shown are illustrated. Figure 3 The embodiment shown can be compared with the one shown in terms of the shape of the semiconductor pattern 140 and the shapes of the gate insulating pattern Gox and the word line WL. Figure 1 and Figure 2 The embodiments shown differ in some respects.

[0067] refer to Figure 3According to some embodiments, the semiconductor pattern 140 may have rounded corners in cross-sections along the second direction DR2 and the third direction DR3. Figure 2 In some embodiments shown, the cross-sectional shape of the semiconductor pattern 140 along the second direction DR2 and the third direction DR3 is rectangular, while... Figure 3 In some embodiments shown, the cross-sectional shape of the semiconductor pattern 140 along the second direction DR2 and the third direction DR3 may be a quadrilateral with rounded corners. In some embodiments, the surface of the semiconductor pattern 140 facing the second direction DR2 may be curved. The surface of the semiconductor pattern 140 facing the second direction DR2 may be a convex surface facing outwards from the semiconductor pattern 140. The gate insulating pattern Gox, the first conductive liner 151, the second conductive liner 153, and the conductive layer 155 surrounding the semiconductor pattern 140 may include curved surfaces along the surface contour of the semiconductor pattern 140.

[0068] In some embodiments, the thickness of the word line WL along the third direction DR3 in a cross-section along the second direction DR2 and the third direction DR3 may not be constant. The thickness of the word line WL along the third direction DR3 may thin as it moves away from the side surface of the semiconductor pattern 140 disposed on the second direction DR2. For example, between adjacent first and second semiconductor patterns on the second direction DR2, the thickness of the word line WL along the third direction DR3 on the side surface of the first semiconductor pattern may thin as it moves toward the midpoint between the first and second semiconductor patterns. The thickness of the word line WL along the third direction DR3 may thicken as it moves toward the side surface of the second semiconductor pattern at the midpoint between the first and second semiconductor patterns.

[0069] In some embodiments, in a cross section along the second direction DR2 and the third direction DR3, the thickness of the conductive layer 155 along the third direction DR3 can be thinned from the side surface of the semiconductor pattern 140 arranged on the second direction DR2 to the middle position of the semiconductor pattern 140.

[0070] In some embodiments, in a cross-section along the second direction DR2 and the third direction DR3, in the extension at the midpoint between adjacent semiconductor patterns 140 on the second direction DR2, portions of the gate insulating pattern Gox, the first conductive liner 151, and the second conductive liner 153 covering the interlayer insulating layers 130 disposed on both sides along the third direction DR3 may protrude relative to each other on the third direction DR3. For example, the gate insulating pattern Gox, the first conductive liner 151, and the second conductive liner 153 may cover adjacent first and second interlayer insulating layers on the third direction DR3. In the extension at the midpoint between adjacent semiconductor patterns 140 on the second direction DR2, portions of the gate insulating pattern Gox, the first conductive liner 151, and the second conductive liner 153 covering the first interlayer insulating layer may protrude on the third direction DR3 toward portions of the gate insulating pattern Gox, the first conductive liner 151, and the second conductive liner 153 covering the second interlayer insulating layer. In the extension at the midpoint between adjacent semiconductor patterns 140 on the second direction DR2, a portion of the gate insulating pattern Gox covering the second interlayer insulating layer, a portion of the first conductive liner 151, and a portion of the second conductive liner 153 may protrude on the third direction DR3 toward the portion of the gate insulating pattern Gox covering the first interlayer insulating layer, the portion of the first conductive liner 151, and the portion of the second conductive liner 153.

[0071] The following text will refer to Figure 4 describe Figure 1 and Figure 2 The example of a modified semiconductor device is shown.

[0072] Figure 4 The following is illustrated according to some embodiments. Figure 1 A cross-sectional view of a semiconductor device taken by the A-A' line. Figure 4 The embodiments shown can be compared with Figure 1 and Figure 2 The embodiments shown are essentially the same. Figure 4 In the embodiment shown, with Figure 1 and Figure 2 The same components shown in the embodiments can be represented by the same symbols. Hereinafter, focus will be placed on those... Figure 1 and Figure 2 The differences between the embodiments shown are described. Figure 4 The comparative embodiments shown are illustrated. Figure 4 The embodiments shown can be compared with those in terms of the shape and structure of the gate insulating pattern Gox and the word line WL. Figure 1 and Figure 2 The embodiments shown differ in some respects.

[0073] refer to Figure 4 According to some embodiments, word lines WL may include a first word line WL1 and a second word line WL2 located on opposite sides of a semiconductor pattern 140 along a third direction DR3. The first word line WL1 and the second word line WL2 may each be located on a surface of the semiconductor pattern 140 facing each other on the third direction DR3. The first word line WL1 and the second word line WL2 may be located on opposite sides of a semiconductor pattern 140 arranged on a second direction DR2. The first word line WL1 and the second word line WL2 may be located on opposite sides of a semiconductor pattern 140 arranged on a second direction DR2 along the third direction DR3. The first word line WL1 and the second word line WL2 may not be located between semiconductor patterns 140 arranged on a second direction DR2. The first word line WL1 and the second word line WL2 may be positioned such that semiconductor patterns 140 arranged on a second direction DR2 are located therebetween. An interlayer insulating layer 130 may be located between semiconductor patterns 140 arranged on a second direction DR2. The first word line WL1 and the second word line WL2 may overlap with the semiconductor pattern 140 on the third direction DR3, but may not overlap on the second direction DR2.

[0074] In some embodiments, the first word line WL1 and the second word line WL2 may respectively include first conductive substrates 151_1 and 151_2, second conductive substrates 153_1 and 153_2, and conductive layers 155_1 and 155_2. A first gate insulating pattern Gox1 may be located between the first word line WL1 and the semiconductor pattern 140, and between the first word line WL1 and the interlayer insulating layer 130. A second gate insulating pattern Gox2 may be located between the second word line WL2 and the semiconductor pattern 140, and between the second word line WL2 and the interlayer insulating layer 130. The first word line WL1 may be separated from the semiconductor pattern 140 by the first gate insulating pattern Gox1. The second word line WL2 may be separated from the semiconductor pattern 140 by the second gate insulating pattern Gox2.

[0075] In some embodiments, the first gate insulating pattern Gox1 may extend on the second direction DR2 and cover the facing surfaces of the semiconductor pattern 140 and the interlayer insulating layer 130 spaced apart from each other on the third direction DR3. The first conductive liner 151_1 of the first word line WL1 may cover the first gate insulating pattern Gox1 and may extend on the second direction DR2. The second conductive liner 153_1 of the first word line WL1 may cover the first conductive liner 151_1 and may extend on the second direction DR2. The conductive layer 155_1 of the first word line WL1 may cover the second conductive liner 153_1 and may extend on the second direction DR2.

[0076] In some embodiments, the second gate insulating pattern Gox2 may extend in the second direction DR2 and cover the facing surfaces of the semiconductor pattern 140 and the interlayer insulating layer 130 that are spaced apart from each other in the third direction. The second conductive liner 153_2 of the second word line WL2 may cover the first gate insulating pattern Gox2 and may extend in the second direction DR2. The second conductive liner 153_2 of the second word line WL2 may cover the first conductive liner 151_2 of the second word line WL2 and may extend in the second direction DR2. The conductive layer 155_2 of the second word line WL2 may cover the second conductive liner 153_2 of the second word line WL2 and may extend in the second direction DR2.

[0077] In some embodiments, semiconductor pattern 140 may be electrically connected to two word lines WL. Semiconductor pattern 140 may be electrically connected to a first word line WL1 and a second word line WL2. According to some embodiments, the area of ​​the channel region of semiconductor pattern 140 may be increased compared to a comparative example including one of the first word line WL1 and the second word line WL2, thereby improving the electrical characteristics of the semiconductor device. In some embodiments, the same voltage may be applied to the first word line WL1 and the second word line WL2, but this disclosure is not limited thereto. According to some embodiments, different voltages may be applied to the first word line WL1 and the second word line WL2. In this case, the first of the first word line WL1 and the second word line WL2 may be used as a front gate and the second may be used as a back gate to improve the electrical characteristics of the semiconductor device.

[0078] Although this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of any invention or what can be claimed, but rather as features that may be specific to particular embodiments of a particular invention. Some features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in certain circumstances, and the combination may be for sub-combinations or variations thereof.

[0079] Although this disclosure has been described in conjunction with currently believed practical embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: substrate; Multiple semiconductor patterns are located on the substrate; Bit lines, the bit lines contacting a first end of each of the plurality of semiconductor patterns in a first direction and extending upward in a third direction perpendicular to the upper surface of the substrate; Multiple word lines, which overlap with the multiple semiconductor patterns in the third direction and extend in a second direction intersecting the first direction; as well as A plurality of capacitors are in contact with the second ends of corresponding semiconductor patterns in the plurality of semiconductor patterns along the first direction. Each of the plurality of word lines includes a first conductive substrate, a second conductive substrate, and a conductive layer sequentially located on corresponding semiconductor patterns among the plurality of semiconductor patterns. The first conductive liner and the second conductive liner may comprise materials that are different from each other, or may comprise the same material having different compositional ratios.

2. The semiconductor device according to claim 1, wherein... The first conductive liner and the second conductive liner comprise different materials. The first conductive substrate comprises at least one of TiSiN, MoSiN, TaSiN, LaSiN, TiAlN, TiAlC, TiWN, TaN, or LaN, and The second conductive liner includes at least one of MoN, TiN, W, Mo, Ta, Al, Cu, or Ru.

3. The semiconductor device according to claim 1, wherein... The first conductive liner and the second conductive liner comprise the same material. The first conductive liner and the second conductive liner comprise at least one of TiSiN, MoSiN, TaSiN, LaSiN, TiAlN, TiAlC, or TiWN. The mass ratio of Si, Al, and W in the first conductive substrate exceeds 12%, and The mass ratio of Si, Al, and W in the second conductive liner is less than 12%.

4. The semiconductor device according to claim 1, wherein Each of the first conductive liner and the second conductive liner comprises a material different from the material of the conductive layer.

5. The semiconductor device according to claim 1, wherein... The second conductive liner surrounds the conductive layer, and the first conductive liner surrounds the second conductive liner.

6. The semiconductor device according to claim 1, wherein The conductive layer is thicker than each of the first conductive liner and the second conductive liner.

7. The semiconductor device according to claim 6, wherein Each of the first conductive liner and the second conductive liner has a thickness of 3 Å or more and 100 Å or less.

8. The semiconductor device according to claim 1, wherein Each of the plurality of word lines surrounds a first surface facing the corresponding semiconductor pattern in the second direction, and surrounds a second surface facing the corresponding semiconductor pattern in the third direction.

9. The semiconductor device according to claim 8, wherein... The plurality of semiconductor patterns include semiconductor patterns arranged in the second direction, and Each of the plurality of word lines is located between adjacent semiconductor patterns arranged in the second direction.

10. The semiconductor device according to claim 9, wherein In a cross-section along the second direction and the third direction, each of the plurality of semiconductor patterns has rounded corners, and each of the plurality of word lines thins along the third direction as it moves away from the side surface of the semiconductor pattern arranged in the second direction.

11. The semiconductor device of claim 1, wherein... Each of the plurality of word lines includes a first word line and a second word line, the first word line and the second word line being located on corresponding semiconductor patterns of the plurality of semiconductor patterns on the third-party facing surfaces, and Each of the first word line and the second word line includes the first conductive liner, the second conductive liner, and the conductive layer.

12. The semiconductor device of claim 11, wherein... The first word line and the second word line are located on opposite sides of the plurality of semiconductor patterns arranged in the second direction.

13. A semiconductor device, said semiconductor device comprising: substrate; Multiple semiconductor patterns are located on the substrate; Bit lines, the bit lines contacting a first end of each of the plurality of semiconductor patterns in a first direction and extending upward in a third direction perpendicular to the upper surface of the substrate; Multiple word lines, which overlap with the multiple semiconductor patterns in the third direction and extend in a second direction intersecting the first direction; as well as A plurality of capacitors are in contact with a second end of each of the plurality of semiconductor patterns along the first direction. Each of the plurality of word lines includes: a first conductive liner located on a corresponding semiconductor pattern among the plurality of semiconductor patterns; a second conductive liner located on the first conductive liner; and a conductive layer located on the second conductive liner. The conductive layer is thicker than each of the first conductive liner and the second conductive liner.

14. The semiconductor device of claim 13, wherein The second conductive liner comprises a material different from that of the first conductive liner.

15. The semiconductor device of claim 13, wherein... The first conductive liner and the second conductive liner comprise the same material with different composition ratios.

16. The semiconductor device of claim 13, wherein The conductive layer comprises a material different from the materials of the first conductive liner and the second conductive liner.

17. The semiconductor device of claim 13, wherein... Each of the plurality of word lines surrounds the outer peripheral surface of the corresponding semiconductor pattern among the plurality of semiconductor patterns centered on the first direction.

18. The semiconductor device of claim 13, wherein... Each of the plurality of word lines includes a first word line and a second word line located on opposite sides of the corresponding semiconductor pattern in the third direction among the plurality of semiconductor patterns.

19. A semiconductor device, the semiconductor device comprising: substrate; Multiple semiconductor patterns and multiple interlayer insulating layers are alternately located on the substrate; Bit lines, the bit lines contacting a first end of each of the plurality of semiconductor patterns in a first direction and extending upward in a third direction perpendicular to the upper surface of the substrate; Multiple word lines, which overlap with the multiple semiconductor patterns in the third direction and extend in a second direction intersecting the first direction; as well as Multiple capacitors, wherein the multiple capacitors are in contact with the second ends of corresponding semiconductor patterns in the multiple semiconductor patterns along the first direction. Each of the multiple word lines includes a first conductive liner, a second conductive liner, and a conductive layer. Wherein, each of the plurality of word lines is located between adjacent semiconductor patterns and interlayer insulating layers in the order of the first conductive liner, the second conductive liner, the conductive layer, the second conductive liner, and the first conductive liner, and... The first conductive liner and the second conductive liner may comprise different materials or the same material having different compositional ratios.

20. The semiconductor device of claim 19, wherein The first conductive liner and the second conductive liner comprise materials different from those of the conductive layer.

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