Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. According to an embodiment, the semiconductor device can include a substrate, a buried oxide layer, a channel portion including a semiconductor layer, a source / drain portion, and a gate stack. The semiconductor layer includes a shell portion and a core portion spaced apart from each other and distributed in a projection direction overlapping each other, the shell portion being on the core portion, the shell portion and the core portion being respectively one of p-type doped and n-type doped.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same having a channel portion including a shell portion and a core portion. Background Technology

[0002] Fully depleted (FD) SOI semiconductor devices, especially oxide semiconductor field-effect transistors (MOS field-effect transistors), can effectively control short-channel effects and enable further miniaturization of devices. However, the fabrication process for FDSOI MOS field-effect transistors is complex and costly, and their performance needs further improvement. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is at least in part to provide a semiconductor device having a channel portion including a metal sulfide layer and a method for manufacturing the same.

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising:

[0005] Substrate;

[0006] Buried oxide layer on substrate;

[0007] The channel portion includes a semiconductor layer stacked above the buried oxide layer;

[0008] Source / leakage sections are arranged above the buried oxygen layer and connected to opposite ends of the channel section; and

[0009] The grid stack between the source and drain sections is arranged on the channel section;

[0010] The semiconductor layer includes at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction.

[0011] The at least one shell and the at least one core are portions of a semiconductor layer, each having opposite doping types.

[0012] In one embodiment, the thickness of one shell portion of at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of at least one core portion is 10 nm to 50 nm.

[0013] In one embodiment, at least one core comprises one core or two cores, and / or wherein the at least one shell comprises two shells.

[0014] In one embodiment, the shell and the core are obtained by performing an ion implantation process on the semiconductor layer.

[0015] In one embodiment, the shell and the core are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.

[0016] In one embodiment, the gate stack includes a work function layer and a gate metal conductive layer.

[0017] In one embodiment, the gate stack includes a first gate dielectric layer.

[0018] In one embodiment, the semiconductor devices are configured as a plurality of semiconductor devices, including n-type semiconductor devices and p-type semiconductor devices, and their respective gate stacks include the same gate dielectric layer, wherein the work function layers on the gate dielectric layer are n-type and p-type, respectively.

[0019] Wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion and an n-type doped core portion, and / or the channel portion of the p-type semiconductor device includes an n-type doped shell portion and a p-type doped core portion.

[0020] In one embodiment, the threshold voltage of the n-type semiconductor device and the threshold voltage of the p-type semiconductor device are set to be substantially symmetrical.

[0021] In one embodiment, there are no gate sidewalls between the gate stack and the source / drain.

[0022] In one embodiment, the semiconductor device is an n-type semiconductor device.

[0023] When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and

[0024] When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core first forms a charge accumulation mode and begins to conduct electricity. Then, a larger absolute value of the gate voltage causes the shell to form an inversion mode and join in conducting electricity.

[0025] In one embodiment, the semiconductor device is a p-type semiconductor device.

[0026] When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and

[0027] When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core first forms a hole accumulation mode and begins to conduct electricity. Then, a larger absolute value of the gate voltage causes the shell to form an inversion mode and join in conducting electricity.

[0028] In one embodiment, at least one shell portion is on top of at least one core portion, or said at least one core portion is on top of at least one shell portion; and / or

[0029] The at least one shell portion and at least one core portion are arranged alternately.

[0030] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0031] A buried oxide layer is formed on the substrate;

[0032] A semiconductor layer is formed on the buried oxide layer;

[0033] A sacrificial gate is formed on the semiconductor layer, and a sacrificial gate sidewall is formed on the sidewall of the sacrificial gate;

[0034] Sources / drains are formed on opposite sides of the sacrificial gate sidewall, and the source / drains overlap with the sacrificial gate in the channel extension direction;

[0035] Remove the sacrificial gate and optionally remove the sidewalls of the sacrificial gate to free up space between the source and drain;

[0036] Forming at least one core and at least one shell in a semiconductor layer in space; and

[0037] A gate stack is formed on the semiconductor layer in space.

[0038] In one embodiment, at least one core and at least one shell are formed in the semiconductor layer by ion implantation.

[0039] In one embodiment, the thickness of one shell portion of at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of at least one core portion is 10 nm to 50 nm.

[0040] In one embodiment, forming the gate stack includes:

[0041] A first gate dielectric layer, a work function layer, and a gate conductive layer are sequentially formed on the exposed surface of the semiconductor layer (including the channel and optional source / drain sidewalls).

[0042] In one embodiment, the method includes: forming a p-type doped shell and an n-type doped core for an n-type semiconductor device; and / or

[0043] For p-type semiconductor devices, an n-type doped shell and a p-type doped core are formed.

[0044] According to embodiments of this disclosure, the channel portion may include a shell portion and a core portion. By changing the absolute value of the gate voltage, the charge of the shell portion and the core portion changes, allowing them to jointly contribute to conductivity, thereby improving the electrical characteristics of the semiconductor device. Furthermore, the method for manufacturing the semiconductor device according to embodiments of this disclosure is simpler and has lower cost. Attached Figure Description

[0045] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0046] Figures 1 to 7 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0047] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0048] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0049] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0050] FDSOI technology has greatly improved device performance, and the application of field-effect transistors on FDSOI has been greatly developed. In the prior art, junctionless field-effect transistors on FDSOI have shown excellent advantages. Furthermore, the inventors have discovered that devices using FDSOI, which include a shell and a core, have further improved performance, surpassing the performance of devices in the prior art. Moreover, they can be integrated with current 10nm node and below process flows, which is expected to enable the integration and innovation of device structure, materials and processes, and has great development potential.

[0051] The inventors have discovered that a channel layer can be fabricated using epitaxial growth techniques. This channel layer can include a shell and a core. For example, in an n-channel field-effect transistor, the shell in the semiconductor layer of the channel is restricted to undoped or lightly p-type doped material, while the core can be a heavily n-type doped layer. The thickness of the shell is comparable to (e.g., on the same order of magnitude) as the thickness of the core, but the thicknesses of both can be adjusted as needed. The fabrication methods for the shell and core are highly reliable; for example, they can be achieved through direct epitaxy or by ion implantation after the semiconductor layer has been formed. FDSOI planar technology has the potential to achieve or surpass the performance of Fin field-effect transistors at the same node, making it competitive in the market.

[0052] According to embodiments of this disclosure, a semiconductor device is provided. Specifically, the semiconductor device may include a channel portion, a gate stack disposed on the channel portion, and source / drain portions 1011 disposed on opposite sides of the gate stack. The channel portion may extend in a first direction, and its opposite ends in the first direction may be connected to the source / drain portions 1011. There may be no gate sidewall between the gate stack and the source / drain portions 1011.

[0053] The channel portion may include a semiconductor layer, such as Si; in one embodiment, the channel portion may also include a semiconductor layer 1005 with high mobility, such as SiGe; in other embodiments, the semiconductor layer 1005 may be partially Si and partially SiGe. The semiconductor layer 1005 includes at least one shell portion 1005-1 and at least one core portion 1005-2. The shell portion 1005-1 is a partially doped region within the semiconductor layer 1005, and the core portion 1005-2 is a partially doped region within the semiconductor layer 1005.

[0054] At least one shell 1005-1 and at least one core 1005-2 means, for example, combinations such as one shell 1005-1 and one core 1005-2, two shells 1005-1 and one core 1005-2, two shells 1005-1 and two cores 1005-2, one shell 1005-1 and two cores 1005-2, etc. It should be understood that there can also be configurations such as three or four shells and / or three or four cores. The number of shells and cores, the doping concentration of shells and cores, and the arrangement between shells and cores can be set according to the required performance. For example, in one embodiment, one shell and one core are arranged alternately. In one embodiment, one core is arranged on top of one shell (not shown).

[0055] A multi-core-shell structure or morphology in the channel portion can be used to adjust the Vt value, achieving multiple Vt values. This invention advantageously realizes a multiple Vt scheme for FDSOI devices by incorporating one or more shells. This is highly advantageous for FDSOI devices because conventional / existing FDSOI devices with multiple Vt values ​​are achieved through back-side wells and biasing methods, which are extremely complex in terms of fabrication and circuit design. The design of this invention allows planar transistors to have multiple shells to fully utilize charge balance effects, while simultaneously enabling both the shell and core to conduct under conduction conditions. More than one shell or more than one core can further improve the uniformity and consistency of the device.

[0056] exist Figure 7 In the illustrated embodiment, by way of example only, the semiconductor device includes a source / drain portion 1011 and a channel portion between the source / drain portion 1011, wherein the channel portion includes a semiconductor layer 1005, the semiconductor layer 1005 including two shell portions 1005-1 and one core portion 1005-2. Compared to a single shell portion, the configuration of two shell portions 1005-1 and one core portion 1005-2 has better uniformity and greater current under the same conditions. In this embodiment, a gate stack is formed between the source and drain and above the channel portion; the gate stack may include a gate dielectric layer and / or a work function layer. In one embodiment, the gate stack may include a work function layer 1019, such as a metal work function layer, particularly, for example, a titanium nitride layer. In one embodiment, the gate stack includes a first gate dielectric layer 1017, such as a hafnium oxide layer. The hafnium oxide layer may have a thickness of approximately 2 nm. The gate stack may also include a gate conductive layer 1021.

[0057] In one embodiment, a sidewall 1009 is formed on the sidewall of the gate stack, the sidewall being located between the gate stack and the source / drain portion 1011. Figure 7 In this embodiment, no sidewalls are provided. Furthermore, Figure 7In one embodiment, the semiconductor device shown includes an interlayer dielectric layer 1013; however, in other embodiments, the semiconductor device may not include an interlayer dielectric layer 1013.

[0058] In embodiments of the present invention, the semiconductor layer 1005 of the channel portion includes at least one shell portion 1005-1 and at least one core portion 1005-2. As an example, in an embodiment of an n-type semiconductor device, n-type ion implantation is performed toward the channel portion using predetermined energy and dose, followed by p-type implantation toward the channel portion of the n-type semiconductor device using different predetermined energy and dose. In this embodiment, two different energies can be used for p-type implantation to form ion doping distributions at different depths of the semiconductor layer 1005, wherein the doses can be the same or different; after ion implantation is completed, rapid laser annealing, such as nanosecond laser annealing, can be performed. Through this process, two shell layers 1005-1 and one core layer 1005-2 are formed within the semiconductor layer 1005 of the channel portion. The depth of the core layer 1005-2 is greater than that of the shell layers 1005-1. Thus, in one projection direction, the two shell layers 1005-1 are substantially stacked on top of the core layer 1005-2, and the two shell layers 1005-1 and the core layer 1005-2 are arranged to be spaced apart from each other. The amplitude or range of the shell layer 1005-1 (thickness in the vertical direction as shown in the figure) is, for example, about 5-10 nm, and the amplitude or range of the core layer 1005-2 (thickness in the vertical direction as shown in the figure) is, for example, about 10-50 nm. In the horizontal direction of the figure, the span of the shell layer 1005-1 and the core layer 1005-2 is substantially similar to the span of the channel portion. However, it should be understood that the characteristics of ion implantation determine that the ion distribution pattern of the shell 1005-1 and the core 1005-2 is not necessarily rectangular, but rather roughly elliptical. Other shapes can be achieved by changing the implantation process.

[0059] This invention provides a method for creating one or more shells in the channel portion using existing injection technology, which can advantageously realize multi-Vt schemes for FDSOI devices in a very simple way. Compared with conventional / existing methods for manufacturing FDSOI devices with multiple Vt, the process is extremely simple, requiring no additional circuit design and corresponding process settings, thus greatly reducing complexity.

[0060] Those skilled in the art know that the energy of ion implantation can determine the depth of the implanted ions, the dose of ion implantation can determine the concentration of the implanted ions, and the combination of the energy and dose of ion implantation can be used to calculate the depth and amplitude of ion distribution in the semiconductor.

[0061] In another embodiment of the present invention, the shell portion 1005-1 may be an undoped portion of the semiconductor layer 1005, or the shell portion 1005-1 may be an undoped region of the semiconductor layer 1005.

[0062] The shell 1005-1 and the core 1005-2 can be formed by ion implantation and subsequent annealing. The distribution of doped ions formed through this process can be as follows: Figure 7 The distribution shown is as follows. Figure 7 The distribution is schematic. Ion implantation is advantageous because it allows for precise control of the distribution range of the shell 1005-1 and core 1005-2, including depth and distribution amplitude, as well as precise control of the ion concentration, i.e., doping concentration, of the shell 1005-1 and core 1005-2. Ion implantation is a mature semiconductor manufacturing process, thus it can be implemented using existing semiconductor process flows at a low cost. Since ion implantation can penetrate multiple layers and the implantation depth can be controlled by the implantation energy, it allows for the direct implantation of ions onto the surface of semiconductor layer 1005 to form the shell 1005-1 and core 1005-2 within semiconductor layer 1005, or it can be performed after other dielectric layers have been formed above semiconductor layer 1005. For example, it can be performed as follows: Figure 6 In the steps shown, ions can be implanted through an opening, as in... Figure 7 The illustrated steps involve ion implantation through an opening and a dielectric layer within the opening. The annealing process of this invention can be achieved via a laser nanosecond annealing process, which offers low thermal costs and is rapid.

[0063] According to an embodiment, the above-described semiconductor device can be configured as a plurality of semiconductor devices, which may include n-type semiconductor devices and p-type semiconductor devices. In the n-type semiconductor device, the shell portion 1005-1 of the semiconductor layer 1005 in the channel portion is a partially p-type doped region, and the core portion 1005-2 is a partially n-type doped region within the semiconductor layer 1005. In the p-type semiconductor device, the shell portion 1005-1 of the semiconductor layer 1005 in the channel portion is a partially n-type doped region, and the core portion 1005-2 is a partially p-type doped region within the semiconductor layer 1005. Each gate stack may include a gate dielectric layer and a work function layer 1021 on the gate dielectric layer. In the n-type semiconductor device, the work function layer is n-type; in other embodiments, in the p-type semiconductor device, the work function layer is p-type. In one embodiment, the threshold voltage of the n-type semiconductor device and the threshold voltage of the p-type semiconductor device can be set to be substantially symmetrical, which may be determined, for example, by the doping dose of the shell portion and the core portion and the work function layer.

[0064] According to the embodiment, the contact resistance between the channel portion and the source / drain portion 1011 of the semiconductor device can be lower in the on-state of the semiconductor device than in the off-state of the semiconductor device.

[0065] According to the embodiment, the above-mentioned semiconductor device can be an n-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (positive voltage), the space charge in the core 1005-2 is balanced by the space charge in the shell 1005-1, becoming completely depleted. When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core 1005-2 first forms an electron accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell 1005-1 to form an inversion mode and jointly join in conducting electricity.

[0066] According to an embodiment, the aforementioned semiconductor device can be a p-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (negative voltage), the space charge in the core 1005-2 is balanced by the space charge in the shell 1005-1, resulting in complete depletion. As the absolute value of the gate voltage gradually increases and exceeds the absolute value of the threshold voltage, the core 1005-2 first forms a hole accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell 1005-1 to form an inversion mode and jointly participate in conduction.

[0067] The following describes a method for manufacturing a transistor device according to an embodiment of the present invention.

[0068] Figures 1 to 7 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0069] like Figure 1 As shown, a buried oxide layer 1003 can be formed on a substrate 1001 (e.g., Si), or a finished silicon-on-insulator (SOI) substrate can be used directly. A semiconductor layer 1005 is formed on the buried oxide layer 1003. In this embodiment, the SOI substrate can be formed using, for example, an SOI fabrication process such as a smart dicing process. The substrate 1001 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Here, a silicon wafer is used as an example to describe the substrate 1001. The buried oxide layer 1003 may include oxides (e.g., silicon oxide). The semiconductor layer 1005 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. The thickness of the semiconductor layer 1005 can be set as needed, and the semiconductor layer 1005 can be grown directly by epitaxy.

[0070] Next, as Figure 2 As shown, a sacrificial gate 1007 can be formed on the semiconductor layer 1005, where the channel extension direction is taken as the first direction (e.g., Figure 2The horizontal direction within the plane of the paper), and the direction that intersects (e.g., is perpendicular to) the first direction as the second direction (e.g., Figure 2 The sacrificial gate 1007 extends along a second direction (perpendicular to the plane of the paper). The sacrificial gate 1007 may comprise polysilicon. For convenience, a hard mask that may be present on the sacrificial gate 1007 is not shown. Sidewalls 1009 of the sacrificial gate 1007 can be formed on its sidewalls using a sidewall forming process. For example, sidewall 1009 may comprise a nitride (e.g., silicon nitride). Figure 2 As shown, in the third party ( Figure 2 In the vertical direction within the paper, the portion of the upper surface of the semiconductor layer 1005 that is not covered by the sacrificial gate 1007 and the sidewall 1009 is exposed.

[0071] like Figure 3 As shown, a source / drain portion 1011 extending upward in a third direction can be formed by, for example, selective epitaxial growth using an exposed portion of the upper surface of the semiconductor layer 1005 as a seed. The source / drain portion 1011 can be formed on opposite sides of the sidewalls 1009 of the sacrificial gate 1007 and can be formed to overlap with the sacrificial gate 1007 in a first direction. The source / drain portion 1011 can comprise various suitable semiconductor materials, for example, Si for an n-type field-effect transistor and SiGe for a p-type field-effect transistor. The source / drain portion 1011 can be doped to the desired conductivity type (n-type doping for an n-type field-effect transistor and p-type doping for a p-type field-effect transistor) by, for example, in-situ doping or ion implantation. Here, advantageously, the height of the source / drain portion 1011 can be less than the height of the sacrificial gate 1007.

[0072] Next, an alternative gate process can be implemented.

[0073] For example, such as Figure 4 As shown, an interlayer dielectric layer 1013 can be formed on the semiconductor layer 1005. The interlayer dielectric layer can be an oxide layer. For example, the interlayer dielectric layer 1013 can be formed by depositing an oxide and then planarizing the oxide deposited by CMP. CMP can be performed up to expose the sacrificial gate 1007 inside the sacrificial gate sidewall 1009.

[0074] like Figure 5 As shown, the sacrificial gate 1007 and sacrificial gate sidewall 1009 can be selectively etched away to free up space 1015 between source / drain portions 1011, forming an opening pattern that exposes the surface of semiconductor layer 1005. Since the sacrificial gate sidewall 1009 is removed in addition to the sacrificial gate 1007, there may be no gate sidewall between the gate stack subsequently formed in the freed space 1015 and the source / drain portions 1011. In another embodiment, the gate sidewall may be retained.

[0075] It should be pointed out here that Figure 5 For convenience, space 1015 is shown as having a substantially uniform width in the vertical direction. However, considering the shape of the sacrificial fence sidewall 1009, space 1015 may have a shape where the lower width is greater than the upper width.

[0076] After that, as Figure 6 As shown, ions can be implanted into the semiconductor layer 1005 using an opening pattern. Multiple ion implantation process parameters can be set according to the number, depth, and concentration of the shell 1005-1 and the core 1005-2, to form ion implantation regions of different depths and concentrations in the semiconductor layer 1005, thereby providing at least one shell 1005-1 and at least one core 1005-2. For example, for an n-type field-effect transistor, n-type ions are first implanted at a predetermined energy to provide the ion distribution for the core 1005-2. Then, the implantation energy is adjusted to implant p-type ions to provide the ion distribution for the shell 1005-1. Subsequently, the implantation energy can be further reduced to implant p-type ions to provide the ion distribution for the second shell 1005-1.

[0077] For a p-type field-effect transistor, p-type ions are first injected with a predetermined energy to provide the ion distribution in the core 1005-2. Then, the injection energy is adjusted to inject n-type ions to provide the ion distribution in the shell 1005-1. Subsequently, the injection energy can be further reduced to inject n-type ions to provide the ion distribution in the second shell 1005-1.

[0078] It should be pointed out here that Figure 6 The ion distribution patterns of the shell 1005-1 and the core 1005-2 are only schematically shown in the figure.

[0079] In this invention, during ion implantation, the presence of the opening pattern allows ions to be implanted into the exposed portion of the semiconductor layer 1005 within the openings. Since the entire SOI substrate is covered by an interlayer dielectric layer 1013, the implanted ions are blocked within this layer. Therefore, a separate hard mask and alignment process are not required for ion implantation, simplifying the manufacturing process and ensuring accurate implantation.

[0080] After that, as Figure 7As shown, a gate stack can be formed in space 1015, for example, by deposition. For instance, a first gate dielectric layer 1017, a work function layer 1019, and a gate conductor layer 1021 can be sequentially formed directly on the surface of semiconductor layer 1005 to obtain the final gate stack. The first gate dielectric layer 1017 can be a high-k gate dielectric, such as a hafnium oxide layer, which can have a thickness of approximately 2 nm. The work function layer 1019 can be TiN. In one embodiment, the gate stack may include a gate conductor layer 1021, which may include a gate electrode metal such as tungsten (W).

[0081] For n-type and p-type field-effect transistors, as described above, corresponding shell portions 1005-1 and core portions 1005-2 can be formed respectively, and n-type and p-type work function layers can be formed respectively. In one embodiment, the threshold voltage of the n-type field-effect transistor and the threshold voltage of the p-type field-effect transistor can be set to be substantially symmetrical. In this case, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost can be reduced.

[0082] like Figure 7 As shown, the semiconductor device according to the embodiment may include a gate stack, and the gate stack may be located between the source / drain portion 1011 and the gate conductive layer 1021.

[0083] In addition, the work function layer includes metallic materials such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum nitride (TiAl), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto.

[0084] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0085] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0086] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Substrate; The buried oxide layer on the substrate; The channel portion includes a semiconductor layer stacked above the buried oxide layer; Source / drain sections are arranged above the buried oxygen layer and connected to opposite ends of the channel section; and A grid stack between the source and drain portions is arranged on the channel portion; The semiconductor layer includes at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction. The at least one shell and the at least one core are portions of the semiconductor layer, each having opposite doping types.

2. The semiconductor device according to claim 1, wherein the thickness of one of the at least one housing portion is 5 nm to 10 nm, and / or the thickness of one of the at least one core portion is 10 nm to 50 nm.

3. The semiconductor device according to claim 1, wherein the at least one core comprises one core or two cores, and / or wherein the at least one housing comprises two housings.

4. The semiconductor device of claim 1, wherein the shell and the core are obtained by performing an ion implantation process on the semiconductor layer.

5. The semiconductor device of claim 4, wherein the housing and the core are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.

6. The semiconductor device of claim 1, wherein the gate stack comprises a work function layer and a gate metal conductive layer.

7. The semiconductor device of claim 6, wherein the gate stack includes a first gate dielectric layer.

8. The semiconductor device according to claim 1, wherein, The semiconductor devices are configured as a plurality of semiconductor devices, including n-type semiconductor devices and p-type semiconductor devices, and their respective gate stacks include the same gate dielectric layer, wherein the work function layers on the gate dielectric layer are n-type and p-type, respectively. Wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion and an n-type doped core portion, and / or the channel portion of the p-type semiconductor device includes an n-type doped shell portion and a p-type doped core portion.

9. The semiconductor device according to claim 8, wherein, The threshold voltage of the n-type semiconductor device and the threshold voltage of the p-type semiconductor device are set to be substantially symmetrical.

10. The semiconductor device according to claim 1, wherein, There are no gate sidewalls between the gate stack and the source / drain.

11. The semiconductor device according to claim 8, wherein the semiconductor device is an n-type semiconductor device. When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core first forms a charge accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell to form an inversion mode and join in conducting electricity.

12. The semiconductor device according to claim 8, wherein the semiconductor device is a p-type semiconductor device. When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and When the gate voltage value gradually exceeds the absolute value of the threshold voltage, the core first forms a hole accumulation mode and begins to conduct electricity. Then, a larger absolute value of the gate voltage causes the shell to form an inversion mode and join in conducting electricity.

13. The semiconductor device of claim 1, wherein the at least one housing portion is on top of at least one core portion, or the at least one core portion is on top of at least one housing portion; and / or The at least one shell portion and at least one core portion are arranged alternately.

14. A method for manufacturing a semiconductor device, comprising: A buried oxide layer is formed on the substrate; A semiconductor layer is formed on the buried oxide layer; A sacrificial gate is formed on the semiconductor layer, and a sacrificial gate sidewall is formed on the sidewall of the sacrificial gate; Source / drain portions are formed on opposite sides of the sacrificial gate sidewall, and the source / drain portions overlap with the sacrificial gate in the channel extension direction; Remove the sacrificial gate and optionally remove the sidewalls of the sacrificial gate to free up space between the source and drain; At least one core and at least one shell are formed in the semiconductor layer within the space; as well as A gate stack is formed on the semiconductor layer in the space.

15. The method according to claim 14, wherein, At least one core and at least one shell are formed in the semiconductor layer by ion implantation.

16. The method of claim 14, wherein, The thickness of one shell portion of the at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of the at least one core portion is 10 nm to 50 nm.

17. The method of claim 14, wherein, Forming the gate stack includes: A first gate dielectric layer, a work function layer, and a gate conductive layer are sequentially formed on the exposed surface of the semiconductor layer.

18. The method of claim 14, wherein the method comprises: For n-type semiconductor devices, a p-type doped shell and an n-type doped core are formed; and / or For p-type semiconductor devices, an n-type doped shell and a p-type doped core are formed.

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